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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f1xx_hal_cortex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of CORTEX HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F1xx_HAL_CORTEX_H |
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| 22 | #define __STM32F1xx_HAL_CORTEX_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f1xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F1xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup CORTEX |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | /* Exported types ------------------------------------------------------------*/ |
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| 39 | /** @defgroup CORTEX_Exported_Types Cortex Exported Types |
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| 40 | * @{ |
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| 41 | */ |
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| 42 | |||
| 43 | #if (__MPU_PRESENT == 1U) |
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| 44 | /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition |
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| 45 | * @brief MPU Region initialization structure |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | typedef struct |
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| 49 | { |
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| 50 | uint8_t Enable; /*!< Specifies the status of the region. |
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| 51 | This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ |
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| 52 | uint8_t Number; /*!< Specifies the number of the region to protect. |
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| 53 | This parameter can be a value of @ref CORTEX_MPU_Region_Number */ |
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| 54 | uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ |
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| 55 | uint8_t Size; /*!< Specifies the size of the region to protect. |
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| 56 | This parameter can be a value of @ref CORTEX_MPU_Region_Size */ |
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| 57 | uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. |
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| 58 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
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| 59 | uint8_t TypeExtField; /*!< Specifies the TEX field level. |
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| 60 | This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ |
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| 61 | uint8_t AccessPermission; /*!< Specifies the region access permission type. |
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| 62 | This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ |
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| 63 | uint8_t DisableExec; /*!< Specifies the instruction access status. |
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| 64 | This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ |
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| 65 | uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. |
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| 66 | This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ |
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| 67 | uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. |
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| 68 | This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ |
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| 69 | uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. |
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| 70 | This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ |
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| 71 | }MPU_Region_InitTypeDef; |
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| 72 | /** |
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| 73 | * @} |
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| 74 | */ |
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| 75 | #endif /* __MPU_PRESENT */ |
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| 76 | |||
| 77 | /** |
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| 78 | * @} |
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| 79 | */ |
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| 80 | |||
| 81 | /* Exported constants --------------------------------------------------------*/ |
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| 82 | |||
| 83 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants |
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| 84 | * @{ |
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| 85 | */ |
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| 86 | |||
| 87 | /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group |
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| 88 | * @{ |
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| 89 | */ |
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| 90 | #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority |
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| 91 | 4 bits for subpriority */ |
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| 92 | #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority |
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| 93 | 3 bits for subpriority */ |
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| 94 | #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority |
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| 95 | 2 bits for subpriority */ |
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| 96 | #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority |
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| 97 | 1 bits for subpriority */ |
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| 98 | #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority |
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| 99 | |||
| 100 | /** |
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| 101 | * @} |
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| 102 | */ |
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| 103 | |||
| 104 | /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source |
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| 105 | * @{ |
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| 106 | */ |
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| 107 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U |
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| 108 | #define SYSTICK_CLKSOURCE_HCLK 0x00000004U |
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| 109 | |||
| 110 | /** |
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| 111 | * @} |
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| 112 | */ |
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| 113 | |||
| 114 | #if (__MPU_PRESENT == 1) |
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| 115 | /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control |
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| 116 | * @{ |
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| 117 | */ |
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| 118 | #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U |
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| 119 | #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk |
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| 120 | #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk |
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| 121 | #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) |
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| 122 | |||
| 123 | /** |
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| 124 | * @} |
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| 125 | */ |
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| 126 | |||
| 127 | /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable |
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| 128 | * @{ |
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| 129 | */ |
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| 130 | #define MPU_REGION_ENABLE ((uint8_t)0x01) |
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| 131 | #define MPU_REGION_DISABLE ((uint8_t)0x00) |
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| 132 | /** |
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| 133 | * @} |
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| 134 | */ |
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| 135 | |||
| 136 | /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access |
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| 137 | * @{ |
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| 138 | */ |
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| 139 | #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) |
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| 140 | #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) |
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| 141 | /** |
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| 142 | * @} |
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| 143 | */ |
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| 144 | |||
| 145 | /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable |
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| 146 | * @{ |
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| 147 | */ |
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| 148 | #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) |
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| 149 | #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) |
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| 150 | /** |
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| 151 | * @} |
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| 152 | */ |
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| 153 | |||
| 154 | /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable |
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| 155 | * @{ |
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| 156 | */ |
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| 157 | #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) |
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| 158 | #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) |
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| 159 | /** |
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| 160 | * @} |
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| 161 | */ |
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| 162 | |||
| 163 | /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable |
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| 164 | * @{ |
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| 165 | */ |
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| 166 | #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) |
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| 167 | #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) |
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| 168 | /** |
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| 169 | * @} |
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| 170 | */ |
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| 171 | |||
| 172 | /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels |
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| 173 | * @{ |
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| 174 | */ |
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| 175 | #define MPU_TEX_LEVEL0 ((uint8_t)0x00) |
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| 176 | #define MPU_TEX_LEVEL1 ((uint8_t)0x01) |
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| 177 | #define MPU_TEX_LEVEL2 ((uint8_t)0x02) |
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| 178 | /** |
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| 179 | * @} |
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| 180 | */ |
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| 181 | |||
| 182 | /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size |
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| 183 | * @{ |
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| 184 | */ |
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| 185 | #define MPU_REGION_SIZE_32B ((uint8_t)0x04) |
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| 186 | #define MPU_REGION_SIZE_64B ((uint8_t)0x05) |
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| 187 | #define MPU_REGION_SIZE_128B ((uint8_t)0x06) |
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| 188 | #define MPU_REGION_SIZE_256B ((uint8_t)0x07) |
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| 189 | #define MPU_REGION_SIZE_512B ((uint8_t)0x08) |
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| 190 | #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) |
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| 191 | #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) |
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| 192 | #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) |
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| 193 | #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) |
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| 194 | #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) |
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| 195 | #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) |
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| 196 | #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) |
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| 197 | #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) |
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| 198 | #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) |
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| 199 | #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) |
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| 200 | #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) |
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| 201 | #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) |
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| 202 | #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) |
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| 203 | #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) |
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| 204 | #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) |
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| 205 | #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) |
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| 206 | #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) |
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| 207 | #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) |
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| 208 | #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) |
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| 209 | #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) |
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| 210 | #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) |
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| 211 | #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) |
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| 212 | #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) |
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| 213 | /** |
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| 214 | * @} |
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| 215 | */ |
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| 216 | |||
| 217 | /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes |
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| 218 | * @{ |
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| 219 | */ |
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| 220 | #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) |
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| 221 | #define MPU_REGION_PRIV_RW ((uint8_t)0x01) |
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| 222 | #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) |
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| 223 | #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) |
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| 224 | #define MPU_REGION_PRIV_RO ((uint8_t)0x05) |
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| 225 | #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) |
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| 226 | /** |
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| 227 | * @} |
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| 228 | */ |
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| 229 | |||
| 230 | /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number |
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| 231 | * @{ |
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| 232 | */ |
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| 233 | #define MPU_REGION_NUMBER0 ((uint8_t)0x00) |
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| 234 | #define MPU_REGION_NUMBER1 ((uint8_t)0x01) |
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| 235 | #define MPU_REGION_NUMBER2 ((uint8_t)0x02) |
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| 236 | #define MPU_REGION_NUMBER3 ((uint8_t)0x03) |
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| 237 | #define MPU_REGION_NUMBER4 ((uint8_t)0x04) |
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| 238 | #define MPU_REGION_NUMBER5 ((uint8_t)0x05) |
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| 239 | #define MPU_REGION_NUMBER6 ((uint8_t)0x06) |
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| 240 | #define MPU_REGION_NUMBER7 ((uint8_t)0x07) |
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| 241 | /** |
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| 242 | * @} |
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| 243 | */ |
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| 244 | #endif /* __MPU_PRESENT */ |
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| 245 | |||
| 246 | /** |
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| 247 | * @} |
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| 248 | */ |
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| 249 | |||
| 250 | |||
| 251 | /* Exported Macros -----------------------------------------------------------*/ |
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| 252 | |||
| 253 | /* Exported functions --------------------------------------------------------*/ |
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| 254 | /** @addtogroup CORTEX_Exported_Functions |
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| 255 | * @{ |
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| 256 | */ |
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| 257 | |||
| 258 | /** @addtogroup CORTEX_Exported_Functions_Group1 |
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| 259 | * @{ |
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| 260 | */ |
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| 261 | /* Initialization and de-initialization functions *****************************/ |
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| 262 | void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); |
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| 263 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); |
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| 264 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); |
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| 265 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); |
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| 266 | void HAL_NVIC_SystemReset(void); |
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| 267 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); |
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| 268 | /** |
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| 269 | * @} |
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| 270 | */ |
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| 271 | |||
| 272 | /** @addtogroup CORTEX_Exported_Functions_Group2 |
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| 273 | * @{ |
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| 274 | */ |
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| 275 | /* Peripheral Control functions ***********************************************/ |
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| 276 | uint32_t HAL_NVIC_GetPriorityGrouping(void); |
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| 277 | void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); |
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| 278 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); |
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| 279 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); |
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| 280 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); |
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| 281 | uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); |
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| 282 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); |
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| 283 | void HAL_SYSTICK_IRQHandler(void); |
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| 284 | void HAL_SYSTICK_Callback(void); |
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| 285 | |||
| 286 | #if (__MPU_PRESENT == 1U) |
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| 287 | void HAL_MPU_Enable(uint32_t MPU_Control); |
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| 288 | void HAL_MPU_Disable(void); |
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| 289 | void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); |
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| 290 | #endif /* __MPU_PRESENT */ |
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| 291 | /** |
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| 292 | * @} |
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| 293 | */ |
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| 294 | |||
| 295 | /** |
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| 296 | * @} |
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| 297 | */ |
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| 298 | |||
| 299 | /* Private types -------------------------------------------------------------*/ |
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| 300 | /* Private variables ---------------------------------------------------------*/ |
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| 301 | /* Private constants ---------------------------------------------------------*/ |
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| 302 | /* Private macros ------------------------------------------------------------*/ |
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| 303 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros |
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| 304 | * @{ |
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| 305 | */ |
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| 306 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ |
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| 307 | ((GROUP) == NVIC_PRIORITYGROUP_1) || \ |
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| 308 | ((GROUP) == NVIC_PRIORITYGROUP_2) || \ |
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| 309 | ((GROUP) == NVIC_PRIORITYGROUP_3) || \ |
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| 310 | ((GROUP) == NVIC_PRIORITYGROUP_4)) |
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| 311 | |||
| 312 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
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| 313 | |||
| 314 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) |
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| 315 | |||
| 316 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) |
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| 317 | |||
| 318 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ |
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| 319 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) |
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| 320 | |||
| 321 | #if (__MPU_PRESENT == 1U) |
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| 322 | #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ |
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| 323 | ((STATE) == MPU_REGION_DISABLE)) |
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| 324 | |||
| 325 | #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ |
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| 326 | ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) |
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| 327 | |||
| 328 | #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ |
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| 329 | ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) |
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| 330 | |||
| 331 | #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ |
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| 332 | ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) |
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| 333 | |||
| 334 | #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ |
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| 335 | ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) |
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| 336 | |||
| 337 | #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ |
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| 338 | ((TYPE) == MPU_TEX_LEVEL1) || \ |
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| 339 | ((TYPE) == MPU_TEX_LEVEL2)) |
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| 340 | |||
| 341 | #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ |
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| 342 | ((TYPE) == MPU_REGION_PRIV_RW) || \ |
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| 343 | ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ |
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| 344 | ((TYPE) == MPU_REGION_FULL_ACCESS) || \ |
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| 345 | ((TYPE) == MPU_REGION_PRIV_RO) || \ |
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| 346 | ((TYPE) == MPU_REGION_PRIV_RO_URO)) |
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| 347 | |||
| 348 | #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ |
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| 349 | ((NUMBER) == MPU_REGION_NUMBER1) || \ |
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| 350 | ((NUMBER) == MPU_REGION_NUMBER2) || \ |
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| 351 | ((NUMBER) == MPU_REGION_NUMBER3) || \ |
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| 352 | ((NUMBER) == MPU_REGION_NUMBER4) || \ |
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| 353 | ((NUMBER) == MPU_REGION_NUMBER5) || \ |
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| 354 | ((NUMBER) == MPU_REGION_NUMBER6) || \ |
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| 355 | ((NUMBER) == MPU_REGION_NUMBER7)) |
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| 356 | |||
| 357 | #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ |
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| 358 | ((SIZE) == MPU_REGION_SIZE_64B) || \ |
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| 359 | ((SIZE) == MPU_REGION_SIZE_128B) || \ |
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| 360 | ((SIZE) == MPU_REGION_SIZE_256B) || \ |
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| 361 | ((SIZE) == MPU_REGION_SIZE_512B) || \ |
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| 362 | ((SIZE) == MPU_REGION_SIZE_1KB) || \ |
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| 363 | ((SIZE) == MPU_REGION_SIZE_2KB) || \ |
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| 364 | ((SIZE) == MPU_REGION_SIZE_4KB) || \ |
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| 365 | ((SIZE) == MPU_REGION_SIZE_8KB) || \ |
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| 366 | ((SIZE) == MPU_REGION_SIZE_16KB) || \ |
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| 367 | ((SIZE) == MPU_REGION_SIZE_32KB) || \ |
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| 368 | ((SIZE) == MPU_REGION_SIZE_64KB) || \ |
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| 369 | ((SIZE) == MPU_REGION_SIZE_128KB) || \ |
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| 370 | ((SIZE) == MPU_REGION_SIZE_256KB) || \ |
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| 371 | ((SIZE) == MPU_REGION_SIZE_512KB) || \ |
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| 372 | ((SIZE) == MPU_REGION_SIZE_1MB) || \ |
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| 373 | ((SIZE) == MPU_REGION_SIZE_2MB) || \ |
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| 374 | ((SIZE) == MPU_REGION_SIZE_4MB) || \ |
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| 375 | ((SIZE) == MPU_REGION_SIZE_8MB) || \ |
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| 376 | ((SIZE) == MPU_REGION_SIZE_16MB) || \ |
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| 377 | ((SIZE) == MPU_REGION_SIZE_32MB) || \ |
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| 378 | ((SIZE) == MPU_REGION_SIZE_64MB) || \ |
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| 379 | ((SIZE) == MPU_REGION_SIZE_128MB) || \ |
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| 380 | ((SIZE) == MPU_REGION_SIZE_256MB) || \ |
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| 381 | ((SIZE) == MPU_REGION_SIZE_512MB) || \ |
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| 382 | ((SIZE) == MPU_REGION_SIZE_1GB) || \ |
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| 383 | ((SIZE) == MPU_REGION_SIZE_2GB) || \ |
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| 384 | ((SIZE) == MPU_REGION_SIZE_4GB)) |
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| 385 | |||
| 386 | #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) |
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| 387 | #endif /* __MPU_PRESENT */ |
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| 388 | |||
| 389 | /** |
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| 390 | * @} |
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| 391 | */ |
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| 392 | |||
| 393 | /* Private functions ---------------------------------------------------------*/ |
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| 394 | |||
| 395 | /** |
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| 396 | * @} |
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| 397 | */ |
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| 398 | |||
| 399 | /** |
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| 400 | * @} |
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| 401 | */ |
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| 402 | |||
| 403 | #ifdef __cplusplus |
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| 404 | } |
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| 405 | #endif |
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| 406 | |||
| 407 | #endif /* __STM32F1xx_HAL_CORTEX_H */ |
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| 408 | |||
| 409 | |||
| 410 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |