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2 mjames 1 
/**
2 
  ******************************************************************************
3 
  * @file    stm32f1xx_hal_cortex.h
4 
  * @author  MCD Application Team
5 mjames 5 
  * @version V1.0.4
6 
  * @date    29-April-2016
2 mjames 7 
  * @brief   Header file of CORTEX HAL module.
8 
  ******************************************************************************
9 
  * @attention
10 
  *
5 mjames 11 
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2 mjames 12 
  *
13 
  * Redistribution and use in source and binary forms, with or without modification,
14 
  * are permitted provided that the following conditions are met:
15 
  *   1. Redistributions of source code must retain the above copyright notice,
16 
  *      this list of conditions and the following disclaimer.
17 
  *   2. Redistributions in binary form must reproduce the above copyright notice,
18 
  *      this list of conditions and the following disclaimer in the documentation
19 
  *      and/or other materials provided with the distribution.
20 
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
21 
  *      may be used to endorse or promote products derived from this software
22 
  *      without specific prior written permission.
23 
  *
24 
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 
  *
35 
  ******************************************************************************
36 
  */
37 
 
38 
/* Define to prevent recursive inclusion -------------------------------------*/
39 
#ifndef __STM32F1xx_HAL_CORTEX_H
40 
#define __STM32F1xx_HAL_CORTEX_H
41 
 
42 
#ifdef __cplusplus
43 
 extern "C" {
44 
#endif
45 
 
46 
/* Includes ------------------------------------------------------------------*/
47 
#include "stm32f1xx_hal_def.h"
48 
 
49 
/** @addtogroup STM32F1xx_HAL_Driver
50 
  * @{
51 
  */
52 
 
53 
/** @addtogroup CORTEX
54 
  * @{
55 
  */
56 
/* Exported types ------------------------------------------------------------*/
57 
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
58 
  * @{
59 
  */
60 
 
61 
#if (__MPU_PRESENT == 1)
62 
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
63 
  * @brief  MPU Region initialization structure
64 
  * @{
65 
  */
66 
typedef struct
67 
{
68 
  uint8_t                Enable;                /*!< Specifies the status of the region.
69 
                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
70 
  uint8_t                Number;                /*!< Specifies the number of the region to protect.
71 
                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
72 
  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
73 
  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
74 
                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
75 
  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
76 
                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */        
77 
  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
78 
                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                
79 
  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
80 
                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
81 
  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
82 
                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
83 
  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
84 
                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
85 
  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
86 
                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
87 
  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
88 
                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
89 
}MPU_Region_InitTypeDef;
90 
/**
91 
  * @}
92 
  */
93 
#endif /* __MPU_PRESENT */
94 
 
95 
/**
96 
  * @}
97 
  */
98 
 
99 
/* Exported constants --------------------------------------------------------*/
100 
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
101 
  * @{
102 
  */
103 
 
104 
 
105 
/** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group
106 
  * @{
107 
  */
108 
 
109 
#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
110 
                                                                 4 bits for subpriority */
111 
#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
112 
                                                                 3 bits for subpriority */
113 
#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
114 
                                                                 2 bits for subpriority */
115 
#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
116 
                                                                 1 bits for subpriority */
117 
#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
118 
 
119 
/**
120 
  * @}
121 
  */
122 
 
123 
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
124 
  * @{
125 
  */
126 
#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
127 
#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
128 
 
129 
/**
130 
  * @}
131 
  */
132 
 
133 
#if (__MPU_PRESENT == 1)
134 
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
135 
  * @{
136 
  */
137 
#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
138 
#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
139 
#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
140 
#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
141 
/**
142 
  * @}
143 
  */
144 
 
145 
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
146 
  * @{
147 
  */
148 
#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
149 
#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
150 
/**
151 
  * @}
152 
  */
153 
 
154 
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
155 
  * @{
156 
  */
157 
#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
158 
#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
159 
/**
160 
  * @}
161 
  */
162 
 
163 
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
164 
  * @{
165 
  */
166 
#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
167 
#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
168 
/**
169 
  * @}
170 
  */
171 
 
172 
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
173 
  * @{
174 
  */
175 
#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
176 
#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
177 
/**
178 
  * @}
179 
  */
180 
 
181 
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
182 
  * @{
183 
  */
184 
#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
185 
#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
186 
/**
187 
  * @}
188 
  */
189 
 
190 
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
191 
  * @{
192 
  */
193 
#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
194 
#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
195 
#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
196 
/**
197 
  * @}
198 
  */
199 
 
200 
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
201 
  * @{
202 
  */
203 
#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
204 
#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
205 
#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
206 
#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
207 
#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
208 
#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)  
209 
#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
210 
#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
211 
#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
212 
#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
213 
#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
214 
#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
215 
#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
216 
#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
217 
#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
218 
#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
219 
#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
220 
#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
221 
#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
222 
#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
223 
#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
224 
#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
225 
#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
226 
#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
227 
#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
228 
#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
229 
#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
230 
#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
231 
/**                                
232 
  * @}
233 
  */
234 
 
235 
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
236 
  * @{
237 
  */
238 
#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)  
239 
#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
240 
#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)  
241 
#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)  
242 
#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
243 
#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
244 
/**
245 
  * @}
246 
  */
247 
 
248 
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
249 
  * @{
250 
  */
251 
#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)  
252 
#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
253 
#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)  
254 
#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)  
255 
#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
256 
#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
257 
#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
258 
#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
259 
/**
260 
  * @}
261 
  */
262 
#endif /* __MPU_PRESENT */
263 
 
264 
/**
265 
  * @}
266 
  */
267 
 
268 
 
269 
/* Private macro -------------------------------------------------------------*/
270 
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
271 
  * @{
272 
  */  
273 
 
274 
/** @defgroup CORTEX_Preemption_Priority_Group_Macro  CORTEX Preemption Priority Group
275 
  * @{
276 
  */
277 
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
278 
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
279 
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
280 
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
281 
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
282 
 
283 
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
284 
 
285 
#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
286 
 
287 
#define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
288 
 
289 
/**
290 
  * @}
291 
  */
292 
 
293 
/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
294 
  * @{
295 
  */                      
296 
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
297 
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
298 
/**
299 
  * @}
300 
  */
301 
#if (__MPU_PRESENT == 1)
302 
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
303 
                                     ((STATE) == MPU_REGION_DISABLE))
304 
 
305 
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
306 
                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
307 
 
308 
#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
309 
                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
310 
 
311 
#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
312 
                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
313 
 
314 
#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
315 
                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
316 
 
317 
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
318 
                                ((TYPE) == MPU_TEX_LEVEL1)  || \
319 
                                ((TYPE) == MPU_TEX_LEVEL2))
320 
 
321 
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
322 
                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
323 
                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
324 
                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
325 
                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
326 
                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
327 
 
328 
#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
329 
                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
330 
                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
331 
                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
332 
                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
333 
                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
334 
                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
335 
                                         ((NUMBER) == MPU_REGION_NUMBER7))
336 
 
337 
#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
338 
                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
339 
                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
340 
                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
341 
                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
342 
                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
343 
                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
344 
                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
345 
                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
346 
                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
347 
                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
348 
                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
349 
                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
350 
                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
351 
                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
352 
                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
353 
                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
354 
                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
355 
                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
356 
                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
357 
                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
358 
                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
359 
                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
360 
                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
361 
                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
362 
                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
363 
                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
364 
                                     ((SIZE) == MPU_REGION_SIZE_4GB))
365 
 
366 
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
367 
#endif /* __MPU_PRESENT */
368 
 
369 
/**
370 
  * @}
371 
  */
372 
 
373 
/* Exported functions --------------------------------------------------------*/
374 
/** @addtogroup CORTEX_Exported_Functions
375 
  * @{
376 
  */
377 
 
378 
/** @addtogroup CORTEX_Exported_Functions_Group1
379 
  * @{
380 
  */  
381 
/* Initialization and de-initialization functions *****************************/
382 
void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
383 
void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
384 
void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
385 
void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
386 
void     HAL_NVIC_SystemReset(void);
387 
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
388 
/**
389 
  * @}
390 
  */
391 
 
392 
/** @addtogroup CORTEX_Exported_Functions_Group2
393 
  * @{
394 
  */
395 
/* Peripheral Control functions ***********************************************/
396 
#if (__MPU_PRESENT == 1)
397 
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
398 
#endif /* __MPU_PRESENT */
399 
uint32_t HAL_NVIC_GetPriorityGrouping(void);
400 
void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
401 
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
402 
void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
403 
void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
404 
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
405 
void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
406 
void     HAL_SYSTICK_IRQHandler(void);
407 
void     HAL_SYSTICK_Callback(void);
408 
/**
409 
  * @}
410 
  */
411 
 
412 
/**
413 
  * @}
414 
  */
415 
 
416 
/* Private functions ---------------------------------------------------------*/  
417 
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
418 
  * @brief    CORTEX private  functions
419 
  * @{
420 
  */
421 
 
422 
#if (__MPU_PRESENT == 1)
423 
/**
424 
  * @brief  Disables the MPU
425 
  * @retval None
426 
  */
427 
__STATIC_INLINE void HAL_MPU_Disable(void)
428 
{
429 
  /* Disable fault exceptions */
430 
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
431 
 
432 
  /* Disable the MPU */
433 
  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
434 
}
435 
 
436 
/**
437 
  * @brief  Enables the MPU
438 
  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
439 
  *          NMI, FAULTMASK and privileged accessto the default memory
440 
  *          This parameter can be one of the following values:
441 
  *            @arg MPU_HFNMI_PRIVDEF_NONE
442 
  *            @arg MPU_HARDFAULT_NMI
443 
  *            @arg MPU_PRIVILEGED_DEFAULT
444 
  *            @arg MPU_HFNMI_PRIVDEF
445 
  * @retval None
446 
  */
447 
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
448 
{
449 
  /* Enable the MPU */
450 
  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
451 
 
452 
  /* Enable fault exceptions */
453 
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
454 
}
455 
#endif /* __MPU_PRESENT */
456 
 
457 
/**
458 
  * @}
459 
  */
460 
 
461 
/**
462 
  * @}
463 
  */
464 
 
465 
/**
466 
  * @}
467 
  */
468 
 
469 
#ifdef __cplusplus
470 
}
471 
#endif
472 
 
473 
#endif /* __STM32F1xx_HAL_CORTEX_H */
474 
 
475 
 
476 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/