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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_adc.h
		4	* @author MCD Application Team
		5	* @brief Header file containing functions prototypes of ADC HAL library.
		6	******************************************************************************
		7	* @attention
		8	*
		9	*
		10	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		11	* All rights reserved.</center></h2>
		12	*
		13	* This software component is licensed by ST under BSD 3-Clause license,
		14	* the "License"; You may not use this file except in compliance with the
		15	* License. You may obtain a copy of the License at:
		16	* opensource.org/licenses/BSD-3-Clause
		17	*
		18	******************************************************************************
		19	*/
		20
		21	/* Define to prevent recursive inclusion -------------------------------------*/
		22	#ifndef __STM32F1xx_HAL_ADC_H
		23	#define __STM32F1xx_HAL_ADC_H
		24
		25	#ifdef __cplusplus
		26	extern "C" {
		27	#endif
		28
		29	/* Includes ------------------------------------------------------------------*/
		30	#include "stm32f1xx_hal_def.h"
		31
		32	/** @addtogroup STM32F1xx_HAL_Driver
		33	* @{
		34	*/
		35
		36	/** @addtogroup ADC
		37	* @{
		38	*/
		39
		40	/* Exported types ------------------------------------------------------------*/
		41	/** @defgroup ADC_Exported_Types ADC Exported Types
		42	* @{
		43	*/
		44
		45	/**
		46	* @brief Structure definition of ADC and regular group initialization
		47	* @note Parameters of this structure are shared within 2 scopes:
		48	* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
		49	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
		50	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
		51	* ADC can be either disabled or enabled without conversion on going on regular group.
		52	*/
		53	typedef struct
		54	{
		55	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
		56	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
		57	This parameter can be a value of @ref ADC_Data_align */
		58	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
		59	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
		60	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
		61	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
		62	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
		63	Scan direction is upward: from rank1 to rank 'n'.
		64	This parameter can be a value of @ref ADC_Scan_mode
		65	Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
		66	or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
		67	the last conversion of the sequence. All previous conversions would be overwritten by the last one.
		68	Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
		69	FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
		70	after the selected trigger occurred (software start or external trigger).
		71	This parameter can be set to ENABLE or DISABLE. */
		72	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
		73	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
		74	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
		75	FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
		76	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
		77	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
		78	This parameter can be set to ENABLE or DISABLE. */
		79	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
		80	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
		81	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
		82	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
		83	If set to ADC_SOFTWARE_START, external triggers are disabled.
		84	If set to external trigger source, triggering is on event rising edge.
		85	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
		86	}ADC_InitTypeDef;
		87
		88	/**
		89	* @brief Structure definition of ADC channel for regular group
		90	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
		91	* ADC can be either disabled or enabled without conversion on going on regular group.
		92	*/
		93	typedef struct
		94	{
		95	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
		96	This parameter can be a value of @ref ADC_channels
		97	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
		98	Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
		99	Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
		100	It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
		101	Refer to errata sheet of these devices for more details. */
		102	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
		103	This parameter can be a value of @ref ADC_regular_rank
		104	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
		105	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
		106	Unit: ADC clock cycles
		107	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
		108	This parameter can be a value of @ref ADC_sampling_times
		109	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
		110	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
		111	Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
		112	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
		113	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
		114	}ADC_ChannelConfTypeDef;
		115
		116	/**
		117	* @brief ADC Configuration analog watchdog definition
		118	* @note The setting of these parameters with function is conditioned to ADC state.
		119	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
		120	*/
		121	typedef struct
		122	{
		123	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
		124	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
		125	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
		126	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
		127	This parameter can be a value of @ref ADC_channels. */
		128	FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
		129	This parameter can be set to ENABLE or DISABLE */
		130	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		131	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		132	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		133	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		134	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
		135	}ADC_AnalogWDGConfTypeDef;
		136
		137	/**
		138	* @brief HAL ADC state machine: ADC states definition (bitfields)
		139	*/
		140	/* States of ADC global scope */
		141	#define HAL_ADC_STATE_RESET 0x00000000U /!< ADC not yet initialized or disabled /
		142	#define HAL_ADC_STATE_READY 0x00000001U /!< ADC peripheral ready for use /
		143	#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /!< ADC is busy to internal process (initialization, calibration) /
		144	#define HAL_ADC_STATE_TIMEOUT 0x00000004U /!< TimeOut occurrence /
		145
		146	/* States of ADC errors */
		147	#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /!< Internal error occurrence /
		148	#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /!< Configuration error occurrence /
		149	#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /!< DMA error occurrence /
		150
		151	/* States of ADC group regular */
		152	#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
		153	external trigger, low power auto power-on, multimode ADC master control) */
		154	#define HAL_ADC_STATE_REG_EOC 0x00000200U /!< Conversion data available on group regular /
		155	#define HAL_ADC_STATE_REG_OVR 0x00000400U /!< Not available on STM32F1 device: Overrun occurrence /
		156	#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /!< Not available on STM32F1 device: End Of Sampling flag raised /
		157
		158	/* States of ADC group injected */
		159	#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
		160	external trigger, low power auto power-on, multimode ADC master control) */
		161	#define HAL_ADC_STATE_INJ_EOC 0x00002000U /!< Conversion data available on group injected /
		162	#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /!< Not available on STM32F1 device: Injected queue overflow occurrence /
		163
		164	/* States of ADC analog watchdogs */
		165	#define HAL_ADC_STATE_AWD1 0x00010000U /!< Out-of-window occurrence of analog watchdog 1 /
		166	#define HAL_ADC_STATE_AWD2 0x00020000U /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 /
		167	#define HAL_ADC_STATE_AWD3 0x00040000U /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 /
		168
		169	/* States of ADC multi-mode */
		170	#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /!< ADC in multimode slave state, controlled by another ADC master ( /
		171
		172
		173	/**
		174	* @brief ADC handle Structure definition
		175	*/
		176	typedef struct __ADC_HandleTypeDef
		177	{
		178	ADC_TypeDef Instance; /!< Register base address */
		179
		180	ADC_InitTypeDef Init; /!< ADC required parameters /
		181
		182	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
		183
		184	HAL_LockTypeDef Lock; /!< ADC locking object /
		185
		186	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
		187
		188	__IO uint32_t ErrorCode; /!< ADC Error code /
		189
		190	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		191	void (* ConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion complete callback */
		192	void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC conversion DMA half-transfer callback */
		193	void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC analog watchdog 1 callback */
		194	void (* ErrorCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC error callback */
		195	void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC group injected conversion complete callback / /!< ADC end of sampling callback */
		196	void (* MspInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp Init callback */
		197	void (* MspDeInitCallback)(struct __ADC_HandleTypeDef hadc); /!< ADC Msp DeInit callback */
		198	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		199	}ADC_HandleTypeDef;
		200
		201
		202	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		203	/**
		204	* @brief HAL ADC Callback ID enumeration definition
		205	*/
		206	typedef enum
		207	{
		208	HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /!< ADC conversion complete callback ID /
		209	HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /!< ADC conversion DMA half-transfer callback ID /
		210	HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /!< ADC analog watchdog 1 callback ID /
		211	HAL_ADC_ERROR_CB_ID = 0x03U, /!< ADC error callback ID /
		212	HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /!< ADC group injected conversion complete callback ID /
		213	HAL_ADC_MSPINIT_CB_ID = 0x09U, /!< ADC Msp Init callback ID /
		214	HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /!< ADC Msp DeInit callback ID /
		215	} HAL_ADC_CallbackIDTypeDef;
		216
		217	/**
		218	* @brief HAL ADC Callback pointer definition
		219	*/
		220	typedef void (pADC_CallbackTypeDef)(ADC_HandleTypeDef hadc); /!< pointer to a ADC callback function /
		221
		222	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		223
		224	/**
		225	* @}
		226	*/
		227
		228
		229
		230	/* Exported constants --------------------------------------------------------*/
		231
		232	/** @defgroup ADC_Exported_Constants ADC Exported Constants
		233	* @{
		234	*/
		235
		236	/** @defgroup ADC_Error_Code ADC Error Code
		237	* @{
		238	*/
		239	#define HAL_ADC_ERROR_NONE 0x00U /!< No error /
		240	#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
		241	enable/disable, erroneous state */
		242	#define HAL_ADC_ERROR_OVR 0x02U /!< Overrun error /
		243	#define HAL_ADC_ERROR_DMA 0x04U /!< DMA transfer error /
		244
		245	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		246	#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /!< Invalid Callback error /
		247	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		248	/**
		249	* @}
		250	*/
		251
		252
		253	/** @defgroup ADC_Data_align ADC data alignment
		254	* @{
		255	*/
		256	#define ADC_DATAALIGN_RIGHT 0x00000000U
		257	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
		258	/**
		259	* @}
		260	*/
		261
		262	/** @defgroup ADC_Scan_mode ADC scan mode
		263	* @{
		264	*/
		265	/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
		266	/* compatibility with other STM32 devices having a sequencer with */
		267	/* additional options. */
		268	#define ADC_SCAN_DISABLE 0x00000000U
		269	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
		270	/**
		271	* @}
		272	*/
		273
		274	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
		275	* @{
		276	*/
		277	#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
		278	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
		279	/**
		280	* @}
		281	*/
		282
		283	/** @defgroup ADC_channels ADC channels
		284	* @{
		285	*/
		286	/* Note: Depending on devices, some channels may not be available on package */
		287	/* pins. Refer to device datasheet for channels availability. */
		288	#define ADC_CHANNEL_0 0x00000000U
		289	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
		290	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
		291	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		292	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
		293	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		294	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		295	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		296	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
		297	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_0))
		298	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 ))
		299	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		300	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 ))
		301	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		302	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		303	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		304	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
		305	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_0))
		306
		307	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
		308	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
		309	/**
		310	* @}
		311	*/
		312
		313	/** @defgroup ADC_sampling_times ADC sampling times
		314	* @{
		315	*/
		316	#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /!< Sampling time 1.5 ADC clock cycle /
		317	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /!< Sampling time 7.5 ADC clock cycles /
		318	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /!< Sampling time 13.5 ADC clock cycles /
		319	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 28.5 ADC clock cycles /
		320	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /!< Sampling time 41.5 ADC clock cycles /
		321	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 55.5 ADC clock cycles /
		322	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 )) /!< Sampling time 71.5 ADC clock cycles /
		323	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 239.5 ADC clock cycles /
		324	/**
		325	* @}
		326	*/
		327
		328	/** @defgroup ADC_regular_rank ADC rank into regular group
		329	* @{
		330	*/
		331	#define ADC_REGULAR_RANK_1 0x00000001U
		332	#define ADC_REGULAR_RANK_2 0x00000002U
		333	#define ADC_REGULAR_RANK_3 0x00000003U
		334	#define ADC_REGULAR_RANK_4 0x00000004U
		335	#define ADC_REGULAR_RANK_5 0x00000005U
		336	#define ADC_REGULAR_RANK_6 0x00000006U
		337	#define ADC_REGULAR_RANK_7 0x00000007U
		338	#define ADC_REGULAR_RANK_8 0x00000008U
		339	#define ADC_REGULAR_RANK_9 0x00000009U
		340	#define ADC_REGULAR_RANK_10 0x0000000AU
		341	#define ADC_REGULAR_RANK_11 0x0000000BU
		342	#define ADC_REGULAR_RANK_12 0x0000000CU
		343	#define ADC_REGULAR_RANK_13 0x0000000DU
		344	#define ADC_REGULAR_RANK_14 0x0000000EU
		345	#define ADC_REGULAR_RANK_15 0x0000000FU
		346	#define ADC_REGULAR_RANK_16 0x00000010U
		347	/**
		348	* @}
		349	*/
		350
		351	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
		352	* @{
		353	*/
		354	#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
		355	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
		356	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
		357	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		358	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
		359	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
		360	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		361	/**
		362	* @}
		363	*/
		364
		365	/** @defgroup ADC_conversion_group ADC conversion group
		366	* @{
		367	*/
		368	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
		369	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
		370	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
		371	/**
		372	* @}
		373	*/
		374
		375	/** @defgroup ADC_Event_type ADC Event type
		376	* @{
		377	*/
		378	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
		379
		380	#define ADC_AWD1_EVENT ADC_AWD_EVENT /!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs /
		381	/**
		382	* @}
		383	*/
		384
		385	/** @defgroup ADC_interrupts_definition ADC interrupts definition
		386	* @{
		387	*/
		388	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
		389	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
		390	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
		391	/**
		392	* @}
		393	*/
		394
		395	/** @defgroup ADC_flags_definition ADC flags definition
		396	* @{
		397	*/
		398	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
		399	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
		400	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
		401	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
		402	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
		403	/**
		404	* @}
		405	*/
		406
		407
		408	/**
		409	* @}
		410	*/
		411
		412	/* Private constants ---------------------------------------------------------*/
		413
		414	/** @addtogroup ADC_Private_Constants ADC Private Constants
		415	* @{
		416	*/
		417
		418	/** @defgroup ADC_conversion_cycles ADC conversion cycles
		419	* @{
		420	*/
		421	/* ADC conversion cycles (unit: ADC clock cycles) */
		422	/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
		423	/* resolution 12 bits) */
		424	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
		425	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
		426	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
		427	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
		428	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
		429	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
		430	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
		431	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
		432	/**
		433	* @}
		434	*/
		435
		436	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
		437	* @{
		438	*/
		439	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
		440	(ADC_SMPR2_SMP9_2 \| ADC_SMPR2_SMP8_2 \| ADC_SMPR2_SMP7_2 \| ADC_SMPR2_SMP6_2 \| \
		441	ADC_SMPR2_SMP5_2 \| ADC_SMPR2_SMP4_2 \| ADC_SMPR2_SMP3_2 \| ADC_SMPR2_SMP2_2 \| \
		442	ADC_SMPR2_SMP1_2 \| ADC_SMPR2_SMP0_2)
		443	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
		444	(ADC_SMPR1_SMP17_2 \| ADC_SMPR1_SMP16_2 \| ADC_SMPR1_SMP15_2 \| ADC_SMPR1_SMP14_2 \| \
		445	ADC_SMPR1_SMP13_2 \| ADC_SMPR1_SMP12_2 \| ADC_SMPR1_SMP11_2 \| ADC_SMPR1_SMP10_2 )
		446
		447	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
		448	(ADC_SMPR2_SMP9_1 \| ADC_SMPR2_SMP8_1 \| ADC_SMPR2_SMP7_1 \| ADC_SMPR2_SMP6_1 \| \
		449	ADC_SMPR2_SMP5_1 \| ADC_SMPR2_SMP4_1 \| ADC_SMPR2_SMP3_1 \| ADC_SMPR2_SMP2_1 \| \
		450	ADC_SMPR2_SMP1_1 \| ADC_SMPR2_SMP0_1)
		451	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
		452	(ADC_SMPR1_SMP17_1 \| ADC_SMPR1_SMP16_1 \| ADC_SMPR1_SMP15_1 \| ADC_SMPR1_SMP14_1 \| \
		453	ADC_SMPR1_SMP13_1 \| ADC_SMPR1_SMP12_1 \| ADC_SMPR1_SMP11_1 \| ADC_SMPR1_SMP10_1 )
		454
		455	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
		456	(ADC_SMPR2_SMP9_0 \| ADC_SMPR2_SMP8_0 \| ADC_SMPR2_SMP7_0 \| ADC_SMPR2_SMP6_0 \| \
		457	ADC_SMPR2_SMP5_0 \| ADC_SMPR2_SMP4_0 \| ADC_SMPR2_SMP3_0 \| ADC_SMPR2_SMP2_0 \| \
		458	ADC_SMPR2_SMP1_0 \| ADC_SMPR2_SMP0_0)
		459	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
		460	(ADC_SMPR1_SMP17_0 \| ADC_SMPR1_SMP16_0 \| ADC_SMPR1_SMP15_0 \| ADC_SMPR1_SMP14_0 \| \
		461	ADC_SMPR1_SMP13_0 \| ADC_SMPR1_SMP12_0 \| ADC_SMPR1_SMP11_0 \| ADC_SMPR1_SMP10_0 )
		462
		463	#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
		464	#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		465	#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		466	#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		467	#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
		468	#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		469	#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		470	#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		471
		472	#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
		473	#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		474	#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		475	#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		476	#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
		477	#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		478	#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		479	#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		480	/**
		481	* @}
		482	*/
		483
		484	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
		485	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD )
		486
		487	/**
		488	* @}
		489	*/
		490
		491
		492	/* Exported macro ------------------------------------------------------------*/
		493
		494	/** @defgroup ADC_Exported_Macros ADC Exported Macros
		495	* @{
		496	*/
		497	/* Macro for internal HAL driver usage, and possibly can be used into code of */
		498	/* final user. */
		499
		500	/**
		501	* @brief Enable the ADC peripheral
		502	* @note ADC enable requires a delay for ADC stabilization time
		503	* (refer to device datasheet, parameter tSTAB)
		504	* @note On STM32F1, if ADC is already enabled this macro trigs a conversion
		505	* SW start on regular group.
		506	* @param __HANDLE__: ADC handle
		507	* @retval None
		508	*/
		509	#define __HAL_ADC_ENABLE(__HANDLE__) \
		510	(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		511
		512	/**
		513	* @brief Disable the ADC peripheral
		514	* @param __HANDLE__: ADC handle
		515	* @retval None
		516	*/
		517	#define __HAL_ADC_DISABLE(__HANDLE__) \
		518	(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		519
		520	/** @brief Enable the ADC end of conversion interrupt.
		521	* @param __HANDLE__: ADC handle
		522	* @param __INTERRUPT__: ADC Interrupt
		523	* This parameter can be any combination of the following values:
		524	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		525	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		526	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		527	* @retval None
		528	*/
		529	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
		530	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		531
		532	/** @brief Disable the ADC end of conversion interrupt.
		533	* @param __HANDLE__: ADC handle
		534	* @param __INTERRUPT__: ADC Interrupt
		535	* This parameter can be any combination of the following values:
		536	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		537	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		538	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		539	* @retval None
		540	*/
		541	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
		542	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		543
		544	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
		545	* @param __HANDLE__: ADC handle
		546	* @param __INTERRUPT__: ADC interrupt source to check
		547	* This parameter can be any combination of the following values:
		548	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		549	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		550	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		551	* @retval None
		552	*/
		553	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
		554	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
		555
		556	/** @brief Get the selected ADC's flag status.
		557	* @param __HANDLE__: ADC handle
		558	* @param __FLAG__: ADC flag
		559	* This parameter can be any combination of the following values:
		560	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		561	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		562	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		563	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		564	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		565	* @retval None
		566	*/
		567	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
		568	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
		569
		570	/** @brief Clear the ADC's pending flags
		571	* @param __HANDLE__: ADC handle
		572	* @param __FLAG__: ADC flag
		573	* This parameter can be any combination of the following values:
		574	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		575	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		576	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		577	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		578	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		579	* @retval None
		580	*/
		581	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
		582	(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
		583
		584	/** @brief Reset ADC handle state
		585	* @param __HANDLE__: ADC handle
		586	* @retval None
		587	*/
		588	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		589	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
		590	do{ \
		591	(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
		592	(__HANDLE__)->MspInitCallback = NULL; \
		593	(__HANDLE__)->MspDeInitCallback = NULL; \
		594	} while(0)
		595	#else
		596	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
		597	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
		598	#endif
		599
		600	/**
		601	* @}
		602	*/
		603
		604	/* Private macro ------------------------------------------------------------*/
		605
		606	/** @defgroup ADC_Private_Macros ADC Private Macros
		607	* @{
		608	*/
		609	/* Macro reserved for internal HAL driver usage, not intended to be used in */
		610	/* code of final user. */
		611
		612	/**
		613	* @brief Verification of ADC state: enabled or disabled
		614	* @param __HANDLE__: ADC handle
		615	* @retval SET (ADC enabled) or RESET (ADC disabled)
		616	*/
		617	#define ADC_IS_ENABLE(__HANDLE__) \
		618	((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
		619	) ? SET : RESET)
		620
		621	/**
		622	* @brief Test if conversion trigger of regular group is software start
		623	* or external trigger.
		624	* @param __HANDLE__: ADC handle
		625	* @retval SET (software start) or RESET (external trigger)
		626	*/
		627	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
		628	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
		629
		630	/**
		631	* @brief Test if conversion trigger of injected group is software start
		632	* or external trigger.
		633	* @param __HANDLE__: ADC handle
		634	* @retval SET (software start) or RESET (external trigger)
		635	*/
		636	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
		637	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
		638
		639	/**
		640	* @brief Simultaneously clears and sets specific bits of the handle State
		641	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
		642	* the first parameter is the ADC handle State, the second parameter is the
		643	* bit field to clear, the third and last parameter is the bit field to set.
		644	* @retval None
		645	*/
		646	#define ADC_STATE_CLR_SET MODIFY_REG
		647
		648	/**
		649	* @brief Clear ADC error code (set it to error code: "no error")
		650	* @param __HANDLE__: ADC handle
		651	* @retval None
		652	*/
		653	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
		654	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
		655
		656	/**
		657	* @brief Set ADC number of conversions into regular channel sequence length.
		658	* @param _NbrOfConversion_: Regular channel sequence length
		659	* @retval None
		660	*/
		661	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
		662	(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
		663
		664	/**
		665	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
		666	* @param _SAMPLETIME_: Sample time parameter.
		667	* @param _CHANNELNB_: Channel number.
		668	* @retval None
		669	*/
		670	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
		671	((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
		672
		673	/**
		674	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
		675	* @param _SAMPLETIME_: Sample time parameter.
		676	* @param _CHANNELNB_: Channel number.
		677	* @retval None
		678	*/
		679	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
		680	((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
		681
		682	/**
		683	* @brief Set the selected regular channel rank for rank between 1 and 6.
		684	* @param _CHANNELNB_: Channel number.
		685	* @param _RANKNB_: Rank number.
		686	* @retval None
		687	*/
		688	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
		689	((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
		690
		691	/**
		692	* @brief Set the selected regular channel rank for rank between 7 and 12.
		693	* @param _CHANNELNB_: Channel number.
		694	* @param _RANKNB_: Rank number.
		695	* @retval None
		696	*/
		697	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
		698	((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
		699
		700	/**
		701	* @brief Set the selected regular channel rank for rank between 13 and 16.
		702	* @param _CHANNELNB_: Channel number.
		703	* @param _RANKNB_: Rank number.
		704	* @retval None
		705	*/
		706	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
		707	((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
		708
		709	/**
		710	* @brief Set the injected sequence length.
		711	* @param _JSQR_JL_: Sequence length.
		712	* @retval None
		713	*/
		714	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
		715	(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
		716
		717	/**
		718	* @brief Set the selected injected channel rank
		719	* Note: on STM32F1 devices, channel rank position in JSQR register
		720	* is depending on total number of ranks selected into
		721	* injected sequencer (ranks sequence starting from 4-JL)
		722	* @param _CHANNELNB_: Channel number.
		723	* @param _RANKNB_: Rank number.
		724	* @param _JSQR_JL_: Sequence length.
		725	* @retval None
		726	*/
		727	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
		728	((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
		729
		730	/**
		731	* @brief Enable ADC continuous conversion mode.
		732	* @param _CONTINUOUS_MODE_: Continuous mode.
		733	* @retval None
		734	*/
		735	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
		736	((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
		737
		738	/**
		739	* @brief Configures the number of discontinuous conversions for the regular group channels.
		740	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
		741	* @retval None
		742	*/
		743	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
		744	(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
		745
		746	/**
		747	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
		748	* @param _SCAN_MODE_: Scan conversion mode.
		749	* @retval None
		750	*/
		751	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
		752	/* is equivalent to ADC_SCAN_ENABLE. */
		753	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
		754	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
		755	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
		756	)
		757
		758	/**
		759	* @brief Get the maximum ADC conversion cycles on all channels.
		760	* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
		761	* Approximation of sampling time within 4 ranges, returns the highest value:
		762	* below 7.5 cycles {1.5 cycle; 7.5 cycles},
		763	* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
		764	* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
		765	* equal to 239.5 cycles
		766	* Unit: ADC clock cycles
		767	* @param __HANDLE__: ADC handle
		768	* @retval ADC conversion cycles on all channels
		769	*/
		770	#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
		771	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
		772	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
		773	\
		774	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		775	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
		776	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
		777	: \
		778	((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		779	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \|\| \
		780	((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
		781	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
		782	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
		783	)
		784
		785	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
		786	((ALIGN) == ADC_DATAALIGN_LEFT) )
		787
		788	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
		789	((SCAN_MODE) == ADC_SCAN_ENABLE) )
		790
		791	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
		792	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
		793
		794	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
		795	((CHANNEL) == ADC_CHANNEL_1) \|\| \
		796	((CHANNEL) == ADC_CHANNEL_2) \|\| \
		797	((CHANNEL) == ADC_CHANNEL_3) \|\| \
		798	((CHANNEL) == ADC_CHANNEL_4) \|\| \
		799	((CHANNEL) == ADC_CHANNEL_5) \|\| \
		800	((CHANNEL) == ADC_CHANNEL_6) \|\| \
		801	((CHANNEL) == ADC_CHANNEL_7) \|\| \
		802	((CHANNEL) == ADC_CHANNEL_8) \|\| \
		803	((CHANNEL) == ADC_CHANNEL_9) \|\| \
		804	((CHANNEL) == ADC_CHANNEL_10) \|\| \
		805	((CHANNEL) == ADC_CHANNEL_11) \|\| \
		806	((CHANNEL) == ADC_CHANNEL_12) \|\| \
		807	((CHANNEL) == ADC_CHANNEL_13) \|\| \
		808	((CHANNEL) == ADC_CHANNEL_14) \|\| \
		809	((CHANNEL) == ADC_CHANNEL_15) \|\| \
		810	((CHANNEL) == ADC_CHANNEL_16) \|\| \
		811	((CHANNEL) == ADC_CHANNEL_17) )
		812
		813	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
		814	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
		815	((TIME) == ADC_SAMPLETIME_13CYCLES_5) \|\| \
		816	((TIME) == ADC_SAMPLETIME_28CYCLES_5) \|\| \
		817	((TIME) == ADC_SAMPLETIME_41CYCLES_5) \|\| \
		818	((TIME) == ADC_SAMPLETIME_55CYCLES_5) \|\| \
		819	((TIME) == ADC_SAMPLETIME_71CYCLES_5) \|\| \
		820	((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
		821
		822	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
		823	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
		824	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
		825	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
		826	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
		827	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
		828	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
		829	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
		830	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
		831	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
		832	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
		833	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
		834	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
		835	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
		836	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
		837	((CHANNEL) == ADC_REGULAR_RANK_16) )
		838
		839	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
		840	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
		841	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
		842	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
		843	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
		844	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
		845	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
		846
		847	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
		848	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
		849	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
		850
		851	#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
		852
		853
		854	/** @defgroup ADC_range_verification ADC range verification
		855	* For a unique ADC resolution: 12 bits
		856	* @{
		857	*/
		858	#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
		859	/**
		860	* @}
		861	*/
		862
		863	/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
		864	* @{
		865	*/
		866	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
		867	/**
		868	* @}
		869	*/
		870
		871	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
		872	* @{
		873	*/
		874	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
		875	/**
		876	* @}
		877	*/
		878
		879	/**
		880	* @}
		881	*/
		882
		883	/* Include ADC HAL Extension module */
		884	#include "stm32f1xx_hal_adc_ex.h"
		885
		886	/* Exported functions --------------------------------------------------------*/
		887	/** @addtogroup ADC_Exported_Functions
		888	* @{
		889	*/
		890
		891	/** @addtogroup ADC_Exported_Functions_Group1
		892	* @{
		893	*/
		894
		895
		896	/* Initialization and de-initialization functions **********************************/
		897	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
		898	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
		899	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
		900	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
		901
		902	#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
		903	/* Callbacks Register/UnRegister functions ***********************************/
		904	HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
		905	HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
		906	#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
		907
		908	/**
		909	* @}
		910	*/
		911
		912	/* IO operation functions *****************************************************/
		913
		914	/** @addtogroup ADC_Exported_Functions_Group2
		915	* @{
		916	*/
		917
		918
		919	/* Blocking mode: Polling */
		920	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
		921	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
		922	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
		923	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
		924
		925	/* Non-blocking mode: Interruption */
		926	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
		927	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
		928
		929	/* Non-blocking mode: DMA */
		930	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
		931	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
		932
		933	/* ADC retrieve conversion value intended to be used with polling or interruption */
		934	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
		935
		936	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
		937	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
		938	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
		939	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
		940	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
		941	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
		942	/**
		943	* @}
		944	*/
		945
		946
		947	/* Peripheral Control functions ***********************************************/
		948	/** @addtogroup ADC_Exported_Functions_Group3
		949	* @{
		950	*/
		951	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
		952	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
		953	/**
		954	* @}
		955	*/
		956
		957
		958	/* Peripheral State functions *************************************************/
		959	/** @addtogroup ADC_Exported_Functions_Group4
		960	* @{
		961	*/
		962	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
		963	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
		964	/**
		965	* @}
		966	*/
		967
		968
		969	/**
		970	* @}
		971	*/
		972
		973
		974	/* Internal HAL driver functions **********************************************/
		975	/** @addtogroup ADC_Private_Functions
		976	* @{
		977	*/
		978	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
		979	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
		980	void ADC_StabilizationTime(uint32_t DelayUs);
		981	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
		982	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
		983	void ADC_DMAError(DMA_HandleTypeDef *hdma);
		984	/**
		985	* @}
		986	*/
		987
		988
		989	/**
		990	* @}
		991	*/
		992
		993	/**
		994	* @}
		995	*/
		996
		997	#ifdef __cplusplus
		998	}
		999	#endif
		1000
		1001
		1002	#endif /* __STM32F1xx_HAL_ADC_H */
		1003
		1004	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h – Rev 2