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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_adc.h
		4	* @author MCD Application Team
		5	* @brief Header file containing functions prototypes of ADC HAL library.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
		10	*
		11	* Redistribution and use in source and binary forms, with or without modification,
		12	* are permitted provided that the following conditions are met:
		13	* 1. Redistributions of source code must retain the above copyright notice,
		14	* this list of conditions and the following disclaimer.
		15	* 2. Redistributions in binary form must reproduce the above copyright notice,
		16	* this list of conditions and the following disclaimer in the documentation
		17	* and/or other materials provided with the distribution.
		18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		19	* may be used to endorse or promote products derived from this software
		20	* without specific prior written permission.
		21	*
		22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		32	*
		33	******************************************************************************
		34	*/
		35
		36	/* Define to prevent recursive inclusion -------------------------------------*/
		37	#ifndef __STM32F1xx_HAL_ADC_H
		38	#define __STM32F1xx_HAL_ADC_H
		39
		40	#ifdef __cplusplus
		41	extern "C" {
		42	#endif
		43
		44	/* Includes ------------------------------------------------------------------*/
		45	#include "stm32f1xx_hal_def.h"
		46	/** @addtogroup STM32F1xx_HAL_Driver
		47	* @{
		48	*/
		49
		50	/** @addtogroup ADC
		51	* @{
		52	*/
		53
		54	/* Exported types ------------------------------------------------------------*/
		55	/** @defgroup ADC_Exported_Types ADC Exported Types
		56	* @{
		57	*/
		58
		59	/**
		60	* @brief Structure definition of ADC and regular group initialization
		61	* @note Parameters of this structure are shared within 2 scopes:
		62	* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
		63	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
		64	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
		65	* ADC can be either disabled or enabled without conversion on going on regular group.
		66	*/
		67	typedef struct
		68	{
		69	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
		70	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
		71	This parameter can be a value of @ref ADC_Data_align */
		72	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
		73	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
		74	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
		75	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
		76	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
		77	Scan direction is upward: from rank1 to rank 'n'.
		78	This parameter can be a value of @ref ADC_Scan_mode
		79	Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
		80	or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
		81	the last conversion of the sequence. All previous conversions would be overwritten by the last one.
		82	Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
		83	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
		84	after the selected trigger occurred (software start or external trigger).
		85	This parameter can be set to ENABLE or DISABLE. */
		86	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
		87	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
		88	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
		89	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
		90	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
		91	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
		92	This parameter can be set to ENABLE or DISABLE. */
		93	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
		94	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
		95	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
		96	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
		97	If set to ADC_SOFTWARE_START, external triggers are disabled.
		98	If set to external trigger source, triggering is on event rising edge.
		99	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
		100	}ADC_InitTypeDef;
		101
		102	/**
		103	* @brief Structure definition of ADC channel for regular group
		104	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
		105	* ADC can be either disabled or enabled without conversion on going on regular group.
		106	*/
		107	typedef struct
		108	{
		109	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
		110	This parameter can be a value of @ref ADC_channels
		111	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
		112	Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
		113	Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
		114	It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
		115	Refer to errata sheet of these devices for more details. */
		116	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
		117	This parameter can be a value of @ref ADC_regular_rank
		118	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
		119	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
		120	Unit: ADC clock cycles
		121	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
		122	This parameter can be a value of @ref ADC_sampling_times
		123	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
		124	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
		125	Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
		126	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
		127	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
		128	}ADC_ChannelConfTypeDef;
		129
		130	/**
		131	* @brief ADC Configuration analog watchdog definition
		132	* @note The setting of these parameters with function is conditioned to ADC state.
		133	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
		134	*/
		135	typedef struct
		136	{
		137	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
		138	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
		139	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
		140	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
		141	This parameter can be a value of @ref ADC_channels. */
		142	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
		143	This parameter can be set to ENABLE or DISABLE */
		144	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		145	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		146	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		147	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		148	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
		149	}ADC_AnalogWDGConfTypeDef;
		150
		151	/**
		152	* @brief HAL ADC state machine: ADC states definition (bitfields)
		153	*/
		154	/* States of ADC global scope */
		155	#define HAL_ADC_STATE_RESET 0x00000000U /!< ADC not yet initialized or disabled /
		156	#define HAL_ADC_STATE_READY 0x00000001U /!< ADC peripheral ready for use /
		157	#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /!< ADC is busy to internal process (initialization, calibration) /
		158	#define HAL_ADC_STATE_TIMEOUT 0x00000004U /!< TimeOut occurrence /
		159
		160	/* States of ADC errors */
		161	#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /!< Internal error occurrence /
		162	#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /!< Configuration error occurrence /
		163	#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /!< DMA error occurrence /
		164
		165	/* States of ADC group regular */
		166	#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
		167	external trigger, low power auto power-on, multimode ADC master control) */
		168	#define HAL_ADC_STATE_REG_EOC 0x00000200U /!< Conversion data available on group regular /
		169	#define HAL_ADC_STATE_REG_OVR 0x00000400U /!< Not available on STM32F1 device: Overrun occurrence /
		170	#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /!< Not available on STM32F1 device: End Of Sampling flag raised /
		171
		172	/* States of ADC group injected */
		173	#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
		174	external trigger, low power auto power-on, multimode ADC master control) */
		175	#define HAL_ADC_STATE_INJ_EOC 0x00002000U /!< Conversion data available on group injected /
		176	#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /!< Not available on STM32F1 device: Injected queue overflow occurrence /
		177
		178	/* States of ADC analog watchdogs */
		179	#define HAL_ADC_STATE_AWD1 0x00010000U /!< Out-of-window occurrence of analog watchdog 1 /
		180	#define HAL_ADC_STATE_AWD2 0x00020000U /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 /
		181	#define HAL_ADC_STATE_AWD3 0x00040000U /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 /
		182
		183	/* States of ADC multi-mode */
		184	#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /!< ADC in multimode slave state, controlled by another ADC master ( /
		185
		186
		187	/**
		188	* @brief ADC handle Structure definition
		189	*/
		190	typedef struct
		191	{
		192	ADC_TypeDef Instance; /!< Register base address */
		193
		194	ADC_InitTypeDef Init; /!< ADC required parameters /
		195
		196	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
		197
		198	HAL_LockTypeDef Lock; /!< ADC locking object /
		199
		200	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
		201
		202	__IO uint32_t ErrorCode; /!< ADC Error code /
		203	}ADC_HandleTypeDef;
		204	/**
		205	* @}
		206	*/
		207
		208
		209
		210	/* Exported constants --------------------------------------------------------*/
		211
		212	/** @defgroup ADC_Exported_Constants ADC Exported Constants
		213	* @{
		214	*/
		215
		216	/** @defgroup ADC_Error_Code ADC Error Code
		217	* @{
		218	*/
		219	#define HAL_ADC_ERROR_NONE 0x00U /!< No error /
		220	#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
		221	enable/disable, erroneous state */
		222	#define HAL_ADC_ERROR_OVR 0x02U /!< Overrun error /
		223	#define HAL_ADC_ERROR_DMA 0x04U /!< DMA transfer error /
		224
		225	/**
		226	* @}
		227	*/
		228
		229
		230	/** @defgroup ADC_Data_align ADC data alignment
		231	* @{
		232	*/
		233	#define ADC_DATAALIGN_RIGHT 0x00000000U
		234	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
		235	/**
		236	* @}
		237	*/
		238
		239	/** @defgroup ADC_Scan_mode ADC scan mode
		240	* @{
		241	*/
		242	/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
		243	/* compatibility with other STM32 devices having a sequencer with */
		244	/* additional options. */
		245	#define ADC_SCAN_DISABLE 0x00000000U
		246	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
		247	/**
		248	* @}
		249	*/
		250
		251	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
		252	* @{
		253	*/
		254	#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
		255	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
		256	/**
		257	* @}
		258	*/
		259
		260	/** @defgroup ADC_channels ADC channels
		261	* @{
		262	*/
		263	/* Note: Depending on devices, some channels may not be available on package */
		264	/* pins. Refer to device datasheet for channels availability. */
		265	#define ADC_CHANNEL_0 0x00000000U
		266	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
		267	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
		268	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		269	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
		270	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		271	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		272	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		273	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
		274	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_0))
		275	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 ))
		276	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		277	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 ))
		278	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		279	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		280	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		281	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
		282	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_0))
		283
		284	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
		285	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
		286	/**
		287	* @}
		288	*/
		289
		290	/** @defgroup ADC_sampling_times ADC sampling times
		291	* @{
		292	*/
		293	#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /!< Sampling time 1.5 ADC clock cycle /
		294	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /!< Sampling time 7.5 ADC clock cycles /
		295	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /!< Sampling time 13.5 ADC clock cycles /
		296	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 28.5 ADC clock cycles /
		297	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /!< Sampling time 41.5 ADC clock cycles /
		298	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 55.5 ADC clock cycles /
		299	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 )) /!< Sampling time 71.5 ADC clock cycles /
		300	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 239.5 ADC clock cycles /
		301	/**
		302	* @}
		303	*/
		304
		305	/** @defgroup ADC_regular_rank ADC rank into regular group
		306	* @{
		307	*/
		308	#define ADC_REGULAR_RANK_1 0x00000001U
		309	#define ADC_REGULAR_RANK_2 0x00000002U
		310	#define ADC_REGULAR_RANK_3 0x00000003U
		311	#define ADC_REGULAR_RANK_4 0x00000004U
		312	#define ADC_REGULAR_RANK_5 0x00000005U
		313	#define ADC_REGULAR_RANK_6 0x00000006U
		314	#define ADC_REGULAR_RANK_7 0x00000007U
		315	#define ADC_REGULAR_RANK_8 0x00000008U
		316	#define ADC_REGULAR_RANK_9 0x00000009U
		317	#define ADC_REGULAR_RANK_10 0x0000000AU
		318	#define ADC_REGULAR_RANK_11 0x0000000BU
		319	#define ADC_REGULAR_RANK_12 0x0000000CU
		320	#define ADC_REGULAR_RANK_13 0x0000000DU
		321	#define ADC_REGULAR_RANK_14 0x0000000EU
		322	#define ADC_REGULAR_RANK_15 0x0000000FU
		323	#define ADC_REGULAR_RANK_16 0x00000010U
		324	/**
		325	* @}
		326	*/
		327
		328	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
		329	* @{
		330	*/
		331	#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
		332	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
		333	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
		334	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		335	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
		336	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
		337	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		338	/**
		339	* @}
		340	*/
		341
		342	/** @defgroup ADC_conversion_group ADC conversion group
		343	* @{
		344	*/
		345	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
		346	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
		347	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
		348	/**
		349	* @}
		350	*/
		351
		352	/** @defgroup ADC_Event_type ADC Event type
		353	* @{
		354	*/
		355	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
		356
		357	#define ADC_AWD1_EVENT ADC_AWD_EVENT /!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs /
		358	/**
		359	* @}
		360	*/
		361
		362	/** @defgroup ADC_interrupts_definition ADC interrupts definition
		363	* @{
		364	*/
		365	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
		366	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
		367	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
		368	/**
		369	* @}
		370	*/
		371
		372	/** @defgroup ADC_flags_definition ADC flags definition
		373	* @{
		374	*/
		375	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
		376	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
		377	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
		378	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
		379	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
		380	/**
		381	* @}
		382	*/
		383
		384
		385	/**
		386	* @}
		387	*/
		388
		389	/* Private constants ---------------------------------------------------------*/
		390
		391	/** @addtogroup ADC_Private_Constants ADC Private Constants
		392	* @{
		393	*/
		394
		395	/** @defgroup ADC_conversion_cycles ADC conversion cycles
		396	* @{
		397	*/
		398	/* ADC conversion cycles (unit: ADC clock cycles) */
		399	/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
		400	/* resolution 12 bits) */
		401	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
		402	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
		403	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
		404	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
		405	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
		406	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
		407	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
		408	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
		409	/**
		410	* @}
		411	*/
		412
		413	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
		414	* @{
		415	*/
		416	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
		417	(ADC_SMPR2_SMP9_2 \| ADC_SMPR2_SMP8_2 \| ADC_SMPR2_SMP7_2 \| ADC_SMPR2_SMP6_2 \| \
		418	ADC_SMPR2_SMP5_2 \| ADC_SMPR2_SMP4_2 \| ADC_SMPR2_SMP3_2 \| ADC_SMPR2_SMP2_2 \| \
		419	ADC_SMPR2_SMP1_2 \| ADC_SMPR2_SMP0_2)
		420	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
		421	(ADC_SMPR1_SMP17_2 \| ADC_SMPR1_SMP16_2 \| ADC_SMPR1_SMP15_2 \| ADC_SMPR1_SMP14_2 \| \
		422	ADC_SMPR1_SMP13_2 \| ADC_SMPR1_SMP12_2 \| ADC_SMPR1_SMP11_2 \| ADC_SMPR1_SMP10_2 )
		423
		424	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
		425	(ADC_SMPR2_SMP9_1 \| ADC_SMPR2_SMP8_1 \| ADC_SMPR2_SMP7_1 \| ADC_SMPR2_SMP6_1 \| \
		426	ADC_SMPR2_SMP5_1 \| ADC_SMPR2_SMP4_1 \| ADC_SMPR2_SMP3_1 \| ADC_SMPR2_SMP2_1 \| \
		427	ADC_SMPR2_SMP1_1 \| ADC_SMPR2_SMP0_1)
		428	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
		429	(ADC_SMPR1_SMP17_1 \| ADC_SMPR1_SMP16_1 \| ADC_SMPR1_SMP15_1 \| ADC_SMPR1_SMP14_1 \| \
		430	ADC_SMPR1_SMP13_1 \| ADC_SMPR1_SMP12_1 \| ADC_SMPR1_SMP11_1 \| ADC_SMPR1_SMP10_1 )
		431
		432	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
		433	(ADC_SMPR2_SMP9_0 \| ADC_SMPR2_SMP8_0 \| ADC_SMPR2_SMP7_0 \| ADC_SMPR2_SMP6_0 \| \
		434	ADC_SMPR2_SMP5_0 \| ADC_SMPR2_SMP4_0 \| ADC_SMPR2_SMP3_0 \| ADC_SMPR2_SMP2_0 \| \
		435	ADC_SMPR2_SMP1_0 \| ADC_SMPR2_SMP0_0)
		436	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
		437	(ADC_SMPR1_SMP17_0 \| ADC_SMPR1_SMP16_0 \| ADC_SMPR1_SMP15_0 \| ADC_SMPR1_SMP14_0 \| \
		438	ADC_SMPR1_SMP13_0 \| ADC_SMPR1_SMP12_0 \| ADC_SMPR1_SMP11_0 \| ADC_SMPR1_SMP10_0 )
		439
		440	#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
		441	#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		442	#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		443	#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		444	#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
		445	#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		446	#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		447	#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		448
		449	#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
		450	#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		451	#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		452	#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		453	#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
		454	#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		455	#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		456	#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		457	/**
		458	* @}
		459	*/
		460
		461	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
		462	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD )
		463
		464	/**
		465	* @}
		466	*/
		467
		468
		469	/* Exported macro ------------------------------------------------------------*/
		470
		471	/** @defgroup ADC_Exported_Macros ADC Exported Macros
		472	* @{
		473	*/
		474	/* Macro for internal HAL driver usage, and possibly can be used into code of */
		475	/* final user. */
		476
		477	/**
		478	* @brief Enable the ADC peripheral
		479	* @note ADC enable requires a delay for ADC stabilization time
		480	* (refer to device datasheet, parameter tSTAB)
		481	* @note On STM32F1, if ADC is already enabled this macro trigs a conversion
		482	* SW start on regular group.
		483	* @param __HANDLE__: ADC handle
		484	* @retval None
		485	*/
		486	#define __HAL_ADC_ENABLE(__HANDLE__) \
		487	(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		488
		489	/**
		490	* @brief Disable the ADC peripheral
		491	* @param __HANDLE__: ADC handle
		492	* @retval None
		493	*/
		494	#define __HAL_ADC_DISABLE(__HANDLE__) \
		495	(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		496
		497	/** @brief Enable the ADC end of conversion interrupt.
		498	* @param __HANDLE__: ADC handle
		499	* @param __INTERRUPT__: ADC Interrupt
		500	* This parameter can be any combination of the following values:
		501	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		502	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		503	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		504	* @retval None
		505	*/
		506	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
		507	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		508
		509	/** @brief Disable the ADC end of conversion interrupt.
		510	* @param __HANDLE__: ADC handle
		511	* @param __INTERRUPT__: ADC Interrupt
		512	* This parameter can be any combination of the following values:
		513	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		514	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		515	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		516	* @retval None
		517	*/
		518	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
		519	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		520
		521	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
		522	* @param __HANDLE__: ADC handle
		523	* @param __INTERRUPT__: ADC interrupt source to check
		524	* This parameter can be any combination of the following values:
		525	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		526	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		527	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		528	* @retval None
		529	*/
		530	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
		531	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
		532
		533	/** @brief Get the selected ADC's flag status.
		534	* @param __HANDLE__: ADC handle
		535	* @param __FLAG__: ADC flag
		536	* This parameter can be any combination of the following values:
		537	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		538	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		539	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		540	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		541	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		542	* @retval None
		543	*/
		544	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
		545	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
		546
		547	/** @brief Clear the ADC's pending flags
		548	* @param __HANDLE__: ADC handle
		549	* @param __FLAG__: ADC flag
		550	* This parameter can be any combination of the following values:
		551	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		552	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		553	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		554	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		555	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		556	* @retval None
		557	*/
		558	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
		559	(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
		560
		561	/** @brief Reset ADC handle state
		562	* @param __HANDLE__: ADC handle
		563	* @retval None
		564	*/
		565	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
		566	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
		567
		568	/**
		569	* @}
		570	*/
		571
		572	/* Private macro ------------------------------------------------------------*/
		573
		574	/** @defgroup ADC_Private_Macros ADC Private Macros
		575	* @{
		576	*/
		577	/* Macro reserved for internal HAL driver usage, not intended to be used in */
		578	/* code of final user. */
		579
		580	/**
		581	* @brief Verification of ADC state: enabled or disabled
		582	* @param __HANDLE__: ADC handle
		583	* @retval SET (ADC enabled) or RESET (ADC disabled)
		584	*/
		585	#define ADC_IS_ENABLE(__HANDLE__) \
		586	((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
		587	) ? SET : RESET)
		588
		589	/**
		590	* @brief Test if conversion trigger of regular group is software start
		591	* or external trigger.
		592	* @param __HANDLE__: ADC handle
		593	* @retval SET (software start) or RESET (external trigger)
		594	*/
		595	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
		596	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
		597
		598	/**
		599	* @brief Test if conversion trigger of injected group is software start
		600	* or external trigger.
		601	* @param __HANDLE__: ADC handle
		602	* @retval SET (software start) or RESET (external trigger)
		603	*/
		604	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
		605	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
		606
		607	/**
		608	* @brief Simultaneously clears and sets specific bits of the handle State
		609	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
		610	* the first parameter is the ADC handle State, the second parameter is the
		611	* bit field to clear, the third and last parameter is the bit field to set.
		612	* @retval None
		613	*/
		614	#define ADC_STATE_CLR_SET MODIFY_REG
		615
		616	/**
		617	* @brief Clear ADC error code (set it to error code: "no error")
		618	* @param __HANDLE__: ADC handle
		619	* @retval None
		620	*/
		621	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
		622	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
		623
		624	/**
		625	* @brief Set ADC number of conversions into regular channel sequence length.
		626	* @param _NbrOfConversion_: Regular channel sequence length
		627	* @retval None
		628	*/
		629	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
		630	(((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
		631
		632	/**
		633	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
		634	* @param _SAMPLETIME_: Sample time parameter.
		635	* @param _CHANNELNB_: Channel number.
		636	* @retval None
		637	*/
		638	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
		639	((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
		640
		641	/**
		642	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
		643	* @param _SAMPLETIME_: Sample time parameter.
		644	* @param _CHANNELNB_: Channel number.
		645	* @retval None
		646	*/
		647	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
		648	((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
		649
		650	/**
		651	* @brief Set the selected regular channel rank for rank between 1 and 6.
		652	* @param _CHANNELNB_: Channel number.
		653	* @param _RANKNB_: Rank number.
		654	* @retval None
		655	*/
		656	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
		657	((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
		658
		659	/**
		660	* @brief Set the selected regular channel rank for rank between 7 and 12.
		661	* @param _CHANNELNB_: Channel number.
		662	* @param _RANKNB_: Rank number.
		663	* @retval None
		664	*/
		665	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
		666	((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
		667
		668	/**
		669	* @brief Set the selected regular channel rank for rank between 13 and 16.
		670	* @param _CHANNELNB_: Channel number.
		671	* @param _RANKNB_: Rank number.
		672	* @retval None
		673	*/
		674	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
		675	((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
		676
		677	/**
		678	* @brief Set the injected sequence length.
		679	* @param _JSQR_JL_: Sequence length.
		680	* @retval None
		681	*/
		682	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
		683	(((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
		684
		685	/**
		686	* @brief Set the selected injected channel rank
		687	* Note: on STM32F1 devices, channel rank position in JSQR register
		688	* is depending on total number of ranks selected into
		689	* injected sequencer (ranks sequence starting from 4-JL)
		690	* @param _CHANNELNB_: Channel number.
		691	* @param _RANKNB_: Rank number.
		692	* @param _JSQR_JL_: Sequence length.
		693	* @retval None
		694	*/
		695	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
		696	((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
		697
		698	/**
		699	* @brief Enable ADC continuous conversion mode.
		700	* @param _CONTINUOUS_MODE_: Continuous mode.
		701	* @retval None
		702	*/
		703	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
		704	((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
		705
		706	/**
		707	* @brief Configures the number of discontinuous conversions for the regular group channels.
		708	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
		709	* @retval None
		710	*/
		711	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
		712	(((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
		713
		714	/**
		715	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
		716	* @param _SCAN_MODE_: Scan conversion mode.
		717	* @retval None
		718	*/
		719	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
		720	/* is equivalent to ADC_SCAN_ENABLE. */
		721	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
		722	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
		723	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
		724	)
		725
		726	/**
		727	* @brief Get the maximum ADC conversion cycles on all channels.
		728	* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
		729	* Approximation of sampling time within 4 ranges, returns the highest value:
		730	* below 7.5 cycles {1.5 cycle; 7.5 cycles},
		731	* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
		732	* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
		733	* equal to 239.5 cycles
		734	* Unit: ADC clock cycles
		735	* @param __HANDLE__: ADC handle
		736	* @retval ADC conversion cycles on all channels
		737	*/
		738	#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
		739	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
		740	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
		741	\
		742	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		743	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
		744	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
		745	: \
		746	((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		747	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \|\| \
		748	((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
		749	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
		750	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
		751	)
		752
		753	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
		754	((ALIGN) == ADC_DATAALIGN_LEFT) )
		755
		756	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
		757	((SCAN_MODE) == ADC_SCAN_ENABLE) )
		758
		759	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
		760	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
		761
		762	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
		763	((CHANNEL) == ADC_CHANNEL_1) \|\| \
		764	((CHANNEL) == ADC_CHANNEL_2) \|\| \
		765	((CHANNEL) == ADC_CHANNEL_3) \|\| \
		766	((CHANNEL) == ADC_CHANNEL_4) \|\| \
		767	((CHANNEL) == ADC_CHANNEL_5) \|\| \
		768	((CHANNEL) == ADC_CHANNEL_6) \|\| \
		769	((CHANNEL) == ADC_CHANNEL_7) \|\| \
		770	((CHANNEL) == ADC_CHANNEL_8) \|\| \
		771	((CHANNEL) == ADC_CHANNEL_9) \|\| \
		772	((CHANNEL) == ADC_CHANNEL_10) \|\| \
		773	((CHANNEL) == ADC_CHANNEL_11) \|\| \
		774	((CHANNEL) == ADC_CHANNEL_12) \|\| \
		775	((CHANNEL) == ADC_CHANNEL_13) \|\| \
		776	((CHANNEL) == ADC_CHANNEL_14) \|\| \
		777	((CHANNEL) == ADC_CHANNEL_15) \|\| \
		778	((CHANNEL) == ADC_CHANNEL_16) \|\| \
		779	((CHANNEL) == ADC_CHANNEL_17) )
		780
		781	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
		782	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
		783	((TIME) == ADC_SAMPLETIME_13CYCLES_5) \|\| \
		784	((TIME) == ADC_SAMPLETIME_28CYCLES_5) \|\| \
		785	((TIME) == ADC_SAMPLETIME_41CYCLES_5) \|\| \
		786	((TIME) == ADC_SAMPLETIME_55CYCLES_5) \|\| \
		787	((TIME) == ADC_SAMPLETIME_71CYCLES_5) \|\| \
		788	((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
		789
		790	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
		791	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
		792	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
		793	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
		794	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
		795	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
		796	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
		797	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
		798	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
		799	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
		800	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
		801	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
		802	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
		803	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
		804	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
		805	((CHANNEL) == ADC_REGULAR_RANK_16) )
		806
		807	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
		808	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
		809	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
		810	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
		811	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
		812	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
		813	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
		814
		815	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
		816	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
		817	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
		818
		819	#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
		820
		821
		822	/** @defgroup ADC_range_verification ADC range verification
		823	* For a unique ADC resolution: 12 bits
		824	* @{
		825	*/
		826	#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
		827	/**
		828	* @}
		829	*/
		830
		831	/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
		832	* @{
		833	*/
		834	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
		835	/**
		836	* @}
		837	*/
		838
		839	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
		840	* @{
		841	*/
		842	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
		843	/**
		844	* @}
		845	*/
		846
		847	/**
		848	* @}
		849	*/
		850
		851	/* Include ADC HAL Extension module */
		852	#include "stm32f1xx_hal_adc_ex.h"
		853
		854	/* Exported functions --------------------------------------------------------*/
		855	/** @addtogroup ADC_Exported_Functions
		856	* @{
		857	*/
		858
		859	/** @addtogroup ADC_Exported_Functions_Group1
		860	* @{
		861	*/
		862
		863
		864	/* Initialization and de-initialization functions **********************************/
		865	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
		866	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
		867	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
		868	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
		869	/**
		870	* @}
		871	*/
		872
		873	/* IO operation functions *****************************************************/
		874
		875	/** @addtogroup ADC_Exported_Functions_Group2
		876	* @{
		877	*/
		878
		879
		880	/* Blocking mode: Polling */
		881	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
		882	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
		883	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
		884	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
		885
		886	/* Non-blocking mode: Interruption */
		887	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
		888	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
		889
		890	/* Non-blocking mode: DMA */
		891	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
		892	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
		893
		894	/* ADC retrieve conversion value intended to be used with polling or interruption */
		895	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
		896
		897	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
		898	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
		899	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
		900	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
		901	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
		902	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
		903	/**
		904	* @}
		905	*/
		906
		907
		908	/* Peripheral Control functions ***********************************************/
		909	/** @addtogroup ADC_Exported_Functions_Group3
		910	* @{
		911	*/
		912	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
		913	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
		914	/**
		915	* @}
		916	*/
		917
		918
		919	/* Peripheral State functions *************************************************/
		920	/** @addtogroup ADC_Exported_Functions_Group4
		921	* @{
		922	*/
		923	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
		924	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
		925	/**
		926	* @}
		927	*/
		928
		929
		930	/**
		931	* @}
		932	*/
		933
		934
		935	/* Internal HAL driver functions **********************************************/
		936	/** @addtogroup ADC_Private_Functions
		937	* @{
		938	*/
		939	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
		940	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
		941	void ADC_StabilizationTime(uint32_t DelayUs);
		942	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
		943	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
		944	void ADC_DMAError(DMA_HandleTypeDef *hdma);
		945	/**
		946	* @}
		947	*/
		948
		949
		950	/**
		951	* @}
		952	*/
		953
		954	/**
		955	* @}
		956	*/
		957
		958	#ifdef __cplusplus
		959	}
		960	#endif
		961
		962
		963	#endif /* __STM32F1xx_HAL_ADC_H */
		964
		965	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h – Rev 2