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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f1xx_hal_adc.h
		4	* @author MCD Application Team
5	mjames	5	* @version V1.0.4
		6	* @date 29-April-2016
2	mjames	7	* @brief Header file containing functions prototypes of ADC HAL library.
		8	******************************************************************************
		9	* @attention
		10	*
5	mjames	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2	mjames	12	*
		13	* Redistribution and use in source and binary forms, with or without modification,
		14	* are permitted provided that the following conditions are met:
		15	* 1. Redistributions of source code must retain the above copyright notice,
		16	* this list of conditions and the following disclaimer.
		17	* 2. Redistributions in binary form must reproduce the above copyright notice,
		18	* this list of conditions and the following disclaimer in the documentation
		19	* and/or other materials provided with the distribution.
		20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		21	* may be used to endorse or promote products derived from this software
		22	* without specific prior written permission.
		23	*
		24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		34	*
		35	******************************************************************************
		36	*/
		37
		38	/* Define to prevent recursive inclusion -------------------------------------*/
		39	#ifndef __STM32F1xx_HAL_ADC_H
		40	#define __STM32F1xx_HAL_ADC_H
		41
		42	#ifdef __cplusplus
		43	extern "C" {
		44	#endif
		45
		46	/* Includes ------------------------------------------------------------------*/
		47	#include "stm32f1xx_hal_def.h"
		48	/** @addtogroup STM32F1xx_HAL_Driver
		49	* @{
		50	*/
		51
		52	/** @addtogroup ADC
		53	* @{
		54	*/
		55
		56	/* Exported types ------------------------------------------------------------*/
		57	/** @defgroup ADC_Exported_Types ADC Exported Types
		58	* @{
		59	*/
		60
		61	/**
		62	* @brief Structure definition of ADC and regular group initialization
		63	* @note Parameters of this structure are shared within 2 scopes:
		64	* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
		65	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
		66	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
		67	* ADC can be either disabled or enabled without conversion on going on regular group.
		68	*/
		69	typedef struct
		70	{
		71	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
		72	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
		73	This parameter can be a value of @ref ADC_Data_align */
		74	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
		75	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
		76	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
		77	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
		78	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
		79	Scan direction is upward: from rank1 to rank 'n'.
		80	This parameter can be a value of @ref ADC_Scan_mode
		81	Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
		82	or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
		83	the last conversion of the sequence. All previous conversions would be overwritten by the last one.
		84	Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
		85	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
		86	after the selected trigger occurred (software start or external trigger).
		87	This parameter can be set to ENABLE or DISABLE. */
		88	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
		89	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
		90	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
		91	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
		92	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
		93	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
		94	This parameter can be set to ENABLE or DISABLE. */
		95	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
		96	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
		97	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
		98	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
		99	If set to ADC_SOFTWARE_START, external triggers are disabled.
		100	If set to external trigger source, triggering is on event rising edge.
		101	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
		102	}ADC_InitTypeDef;
		103
		104	/**
		105	* @brief Structure definition of ADC channel for regular group
		106	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
		107	* ADC can be either disabled or enabled without conversion on going on regular group.
		108	*/
		109	typedef struct
		110	{
		111	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
		112	This parameter can be a value of @ref ADC_channels
		113	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
		114	Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
		115	Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
		116	It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
		117	Refer to errata sheet of these devices for more details. */
		118	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
		119	This parameter can be a value of @ref ADC_regular_rank
		120	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
		121	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
		122	Unit: ADC clock cycles
		123	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
		124	This parameter can be a value of @ref ADC_sampling_times
		125	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
		126	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
		127	Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
		128	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
		129	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
		130	}ADC_ChannelConfTypeDef;
		131
		132	/**
		133	* @brief ADC Configuration analog watchdog definition
		134	* @note The setting of these parameters with function is conditioned to ADC state.
		135	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
		136	*/
		137	typedef struct
		138	{
		139	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
		140	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
		141	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
		142	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
		143	This parameter can be a value of @ref ADC_channels. */
		144	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
		145	This parameter can be set to ENABLE or DISABLE */
		146	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		147	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		148	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
		149	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
		150	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
		151	}ADC_AnalogWDGConfTypeDef;
		152
		153	/**
		154	* @brief HAL ADC state machine: ADC states definition (bitfields)
		155	*/
		156	/* States of ADC global scope */
		157	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
		158	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
		159	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy to internal process (initialization, calibration) /
		160	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
		161
		162	/* States of ADC errors */
		163	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
		164	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
		165	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
		166
		167	/* States of ADC group regular */
		168	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
		169	external trigger, low power auto power-on, multimode ADC master control) */
		170	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
		171	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Not available on STM32F1 device: Overrun occurrence /
		172	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /!< Not available on STM32F1 device: End Of Sampling flag raised /
		173
		174	/* States of ADC group injected */
		175	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
		176	external trigger, low power auto power-on, multimode ADC master control) */
		177	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Conversion data available on group injected /
		178	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /!< Not available on STM32F1 device: Injected queue overflow occurrence /
		179
		180	/* States of ADC analog watchdogs */
		181	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of analog watchdog 1 /
		182	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 /
		183	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 /
		184
		185	/* States of ADC multi-mode */
		186	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< ADC in multimode slave state, controlled by another ADC master ( /
		187
		188
		189	/**
		190	* @brief ADC handle Structure definition
		191	*/
		192	typedef struct
		193	{
		194	ADC_TypeDef Instance; /!< Register base address */
		195
		196	ADC_InitTypeDef Init; /!< ADC required parameters /
		197
		198	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
		199
		200	HAL_LockTypeDef Lock; /!< ADC locking object /
		201
		202	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
		203
		204	__IO uint32_t ErrorCode; /!< ADC Error code /
		205	}ADC_HandleTypeDef;
		206	/**
		207	* @}
		208	*/
		209
		210
		211
		212	/* Exported constants --------------------------------------------------------*/
		213
		214	/** @defgroup ADC_Exported_Constants ADC Exported Constants
		215	* @{
		216	*/
		217
		218	/** @defgroup ADC_Error_Code ADC Error Code
		219	* @{
		220	*/
		221	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
		222	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
		223	enable/disable, erroneous state */
		224	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< Overrun error /
		225	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
		226
		227	/**
		228	* @}
		229	*/
		230
		231
		232	/** @defgroup ADC_Data_align ADC data alignment
		233	* @{
		234	*/
		235	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
		236	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
		237	/**
		238	* @}
		239	*/
		240
		241	/** @defgroup ADC_Scan_mode ADC scan mode
		242	* @{
		243	*/
		244	/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
		245	/* compatibility with other STM32 devices having a sequencer with */
		246	/* additional options. */
		247	#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
		248	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
		249	/**
		250	* @}
		251	*/
		252
		253	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
		254	* @{
		255	*/
		256	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
		257	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
		258	/**
		259	* @}
		260	*/
		261
		262	/** @defgroup ADC_channels ADC channels
		263	* @{
		264	*/
		265	/* Note: Depending on devices, some channels may not be available on package */
		266	/* pins. Refer to device datasheet for channels availability. */
		267	#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
		268	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
		269	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
		270	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		271	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
		272	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		273	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		274	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		275	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
		276	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_0))
		277	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 ))
		278	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		279	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 ))
		280	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
		281	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 ))
		282	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
		283	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
		284	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_0))
		285
		286	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
		287	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
		288	/**
		289	* @}
		290	*/
		291
		292	/** @defgroup ADC_sampling_times ADC sampling times
		293	* @{
		294	*/
		295	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /!< Sampling time 1.5 ADC clock cycle /
		296	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /!< Sampling time 7.5 ADC clock cycles /
		297	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /!< Sampling time 13.5 ADC clock cycles /
		298	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 28.5 ADC clock cycles /
		299	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /!< Sampling time 41.5 ADC clock cycles /
		300	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 55.5 ADC clock cycles /
		301	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 )) /!< Sampling time 71.5 ADC clock cycles /
		302	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 239.5 ADC clock cycles /
		303	/**
		304	* @}
		305	*/
		306
		307	/** @defgroup ADC_regular_rank ADC rank into regular group
		308	* @{
		309	*/
		310	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
		311	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
		312	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
		313	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
		314	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
		315	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
		316	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
		317	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
		318	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
		319	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
		320	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
		321	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
		322	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
		323	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
		324	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
		325	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
		326	/**
		327	* @}
		328	*/
		329
		330	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
		331	* @{
		332	*/
		333	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
		334	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
		335	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
		336	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		337	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
		338	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
		339	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
		340	/**
		341	* @}
		342	*/
		343
		344	/** @defgroup ADC_conversion_group ADC conversion group
		345	* @{
		346	*/
		347	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
		348	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
		349	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
		350	/**
		351	* @}
		352	*/
		353
		354	/** @defgroup ADC_Event_type ADC Event type
		355	* @{
		356	*/
		357	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
		358
		359	#define ADC_AWD1_EVENT ADC_AWD_EVENT /!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs /
		360	/**
		361	* @}
		362	*/
		363
		364	/** @defgroup ADC_interrupts_definition ADC interrupts definition
		365	* @{
		366	*/
		367	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
		368	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
		369	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
		370	/**
		371	* @}
		372	*/
		373
		374	/** @defgroup ADC_flags_definition ADC flags definition
		375	* @{
		376	*/
		377	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
		378	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
		379	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
		380	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
		381	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
		382	/**
		383	* @}
		384	*/
		385
		386
		387	/**
		388	* @}
		389	*/
		390
		391	/* Private constants ---------------------------------------------------------*/
		392
		393	/** @addtogroup ADC_Private_Constants ADC Private Constants
		394	* @{
		395	*/
		396
		397	/** @defgroup ADC_conversion_cycles ADC conversion cycles
		398	* @{
		399	*/
		400	/* ADC conversion cycles (unit: ADC clock cycles) */
		401	/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
		402	/* resolution 12 bits) */
		403	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
		404	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
		405	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
		406	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
		407	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
		408	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
		409	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
		410	#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
		411	/**
		412	* @}
		413	*/
		414
		415	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
		416	* @{
		417	*/
		418	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
		419	(ADC_SMPR2_SMP9_2 \| ADC_SMPR2_SMP8_2 \| ADC_SMPR2_SMP7_2 \| ADC_SMPR2_SMP6_2 \| \
		420	ADC_SMPR2_SMP5_2 \| ADC_SMPR2_SMP4_2 \| ADC_SMPR2_SMP3_2 \| ADC_SMPR2_SMP2_2 \| \
		421	ADC_SMPR2_SMP1_2 \| ADC_SMPR2_SMP0_2)
		422	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
		423	(ADC_SMPR1_SMP17_2 \| ADC_SMPR1_SMP16_2 \| ADC_SMPR1_SMP15_2 \| ADC_SMPR1_SMP14_2 \| \
		424	ADC_SMPR1_SMP13_2 \| ADC_SMPR1_SMP12_2 \| ADC_SMPR1_SMP11_2 \| ADC_SMPR1_SMP10_2 )
		425
		426	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
		427	(ADC_SMPR2_SMP9_1 \| ADC_SMPR2_SMP8_1 \| ADC_SMPR2_SMP7_1 \| ADC_SMPR2_SMP6_1 \| \
		428	ADC_SMPR2_SMP5_1 \| ADC_SMPR2_SMP4_1 \| ADC_SMPR2_SMP3_1 \| ADC_SMPR2_SMP2_1 \| \
		429	ADC_SMPR2_SMP1_1 \| ADC_SMPR2_SMP0_1)
		430	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
		431	(ADC_SMPR1_SMP17_1 \| ADC_SMPR1_SMP16_1 \| ADC_SMPR1_SMP15_1 \| ADC_SMPR1_SMP14_1 \| \
		432	ADC_SMPR1_SMP13_1 \| ADC_SMPR1_SMP12_1 \| ADC_SMPR1_SMP11_1 \| ADC_SMPR1_SMP10_1 )
		433
		434	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
		435	(ADC_SMPR2_SMP9_0 \| ADC_SMPR2_SMP8_0 \| ADC_SMPR2_SMP7_0 \| ADC_SMPR2_SMP6_0 \| \
		436	ADC_SMPR2_SMP5_0 \| ADC_SMPR2_SMP4_0 \| ADC_SMPR2_SMP3_0 \| ADC_SMPR2_SMP2_0 \| \
		437	ADC_SMPR2_SMP1_0 \| ADC_SMPR2_SMP0_0)
		438	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
		439	(ADC_SMPR1_SMP17_0 \| ADC_SMPR1_SMP16_0 \| ADC_SMPR1_SMP15_0 \| ADC_SMPR1_SMP14_0 \| \
		440	ADC_SMPR1_SMP13_0 \| ADC_SMPR1_SMP12_0 \| ADC_SMPR1_SMP11_0 \| ADC_SMPR1_SMP10_0 )
		441
		442	#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
		443	#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		444	#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		445	#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		446	#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
		447	#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		448	#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
		449	#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
		450
		451	#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
		452	#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		453	#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		454	#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		455	#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
		456	#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		457	#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
		458	#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
		459	/**
		460	* @}
		461	*/
		462
		463	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
		464	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD )
		465
		466	/**
		467	* @}
		468	*/
		469
		470
		471	/* Exported macro ------------------------------------------------------------*/
		472
		473	/** @defgroup ADC_Exported_Macros ADC Exported Macros
		474	* @{
		475	*/
		476	/* Macro for internal HAL driver usage, and possibly can be used into code of */
		477	/* final user. */
		478
		479	/**
		480	* @brief Enable the ADC peripheral
		481	* @note ADC enable requires a delay for ADC stabilization time
		482	* (refer to device datasheet, parameter tSTAB)
		483	* @note On STM32F1, if ADC is already enabled this macro trigs a conversion
		484	* SW start on regular group.
		485	* @param __HANDLE__: ADC handle
		486	* @retval None
		487	*/
		488	#define __HAL_ADC_ENABLE(__HANDLE__) \
		489	(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		490
		491	/**
		492	* @brief Disable the ADC peripheral
		493	* @param __HANDLE__: ADC handle
		494	* @retval None
		495	*/
		496	#define __HAL_ADC_DISABLE(__HANDLE__) \
		497	(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
		498
		499	/** @brief Enable the ADC end of conversion interrupt.
		500	* @param __HANDLE__: ADC handle
		501	* @param __INTERRUPT__: ADC Interrupt
		502	* This parameter can be any combination of the following values:
		503	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		504	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		505	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		506	* @retval None
		507	*/
		508	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
		509	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		510
		511	/** @brief Disable the ADC end of conversion interrupt.
		512	* @param __HANDLE__: ADC handle
		513	* @param __INTERRUPT__: ADC Interrupt
		514	* This parameter can be any combination of the following values:
		515	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		516	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		517	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		518	* @retval None
		519	*/
		520	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
		521	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
		522
		523	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
		524	* @param __HANDLE__: ADC handle
		525	* @param __INTERRUPT__: ADC interrupt source to check
		526	* This parameter can be any combination of the following values:
		527	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
		528	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
		529	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
		530	* @retval None
		531	*/
		532	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
		533	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
		534
		535	/** @brief Get the selected ADC's flag status.
		536	* @param __HANDLE__: ADC handle
		537	* @param __FLAG__: ADC flag
		538	* This parameter can be any combination of the following values:
		539	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		540	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		541	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		542	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		543	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		544	* @retval None
		545	*/
		546	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
		547	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
		548
		549	/** @brief Clear the ADC's pending flags
		550	* @param __HANDLE__: ADC handle
		551	* @param __FLAG__: ADC flag
		552	* This parameter can be any combination of the following values:
		553	* @arg ADC_FLAG_STRT: ADC Regular group start flag
		554	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
		555	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
		556	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
		557	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
		558	* @retval None
		559	*/
		560	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
		561	(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
		562
		563	/** @brief Reset ADC handle state
		564	* @param __HANDLE__: ADC handle
		565	* @retval None
		566	*/
		567	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
		568	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
		569
		570	/**
		571	* @}
		572	*/
		573
		574	/* Private macro ------------------------------------------------------------*/
		575
		576	/** @defgroup ADC_Private_Macros ADC Private Macros
		577	* @{
		578	*/
		579	/* Macro reserved for internal HAL driver usage, not intended to be used in */
		580	/* code of final user. */
		581
		582	/**
		583	* @brief Verification of ADC state: enabled or disabled
		584	* @param __HANDLE__: ADC handle
		585	* @retval SET (ADC enabled) or RESET (ADC disabled)
		586	*/
		587	#define ADC_IS_ENABLE(__HANDLE__) \
		588	((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
		589	) ? SET : RESET)
		590
		591	/**
		592	* @brief Test if conversion trigger of regular group is software start
		593	* or external trigger.
		594	* @param __HANDLE__: ADC handle
		595	* @retval SET (software start) or RESET (external trigger)
		596	*/
		597	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
		598	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
		599
		600	/**
		601	* @brief Test if conversion trigger of injected group is software start
		602	* or external trigger.
		603	* @param __HANDLE__: ADC handle
		604	* @retval SET (software start) or RESET (external trigger)
		605	*/
		606	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
		607	(READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
		608
		609	/**
		610	* @brief Simultaneously clears and sets specific bits of the handle State
		611	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
		612	* the first parameter is the ADC handle State, the second parameter is the
		613	* bit field to clear, the third and last parameter is the bit field to set.
		614	* @retval None
		615	*/
		616	#define ADC_STATE_CLR_SET MODIFY_REG
		617
		618	/**
		619	* @brief Clear ADC error code (set it to error code: "no error")
		620	* @param __HANDLE__: ADC handle
		621	* @retval None
		622	*/
		623	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
		624	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
		625
		626	/**
		627	* @brief Set ADC number of conversions into regular channel sequence length.
		628	* @param _NbrOfConversion_: Regular channel sequence length
		629	* @retval None
		630	*/
		631	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
		632	(((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
		633
		634	/**
		635	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
		636	* @param _SAMPLETIME_: Sample time parameter.
		637	* @param _CHANNELNB_: Channel number.
		638	* @retval None
		639	*/
		640	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
		641	((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10)))
		642
		643	/**
		644	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
		645	* @param _SAMPLETIME_: Sample time parameter.
		646	* @param _CHANNELNB_: Channel number.
		647	* @retval None
		648	*/
		649	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
		650	((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_)))
		651
		652	/**
		653	* @brief Set the selected regular channel rank for rank between 1 and 6.
		654	* @param _CHANNELNB_: Channel number.
		655	* @param _RANKNB_: Rank number.
		656	* @retval None
		657	*/
		658	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
		659	((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1)))
		660
		661	/**
		662	* @brief Set the selected regular channel rank for rank between 7 and 12.
		663	* @param _CHANNELNB_: Channel number.
		664	* @param _RANKNB_: Rank number.
		665	* @retval None
		666	*/
		667	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
		668	((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7)))
		669
		670	/**
		671	* @brief Set the selected regular channel rank for rank between 13 and 16.
		672	* @param _CHANNELNB_: Channel number.
		673	* @param _RANKNB_: Rank number.
		674	* @retval None
		675	*/
		676	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
		677	((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13)))
		678
		679	/**
		680	* @brief Set the injected sequence length.
		681	* @param _JSQR_JL_: Sequence length.
		682	* @retval None
		683	*/
		684	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
		685	(((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL))
		686
		687	/**
		688	* @brief Set the selected injected channel rank
		689	* Note: on STM32F1 devices, channel rank position in JSQR register
		690	* is depending on total number of ranks selected into
		691	* injected sequencer (ranks sequence starting from 4-JL)
		692	* @param _CHANNELNB_: Channel number.
		693	* @param _RANKNB_: Rank number.
		694	* @param _JSQR_JL_: Sequence length.
		695	* @retval None
		696	*/
		697	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
		698	((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
		699
		700	/**
		701	* @brief Enable ADC continuous conversion mode.
		702	* @param _CONTINUOUS_MODE_: Continuous mode.
		703	* @retval None
		704	*/
		705	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
		706	((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
		707
		708	/**
		709	* @brief Configures the number of discontinuous conversions for the regular group channels.
		710	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
		711	* @retval None
		712	*/
		713	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
		714	(((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
		715
		716	/**
		717	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
		718	* @param _SCAN_MODE_: Scan conversion mode.
		719	* @retval None
		720	*/
		721	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
		722	/* is equivalent to ADC_SCAN_ENABLE. */
		723	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
		724	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
		725	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
		726	)
		727
		728	/**
		729	* @brief Get the maximum ADC conversion cycles on all channels.
		730	* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
		731	* Approximation of sampling time within 4 ranges, returns the highest value:
		732	* below 7.5 cycles {1.5 cycle; 7.5 cycles},
		733	* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
		734	* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
		735	* equal to 239.5 cycles
		736	* Unit: ADC clock cycles
		737	* @param __HANDLE__: ADC handle
		738	* @retval ADC conversion cycles on all channels
		739	*/
		740	#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
		741	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
		742	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
		743	\
		744	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		745	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
		746	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
		747	: \
		748	((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
		749	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \|\| \
		750	((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
		751	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
		752	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
		753	)
		754
		755	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
		756	((ALIGN) == ADC_DATAALIGN_LEFT) )
		757
		758	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
		759	((SCAN_MODE) == ADC_SCAN_ENABLE) )
		760
		761	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
		762	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
		763
		764	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
		765	((CHANNEL) == ADC_CHANNEL_1) \|\| \
		766	((CHANNEL) == ADC_CHANNEL_2) \|\| \
		767	((CHANNEL) == ADC_CHANNEL_3) \|\| \
		768	((CHANNEL) == ADC_CHANNEL_4) \|\| \
		769	((CHANNEL) == ADC_CHANNEL_5) \|\| \
		770	((CHANNEL) == ADC_CHANNEL_6) \|\| \
		771	((CHANNEL) == ADC_CHANNEL_7) \|\| \
		772	((CHANNEL) == ADC_CHANNEL_8) \|\| \
		773	((CHANNEL) == ADC_CHANNEL_9) \|\| \
		774	((CHANNEL) == ADC_CHANNEL_10) \|\| \
		775	((CHANNEL) == ADC_CHANNEL_11) \|\| \
		776	((CHANNEL) == ADC_CHANNEL_12) \|\| \
		777	((CHANNEL) == ADC_CHANNEL_13) \|\| \
		778	((CHANNEL) == ADC_CHANNEL_14) \|\| \
		779	((CHANNEL) == ADC_CHANNEL_15) \|\| \
		780	((CHANNEL) == ADC_CHANNEL_16) \|\| \
		781	((CHANNEL) == ADC_CHANNEL_17) )
		782
		783	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
		784	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
		785	((TIME) == ADC_SAMPLETIME_13CYCLES_5) \|\| \
		786	((TIME) == ADC_SAMPLETIME_28CYCLES_5) \|\| \
		787	((TIME) == ADC_SAMPLETIME_41CYCLES_5) \|\| \
		788	((TIME) == ADC_SAMPLETIME_55CYCLES_5) \|\| \
		789	((TIME) == ADC_SAMPLETIME_71CYCLES_5) \|\| \
		790	((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
		791
		792	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
		793	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
		794	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
		795	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
		796	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
		797	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
		798	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
		799	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
		800	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
		801	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
		802	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
		803	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
		804	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
		805	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
		806	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
		807	((CHANNEL) == ADC_REGULAR_RANK_16) )
		808
		809	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
		810	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
		811	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
		812	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
		813	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
		814	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
		815	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
		816
		817	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
		818	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
		819	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
		820
		821	#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
		822
		823
		824	/** @defgroup ADC_range_verification ADC range verification
		825	* For a unique ADC resolution: 12 bits
		826	* @{
		827	*/
		828	#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
		829	/**
		830	* @}
		831	*/
		832
		833	/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
		834	* @{
		835	*/
		836	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
		837	/**
		838	* @}
		839	*/
		840
		841	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
		842	* @{
		843	*/
		844	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
		845	/**
		846	* @}
		847	*/
		848
		849	/**
		850	* @}
		851	*/
		852
		853	/* Include ADC HAL Extension module */
		854	#include "stm32f1xx_hal_adc_ex.h"
		855
		856	/* Exported functions --------------------------------------------------------*/
		857	/** @addtogroup ADC_Exported_Functions
		858	* @{
		859	*/
		860
		861	/** @addtogroup ADC_Exported_Functions_Group1
		862	* @{
		863	*/
		864
		865
		866	/* Initialization and de-initialization functions **********************************/
		867	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
		868	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
		869	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
		870	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
		871	/**
		872	* @}
		873	*/
		874
		875	/* IO operation functions *****************************************************/
		876
		877	/** @addtogroup ADC_Exported_Functions_Group2
		878	* @{
		879	*/
		880
		881
		882	/* Blocking mode: Polling */
		883	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
		884	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
		885	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
		886	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
		887
		888	/* Non-blocking mode: Interruption */
		889	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
		890	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
		891
		892	/* Non-blocking mode: DMA */
		893	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
		894	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
		895
		896	/* ADC retrieve conversion value intended to be used with polling or interruption */
		897	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
		898
		899	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
		900	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
		901	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
		902	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
		903	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
		904	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
		905	/**
		906	* @}
		907	*/
		908
		909
		910	/* Peripheral Control functions ***********************************************/
		911	/** @addtogroup ADC_Exported_Functions_Group3
		912	* @{
		913	*/
		914	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
		915	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
		916	/**
		917	* @}
		918	*/
		919
		920
		921	/* Peripheral State functions *************************************************/
		922	/** @addtogroup ADC_Exported_Functions_Group4
		923	* @{
		924	*/
		925	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
		926	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
		927	/**
		928	* @}
		929	*/
		930
		931
		932	/**
		933	* @}
		934	*/
		935
		936
		937	/* Internal HAL driver functions **********************************************/
		938	/** @addtogroup ADC_Private_Functions
		939	* @{
		940	*/
		941	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
		942	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
		943	void ADC_StabilizationTime(uint32_t DelayUs);
		944	void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
		945	void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
		946	void ADC_DMAError(DMA_HandleTypeDef *hdma);
		947	/**
		948	* @}
		949	*/
		950
		951
		952	/**
		953	* @}
		954	*/
		955
		956	/**
		957	* @}
		958	*/
		959
		960	#ifdef __cplusplus
		961	}
		962	#endif
		963
		964
		965	#endif /* __STM32F1xx_HAL_ADC_H */
		966
		967	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h – Rev 5