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/**

  ******************************************************************************

  * @file    stm32_hal_legacy.h

  * @author  MCD Application Team

  * @brief   This file contains aliases definition for the STM32Cube HAL constants

  *          macros and functions maintained for legacy purpose.

  ******************************************************************************

  * @attention

  *

  * Copyright (c) 2021 STMicroelectronics.

  * All rights reserved.

  *

  * This software is licensed under terms that can be found in the LICENSE file

  * in the root directory of this software component.

  * If no LICENSE file comes with this software, it is provided AS-IS.

  *

  ******************************************************************************

  */

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef STM32_HAL_LEGACY

#define STM32_HAL_LEGACY

#ifdef __cplusplus

extern "C" {

#endif

/* Includes ------------------------------------------------------------------*/

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose

  * @{

  */

#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR

#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR

#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR

#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)

#define CRYP_DATATYPE_32B               CRYP_NO_SWAP

#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP

#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP

#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP

#if defined(STM32U5)

#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF

#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF

#endif /* STM32U5 */

#endif /* STM32U5 || STM32H7 || STM32MP1 */

/**

  * @}

  */

/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose

  * @{

  */

#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B

#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B

#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B

#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B

#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN

#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED

#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV

#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV

#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV

#define REGULAR_GROUP                   ADC_REGULAR_GROUP

#define INJECTED_GROUP                  ADC_INJECTED_GROUP

#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP

#define AWD_EVENT                       ADC_AWD_EVENT

#define AWD1_EVENT                      ADC_AWD1_EVENT

#define AWD2_EVENT                      ADC_AWD2_EVENT

#define AWD3_EVENT                      ADC_AWD3_EVENT

#define OVR_EVENT                       ADC_OVR_EVENT

#define JQOVF_EVENT                     ADC_JQOVF_EVENT

#define ALL_CHANNELS                    ADC_ALL_CHANNELS

#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS

#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS

#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR

#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT

#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1

#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2

#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4

#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6

#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8

#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO

#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2

#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO

#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4

#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO

#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11

#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1

#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE

#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING

#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING

#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING

#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5

#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY

#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY

#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC

#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC

#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL

#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL

#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1

#if defined(STM32H7)

#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT

#endif /* STM32H7 */

#if defined(STM32U5)

#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES

#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES

#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5

#endif /* STM32U5 */

#if defined(STM32H5)

#define ADC_CHANNEL_VCORE               ADC_CHANNEL_VDDCORE

#endif /* STM32H5 */

/**

  * @}

  */

/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose

  * @{

  */

#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG

/**

  * @}

  */

/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose

  * @{

  */

#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE

#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE

#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1

#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2

#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3

#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4

#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5

#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6

#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7

#if defined(STM32L0)

#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM 

                                                                       input 1 for COMP1, LPTIM input 2 for COMP2 */

#endif

#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR

#if defined(STM32F373xC) || defined(STM32F378xx)

#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1

#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR

#endif /* STM32F373xC || STM32F378xx */

#if defined(STM32L0) || defined(STM32L4)

#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1

#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2

#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3

#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4

#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5

#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6

#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT

#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT

#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT

#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT

#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1

#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2

#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1

#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2

#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1

#if defined(STM32L0)

/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */

/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */

/* to the second dedicated IO (only for COMP2).                               */

#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2

#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2

#else

#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2

#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3

#endif

#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4

#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5

#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW

#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH

/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */

/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */

#if defined(COMP_CSR_LOCK)

#define COMP_FLAG_LOCK                 COMP_CSR_LOCK

#elif defined(COMP_CSR_COMP1LOCK)

#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK

#elif defined(COMP_CSR_COMPxLOCK)

#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK

#endif

#if defined(STM32L4)

#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1

#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1

#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1

#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2

#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2

#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2

#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE

#endif

#if defined(STM32L0)

#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED

#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER

#else

#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED

#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED

#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER

#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER

#endif

#endif

#if defined(STM32U5)

#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG

#endif

/**

  * @}

  */

/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose

  * @{

  */

#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig

#if defined(STM32U5)

#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE

#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE

#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE

#endif /* STM32U5 */

/**

  * @}

  */

/** @defgroup CRC_Aliases CRC API aliases

  * @{

  */

#if defined(STM32H5) || defined(STM32C0)

#else

#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 

                                                                          inter STM32 series compatibility  */

#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 

                                                                          inter STM32 series compatibility */

#endif

/**

  * @}

  */

/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose

  * @{

  */

#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE

#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE

/**

  * @}

  */

/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose

  * @{

  */

#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1

#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2

#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1

#define DAC_WAVE_NONE                                   0x00000000U

#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0

#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1

#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE

#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE

#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE

#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)

#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL

#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL

#endif

#if defined(STM32U5)

#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1

#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1

#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1

#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1

#endif

#if defined(STM32H5)

#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1

#define DAC_TRIGGER_LPTIM2_OUT       DAC_TRIGGER_LPTIM2_CH1

#endif

#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \

    defined(STM32F4) || defined(STM32G4)

#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID

#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID

#endif

/**

  * @}

  */

/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose

  * @{

  */

#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2

#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4

#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5

#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4

#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2

#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32

#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6

#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7

#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67

#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67

#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76

#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6

#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7

#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6

#define IS_HAL_REMAPDMA                          IS_DMA_REMAP

#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE

#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE

#if defined(STM32L4)

#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0

#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1

#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2

#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3

#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4

#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5

#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6

#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7

#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8

#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9

#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10

#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11

#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12

#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13

#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14

#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT

#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE

#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT

#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT

#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT

#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT

#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING

#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING

#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING

#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \

    defined(STM32L4S7xx) || defined(STM32L4S9xx)

#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI

#endif

#endif /* STM32L4 */

#if defined(STM32G0)

#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1

#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2

#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM

#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM

#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM

#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM

#endif

#if defined(STM32H7)

#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1

#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2

#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX

#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT

#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT

#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT

#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0

#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT

#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT

#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT

#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP

#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0

#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2

#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT

#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT

#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT

#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT

#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT

#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT

#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT

#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT

#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING

#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING

#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING

#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT

#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT

#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT

#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT

#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT

#endif /* STM32H7 */

#if defined(STM32U5)

#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI

#endif /* STM32U5 */

/**

  * @}

  */

/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose

  * @{

  */

#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE

#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD

#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD

#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD

#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS

#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES

#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES

#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE

#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE

#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE

#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE

#define OBEX_PCROP                    OPTIONBYTE_PCROP

#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG

#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE

#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE

#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE

#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD

#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD

#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE

#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD

#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD

#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE

#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD

#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD

#define PAGESIZE                      FLASH_PAGE_SIZE

#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE

#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD

#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD

#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1

#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2

#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3

#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4

#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST

#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST

#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA

#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB

#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA

#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB

#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE

#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN

#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE

#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN

#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE

#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD

#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG

#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS

#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP

#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV

#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR

#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG

#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION

#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA

#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE

#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE

#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS

#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS

#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST

#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR

#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO

#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION

#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS

#define OB_WDG_SW                     OB_IWDG_SW

#define OB_WDG_HW                     OB_IWDG_HW

#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET

#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET

#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET

#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET

#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR

#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0

#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1

#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2

#if defined(STM32G0) || defined(STM32C0)

#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE

#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH

#else

#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE

#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE

#endif

#if defined(STM32H7)

#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1

#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1

#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1

#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2

#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2

#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2

#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE

#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL

#endif /* STM32H7 */

#if defined(STM32U5)

#define OB_USER_nRST_STOP             OB_USER_NRST_STOP

#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY

#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW

#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0

#define OB_USER_nBOOT0                OB_USER_NBOOT0

#define OB_nBOOT0_RESET               OB_NBOOT0_RESET

#define OB_nBOOT0_SET                 OB_NBOOT0_SET

#define OB_USER_SRAM134_RST           OB_USER_SRAM_RST

#define OB_SRAM134_RST_ERASE          OB_SRAM_RST_ERASE

#define OB_SRAM134_RST_NOT_ERASE      OB_SRAM_RST_NOT_ERASE

#endif /* STM32U5 */

/**

  * @}

  */

/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose

  * @{

  */

#if defined(STM32H7)

#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE

#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE

#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET

#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET

#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE

#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE

#endif /* STM32H7 */

/**

  * @}

  */

/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose

  * @{

  */

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9

#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1

#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2

#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3

#if defined(STM32G4)

#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster

#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster

#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD

#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD

#endif /* STM32G4 */

#if defined(STM32H5)

#define SYSCFG_IT_FPU_IOC         SBS_IT_FPU_IOC

#define SYSCFG_IT_FPU_DZC         SBS_IT_FPU_DZC

#define SYSCFG_IT_FPU_UFC         SBS_IT_FPU_UFC

#define SYSCFG_IT_FPU_OFC         SBS_IT_FPU_OFC

#define SYSCFG_IT_FPU_IDC         SBS_IT_FPU_IDC

#define SYSCFG_IT_FPU_IXC         SBS_IT_FPU_IXC

#define SYSCFG_BREAK_FLASH_ECC    SBS_BREAK_FLASH_ECC

#define SYSCFG_BREAK_PVD          SBS_BREAK_PVD

#define SYSCFG_BREAK_SRAM_ECC     SBS_BREAK_SRAM_ECC

#define SYSCFG_BREAK_LOCKUP       SBS_BREAK_LOCKUP

#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_VOLTAGE_SCALE0

#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_VOLTAGE_SCALE1

#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_VOLTAGE_SCALE2

#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_VOLTAGE_SCALE3

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   VREFBUF_HIGH_IMPEDANCE_DISABLE

#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_HIGH_IMPEDANCE_ENABLE

#define SYSCFG_FASTMODEPLUS_PB6   SBS_FASTMODEPLUS_PB6

#define SYSCFG_FASTMODEPLUS_PB7   SBS_FASTMODEPLUS_PB7

#define SYSCFG_FASTMODEPLUS_PB8   SBS_FASTMODEPLUS_PB8

#define SYSCFG_FASTMODEPLUS_PB9   SBS_FASTMODEPLUS_PB9

#define SYSCFG_ETH_MII   SBS_ETH_MII

#define SYSCFG_ETH_RMII  SBS_ETH_RMII

#define IS_SYSCFG_ETHERNET_CONFIG  IS_SBS_ETHERNET_CONFIG

#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE   SBS_MEMORIES_ERASE_FLAG_IPMEE

#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR    SBS_MEMORIES_ERASE_FLAG_MCLR

#define IS_SYSCFG_MEMORIES_ERASE_FLAG      IS_SBS_MEMORIES_ERASE_FLAG

#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG

#define SYSCFG_MPU_NSEC   SBS_MPU_NSEC

#define SYSCFG_VTOR_NSEC  SBS_VTOR_NSEC

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

#define SYSCFG_SAU              SBS_SAU

#define SYSCFG_MPU_SEC          SBS_MPU_SEC

#define SYSCFG_VTOR_AIRCR_SEC   SBS_VTOR_AIRCR_SEC

#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL

#else

#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL

#endif /* __ARM_FEATURE_CMSE */

#define SYSCFG_CLK      SBS_CLK

#define SYSCFG_CLASSB   SBS_CLASSB

#define SYSCFG_FPU      SBS_FPU

#define SYSCFG_ALL      SBS_ALL

#define SYSCFG_SEC      SBS_SEC

#define SYSCFG_NSEC     SBS_NSEC

#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE   __HAL_SBS_FPU_INTERRUPT_ENABLE

#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE  __HAL_SBS_FPU_INTERRUPT_DISABLE

#define __HAL_SYSCFG_BREAK_ECC_LOCK        __HAL_SBS_BREAK_ECC_LOCK

#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK     __HAL_SBS_BREAK_LOCKUP_LOCK

#define __HAL_SYSCFG_BREAK_PVD_LOCK        __HAL_SBS_BREAK_PVD_LOCK

#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK   __HAL_SBS_BREAK_SRAM_ECC_LOCK

#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE   __HAL_SBS_FASTMODEPLUS_ENABLE

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE  __HAL_SBS_FASTMODEPLUS_DISABLE

#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS    __HAL_SBS_GET_MEMORIES_ERASE_STATUS

#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS  __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS

#define IS_SYSCFG_FPU_INTERRUPT    IS_SBS_FPU_INTERRUPT

#define IS_SYSCFG_BREAK_CONFIG     IS_SBS_BREAK_CONFIG

#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE     IS_VREFBUF_VOLTAGE_SCALE

#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE    IS_VREFBUF_HIGH_IMPEDANCE

#define IS_SYSCFG_VREFBUF_TRIMMING  IS_VREFBUF_TRIMMING

#define IS_SYSCFG_FASTMODEPLUS      IS_SBS_FASTMODEPLUS

#define IS_SYSCFG_ITEMS_ATTRIBUTES  IS_SBS_ITEMS_ATTRIBUTES

#define IS_SYSCFG_ATTRIBUTES        IS_SBS_ATTRIBUTES

#define IS_SYSCFG_LOCK_ITEMS        IS_SBS_LOCK_ITEMS

#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig   HAL_VREFBUF_VoltageScalingConfig

#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig    HAL_VREFBUF_HighImpedanceConfig

#define HAL_SYSCFG_VREFBUF_TrimmingConfig         HAL_VREFBUF_TrimmingConfig

#define HAL_SYSCFG_EnableVREFBUF                  HAL_EnableVREFBUF

#define HAL_SYSCFG_DisableVREFBUF                 HAL_DisableVREFBUF

#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SBS_EnableIOAnalogSwitchBooster

#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SBS_DisableIOAnalogSwitchBooster

#define HAL_SYSCFG_ETHInterfaceSelect             HAL_SBS_ETHInterfaceSelect

#define HAL_SYSCFG_Lock     HAL_SBS_Lock

#define HAL_SYSCFG_GetLock  HAL_SBS_GetLock

#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)

#define HAL_SYSCFG_ConfigAttributes     HAL_SBS_ConfigAttributes

#define HAL_SYSCFG_GetConfigAttributes  HAL_SBS_GetConfigAttributes

#endif /* __ARM_FEATURE_CMSE */

#endif /* STM32H5 */

/**

  * @}

  */

/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose

  * @{

  */

#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)

#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE

#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE

#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8

#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16

#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)

#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE

#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE

#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8

#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16

#endif

/**

  * @}

  */

/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose

  * @{

  */

#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef

#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef

/**

  * @}

  */

/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose

  * @{

  */

#define GET_GPIO_SOURCE                           GPIO_GET_INDEX

#define GET_GPIO_INDEX                            GPIO_GET_INDEX

#if defined(STM32F4)

#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO

#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO

#endif

#if defined(STM32F7)

#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1

#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1

#endif

#if defined(STM32L4)

#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1

#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1

#endif

#if defined(STM32H7)

#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1

#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1

#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1

#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2

#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2

#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2

#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \

    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)

#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS

#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS

#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS

#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \

         STM32H757xx */

#endif /* STM32H7 */

#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1

#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1

#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1

#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \

    defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)

#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW

#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM

#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH

#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH

#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/

#if defined(STM32L1)

#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW

#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM

#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH

#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH

#endif /* STM32L1 */

#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)

#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW

#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM

#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH

#endif /* STM32F0 || STM32F3 || STM32F1 */

#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1

#if defined(STM32U5) || defined(STM32H5)

#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ

#endif /* STM32U5 || STM32H5 */

#if defined(STM32U5)

#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP

#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1

#endif /* STM32U5 */

/**

  * @}

  */

/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose

  * @{

  */

#if defined(STM32U5)

#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI

#define GTZC_PERIPH_LTDC                      GTZC_PERIPH_LTDCUSB

#endif /* STM32U5 */

#if defined(STM32H5)

#define GTZC_PERIPH_DAC12                     GTZC_PERIPH_DAC1

#define GTZC_PERIPH_ADC12                     GTZC_PERIPH_ADC

#define GTZC_PERIPH_USBFS                     GTZC_PERIPH_USB

#endif /* STM32H5 */

#if defined(STM32H5) || defined(STM32U5)

#define GTZC_MCPBB_NB_VCTR_REG_MAX            GTZC_MPCBB_NB_VCTR_REG_MAX

#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX        GTZC_MPCBB_NB_LCK_VCTR_REG_MAX

#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED        GTZC_MPCBB_SUPERBLOCK_UNLOCKED

#define GTZC_MCPBB_SUPERBLOCK_LOCKED          GTZC_MPCBB_SUPERBLOCK_LOCKED

#define GTZC_MCPBB_BLOCK_NSEC                 GTZC_MPCBB_BLOCK_NSEC

#define GTZC_MCPBB_BLOCK_SEC                  GTZC_MPCBB_BLOCK_SEC

#define GTZC_MCPBB_BLOCK_NPRIV                GTZC_MPCBB_BLOCK_NPRIV

#define GTZC_MCPBB_BLOCK_PRIV                 GTZC_MPCBB_BLOCK_PRIV

#define GTZC_MCPBB_LOCK_OFF                   GTZC_MPCBB_LOCK_OFF

#define GTZC_MCPBB_LOCK_ON                    GTZC_MPCBB_LOCK_ON

#endif /* STM32H5 || STM32U5 */

/**

  * @}

  */

/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose

  * @{

  */

#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7

#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7

#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER

#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER

#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD

#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD

#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER

#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER

#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE

#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE

#if defined(STM32G4)

#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig

#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable

#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable

#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset

#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A

#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B

#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL

#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL

#endif /* STM32G4 */

#if defined(STM32H7)

#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1

#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2

#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6

#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7

#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9

#endif /* STM32H7 */

#if defined(STM32F3)

/** @brief Constants defining available sources associated to external events.

  */

#define HRTIM_EVENTSRC_1              (0x00000000U)

#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)

#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)

/** @brief Constants defining the DLL calibration periods (in micro seconds)

  */

#define HRTIM_CALIBRATIONRATE_7300             0x00000000U

#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)

#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)

#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)

#endif /* STM32F3 */

/**

  * @}

  */