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/**

  ******************************************************************************

  * @file    stm32_hal_legacy.h

  * @author  MCD Application Team

  * @version V1.0.4

  * @date    29-April-2016

  * @brief   This file contains aliases definition for the STM32Cube HAL constants

  *          macros and functions maintained for legacy purpose.

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  *

  * Redistribution and use in source and binary forms, with or without modification,

  * are permitted provided that the following conditions are met:

  *   1. Redistributions of source code must retain the above copyright notice,

  *      this list of conditions and the following disclaimer.

  *   2. Redistributions in binary form must reproduce the above copyright notice,

  *      this list of conditions and the following disclaimer in the documentation

  *      and/or other materials provided with the distribution.

  *   3. Neither the name of STMicroelectronics nor the names of its contributors

  *      may be used to endorse or promote products derived from this software

  *      without specific prior written permission.

  *

  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  *

  ******************************************************************************

  */

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef __STM32_HAL_LEGACY

#define __STM32_HAL_LEGACY

#ifdef __cplusplus

 extern "C" {

#endif

/* Includes ------------------------------------------------------------------*/

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose

  * @{

  */

#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR

#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR

#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR

/**

  * @}

  */

/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose

  * @{

  */

#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B

#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B

#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B

#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B

#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN

#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED

#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV

#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV

#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV

#define REGULAR_GROUP                   ADC_REGULAR_GROUP

#define INJECTED_GROUP                  ADC_INJECTED_GROUP

#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP

#define AWD_EVENT                       ADC_AWD_EVENT

#define AWD1_EVENT                      ADC_AWD1_EVENT

#define AWD2_EVENT                      ADC_AWD2_EVENT

#define AWD3_EVENT                      ADC_AWD3_EVENT

#define OVR_EVENT                       ADC_OVR_EVENT

#define JQOVF_EVENT                     ADC_JQOVF_EVENT

#define ALL_CHANNELS                    ADC_ALL_CHANNELS

#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS

#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS

#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR

#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT

#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1

#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2

#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4

#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6

#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8

#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO 

#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2 

#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO 

#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4  

#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO

#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11

#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1

#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE

#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING

#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING

#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING

#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5

#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY

#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY

#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC

#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC

#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL

#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL

#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1 

/**

  * @}

  */

/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose

  * @{

  */

#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 

/**

  * @}

  */  

/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose

  * @{

  */

#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE

#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE

#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1

#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2

#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3

#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4

#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5

#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6

#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7

#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR

#if defined(STM32F373xC) || defined(STM32F378xx)

#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1

#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR

#endif /* STM32F373xC || STM32F378xx */

#if defined(STM32L0) || defined(STM32L4)

#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1

#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2

#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3

#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT

#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT

#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT

#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT

#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1

#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2

#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1

#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2

#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1

#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2

#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3

#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4

#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5

#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW

#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH

/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */

/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */

#if defined(COMP_CSR_LOCK)

#define COMP_FLAG_LOCK                 COMP_CSR_LOCK

#elif defined(COMP_CSR_COMP1LOCK)

#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK

#elif defined(COMP_CSR_COMPxLOCK)

#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK

#endif

#if defined(STM32L4)

#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1

#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1

#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1

#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2

#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2

#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2

#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE

#endif

#if defined(STM32L0)

#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED

#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER

#else

#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED

#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED

#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER

#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER

#endif

#endif

/**

  * @}

  */

/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose

  * @{

  */

#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig

/**

  * @}

  */

/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose

  * @{

  */

#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE

#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE

/**

  * @}

  */

/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose

  * @{

  */

#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1

#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2

#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1

#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)

#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)

#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           

#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE

#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE

#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE

/**

  * @}

  */

/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose

  * @{

  */

#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2       

#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4 

#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5   

#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4       

#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2       

#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32

#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6

#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      

#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  

#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 

#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  

#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   

#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     

#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      

#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6    

#define IS_HAL_REMAPDMA                          IS_DMA_REMAP  

#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE

#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE

/**

  * @}

  */

/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose

  * @{

  */

#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE

#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD

#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD

#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD

#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS

#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES

#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES

#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE

#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE

#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE

#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE

#define OBEX_PCROP                    OPTIONBYTE_PCROP

#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG

#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE

#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE

#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE

#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD

#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD

#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE

#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD

#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD

#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE

#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD

#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD

#define PAGESIZE                      FLASH_PAGE_SIZE

#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE

#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD

#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD

#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1

#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2

#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3

#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4

#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST

#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST

#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA

#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB

#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA

#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB

#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE

#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN

#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE

#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN

#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE

#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD

#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG

#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS

#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP

#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV

#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR

#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG

#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION

#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA

#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE

#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE

#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS

#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS

#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST

#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR

#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO

#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION

#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS

#define OB_WDG_SW                     OB_IWDG_SW

#define OB_WDG_HW                     OB_IWDG_HW

#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET

#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET

#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET

#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET

#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR

#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0

#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1

#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2

/**

  * @}

  */

/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose

  * @{

  */

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8

#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9

#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1

#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2

#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3

/**

  * @}

  */

/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose

  * @{

  */

#if defined(STM32L4) || defined(STM32F7)

#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE

#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE

#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8

#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16

#else

#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE

#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE

#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8

#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16

#endif

/**

  * @}

  */

/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose

  * @{

  */

#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef

#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef

/**

  * @}

  */

/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose

  * @{

  */

#define GET_GPIO_SOURCE                           GPIO_GET_INDEX

#define GET_GPIO_INDEX                            GPIO_GET_INDEX

#if defined(STM32F4)

#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO

#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO

#endif

#if defined(STM32F7)

#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1

#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1

#endif

#if defined(STM32L4)

#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1

#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1

#endif

#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1

#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1

#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1

#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)

#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW     

#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM     

#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH     

#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH       

#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */

#if defined(STM32L1) 

 #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW     

 #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM     

 #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH     

 #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH     

#endif /* STM32L1 */

#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)

 #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW

 #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM

 #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH

#endif /* STM32F0 || STM32F3 || STM32F1 */

#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1

/**

  * @}

  */

/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose

  * @{

  */

#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7

#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7

#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7

#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER

#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER

#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD

#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD

#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER

#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER

#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE

#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE

/**

  * @}

  */

/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose

  * @{

  */

#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE

#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE

#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE

#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE

#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE

#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE

#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE

#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE

#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)

#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX

#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX

#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX

#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX

#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX

#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX

#endif

/**

  * @}

  */

/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose

  * @{

  */

#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE

#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE

/**

  * @}

  */

/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose

  * @{

  */

#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD

#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE

#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE

#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE

/**

  * @}

  */

/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose

  * @{

  */

#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION

#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS

#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS

#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS

#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING

#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING

#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING

#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION

#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS

#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS

#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS        

/* The following 3 definition have also been present in a temporary version of lptim.h */

/* They need to be renamed also to the right name, just in case */

#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS

#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS

#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS

/**

  * @}

  */

/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose

  * @{

  */

#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b

#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b

#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b

#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b

#define NAND_AddressTypedef             NAND_AddressTypeDef

#define __ARRAY_ADDRESS                 ARRAY_ADDRESS

#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE

#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE

#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE

#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE

/**

  * @}

  */

/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose

  * @{

  */

#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef

#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS

#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING

#define NOR_ERROR                      HAL_NOR_STATUS_ERROR

#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT

#define __NOR_WRITE                    NOR_WRITE

#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT

/**

  * @}

  */

/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose

  * @{

  */

#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0

#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1

#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2

#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3

#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0

#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1

#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2

#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3   

#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0

#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1

#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0

#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1

#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0

#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1    

#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1

#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO             

#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0            

#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1          

/**

  * @}

  */

/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose

  * @{

  */

#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS

#if defined(STM32F7) 

  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL

#endif

/**

  * @}

  */

/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose

  * @{

  */

/* Compact Flash-ATA registers description */

#define CF_DATA                       ATA_DATA                

#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT        

#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER       

#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW        

#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH       

#define CF_CARD_HEAD                  ATA_CARD_HEAD           

#define CF_STATUS_CMD                 ATA_STATUS_CMD          

#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE

#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA    

/* Compact Flash-ATA commands */

#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD 

#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD

#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD

#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD

#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef

#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS

#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING

#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR

#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT

/**

  * @}

  */

/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose

  * @{

  */

#define FORMAT_BIN                  RTC_FORMAT_BIN

#define FORMAT_BCD                  RTC_FORMAT_BCD

#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE

#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE

#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE

#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE

#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE

#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 

#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 

#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE

#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 

#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 

#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE

#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 

#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 

#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT

#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 

#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1

#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2

#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE

#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1

#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1

#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 

#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1 

#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1

/**

  * @}

  */

/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose

  * @{

  */

#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE

#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE

#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE

#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE

#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE

#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE

#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE

#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE

#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE

#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE

/**

  * @}

  */

/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose

  * @{

  */

#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE

#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE

#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE

#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE

#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE

#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE

#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE

#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE

#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE

#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE

#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN

/**

  * @}

  */

/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose

  * @{

  */

#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE

#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE

#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE

#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE

#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE

#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE

/**

  * @}

  */

/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose

  * @{

  */

#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK

#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK

#define TIM_DMABase_CR1                  TIM_DMABASE_CR1

#define TIM_DMABase_CR2                  TIM_DMABASE_CR2

#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR

#define TIM_DMABase_DIER                 TIM_DMABASE_DIER

#define TIM_DMABase_SR                   TIM_DMABASE_SR

#define TIM_DMABase_EGR                  TIM_DMABASE_EGR

#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1

#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2

#define TIM_DMABase_CCER                 TIM_DMABASE_CCER

#define TIM_DMABase_CNT                  TIM_DMABASE_CNT

#define TIM_DMABase_PSC                  TIM_DMABASE_PSC

#define TIM_DMABase_ARR                  TIM_DMABASE_ARR

#define TIM_DMABase_RCR                  TIM_DMABASE_RCR

#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1

#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2

#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3

#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4

#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR

#define TIM_DMABase_DCR                  TIM_DMABASE_DCR

#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR

#define TIM_DMABase_OR1                  TIM_DMABASE_OR1

#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3

#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5

#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6

#define TIM_DMABase_OR2                  TIM_DMABASE_OR2

#define TIM_DMABase_OR3                  TIM_DMABASE_OR3

#define TIM_DMABase_OR                   TIM_DMABASE_OR

#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE

#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1

#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2

#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3

#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4

#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM

#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER

#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK

#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2

#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER

#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS

#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS

#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS

#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS

#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS

#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS

#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS

#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS

#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS

#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS

#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS

#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS

#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS

#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS

#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS

#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS

#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS

/**

  * @}

  */

/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose

  * @{

  */

#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING

#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING

/**

  * @}

  */

/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose

  * @{

  */

#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE

#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE

#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE

#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE

#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE

#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE

#define __DIV_SAMPLING16                UART_DIV_SAMPLING16

#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16

#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16

#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16

#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8

#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8

#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8

#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8

#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE

#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK

/**

  * @}

  */

/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose

  * @{

  */

#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE

#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE

#define USARTNACK_ENABLED               USART_NACK_ENABLE

#define USARTNACK_DISABLED              USART_NACK_DISABLE

/**

  * @}

  */

/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose

  * @{

  */

#define CFR_BASE                    WWDG_CFR_BASE

/**

  * @}

  */

/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose

  * @{

  */

#define CAN_FilterFIFO0             CAN_FILTER_FIFO0

#define CAN_FilterFIFO1             CAN_FILTER_FIFO1

#define CAN_IT_RQCP0                CAN_IT_TME

#define CAN_IT_RQCP1                CAN_IT_TME

#define CAN_IT_RQCP2                CAN_IT_TME

#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE

#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE

#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)

#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)

#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)

/**

  * @}

  */

/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose

  * @{

  */

#define VLAN_TAG                ETH_VLAN_TAG

#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD

#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD

#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD

#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK

#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK

#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK

#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK

#define ETH_MMCCR              ((uint32_t)0x00000100U)  

#define ETH_MMCRIR             ((uint32_t)0x00000104U)  

#define ETH_MMCTIR             ((uint32_t)0x00000108U)  

#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  

#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  

#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  

#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  

#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  

#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  

#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  

#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)

#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */

#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */

#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */

#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */

#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */

#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */

#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */

#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */

#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */

#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */

#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */

#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */

#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */

#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */

#if defined(STM32F1)

#else

#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */

#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */

#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */

#endif

#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */

#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */

#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */

#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */

#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */

#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */

#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */

/**

  * @}

  */

/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose

  * @{

  */

#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR

#define DCMI_IT_OVF             DCMI_IT_OVR

#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI

#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI

#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop

#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop

#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop

/**

  * @}

  */  

#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\

    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)

/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose

  * @{

  */

#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888

#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888  

#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565  

#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555

#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444

#define CM_ARGB8888             DMA2D_INPUT_ARGB8888

#define CM_RGB888               DMA2D_INPUT_RGB888  

#define CM_RGB565               DMA2D_INPUT_RGB565  

#define CM_ARGB1555             DMA2D_INPUT_ARGB1555

#define CM_ARGB4444             DMA2D_INPUT_ARGB4444

#define CM_L8                   DMA2D_INPUT_L8      

#define CM_AL44                 DMA2D_INPUT_AL44    

#define CM_AL88                 DMA2D_INPUT_AL88    

#define CM_L4                   DMA2D_INPUT_L4      

#define CM_A8                   DMA2D_INPUT_A8      

#define CM_A4                   DMA2D_INPUT_A4      

/**

  * @}

  */    

#endif  /* STM32L4xx ||  STM32F7*/

/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose

  * @{