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2 mjames 1 
/**
2 
  ******************************************************************************
3 
  * @file    stm32f0xx_ll_tim.c
4 
  * @author  MCD Application Team
5 
  * @brief   TIM LL module driver.
6 
  ******************************************************************************
7 
  * @attention
8 
  *
9 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 
  * All rights reserved.</center></h2>
11 
  *
12 
  * This software component is licensed by ST under BSD 3-Clause license,
13 
  * the "License"; You may not use this file except in compliance with the
14 
  * License. You may obtain a copy of the License at:
15 
  *                        opensource.org/licenses/BSD-3-Clause
16 
  *
17 
  ******************************************************************************
18 
  */
19 
#if defined(USE_FULL_LL_DRIVER)
20 
 
21 
/* Includes ------------------------------------------------------------------*/
22 
#include "stm32f0xx_ll_tim.h"
23 
#include "stm32f0xx_ll_bus.h"
24 
 
25 
#ifdef  USE_FULL_ASSERT
26 
#include "stm32_assert.h"
27 
#else
28 
#define assert_param(expr) ((void)0U)
29 
#endif /* USE_FULL_ASSERT */
30 
 
31 
/** @addtogroup STM32F0xx_LL_Driver
32 
  * @{
33 
  */
34 
 
35 
#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
36 
 
37 
/** @addtogroup TIM_LL
38 
  * @{
39 
  */
40 
 
41 
/* Private types -------------------------------------------------------------*/
42 
/* Private variables ---------------------------------------------------------*/
43 
/* Private constants ---------------------------------------------------------*/
44 
/* Private macros ------------------------------------------------------------*/
45 
/** @addtogroup TIM_LL_Private_Macros
46 
  * @{
47 
  */
48 
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52 
                                          || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53 
 
54 
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55 
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56 
                                            || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57 
 
58 
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 
                                     || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 
                                     || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 
                                     || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 
                                     || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 
                                     || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
66 
 
67 
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
68 
                                      || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
69 
 
70 
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
71 
                                         || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
72 
 
73 
#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
74 
                                          || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
75 
 
76 
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
77 
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
78 
                                          || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
79 
 
80 
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
81 
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
82 
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
83 
                                    || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
84 
 
85 
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
86 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
87 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
88 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
89 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
90 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
91 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
92 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
93 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
94 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
95 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
96 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
97 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
98 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
99 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
100 
                                        || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
101 
 
102 
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
103 
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
104 
                                          || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
105 
 
106 
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
107 
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
108 
                                          || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
109 
 
110 
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
111 
                                                  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
112 
 
113 
#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
114 
                                         || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
115 
 
116 
#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
117 
                                         || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
118 
 
119 
#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
120 
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
121 
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
122 
                                         || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
123 
 
124 
#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
125 
                                          || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
126 
 
127 
#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
128 
                                             || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
129 
 
130 
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
131 
                                                     || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
132 
/**
133 
  * @}
134 
  */
135 
 
136 
 
137 
/* Private function prototypes -----------------------------------------------*/
138 
/** @defgroup TIM_LL_Private_Functions TIM Private Functions
139 
  * @{
140 
  */
141 
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
145 
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
149 
/**
150 
  * @}
151 
  */
152 
 
153 
/* Exported functions --------------------------------------------------------*/
154 
/** @addtogroup TIM_LL_Exported_Functions
155 
  * @{
156 
  */
157 
 
158 
/** @addtogroup TIM_LL_EF_Init
159 
  * @{
160 
  */
161 
 
162 
/**
163 
  * @brief  Set TIMx registers to their reset values.
164 
  * @param  TIMx Timer instance
165 
  * @retval An ErrorStatus enumeration value:
166 
  *          - SUCCESS: TIMx registers are de-initialized
167 
  *          - ERROR: invalid TIMx instance
168 
  */
169 
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
170 
{
171 
  ErrorStatus result = SUCCESS;
172 
 
173 
  /* Check the parameters */
174 
  assert_param(IS_TIM_INSTANCE(TIMx));
175 
 
176 
  if (TIMx == TIM1)
177 
  {
178 
    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1);
179 
    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1);
180 
  }
181 
#if defined (TIM2)
182 
  else if (TIMx == TIM2)
183 
  {
184 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
185 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
186 
  }
6 mjames 187 
#endif /* TIM2 */
2 mjames 188 
#if defined(TIM3)
189 
  else if (TIMx == TIM3)
190 
  {
191 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
192 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
193 
  }
6 mjames 194 
#endif /* TIM3 */
2 mjames 195 
#if defined(TIM5)
196 
  else if (TIMx == TIM5)
197 
  {
198 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
199 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
200 
  }
6 mjames 201 
#endif /* TIM5 */
2 mjames 202 
#if defined (TIM6)
203 
  else if (TIMx == TIM6)
204 
  {
205 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
206 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
207 
  }
6 mjames 208 
#endif /* TIM6 */
2 mjames 209 
#if defined (TIM7)
210 
  else if (TIMx == TIM7)
211 
  {
212 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
213 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
214 
  }
6 mjames 215 
#endif /* TIM7 */
2 mjames 216 
#if defined(TIM8)
217 
  else if (TIMx == TIM8)
218 
  {
219 
    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
220 
    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
221 
  }
6 mjames 222 
#endif /* TIM8 */
2 mjames 223 
#if defined (TIM14)
224 
  else if (TIMx == TIM14)
225 
  {
226 
    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
227 
    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
228 
  }
6 mjames 229 
#endif /* TIM14 */
2 mjames 230 
#if defined (TIM15)
231 
  else if (TIMx == TIM15)
232 
  {
233 
    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15);
234 
    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15);
235 
  }
6 mjames 236 
#endif /* TIM15 */
2 mjames 237 
#if defined (TIM16)
238 
  else if (TIMx == TIM16)
239 
  {
240 
    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16);
241 
    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16);
242 
  }
6 mjames 243 
#endif /* TIM16 */
2 mjames 244 
#if defined(TIM17)
245 
  else if (TIMx == TIM17)
246 
  {
247 
    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17);
248 
    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17);
249 
  }
6 mjames 250 
#endif /* TIM17 */
2 mjames 251 
  else
252 
  {
253 
    result = ERROR;
254 
  }
255 
 
256 
  return result;
257 
}
258 
 
259 
/**
260 
  * @brief  Set the fields of the time base unit configuration data structure
261 
  *         to their default values.
262 
  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
263 
  * @retval None
264 
  */
265 
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
266 
{
267 
  /* Set the default configuration */
268 
  TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
269 
  TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
270 
  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
271 
  TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
6 mjames 272 
  TIM_InitStruct->RepetitionCounter = 0x00000000U;
2 mjames 273 
}
274 
 
275 
/**
276 
  * @brief  Configure the TIMx time base unit.
277 
  * @param  TIMx Timer Instance
6 mjames 278 
  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
279 
  *         (TIMx time base unit configuration data structure)
2 mjames 280 
  * @retval An ErrorStatus enumeration value:
281 
  *          - SUCCESS: TIMx registers are de-initialized
282 
  *          - ERROR: not applicable
283 
  */
284 
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
285 
{
286 
  uint32_t tmpcr1;
287 
 
288 
  /* Check the parameters */
289 
  assert_param(IS_TIM_INSTANCE(TIMx));
290 
  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
291 
  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
292 
 
293 
  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
294 
 
295 
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
296 
  {
297 
    /* Select the Counter Mode */
298 
    MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
299 
  }
300 
 
301 
  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
302 
  {
303 
    /* Set the clock division */
304 
    MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
305 
  }
306 
 
307 
  /* Write to TIMx CR1 */
308 
  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
309 
 
310 
  /* Set the Autoreload value */
311 
  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
312 
 
313 
  /* Set the Prescaler value */
314 
  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
315 
 
316 
  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
317 
  {
318 
    /* Set the Repetition Counter value */
319 
    LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
320 
  }
321 
 
322 
  /* Generate an update event to reload the Prescaler
323 
     and the repetition counter value (if applicable) immediately */
324 
  LL_TIM_GenerateEvent_UPDATE(TIMx);
325 
 
326 
  return SUCCESS;
327 
}
328 
 
329 
/**
330 
  * @brief  Set the fields of the TIMx output channel configuration data
331 
  *         structure to their default values.
6 mjames 332 
  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
333 
  *         (the output channel configuration data structure)
2 mjames 334 
  * @retval None
335 
  */
336 
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
337 
{
338 
  /* Set the default configuration */
339 
  TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
340 
  TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
341 
  TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
342 
  TIM_OC_InitStruct->CompareValue = 0x00000000U;
343 
  TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
344 
  TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
345 
  TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
346 
  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
347 
}
348 
 
349 
/**
350 
  * @brief  Configure the TIMx output channel.
351 
  * @param  TIMx Timer Instance
352 
  * @param  Channel This parameter can be one of the following values:
353 
  *         @arg @ref LL_TIM_CHANNEL_CH1
354 
  *         @arg @ref LL_TIM_CHANNEL_CH2
355 
  *         @arg @ref LL_TIM_CHANNEL_CH3
356 
  *         @arg @ref LL_TIM_CHANNEL_CH4
6 mjames 357 
  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
358 
  *         data structure)
2 mjames 359 
  * @retval An ErrorStatus enumeration value:
360 
  *          - SUCCESS: TIMx output channel is initialized
361 
  *          - ERROR: TIMx output channel is not initialized
362 
  */
363 
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
364 
{
365 
  ErrorStatus result = ERROR;
366 
 
367 
  switch (Channel)
368 
  {
369 
    case LL_TIM_CHANNEL_CH1:
370 
      result = OC1Config(TIMx, TIM_OC_InitStruct);
371 
      break;
372 
    case LL_TIM_CHANNEL_CH2:
373 
      result = OC2Config(TIMx, TIM_OC_InitStruct);
374 
      break;
375 
    case LL_TIM_CHANNEL_CH3:
376 
      result = OC3Config(TIMx, TIM_OC_InitStruct);
377 
      break;
378 
    case LL_TIM_CHANNEL_CH4:
379 
      result = OC4Config(TIMx, TIM_OC_InitStruct);
380 
      break;
381 
    default:
382 
      break;
383 
  }
384 
 
385 
  return result;
386 
}
387 
 
388 
/**
389 
  * @brief  Set the fields of the TIMx input channel configuration data
390 
  *         structure to their default values.
6 mjames 391 
  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
392 
  *         data structure)
2 mjames 393 
  * @retval None
394 
  */
395 
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
396 
{
397 
  /* Set the default configuration */
398 
  TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
399 
  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
400 
  TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
401 
  TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
402 
}
403 
 
404 
/**
405 
  * @brief  Configure the TIMx input channel.
406 
  * @param  TIMx Timer Instance
407 
  * @param  Channel This parameter can be one of the following values:
408 
  *         @arg @ref LL_TIM_CHANNEL_CH1
409 
  *         @arg @ref LL_TIM_CHANNEL_CH2
410 
  *         @arg @ref LL_TIM_CHANNEL_CH3
411 
  *         @arg @ref LL_TIM_CHANNEL_CH4
6 mjames 412 
  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
413 
  *         structure)
2 mjames 414 
  * @retval An ErrorStatus enumeration value:
415 
  *          - SUCCESS: TIMx output channel is initialized
416 
  *          - ERROR: TIMx output channel is not initialized
417 
  */
418 
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
419 
{
420 
  ErrorStatus result = ERROR;
421 
 
422 
  switch (Channel)
423 
  {
424 
    case LL_TIM_CHANNEL_CH1:
425 
      result = IC1Config(TIMx, TIM_IC_InitStruct);
426 
      break;
427 
    case LL_TIM_CHANNEL_CH2:
428 
      result = IC2Config(TIMx, TIM_IC_InitStruct);
429 
      break;
430 
    case LL_TIM_CHANNEL_CH3:
431 
      result = IC3Config(TIMx, TIM_IC_InitStruct);
432 
      break;
433 
    case LL_TIM_CHANNEL_CH4:
434 
      result = IC4Config(TIMx, TIM_IC_InitStruct);
435 
      break;
436 
    default:
437 
      break;
438 
  }
439 
 
440 
  return result;
441 
}
442 
 
443 
/**
444 
  * @brief  Fills each TIM_EncoderInitStruct field with its default value
6 mjames 445 
  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
446 
  *         configuration data structure)
2 mjames 447 
  * @retval None
448 
  */
449 
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
450 
{
451 
  /* Set the default configuration */
452 
  TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
453 
  TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
454 
  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
455 
  TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
456 
  TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
457 
  TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
458 
  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
459 
  TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
460 
  TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
461 
}
462 
 
463 
/**
464 
  * @brief  Configure the encoder interface of the timer instance.
465 
  * @param  TIMx Timer Instance
6 mjames 466 
  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
467 
  *         configuration data structure)
2 mjames 468 
  * @retval An ErrorStatus enumeration value:
469 
  *          - SUCCESS: TIMx registers are de-initialized
470 
  *          - ERROR: not applicable
471 
  */
472 
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
473 
{
474 
  uint32_t tmpccmr1;
475 
  uint32_t tmpccer;
476 
 
477 
  /* Check the parameters */
478 
  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
479 
  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
480 
  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
481 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
482 
  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
483 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
484 
  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
485 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
486 
  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
487 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
488 
 
489 
  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
490 
  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
491 
 
492 
  /* Get the TIMx CCMR1 register value */
493 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
494 
 
495 
  /* Get the TIMx CCER register value */
496 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
497 
 
498 
  /* Configure TI1 */
499 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
500 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
501 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
502 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
503 
 
504 
  /* Configure TI2 */
505 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
506 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
507 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
508 
  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
509 
 
510 
  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
511 
  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
512 
  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
513 
  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
514 
  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
515 
 
516 
  /* Set encoder mode */
517 
  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
518 
 
519 
  /* Write to TIMx CCMR1 */
520 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
521 
 
522 
  /* Write to TIMx CCER */
523 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
524 
 
525 
  return SUCCESS;
526 
}
527 
 
528 
/**
529 
  * @brief  Set the fields of the TIMx Hall sensor interface configuration data
530 
  *         structure to their default values.
6 mjames 531 
  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
532 
  *         configuration data structure)
2 mjames 533 
  * @retval None
534 
  */
535 
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
536 
{
537 
  /* Set the default configuration */
538 
  TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
539 
  TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
540 
  TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
541 
  TIM_HallSensorInitStruct->CommutationDelay  = 0U;
542 
}
543 
 
544 
/**
545 
  * @brief  Configure the Hall sensor interface of the timer instance.
546 
  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
547 
  *       to the TI1 input channel
548 
  * @note TIMx slave mode controller is configured in reset mode.
549 
          Selected internal trigger is TI1F_ED.
550 
  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
551 
  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
552 
  *       between 2 changes on the inputs. It gives information about motor speed.
553 
  * @note Channel 2 is configured in output PWM 2 mode.
554 
  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
555 
  * @note OC2REF is selected as trigger output on TRGO.
556 
  * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
557 
  *       when TIMx operates in Hall sensor interface mode.
558 
  * @param  TIMx Timer Instance
6 mjames 559 
  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
560 
  *         interface configuration data structure)
2 mjames 561 
  * @retval An ErrorStatus enumeration value:
562 
  *          - SUCCESS: TIMx registers are de-initialized
563 
  *          - ERROR: not applicable
564 
  */
565 
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
566 
{
567 
  uint32_t tmpcr2;
568 
  uint32_t tmpccmr1;
569 
  uint32_t tmpccer;
570 
  uint32_t tmpsmcr;
571 
 
572 
  /* Check the parameters */
573 
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
574 
  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
575 
  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
576 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
577 
 
578 
  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
579 
  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
580 
 
581 
  /* Get the TIMx CR2 register value */
582 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
583 
 
584 
  /* Get the TIMx CCMR1 register value */
585 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
586 
 
587 
  /* Get the TIMx CCER register value */
588 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
589 
 
590 
  /* Get the TIMx SMCR register value */
591 
  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
592 
 
593 
  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
594 
  tmpcr2 |= TIM_CR2_TI1S;
595 
 
596 
  /* OC2REF signal is used as trigger output (TRGO) */
597 
  tmpcr2 |= LL_TIM_TRGO_OC2REF;
598 
 
599 
  /* Configure the slave mode controller */
600 
  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
601 
  tmpsmcr |= LL_TIM_TS_TI1F_ED;
602 
  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
603 
 
604 
  /* Configure input channel 1 */
605 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
606 
  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
607 
  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
608 
  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
609 
 
610 
  /* Configure input channel 2 */
611 
  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
612 
  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
613 
 
614 
  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
615 
  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
616 
  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
617 
  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
618 
 
619 
  /* Write to TIMx CR2 */
620 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
621 
 
622 
  /* Write to TIMx SMCR */
623 
  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
624 
 
625 
  /* Write to TIMx CCMR1 */
626 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
627 
 
628 
  /* Write to TIMx CCER */
629 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
630 
 
631 
  /* Write to TIMx CCR2 */
632 
  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
633 
 
634 
  return SUCCESS;
635 
}
636 
 
637 
/**
638 
  * @brief  Set the fields of the Break and Dead Time configuration data structure
639 
  *         to their default values.
6 mjames 640 
  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
641 
  *         data structure)
2 mjames 642 
  * @retval None
643 
  */
644 
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
645 
{
646 
  /* Set the default configuration */
647 
  TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
648 
  TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
649 
  TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
650 
  TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
651 
  TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
652 
  TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
653 
  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
654 
}
655 
 
656 
/**
657 
  * @brief  Configure the Break and Dead Time feature of the timer instance.
658 
  * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
659 
  *  depending on the LOCK configuration, it can be necessary to configure all of
660 
  *  them during the first write access to the TIMx_BDTR register.
661 
  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
662 
  *       a timer instance provides a break input.
663 
  * @param  TIMx Timer Instance
6 mjames 664 
  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
665 
  *         data structure)
2 mjames 666 
  * @retval An ErrorStatus enumeration value:
667 
  *          - SUCCESS: Break and Dead Time is initialized
668 
  *          - ERROR: not applicable
669 
  */
670 
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
671 
{
672 
  uint32_t tmpbdtr = 0;
673 
 
674 
  /* Check the parameters */
675 
  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
676 
  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
677 
  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
678 
  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
679 
  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
680 
  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
681 
  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
682 
 
683 
  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
684 
  the OSSI State, the dead time value and the Automatic Output Enable Bit */
685 
 
686 
  /* Set the BDTR bits */
687 
  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
688 
  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
689 
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
690 
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
691 
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
692 
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
693 
  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
694 
  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
695 
 
696 
  /* Set TIMx_BDTR */
697 
  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
698 
 
699 
  return SUCCESS;
700 
}
701 
/**
702 
  * @}
703 
  */
704 
 
705 
/**
706 
  * @}
707 
  */
708 
 
709 
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
710 
  *  @brief   Private functions
711 
  * @{
712 
  */
713 
/**
714 
  * @brief  Configure the TIMx output channel 1.
715 
  * @param  TIMx Timer Instance
716 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
717 
  * @retval An ErrorStatus enumeration value:
718 
  *          - SUCCESS: TIMx registers are de-initialized
719 
  *          - ERROR: not applicable
720 
  */
721 
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
722 
{
723 
  uint32_t tmpccmr1;
724 
  uint32_t tmpccer;
725 
  uint32_t tmpcr2;
726 
 
727 
  /* Check the parameters */
728 
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
729 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
730 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
731 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
732 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
733 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
734 
 
735 
  /* Disable the Channel 1: Reset the CC1E Bit */
736 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
737 
 
738 
  /* Get the TIMx CCER register value */
739 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
740 
 
741 
  /* Get the TIMx CR2 register value */
742 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
743 
 
744 
  /* Get the TIMx CCMR1 register value */
745 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
746 
 
747 
  /* Reset Capture/Compare selection Bits */
748 
  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
749 
 
750 
  /* Set the Output Compare Mode */
751 
  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
752 
 
753 
  /* Set the Output Compare Polarity */
754 
  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
755 
 
756 
  /* Set the Output State */
757 
  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
758 
 
759 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
760 
  {
761 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
762 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
763 
 
764 
    /* Set the complementary output Polarity */
765 
    MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
766 
 
767 
    /* Set the complementary output State */
768 
    MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
769 
 
770 
    /* Set the Output Idle state */
771 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
772 
 
773 
    /* Set the complementary output Idle state */
774 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
775 
  }
776 
 
777 
  /* Write to TIMx CR2 */
778 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
779 
 
780 
  /* Write to TIMx CCMR1 */
781 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
782 
 
783 
  /* Set the Capture Compare Register value */
784 
  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
785 
 
786 
  /* Write to TIMx CCER */
787 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
788 
 
789 
  return SUCCESS;
790 
}
791 
 
792 
/**
793 
  * @brief  Configure the TIMx output channel 2.
794 
  * @param  TIMx Timer Instance
795 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
796 
  * @retval An ErrorStatus enumeration value:
797 
  *          - SUCCESS: TIMx registers are de-initialized
798 
  *          - ERROR: not applicable
799 
  */
800 
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
801 
{
802 
  uint32_t tmpccmr1;
803 
  uint32_t tmpccer;
804 
  uint32_t tmpcr2;
805 
 
806 
  /* Check the parameters */
807 
  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
808 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
809 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
810 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
811 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
812 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
813 
 
814 
  /* Disable the Channel 2: Reset the CC2E Bit */
815 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
816 
 
817 
  /* Get the TIMx CCER register value */
818 
  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
819 
 
820 
  /* Get the TIMx CR2 register value */
821 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
822 
 
823 
  /* Get the TIMx CCMR1 register value */
824 
  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
825 
 
826 
  /* Reset Capture/Compare selection Bits */
827 
  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
828 
 
829 
  /* Select the Output Compare Mode */
830 
  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
831 
 
832 
  /* Set the Output Compare Polarity */
833 
  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
834 
 
835 
  /* Set the Output State */
836 
  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
837 
 
838 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
839 
  {
840 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
841 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
842 
 
843 
    /* Set the complementary output Polarity */
844 
    MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
845 
 
846 
    /* Set the complementary output State */
847 
    MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
848 
 
849 
    /* Set the Output Idle state */
850 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
851 
 
852 
    /* Set the complementary output Idle state */
853 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
854 
  }
855 
 
856 
  /* Write to TIMx CR2 */
857 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
858 
 
859 
  /* Write to TIMx CCMR1 */
860 
  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
861 
 
862 
  /* Set the Capture Compare Register value */
863 
  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
864 
 
865 
  /* Write to TIMx CCER */
866 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
867 
 
868 
  return SUCCESS;
869 
}
870 
 
871 
/**
872 
  * @brief  Configure the TIMx output channel 3.
873 
  * @param  TIMx Timer Instance
874 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
875 
  * @retval An ErrorStatus enumeration value:
876 
  *          - SUCCESS: TIMx registers are de-initialized
877 
  *          - ERROR: not applicable
878 
  */
879 
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
880 
{
881 
  uint32_t tmpccmr2;
882 
  uint32_t tmpccer;
883 
  uint32_t tmpcr2;
884 
 
885 
  /* Check the parameters */
886 
  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
887 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
888 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
889 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
890 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
891 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
892 
 
893 
  /* Disable the Channel 3: Reset the CC3E Bit */
894 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
895 
 
896 
  /* Get the TIMx CCER register value */
897 
  tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
898 
 
899 
  /* Get the TIMx CR2 register value */
900 
  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
901 
 
902 
  /* Get the TIMx CCMR2 register value */
903 
  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
904 
 
905 
  /* Reset Capture/Compare selection Bits */
906 
  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
907 
 
908 
  /* Select the Output Compare Mode */
909 
  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
910 
 
911 
  /* Set the Output Compare Polarity */
912 
  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
913 
 
914 
  /* Set the Output State */
915 
  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
916 
 
917 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
918 
  {
919 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
920 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
921 
 
922 
    /* Set the complementary output Polarity */
923 
    MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
924 
 
925 
    /* Set the complementary output State */
926 
    MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
927 
 
928 
    /* Set the Output Idle state */
929 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
930 
 
931 
    /* Set the complementary output Idle state */
932 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
933 
  }
934 
 
935 
  /* Write to TIMx CR2 */
936 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
937 
 
938 
  /* Write to TIMx CCMR2 */
939 
  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
940 
 
941 
  /* Set the Capture Compare Register value */
942 
  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
943 
 
944 
  /* Write to TIMx CCER */
945 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
946 
 
947 
  return SUCCESS;
948 
}
949 
 
950 
/**
951 
  * @brief  Configure the TIMx output channel 4.
952 
  * @param  TIMx Timer Instance
953 
  * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
954 
  * @retval An ErrorStatus enumeration value:
955 
  *          - SUCCESS: TIMx registers are de-initialized
956 
  *          - ERROR: not applicable
957 
  */
958 
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
959 
{
960 
  uint32_t tmpccmr2;
961 
  uint32_t tmpccer;
962 
  uint32_t tmpcr2;
963 
 
964 
  /* Check the parameters */
965 
  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
966 
  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
967 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
968 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
969 
  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
970 
  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
971 
 
972 
  /* Disable the Channel 4: Reset the CC4E Bit */
973 
  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
974 
 
975 
  /* Get the TIMx CCER register value */
976 
  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
977 
 
978 
  /* Get the TIMx CR2 register value */
979 
  tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
980 
 
981 
  /* Get the TIMx CCMR2 register value */
982 
  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
983 
 
984 
  /* Reset Capture/Compare selection Bits */
985 
  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
986 
 
987 
  /* Select the Output Compare Mode */
988 
  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
989 
 
990 
  /* Set the Output Compare Polarity */
991 
  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
992 
 
993 
  /* Set the Output State */
994 
  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
995 
 
996 
  if (IS_TIM_BREAK_INSTANCE(TIMx))
997 
  {
998 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
999 
    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1000 
 
1001 
    /* Set the Output Idle state */
1002 
    MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1003 
  }
1004 
 
1005 
  /* Write to TIMx CR2 */
1006 
  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1007 
 
1008 
  /* Write to TIMx CCMR2 */
1009 
  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1010 
 
1011 
  /* Set the Capture Compare Register value */
1012 
  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1013 
 
1014 
  /* Write to TIMx CCER */
1015 
  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1016 
 
1017 
  return SUCCESS;
1018 
}
1019 
 
1020 
 
1021 
/**
1022 
  * @brief  Configure the TIMx input channel 1.
1023 
  * @param  TIMx Timer Instance
1024 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1025 
  * @retval An ErrorStatus enumeration value:
1026 
  *          - SUCCESS: TIMx registers are de-initialized
1027 
  *          - ERROR: not applicable
1028 
  */
1029 
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1030 
{
1031 
  /* Check the parameters */
1032 
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1033 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1034 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1035 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1036 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1037 
 
1038 
  /* Disable the Channel 1: Reset the CC1E Bit */
1039 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1040 
 
1041 
  /* Select the Input and set the filter and the prescaler value */
1042 
  MODIFY_REG(TIMx->CCMR1,
1043 
             (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1044 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1045 
 
1046 
  /* Select the Polarity and set the CC1E Bit */
1047 
  MODIFY_REG(TIMx->CCER,
1048 
             (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1049 
             (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1050 
 
1051 
  return SUCCESS;
1052 
}
1053 
 
1054 
/**
1055 
  * @brief  Configure the TIMx input channel 2.
1056 
  * @param  TIMx Timer Instance
1057 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1058 
  * @retval An ErrorStatus enumeration value:
1059 
  *          - SUCCESS: TIMx registers are de-initialized
1060 
  *          - ERROR: not applicable
1061 
  */
1062 
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1063 
{
1064 
  /* Check the parameters */
1065 
  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1066 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1067 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1068 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1069 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1070 
 
1071 
  /* Disable the Channel 2: Reset the CC2E Bit */
1072 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1073 
 
1074 
  /* Select the Input and set the filter and the prescaler value */
1075 
  MODIFY_REG(TIMx->CCMR1,
1076 
             (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1077 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1078 
 
1079 
  /* Select the Polarity and set the CC2E Bit */
1080 
  MODIFY_REG(TIMx->CCER,
1081 
             (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1082 
             ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1083 
 
1084 
  return SUCCESS;
1085 
}
1086 
 
1087 
/**
1088 
  * @brief  Configure the TIMx input channel 3.
1089 
  * @param  TIMx Timer Instance
1090 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1091 
  * @retval An ErrorStatus enumeration value:
1092 
  *          - SUCCESS: TIMx registers are de-initialized
1093 
  *          - ERROR: not applicable
1094 
  */
1095 
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1096 
{
1097 
  /* Check the parameters */
1098 
  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1099 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1100 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1101 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1102 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1103 
 
1104 
  /* Disable the Channel 3: Reset the CC3E Bit */
1105 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1106 
 
1107 
  /* Select the Input and set the filter and the prescaler value */
1108 
  MODIFY_REG(TIMx->CCMR2,
1109 
             (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1110 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1111 
 
1112 
  /* Select the Polarity and set the CC3E Bit */
1113 
  MODIFY_REG(TIMx->CCER,
1114 
             (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1115 
             ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1116 
 
1117 
  return SUCCESS;
1118 
}
1119 
 
1120 
/**
1121 
  * @brief  Configure the TIMx input channel 4.
1122 
  * @param  TIMx Timer Instance
1123 
  * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1124 
  * @retval An ErrorStatus enumeration value:
1125 
  *          - SUCCESS: TIMx registers are de-initialized
1126 
  *          - ERROR: not applicable
1127 
  */
1128 
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1129 
{
1130 
  /* Check the parameters */
1131 
  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1132 
  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1133 
  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1134 
  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1135 
  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1136 
 
1137 
  /* Disable the Channel 4: Reset the CC4E Bit */
1138 
  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1139 
 
1140 
  /* Select the Input and set the filter and the prescaler value */
1141 
  MODIFY_REG(TIMx->CCMR2,
1142 
             (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1143 
             (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1144 
 
1145 
  /* Select the Polarity and set the CC2E Bit */
1146 
  MODIFY_REG(TIMx->CCER,
1147 
             (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1148 
             ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1149 
 
1150 
  return SUCCESS;
1151 
}
1152 
 
1153 
 
1154 
/**
1155 
  * @}
1156 
  */
1157 
 
1158 
/**
1159 
  * @}
1160 
  */
1161 
 
1162 
#endif /* TIM1 || TIM2 || TIM3  || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
1163 
 
1164 
/**
1165 
  * @}
1166 
  */
1167 
 
1168 
#endif /* USE_FULL_LL_DRIVER */
1169 
 
1170 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/