WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_dma.c
		4	* @author MCD Application Team
		5	* @brief DMA LL module driver.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	#if defined(USE_FULL_LL_DRIVER)
		21
		22	/* Includes ------------------------------------------------------------------*/
		23	#include "stm32f0xx_ll_dma.h"
		24	#include "stm32f0xx_ll_bus.h"
		25	#ifdef USE_FULL_ASSERT
		26	#include "stm32_assert.h"
		27	#else
		28	#define assert_param(expr) ((void)0U)
		29	#endif
		30
		31	/** @addtogroup STM32F0xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (DMA1) \|\| defined (DMA2)
		36
		37	/** @defgroup DMA_LL DMA
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/* Private constants ---------------------------------------------------------*/
		44	/* Private macros ------------------------------------------------------------*/
		45	/** @addtogroup DMA_LL_Private_Macros
		46	* @{
		47	*/
		48	#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) \|\| \
		49	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) \|\| \
		50	((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
		51
		52	#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) \|\| \
		53	((__VALUE__) == LL_DMA_MODE_CIRCULAR))
		54
		55	#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) \|\| \
		56	((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
		57
		58	#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) \|\| \
		59	((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
		60
		61	#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) \|\| \
		62	((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) \|\| \
		63	((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
		64
		65	#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) \|\| \
		66	((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) \|\| \
		67	((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
		68
		69	#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
		70
		71	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
		72	#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) \|\| \
		73	((__VALUE__) == LL_DMA_REQUEST_1) \|\| \
		74	((__VALUE__) == LL_DMA_REQUEST_2) \|\| \
		75	((__VALUE__) == LL_DMA_REQUEST_3) \|\| \
		76	((__VALUE__) == LL_DMA_REQUEST_4) \|\| \
		77	((__VALUE__) == LL_DMA_REQUEST_5) \|\| \
		78	((__VALUE__) == LL_DMA_REQUEST_6) \|\| \
		79	((__VALUE__) == LL_DMA_REQUEST_7) \|\| \
		80	((__VALUE__) == LL_DMA_REQUEST_8) \|\| \
		81	((__VALUE__) == LL_DMA_REQUEST_9) \|\| \
		82	((__VALUE__) == LL_DMA_REQUEST_10) \|\| \
		83	((__VALUE__) == LL_DMA_REQUEST_11) \|\| \
		84	((__VALUE__) == LL_DMA_REQUEST_12) \|\| \
		85	((__VALUE__) == LL_DMA_REQUEST_13) \|\| \
		86	((__VALUE__) == LL_DMA_REQUEST_14) \|\| \
		87	((__VALUE__) == LL_DMA_REQUEST_15))
		88	#endif
		89
		90	#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) \|\| \
		91	((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) \|\| \
		92	((__VALUE__) == LL_DMA_PRIORITY_HIGH) \|\| \
		93	((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
		94
		95	#if defined (DMA2)
		96	#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
		97	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		98	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		99	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		100	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		101	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		102	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		103	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		104	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
		105	(((INSTANCE) == DMA2) && \
		106	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		107	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		108	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		109	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		110	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		111	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		112	((CHANNEL) == LL_DMA_CHANNEL_7))))
		113	#else
		114	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		115	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		116	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		117	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		118	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		119	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		120	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		121	((CHANNEL) == LL_DMA_CHANNEL_7))) \|\| \
		122	(((INSTANCE) == DMA2) && \
		123	(((CHANNEL) == LL_DMA_CHANNEL_1) \|\| \
		124	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		125	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		126	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		127	((CHANNEL) == LL_DMA_CHANNEL_5))))
		128	#endif
		129	#else
		130	#if defined(DMA1_Channel6) && defined(DMA1_Channel7)
		131	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		132	(((CHANNEL) == LL_DMA_CHANNEL_1)\|\| \
		133	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		134	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		135	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		136	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		137	((CHANNEL) == LL_DMA_CHANNEL_6) \|\| \
		138	((CHANNEL) == LL_DMA_CHANNEL_7))))
		139	#elif defined (DMA1_Channel6)
		140	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		141	(((CHANNEL) == LL_DMA_CHANNEL_1)\|\| \
		142	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		143	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		144	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		145	((CHANNEL) == LL_DMA_CHANNEL_5) \|\| \
		146	((CHANNEL) == LL_DMA_CHANNEL_6))))
		147	#else
		148	#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
		149	(((CHANNEL) == LL_DMA_CHANNEL_1)\|\| \
		150	((CHANNEL) == LL_DMA_CHANNEL_2) \|\| \
		151	((CHANNEL) == LL_DMA_CHANNEL_3) \|\| \
		152	((CHANNEL) == LL_DMA_CHANNEL_4) \|\| \
		153	((CHANNEL) == LL_DMA_CHANNEL_5))))
		154	#endif /* DMA1_Channel6 && DMA1_Channel7 */
		155	#endif
		156	/**
		157	* @}
		158	*/
		159
		160	/* Private function prototypes -----------------------------------------------*/
		161
		162	/* Exported functions --------------------------------------------------------*/
		163	/** @addtogroup DMA_LL_Exported_Functions
		164	* @{
		165	*/
		166
		167	/** @addtogroup DMA_LL_EF_Init
		168	* @{
		169	*/
		170
		171	/**
		172	* @brief De-initialize the DMA registers to their default reset values.
		173	* @param DMAx DMAx Instance
		174	* @param Channel This parameter can be one of the following values:
		175	* @arg @ref LL_DMA_CHANNEL_1
		176	* @arg @ref LL_DMA_CHANNEL_2
		177	* @arg @ref LL_DMA_CHANNEL_3
		178	* @arg @ref LL_DMA_CHANNEL_4
		179	* @arg @ref LL_DMA_CHANNEL_5
		180	* @arg @ref LL_DMA_CHANNEL_6 (*)
		181	* @arg @ref LL_DMA_CHANNEL_7 (*)
		182	*
		183	* (*) value not defined in all devices
		184	* @retval An ErrorStatus enumeration value:
		185	* - SUCCESS: DMA registers are de-initialized
		186	* - ERROR: DMA registers are not de-initialized
		187	*/
		188	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
		189	{
		190	DMA_Channel_TypeDef tmp = (DMA_Channel_TypeDef )DMA1_Channel1;
		191	ErrorStatus status = SUCCESS;
		192
		193	/* Check the DMA Instance DMAx and Channel parameters*/
		194	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
		195
		196	tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
		197
		198	/* Disable the selected DMAx_Channely */
		199	CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
		200
		201	/* Reset DMAx_Channely control register */
		202	LL_DMA_WriteReg(tmp, CCR, 0U);
		203
		204	/* Reset DMAx_Channely remaining bytes register */
		205	LL_DMA_WriteReg(tmp, CNDTR, 0U);
		206
		207	/* Reset DMAx_Channely peripheral address register */
		208	LL_DMA_WriteReg(tmp, CPAR, 0U);
		209
		210	/* Reset DMAx_Channely memory address register */
		211	LL_DMA_WriteReg(tmp, CMAR, 0U);
		212
		213	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
		214	/* Reset Request register field for DMAx Channel */
		215	LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
		216	#endif
		217
		218	if (Channel == LL_DMA_CHANNEL_1)
		219	{
		220	/* Reset interrupt pending bits for DMAx Channel1 */
		221	LL_DMA_ClearFlag_GI1(DMAx);
		222	}
		223	else if (Channel == LL_DMA_CHANNEL_2)
		224	{
		225	/* Reset interrupt pending bits for DMAx Channel2 */
		226	LL_DMA_ClearFlag_GI2(DMAx);
		227	}
		228	else if (Channel == LL_DMA_CHANNEL_3)
		229	{
		230	/* Reset interrupt pending bits for DMAx Channel3 */
		231	LL_DMA_ClearFlag_GI3(DMAx);
		232	}
		233	else if (Channel == LL_DMA_CHANNEL_4)
		234	{
		235	/* Reset interrupt pending bits for DMAx Channel4 */
		236	LL_DMA_ClearFlag_GI4(DMAx);
		237	}
		238	else if (Channel == LL_DMA_CHANNEL_5)
		239	{
		240	/* Reset interrupt pending bits for DMAx Channel5 */
		241	LL_DMA_ClearFlag_GI5(DMAx);
		242	}
		243
		244	#if defined(DMA1_Channel6)
		245	else if (Channel == LL_DMA_CHANNEL_6)
		246	{
		247	/* Reset interrupt pending bits for DMAx Channel6 */
		248	LL_DMA_ClearFlag_GI6(DMAx);
		249	}
		250	#endif
		251	#if defined(DMA1_Channel7)
		252	else if (Channel == LL_DMA_CHANNEL_7)
		253	{
		254	/* Reset interrupt pending bits for DMAx Channel7 */
		255	LL_DMA_ClearFlag_GI7(DMAx);
		256	}
		257	#endif
		258	else
		259	{
		260	status = ERROR;
		261	}
		262
		263	return status;
		264	}
		265
		266	/**
		267	* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
		268	* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
		269	* @arg @ref __LL_DMA_GET_INSTANCE
		270	* @arg @ref __LL_DMA_GET_CHANNEL
		271	* @param DMAx DMAx Instance
		272	* @param Channel This parameter can be one of the following values:
		273	* @arg @ref LL_DMA_CHANNEL_1
		274	* @arg @ref LL_DMA_CHANNEL_2
		275	* @arg @ref LL_DMA_CHANNEL_3
		276	* @arg @ref LL_DMA_CHANNEL_4
		277	* @arg @ref LL_DMA_CHANNEL_5
		278	* @arg @ref LL_DMA_CHANNEL_6 (*)
		279	* @arg @ref LL_DMA_CHANNEL_7 (*)
		280	*
		281	* (*) value not defined in all devices
		282	* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
		283	* @retval An ErrorStatus enumeration value:
		284	* - SUCCESS: DMA registers are initialized
		285	* - ERROR: Not applicable
		286	*/
		287	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Channel, LL_DMA_InitTypeDef DMA_InitStruct)
		288	{
		289	/* Check the DMA Instance DMAx and Channel parameters*/
		290	assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
		291
		292	/* Check the DMA parameters from DMA_InitStruct */
		293	assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
		294	assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
		295	assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
		296	assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
		297	assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
		298	assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
		299	assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
		300	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
		301	assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
		302	#endif
		303	assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
		304
		305	/*---------------------------- DMAx CCR Configuration ------------------------
		306	* Configure DMAx_Channely: data transfer direction, data transfer mode,
		307	* peripheral and memory increment mode,
		308	* data size alignment and priority level with parameters :
		309	* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
		310	* - Mode: DMA_CCR_CIRC bit
		311	* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
		312	* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
		313	* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
		314	* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
		315	* - Priority: DMA_CCR_PL[1:0] bits
		316	*/
		317	LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction \| \
		318	DMA_InitStruct->Mode \| \
		319	DMA_InitStruct->PeriphOrM2MSrcIncMode \| \
		320	DMA_InitStruct->MemoryOrM2MDstIncMode \| \
		321	DMA_InitStruct->PeriphOrM2MSrcDataSize \| \
		322	DMA_InitStruct->MemoryOrM2MDstDataSize \| \
		323	DMA_InitStruct->Priority);
		324
		325	/*-------------------------- DMAx CMAR Configuration -------------------------
		326	* Configure the memory or destination base address with parameter :
		327	* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
		328	*/
		329	LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
		330
		331	/*-------------------------- DMAx CPAR Configuration -------------------------
		332	* Configure the peripheral or source base address with parameter :
		333	* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
		334	*/
		335	LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
		336
		337	/*--------------------------- DMAx CNDTR Configuration -----------------------
		338	* Configure the peripheral base address with parameter :
		339	* - NbData: DMA_CNDTR_NDT[15:0] bits
		340	*/
		341	LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
		342
		343	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
		344	/*--------------------------- DMAx CSELR Configuration -----------------------
		345	* Configure the DMA request for DMA instance on Channel x with parameter :
		346	* - PeriphRequest: DMA_CSELR[31:0] bits
		347	*/
		348	LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
		349	#endif
		350
		351	return SUCCESS;
		352	}
		353
		354	/**
		355	* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
		356	* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
		357	* @retval None
		358	*/
		359	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
		360	{
		361	/* Set DMA_InitStruct fields to default values */
		362	DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
		363	DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
		364	DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
		365	DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
		366	DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
		367	DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
		368	DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
		369	DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
		370	DMA_InitStruct->NbData = 0x00000000U;
		371	#if (defined(DMA1_CSELR_DEFAULT)\|\|defined(DMA2_CSELR_DEFAULT))
		372	DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
		373	#endif
		374	DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
		375	}
		376
		377	/**
		378	* @}
		379	*/
		380
		381	/**
		382	* @}
		383	*/
		384
		385	/**
		386	* @}
		387	*/
		388
		389	#endif /* DMA1 \|\| DMA2 */
		390
		391	/**
		392	* @}
		393	*/
		394
		395	#endif /* USE_FULL_LL_DRIVER */
		396
		397	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_dma.c – Rev 2