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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_ll_adc.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief ADC LL module driver |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | #if defined(USE_FULL_LL_DRIVER) |
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| 21 | |||
| 22 | /* Includes ------------------------------------------------------------------*/ |
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| 23 | #include "stm32f0xx_ll_adc.h" |
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| 24 | #include "stm32f0xx_ll_bus.h" |
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| 25 | |||
| 26 | #ifdef USE_FULL_ASSERT |
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| 27 | #include "stm32_assert.h" |
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| 28 | #else |
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| 29 | #define assert_param(expr) ((void)0U) |
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| 30 | #endif |
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| 31 | |||
| 32 | /** @addtogroup STM32F0xx_LL_Driver |
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| 33 | * @{ |
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| 34 | */ |
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| 35 | |||
| 36 | #if defined (ADC1) |
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| 37 | |||
| 38 | /** @addtogroup ADC_LL ADC |
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| 39 | * @{ |
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| 40 | */ |
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| 41 | |||
| 42 | /* Private types -------------------------------------------------------------*/ |
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| 43 | /* Private variables ---------------------------------------------------------*/ |
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| 44 | /* Private constants ---------------------------------------------------------*/ |
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| 45 | /** @addtogroup ADC_LL_Private_Constants |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | |||
| 49 | /* Definitions of ADC hardware constraints delays */ |
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| 50 | /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ |
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| 51 | /* not timeout values: */ |
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| 52 | /* Timeout values for ADC operations are dependent to device clock */ |
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| 53 | /* configuration (system clock versus ADC clock), */ |
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| 54 | /* and therefore must be defined in user application. */ |
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| 55 | /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ |
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| 56 | /* values definition. */ |
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| 57 | /* Note: ADC timeout values are defined here in CPU cycles to be independent */ |
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| 58 | /* of device clock setting. */ |
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| 59 | /* In user application, ADC timeout values should be defined with */ |
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| 60 | /* temporal values, in function of device clock settings. */ |
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| 61 | /* Highest ratio CPU clock frequency vs ADC clock frequency: */ |
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| 62 | /* - ADC clock from synchronous clock with AHB prescaler 512, */ |
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| 63 | /* APB prescaler 16, ADC prescaler 4. */ |
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| 64 | /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */ |
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| 65 | /* with highest ratio CPU clock frequency vs HSI clock frequency: */ |
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| 66 | /* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */ |
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| 67 | /* Unit: CPU cycles. */ |
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| 68 | #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) |
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| 69 | #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) |
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| 70 | #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) |
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| 71 | |||
| 72 | /** |
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| 73 | * @} |
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| 74 | */ |
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| 75 | |||
| 76 | /* Private macros ------------------------------------------------------------*/ |
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| 77 | |||
| 78 | /** @addtogroup ADC_LL_Private_Macros |
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| 79 | * @{ |
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| 80 | */ |
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| 81 | |||
| 82 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 83 | /* common to several ADC instances. */ |
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| 84 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 85 | /* ADC instance. */ |
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| 86 | #define IS_LL_ADC_CLOCK(__CLOCK__) \ |
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| 87 | ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ |
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| 88 | || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ |
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| 89 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \ |
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| 90 | ) |
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| 91 | |||
| 92 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
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| 93 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
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| 94 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
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| 95 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
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| 96 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
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| 97 | ) |
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| 98 | |||
| 99 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
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| 100 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
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| 101 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
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| 102 | ) |
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| 103 | |||
| 104 | #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ |
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| 105 | ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ |
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| 106 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
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| 107 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \ |
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| 108 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \ |
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| 109 | ) |
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| 110 | |||
| 111 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
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| 112 | /* ADC group regular */ |
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| 113 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
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| 114 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
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| 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ |
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| 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \ |
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| 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
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| 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
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| 119 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ |
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| 120 | ) |
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| 121 | |||
| 122 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
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| 123 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
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| 124 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
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| 125 | ) |
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| 126 | |||
| 127 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
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| 128 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
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| 129 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
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| 130 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
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| 131 | ) |
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| 132 | |||
| 133 | #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ |
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| 134 | ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ |
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| 135 | || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ |
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| 136 | ) |
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| 137 | |||
| 138 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
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| 139 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
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| 140 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
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| 141 | ) |
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| 142 | |||
| 143 | /** |
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| 144 | * @} |
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| 145 | */ |
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| 146 | |||
| 147 | |||
| 148 | /* Private function prototypes -----------------------------------------------*/ |
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| 149 | |||
| 150 | /* Exported functions --------------------------------------------------------*/ |
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| 151 | /** @addtogroup ADC_LL_Exported_Functions |
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| 152 | * @{ |
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| 153 | */ |
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| 154 | |||
| 155 | /** @addtogroup ADC_LL_EF_Init |
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| 156 | * @{ |
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| 157 | */ |
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| 158 | |||
| 159 | /** |
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| 160 | * @brief De-initialize registers of all ADC instances belonging to |
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| 161 | * the same ADC common instance to their default reset values. |
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| 162 | * @note This function is performing a hard reset, using high level |
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| 163 | * clock source RCC ADC reset. |
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| 164 | * @param ADCxy_COMMON ADC common instance |
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| 165 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
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| 166 | * @retval An ErrorStatus enumeration value: |
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| 167 | * - SUCCESS: ADC common registers are de-initialized |
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| 168 | * - ERROR: not applicable |
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| 169 | */ |
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| 170 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
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| 171 | { |
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| 172 | /* Check the parameters */ |
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| 173 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
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| 174 | |||
| 175 | /* Force reset of ADC clock (core clock) */ |
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| 176 | LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1); |
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| 177 | |||
| 178 | /* Release reset of ADC clock (core clock) */ |
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| 179 | LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1); |
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| 180 | |||
| 181 | return SUCCESS; |
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| 182 | } |
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| 183 | |||
| 184 | |||
| 185 | /** |
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| 186 | * @brief De-initialize registers of the selected ADC instance |
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| 187 | * to their default reset values. |
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| 188 | * @note To reset all ADC instances quickly (perform a hard reset), |
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| 189 | * use function @ref LL_ADC_CommonDeInit(). |
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| 190 | * @note If this functions returns error status, it means that ADC instance |
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| 191 | * is in an unknown state. |
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| 192 | * In this case, perform a hard reset using high level |
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| 193 | * clock source RCC ADC reset. |
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| 194 | * Refer to function @ref LL_ADC_CommonDeInit(). |
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| 195 | * @param ADCx ADC instance |
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| 196 | * @retval An ErrorStatus enumeration value: |
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| 197 | * - SUCCESS: ADC registers are de-initialized |
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| 198 | * - ERROR: ADC registers are not de-initialized |
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| 199 | */ |
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| 200 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
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| 201 | { |
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| 202 | ErrorStatus status = SUCCESS; |
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| 203 | |||
| 204 | __IO uint32_t timeout_cpu_cycles = 0U; |
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| 205 | |||
| 206 | /* Check the parameters */ |
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| 207 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
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| 208 | |||
| 209 | /* Disable ADC instance if not already disabled. */ |
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| 210 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
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| 211 | { |
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| 212 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
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| 213 | /* have an external trigger event occurring during the conversion stop */ |
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| 214 | /* ADC disable process. */ |
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| 215 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
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| 216 | |||
| 217 | /* Stop potential ADC conversion on going on ADC group regular. */ |
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| 218 | if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) |
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| 219 | { |
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| 220 | if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) |
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| 221 | { |
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| 222 | LL_ADC_REG_StopConversion(ADCx); |
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| 223 | } |
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| 224 | } |
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| 225 | |||
| 226 | /* Wait for ADC conversions are effectively stopped */ |
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| 227 | timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; |
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| 228 | while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U) |
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| 229 | { |
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| 230 | if(timeout_cpu_cycles-- == 0U) |
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| 231 | { |
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| 232 | /* Time-out error */ |
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| 233 | status = ERROR; |
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| 234 | } |
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| 235 | } |
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| 236 | |||
| 237 | /* Disable the ADC instance */ |
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| 238 | LL_ADC_Disable(ADCx); |
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| 239 | |||
| 240 | /* Wait for ADC instance is effectively disabled */ |
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| 241 | timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; |
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| 242 | while (LL_ADC_IsDisableOngoing(ADCx) == 1U) |
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| 243 | { |
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| 244 | if(timeout_cpu_cycles-- == 0U) |
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| 245 | { |
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| 246 | /* Time-out error */ |
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| 247 | status = ERROR; |
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| 248 | } |
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| 249 | } |
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| 250 | } |
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| 251 | |||
| 252 | /* Check whether ADC state is compliant with expected state */ |
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| 253 | if(READ_BIT(ADCx->CR, |
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| 254 | ( ADC_CR_ADSTP | ADC_CR_ADSTART |
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| 255 | | ADC_CR_ADDIS | ADC_CR_ADEN ) |
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| 256 | ) |
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| 257 | == 0U) |
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| 258 | { |
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| 259 | /* ========== Reset ADC registers ========== */ |
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| 260 | /* Reset register IER */ |
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| 261 | CLEAR_BIT(ADCx->IER, |
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| 262 | ( LL_ADC_IT_ADRDY |
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| 263 | | LL_ADC_IT_EOC |
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| 264 | | LL_ADC_IT_EOS |
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| 265 | | LL_ADC_IT_OVR |
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| 266 | | LL_ADC_IT_EOSMP |
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| 267 | | LL_ADC_IT_AWD1 ) |
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| 268 | ); |
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| 269 | |||
| 270 | /* Reset register ISR */ |
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| 271 | SET_BIT(ADCx->ISR, |
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| 272 | ( LL_ADC_FLAG_ADRDY |
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| 273 | | LL_ADC_FLAG_EOC |
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| 274 | | LL_ADC_FLAG_EOS |
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| 275 | | LL_ADC_FLAG_OVR |
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| 276 | | LL_ADC_FLAG_EOSMP |
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| 277 | | LL_ADC_FLAG_AWD1 ) |
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| 278 | ); |
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| 279 | |||
| 280 | /* Reset register CR */ |
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| 281 | /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ |
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| 282 | /* "read-set": no direct reset applicable. */ |
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| 283 | /* No action on register CR */ |
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| 284 | |||
| 285 | /* Reset register CFGR1 */ |
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| 286 | CLEAR_BIT(ADCx->CFGR1, |
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| 287 | ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN |
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| 288 | | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
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| 289 | | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
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| 290 | | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) |
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| 291 | ); |
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| 292 | |||
| 293 | /* Reset register CFGR2 */ |
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| 294 | /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ |
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| 295 | /* already done above. */ |
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| 296 | CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE); |
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| 297 | |||
| 298 | /* Reset register SMPR */ |
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| 299 | CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP); |
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| 300 | |||
| 301 | /* Reset register TR */ |
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| 302 | MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT); |
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| 303 | |||
| 304 | /* Reset register CHSELR */ |
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| 305 | #if defined(ADC_CCR_VBATEN) |
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| 306 | CLEAR_BIT(ADCx->CHSELR, |
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| 307 | ( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 |
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| 308 | | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 |
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| 309 | | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 |
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| 310 | | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 |
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| 311 | | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) |
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| 312 | ); |
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| 313 | #else |
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| 314 | CLEAR_BIT(ADCx->CHSELR, |
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| 315 | ( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 |
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| 316 | | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 |
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| 317 | | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 |
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| 318 | | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 |
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| 319 | | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) |
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| 320 | ); |
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| 321 | #endif |
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| 322 | |||
| 323 | /* Reset register DR */ |
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| 324 | /* bits in access mode read only, no direct reset applicable */ |
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| 325 | |||
| 326 | } |
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| 327 | else |
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| 328 | { |
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| 329 | /* ADC instance is in an unknown state */ |
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| 330 | /* Need to performing a hard reset of ADC instance, using high level */ |
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| 331 | /* clock source RCC ADC reset. */ |
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| 332 | /* Caution: On this STM32 serie, if several ADC instances are available */ |
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| 333 | /* on the selected device, RCC ADC reset will reset */ |
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| 334 | /* all ADC instances belonging to the common ADC instance. */ |
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| 335 | status = ERROR; |
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| 336 | } |
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| 337 | |||
| 338 | return status; |
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| 339 | } |
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| 340 | |||
| 341 | /** |
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| 342 | * @brief Initialize some features of ADC instance. |
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| 343 | * @note These parameters have an impact on ADC scope: ADC instance. |
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| 344 | * Refer to corresponding unitary functions into |
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| 345 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
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| 346 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
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| 347 | * is conditioned to ADC state: |
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| 348 | * ADC instance must be disabled. |
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| 349 | * This condition is applied to all ADC features, for efficiency |
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| 350 | * and compatibility over all STM32 families. However, the different |
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| 351 | * features can be set under different ADC state conditions |
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| 352 | * (setting possible with ADC enabled without conversion on going, |
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| 353 | * ADC enabled with conversion on going, ...) |
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| 354 | * Each feature can be updated afterwards with a unitary function |
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| 355 | * and potentially with ADC in a different state than disabled, |
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| 356 | * refer to description of each function for setting |
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| 357 | * conditioned to ADC state. |
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| 358 | * @note After using this function, some other features must be configured |
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| 359 | * using LL unitary functions. |
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| 360 | * The minimum configuration remaining to be done is: |
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| 361 | * - Set ADC group regular sequencer: |
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| 362 | * map channel on rank corresponding to channel number. |
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| 363 | * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); |
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| 364 | * - Set ADC channel sampling time |
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| 365 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
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| 366 | * @param ADCx ADC instance |
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| 367 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
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| 368 | * @retval An ErrorStatus enumeration value: |
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| 369 | * - SUCCESS: ADC registers are initialized |
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| 370 | * - ERROR: ADC registers are not initialized |
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| 371 | */ |
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| 372 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
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| 373 | { |
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| 374 | ErrorStatus status = SUCCESS; |
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| 375 | |||
| 376 | /* Check the parameters */ |
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| 377 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
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| 378 | |||
| 379 | assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); |
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| 380 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
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| 381 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
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| 382 | assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); |
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| 383 | |||
| 384 | /* Note: Hardware constraint (refer to description of this function): */ |
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| 385 | /* ADC instance must be disabled. */ |
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| 386 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
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| 387 | { |
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| 388 | /* Configuration of ADC hierarchical scope: */ |
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| 389 | /* - ADC instance */ |
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| 390 | /* - Set ADC data resolution */ |
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| 391 | /* - Set ADC conversion data alignment */ |
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| 392 | /* - Set ADC low power mode */ |
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| 393 | MODIFY_REG(ADCx->CFGR1, |
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| 394 | ADC_CFGR1_RES |
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| 395 | | ADC_CFGR1_ALIGN |
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| 396 | | ADC_CFGR1_WAIT |
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| 397 | | ADC_CFGR1_AUTOFF |
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| 398 | , |
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| 399 | ADC_InitStruct->Resolution |
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| 400 | | ADC_InitStruct->DataAlignment |
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| 401 | | ADC_InitStruct->LowPowerMode |
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| 402 | ); |
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| 403 | |||
| 404 | MODIFY_REG(ADCx->CFGR2, |
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| 405 | ADC_CFGR2_CKMODE |
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| 406 | , |
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| 407 | ADC_InitStruct->Clock |
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| 408 | ); |
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| 409 | } |
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| 410 | else |
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| 411 | { |
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| 412 | /* Initialization error: ADC instance is not disabled. */ |
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| 413 | status = ERROR; |
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| 414 | } |
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| 415 | return status; |
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| 416 | } |
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| 417 | |||
| 418 | /** |
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| 419 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
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| 420 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
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| 421 | * whose fields will be set to default values. |
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| 422 | * @retval None |
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| 423 | */ |
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| 424 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
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| 425 | { |
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| 426 | /* Set ADC_InitStruct fields to default values */ |
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| 427 | /* Set fields of ADC instance */ |
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| 428 | ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; |
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| 429 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
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| 430 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
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| 431 | ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; |
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| 432 | |||
| 433 | } |
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| 434 | |||
| 435 | /** |
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| 436 | * @brief Initialize some features of ADC group regular. |
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| 437 | * @note These parameters have an impact on ADC scope: ADC group regular. |
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| 438 | * Refer to corresponding unitary functions into |
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| 439 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
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| 440 | * (functions with prefix "REG"). |
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| 441 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
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| 442 | * is conditioned to ADC state: |
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| 443 | * ADC instance must be disabled. |
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| 444 | * This condition is applied to all ADC features, for efficiency |
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| 445 | * and compatibility over all STM32 families. However, the different |
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| 446 | * features can be set under different ADC state conditions |
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| 447 | * (setting possible with ADC enabled without conversion on going, |
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| 448 | * ADC enabled with conversion on going, ...) |
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| 449 | * Each feature can be updated afterwards with a unitary function |
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| 450 | * and potentially with ADC in a different state than disabled, |
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| 451 | * refer to description of each function for setting |
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| 452 | * conditioned to ADC state. |
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| 453 | * @note After using this function, other features must be configured |
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| 454 | * using LL unitary functions. |
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| 455 | * The minimum configuration remaining to be done is: |
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| 456 | * - Set ADC group regular sequencer: |
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| 457 | * map channel on rank corresponding to channel number. |
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| 458 | * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); |
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| 459 | * - Set ADC channel sampling time |
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| 460 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
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| 461 | * @param ADCx ADC instance |
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| 462 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
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| 463 | * @retval An ErrorStatus enumeration value: |
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| 464 | * - SUCCESS: ADC registers are initialized |
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| 465 | * - ERROR: ADC registers are not initialized |
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| 466 | */ |
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| 467 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
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| 468 | { |
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| 469 | ErrorStatus status = SUCCESS; |
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| 470 | |||
| 471 | /* Check the parameters */ |
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| 472 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
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| 473 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
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| 474 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
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| 475 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
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| 476 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
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| 477 | assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); |
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| 478 | |||
| 479 | /* Note: Hardware constraint (refer to description of this function): */ |
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| 480 | /* ADC instance must be disabled. */ |
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| 481 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
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| 482 | { |
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| 483 | /* Configuration of ADC hierarchical scope: */ |
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| 484 | /* - ADC group regular */ |
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| 485 | /* - Set ADC group regular trigger source */ |
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| 486 | /* - Set ADC group regular sequencer discontinuous mode */ |
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| 487 | /* - Set ADC group regular continuous mode */ |
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| 488 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
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| 489 | /* transfer by DMA, and DMA requests mode */ |
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| 490 | /* - Set ADC group regular overrun behavior */ |
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| 491 | /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ |
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| 492 | /* setting of trigger source to SW start. */ |
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| 493 | MODIFY_REG(ADCx->CFGR1, |
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| 494 | ADC_CFGR1_EXTSEL |
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| 495 | | ADC_CFGR1_EXTEN |
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| 496 | | ADC_CFGR1_DISCEN |
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| 497 | | ADC_CFGR1_CONT |
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| 498 | | ADC_CFGR1_DMAEN |
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| 499 | | ADC_CFGR1_DMACFG |
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| 500 | | ADC_CFGR1_OVRMOD |
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| 501 | , |
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| 502 | ADC_REG_InitStruct->TriggerSource |
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| 503 | | ADC_REG_InitStruct->SequencerDiscont |
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| 504 | | ADC_REG_InitStruct->ContinuousMode |
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| 505 | | ADC_REG_InitStruct->DMATransfer |
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| 506 | | ADC_REG_InitStruct->Overrun |
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| 507 | ); |
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| 508 | |||
| 509 | } |
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| 510 | else |
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| 511 | { |
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| 512 | /* Initialization error: ADC instance is not disabled. */ |
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| 513 | status = ERROR; |
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| 514 | } |
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| 515 | return status; |
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| 516 | } |
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| 517 | |||
| 518 | /** |
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| 519 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
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| 520 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
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| 521 | * whose fields will be set to default values. |
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| 522 | * @retval None |
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| 523 | */ |
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| 524 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
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| 525 | { |
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| 526 | /* Set ADC_REG_InitStruct fields to default values */ |
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| 527 | /* Set fields of ADC group regular */ |
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| 528 | /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ |
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| 529 | /* setting of trigger source to SW start. */ |
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| 530 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
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| 531 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
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| 532 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
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| 533 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
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| 534 | ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; |
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| 535 | } |
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| 536 | |||
| 537 | /** |
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| 538 | * @} |
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| 539 | */ |
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| 540 | |||
| 541 | /** |
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| 542 | * @} |
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| 543 | */ |
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| 544 | |||
| 545 | /** |
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| 546 | * @} |
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| 547 | */ |
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| 548 | |||
| 549 | #endif /* ADC1 */ |
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| 550 | |||
| 551 | /** |
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| 552 | * @} |
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| 553 | */ |
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| 554 | |||
| 555 | #endif /* USE_FULL_LL_DRIVER */ |
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| 556 | |||
| 557 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |