WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_adc.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_adc.c
		4	* @author MCD Application Team
		5	* @brief ADC LL module driver
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	#if defined(USE_FULL_LL_DRIVER)
		21
		22	/* Includes ------------------------------------------------------------------*/
		23	#include "stm32f0xx_ll_adc.h"
		24	#include "stm32f0xx_ll_bus.h"
		25
		26	#ifdef USE_FULL_ASSERT
		27	#include "stm32_assert.h"
		28	#else
		29	#define assert_param(expr) ((void)0U)
		30	#endif
		31
		32	/** @addtogroup STM32F0xx_LL_Driver
		33	* @{
		34	*/
		35
		36	#if defined (ADC1)
		37
		38	/** @addtogroup ADC_LL ADC
		39	* @{
		40	*/
		41
		42	/* Private types -------------------------------------------------------------*/
		43	/* Private variables ---------------------------------------------------------*/
		44	/* Private constants ---------------------------------------------------------*/
		45	/** @addtogroup ADC_LL_Private_Constants
		46	* @{
		47	*/
		48
		49	/* Definitions of ADC hardware constraints delays */
		50	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
		51	/* not timeout values: */
		52	/* Timeout values for ADC operations are dependent to device clock */
		53	/* configuration (system clock versus ADC clock), */
		54	/* and therefore must be defined in user application. */
		55	/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
		56	/* values definition. */
		57	/* Note: ADC timeout values are defined here in CPU cycles to be independent */
		58	/* of device clock setting. */
		59	/* In user application, ADC timeout values should be defined with */
		60	/* temporal values, in function of device clock settings. */
		61	/* Highest ratio CPU clock frequency vs ADC clock frequency: */
		62	/* - ADC clock from synchronous clock with AHB prescaler 512, */
		63	/* APB prescaler 16, ADC prescaler 4. */
		64	/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
		65	/* with highest ratio CPU clock frequency vs HSI clock frequency: */
		66	/* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
		67	/* Unit: CPU cycles. */
		68	#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
		69	#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
		70	#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
		71
		72	/**
		73	* @}
		74	*/
		75
		76	/* Private macros ------------------------------------------------------------*/
		77
		78	/** @addtogroup ADC_LL_Private_Macros
		79	* @{
		80	*/
		81
		82	/* Check of parameters for configuration of ADC hierarchical scope: */
		83	/* common to several ADC instances. */
		84	/* Check of parameters for configuration of ADC hierarchical scope: */
		85	/* ADC instance. */
		86	#define IS_LL_ADC_CLOCK(__CLOCK__) \
		87	( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
		88	\|\| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
		89	\|\| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
		90	)
		91
		92	#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
		93	( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
		94	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
		95	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
		96	\|\| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
		97	)
		98
		99	#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
		100	( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
		101	\|\| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
		102	)
		103
		104	#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
		105	( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
		106	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
		107	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
		108	\|\| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
		109	)
		110
		111	/* Check of parameters for configuration of ADC hierarchical scope: */
		112	/* ADC group regular */
		113	#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
		114	( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
		115	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
		116	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
		117	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
		118	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
		119	\|\| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
		120	)
		121
		122	#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
		123	( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
		124	\|\| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
		125	)
		126
		127	#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
		128	( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
		129	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
		130	\|\| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
		131	)
		132
		133	#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
		134	( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
		135	\|\| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
		136	)
		137
		138	#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
		139	( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
		140	\|\| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
		141	)
		142
		143	/**
		144	* @}
		145	*/
		146
		147
		148	/* Private function prototypes -----------------------------------------------*/
		149
		150	/* Exported functions --------------------------------------------------------*/
		151	/** @addtogroup ADC_LL_Exported_Functions
		152	* @{
		153	*/
		154
		155	/** @addtogroup ADC_LL_EF_Init
		156	* @{
		157	*/
		158
		159	/**
		160	* @brief De-initialize registers of all ADC instances belonging to
		161	* the same ADC common instance to their default reset values.
		162	* @note This function is performing a hard reset, using high level
		163	* clock source RCC ADC reset.
		164	* @param ADCxy_COMMON ADC common instance
		165	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		166	* @retval An ErrorStatus enumeration value:
		167	* - SUCCESS: ADC common registers are de-initialized
		168	* - ERROR: not applicable
		169	*/
		170	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
		171	{
		172	/* Check the parameters */
		173	assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
		174
		175	/* Force reset of ADC clock (core clock) */
		176	LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
		177
		178	/* Release reset of ADC clock (core clock) */
		179	LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
		180
		181	return SUCCESS;
		182	}
		183
		184
		185	/**
		186	* @brief De-initialize registers of the selected ADC instance
		187	* to their default reset values.
		188	* @note To reset all ADC instances quickly (perform a hard reset),
		189	* use function @ref LL_ADC_CommonDeInit().
		190	* @note If this functions returns error status, it means that ADC instance
		191	* is in an unknown state.
		192	* In this case, perform a hard reset using high level
		193	* clock source RCC ADC reset.
		194	* Refer to function @ref LL_ADC_CommonDeInit().
		195	* @param ADCx ADC instance
		196	* @retval An ErrorStatus enumeration value:
		197	* - SUCCESS: ADC registers are de-initialized
		198	* - ERROR: ADC registers are not de-initialized
		199	*/
		200	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
		201	{
		202	ErrorStatus status = SUCCESS;
		203
		204	__IO uint32_t timeout_cpu_cycles = 0U;
		205
		206	/* Check the parameters */
		207	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		208
		209	/* Disable ADC instance if not already disabled. */
		210	if(LL_ADC_IsEnabled(ADCx) == 1U)
		211	{
		212	/* Set ADC group regular trigger source to SW start to ensure to not */
		213	/* have an external trigger event occurring during the conversion stop */
		214	/* ADC disable process. */
		215	LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
		216
		217	/* Stop potential ADC conversion on going on ADC group regular. */
		218	if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
		219	{
		220	if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
		221	{
		222	LL_ADC_REG_StopConversion(ADCx);
		223	}
		224	}
		225
		226	/* Wait for ADC conversions are effectively stopped */
		227	timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
		228	while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
		229	{
		230	if(timeout_cpu_cycles-- == 0U)
		231	{
		232	/* Time-out error */
		233	status = ERROR;
		234	}
		235	}
		236
		237	/* Disable the ADC instance */
		238	LL_ADC_Disable(ADCx);
		239
		240	/* Wait for ADC instance is effectively disabled */
		241	timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
		242	while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
		243	{
		244	if(timeout_cpu_cycles-- == 0U)
		245	{
		246	/* Time-out error */
		247	status = ERROR;
		248	}
		249	}
		250	}
		251
		252	/* Check whether ADC state is compliant with expected state */
		253	if(READ_BIT(ADCx->CR,
		254	( ADC_CR_ADSTP \| ADC_CR_ADSTART
		255	\| ADC_CR_ADDIS \| ADC_CR_ADEN )
		256	)
		257	== 0U)
		258	{
		259	/* ========== Reset ADC registers ========== */
		260	/* Reset register IER */
		261	CLEAR_BIT(ADCx->IER,
		262	( LL_ADC_IT_ADRDY
		263	\| LL_ADC_IT_EOC
		264	\| LL_ADC_IT_EOS
		265	\| LL_ADC_IT_OVR
		266	\| LL_ADC_IT_EOSMP
		267	\| LL_ADC_IT_AWD1 )
		268	);
		269
		270	/* Reset register ISR */
		271	SET_BIT(ADCx->ISR,
		272	( LL_ADC_FLAG_ADRDY
		273	\| LL_ADC_FLAG_EOC
		274	\| LL_ADC_FLAG_EOS
		275	\| LL_ADC_FLAG_OVR
		276	\| LL_ADC_FLAG_EOSMP
		277	\| LL_ADC_FLAG_AWD1 )
		278	);
		279
		280	/* Reset register CR */
		281	/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
		282	/* "read-set": no direct reset applicable. */
		283	/* No action on register CR */
		284
		285	/* Reset register CFGR1 */
		286	CLEAR_BIT(ADCx->CFGR1,
		287	( ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_DISCEN
		288	\| ADC_CFGR1_AUTOFF \| ADC_CFGR1_WAIT \| ADC_CFGR1_CONT \| ADC_CFGR1_OVRMOD
		289	\| ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL \| ADC_CFGR1_ALIGN \| ADC_CFGR1_RES
		290	\| ADC_CFGR1_SCANDIR \| ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN )
		291	);
		292
		293	/* Reset register CFGR2 */
		294	/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
		295	/* already done above. */
		296	CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
		297
		298	/* Reset register SMPR */
		299	CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
		300
		301	/* Reset register TR */
		302	MODIFY_REG(ADCx->TR, ADC_TR_HT \| ADC_TR_LT, ADC_TR_HT);
		303
		304	/* Reset register CHSELR */
		305	#if defined(ADC_CCR_VBATEN)
		306	CLEAR_BIT(ADCx->CHSELR,
		307	( ADC_CHSELR_CHSEL18 \| ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16
		308	\| ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12
		309	\| ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8
		310	\| ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4
		311	\| ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0 )
		312	);
		313	#else
		314	CLEAR_BIT(ADCx->CHSELR,
		315	( ADC_CHSELR_CHSEL17 \| ADC_CHSELR_CHSEL16
		316	\| ADC_CHSELR_CHSEL15 \| ADC_CHSELR_CHSEL14 \| ADC_CHSELR_CHSEL13 \| ADC_CHSELR_CHSEL12
		317	\| ADC_CHSELR_CHSEL11 \| ADC_CHSELR_CHSEL10 \| ADC_CHSELR_CHSEL9 \| ADC_CHSELR_CHSEL8
		318	\| ADC_CHSELR_CHSEL7 \| ADC_CHSELR_CHSEL6 \| ADC_CHSELR_CHSEL5 \| ADC_CHSELR_CHSEL4
		319	\| ADC_CHSELR_CHSEL3 \| ADC_CHSELR_CHSEL2 \| ADC_CHSELR_CHSEL1 \| ADC_CHSELR_CHSEL0 )
		320	);
		321	#endif
		322
		323	/* Reset register DR */
		324	/* bits in access mode read only, no direct reset applicable */
		325
		326	}
		327	else
		328	{
		329	/* ADC instance is in an unknown state */
		330	/* Need to performing a hard reset of ADC instance, using high level */
		331	/* clock source RCC ADC reset. */
		332	/* Caution: On this STM32 serie, if several ADC instances are available */
		333	/* on the selected device, RCC ADC reset will reset */
		334	/* all ADC instances belonging to the common ADC instance. */
		335	status = ERROR;
		336	}
		337
		338	return status;
		339	}
		340
		341	/**
		342	* @brief Initialize some features of ADC instance.
		343	* @note These parameters have an impact on ADC scope: ADC instance.
		344	* Refer to corresponding unitary functions into
		345	* @ref ADC_LL_EF_Configuration_ADC_Instance .
		346	* @note The setting of these parameters by function @ref LL_ADC_Init()
		347	* is conditioned to ADC state:
		348	* ADC instance must be disabled.
		349	* This condition is applied to all ADC features, for efficiency
		350	* and compatibility over all STM32 families. However, the different
		351	* features can be set under different ADC state conditions
		352	* (setting possible with ADC enabled without conversion on going,
		353	* ADC enabled with conversion on going, ...)
		354	* Each feature can be updated afterwards with a unitary function
		355	* and potentially with ADC in a different state than disabled,
		356	* refer to description of each function for setting
		357	* conditioned to ADC state.
		358	* @note After using this function, some other features must be configured
		359	* using LL unitary functions.
		360	* The minimum configuration remaining to be done is:
		361	* - Set ADC group regular sequencer:
		362	* map channel on rank corresponding to channel number.
		363	* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
		364	* - Set ADC channel sampling time
		365	* Refer to function LL_ADC_SetChannelSamplingTime();
		366	* @param ADCx ADC instance
		367	* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
		368	* @retval An ErrorStatus enumeration value:
		369	* - SUCCESS: ADC registers are initialized
		370	* - ERROR: ADC registers are not initialized
		371	*/
		372	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct)
		373	{
		374	ErrorStatus status = SUCCESS;
		375
		376	/* Check the parameters */
		377	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		378
		379	assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
		380	assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
		381	assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
		382	assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
		383
		384	/* Note: Hardware constraint (refer to description of this function): */
		385	/* ADC instance must be disabled. */
		386	if(LL_ADC_IsEnabled(ADCx) == 0U)
		387	{
		388	/* Configuration of ADC hierarchical scope: */
		389	/* - ADC instance */
		390	/* - Set ADC data resolution */
		391	/* - Set ADC conversion data alignment */
		392	/* - Set ADC low power mode */
		393	MODIFY_REG(ADCx->CFGR1,
		394	ADC_CFGR1_RES
		395	\| ADC_CFGR1_ALIGN
		396	\| ADC_CFGR1_WAIT
		397	\| ADC_CFGR1_AUTOFF
		398	,
		399	ADC_InitStruct->Resolution
		400	\| ADC_InitStruct->DataAlignment
		401	\| ADC_InitStruct->LowPowerMode
		402	);
		403
		404	MODIFY_REG(ADCx->CFGR2,
		405	ADC_CFGR2_CKMODE
		406	,
		407	ADC_InitStruct->Clock
		408	);
		409	}
		410	else
		411	{
		412	/* Initialization error: ADC instance is not disabled. */
		413	status = ERROR;
		414	}
		415	return status;
		416	}
		417
		418	/**
		419	* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
		420	* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
		421	* whose fields will be set to default values.
		422	* @retval None
		423	*/
		424	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
		425	{
		426	/* Set ADC_InitStruct fields to default values */
		427	/* Set fields of ADC instance */
		428	ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
		429	ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
		430	ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
		431	ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
		432
		433	}
		434
		435	/**
		436	* @brief Initialize some features of ADC group regular.
		437	* @note These parameters have an impact on ADC scope: ADC group regular.
		438	* Refer to corresponding unitary functions into
		439	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
		440	* (functions with prefix "REG").
		441	* @note The setting of these parameters by function @ref LL_ADC_Init()
		442	* is conditioned to ADC state:
		443	* ADC instance must be disabled.
		444	* This condition is applied to all ADC features, for efficiency
		445	* and compatibility over all STM32 families. However, the different
		446	* features can be set under different ADC state conditions
		447	* (setting possible with ADC enabled without conversion on going,
		448	* ADC enabled with conversion on going, ...)
		449	* Each feature can be updated afterwards with a unitary function
		450	* and potentially with ADC in a different state than disabled,
		451	* refer to description of each function for setting
		452	* conditioned to ADC state.
		453	* @note After using this function, other features must be configured
		454	* using LL unitary functions.
		455	* The minimum configuration remaining to be done is:
		456	* - Set ADC group regular sequencer:
		457	* map channel on rank corresponding to channel number.
		458	* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
		459	* - Set ADC channel sampling time
		460	* Refer to function LL_ADC_SetChannelSamplingTime();
		461	* @param ADCx ADC instance
		462	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
		463	* @retval An ErrorStatus enumeration value:
		464	* - SUCCESS: ADC registers are initialized
		465	* - ERROR: ADC registers are not initialized
		466	*/
		467	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct)
		468	{
		469	ErrorStatus status = SUCCESS;
		470
		471	/* Check the parameters */
		472	assert_param(IS_ADC_ALL_INSTANCE(ADCx));
		473	assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
		474	assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
		475	assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
		476	assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
		477	assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
		478
6	mjames	479	/* ADC group regular continuous mode and discontinuous mode */
		480	/* can not be enabled simultenaeously */
		481	assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
		482	\|\| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
		483
2	mjames	484	/* Note: Hardware constraint (refer to description of this function): */
		485	/* ADC instance must be disabled. */
		486	if(LL_ADC_IsEnabled(ADCx) == 0U)
		487	{
		488	/* Configuration of ADC hierarchical scope: */
		489	/* - ADC group regular */
		490	/* - Set ADC group regular trigger source */
		491	/* - Set ADC group regular sequencer discontinuous mode */
		492	/* - Set ADC group regular continuous mode */
		493	/* - Set ADC group regular conversion data transfer: no transfer or */
		494	/* transfer by DMA, and DMA requests mode */
		495	/* - Set ADC group regular overrun behavior */
		496	/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
		497	/* setting of trigger source to SW start. */
		498	MODIFY_REG(ADCx->CFGR1,
		499	ADC_CFGR1_EXTSEL
		500	\| ADC_CFGR1_EXTEN
		501	\| ADC_CFGR1_DISCEN
		502	\| ADC_CFGR1_CONT
		503	\| ADC_CFGR1_DMAEN
		504	\| ADC_CFGR1_DMACFG
		505	\| ADC_CFGR1_OVRMOD
		506	,
		507	ADC_REG_InitStruct->TriggerSource
		508	\| ADC_REG_InitStruct->SequencerDiscont
		509	\| ADC_REG_InitStruct->ContinuousMode
		510	\| ADC_REG_InitStruct->DMATransfer
		511	\| ADC_REG_InitStruct->Overrun
		512	);
		513
		514	}
		515	else
		516	{
		517	/* Initialization error: ADC instance is not disabled. */
		518	status = ERROR;
		519	}
		520	return status;
		521	}
		522
		523	/**
		524	* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
		525	* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
		526	* whose fields will be set to default values.
		527	* @retval None
		528	*/
		529	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
		530	{
		531	/* Set ADC_REG_InitStruct fields to default values */
		532	/* Set fields of ADC group regular */
		533	/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
		534	/* setting of trigger source to SW start. */
		535	ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
		536	ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
		537	ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
		538	ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
		539	ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
		540	}
		541
		542	/**
		543	* @}
		544	*/
		545
		546	/**
		547	* @}
		548	*/
		549
		550	/**
		551	* @}
		552	*/
		553
		554	#endif /* ADC1 */
		555
		556	/**
		557	* @}
		558	*/
		559
		560	#endif /* USE_FULL_LL_DRIVER */
		561
		562	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_ll_adc.c – Rev 6