WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_hal_tim.c
		4	* @author MCD Application Team
		5	* @brief TIM HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Timer (TIM) peripheral:
		8	* + TIM Time Base Initialization
		9	* + TIM Time Base Start
		10	* + TIM Time Base Start Interruption
		11	* + TIM Time Base Start DMA
		12	* + TIM Output Compare/PWM Initialization
		13	* + TIM Output Compare/PWM Channel Configuration
		14	* + TIM Output Compare/PWM Start
		15	* + TIM Output Compare/PWM Start Interruption
		16	* + TIM Output Compare/PWM Start DMA
		17	* + TIM Input Capture Initialization
		18	* + TIM Input Capture Channel Configuration
		19	* + TIM Input Capture Start
		20	* + TIM Input Capture Start Interruption
		21	* + TIM Input Capture Start DMA
		22	* + TIM One Pulse Initialization
		23	* + TIM One Pulse Channel Configuration
		24	* + TIM One Pulse Start
		25	* + TIM Encoder Interface Initialization
		26	* + TIM Encoder Interface Start
		27	* + TIM Encoder Interface Start Interruption
		28	* + TIM Encoder Interface Start DMA
		29	* + Commutation Event configuration with Interruption and DMA
		30	* + TIM OCRef clear configuration
		31	* + TIM External Clock configuration
		32	@verbatim
		33	==============================================================================
		34	##### TIMER Generic features #####
		35	==============================================================================
		36	[..] The Timer features include:
		37	(#) 16-bit up, down, up/down auto-reload counter.
		38	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
		39	counter clock frequency either by any factor between 1 and 65536.
		40	(#) Up to 4 independent channels for:
		41	(++) Input Capture
		42	(++) Output Compare
		43	(++) PWM generation (Edge and Center-aligned Mode)
		44	(++) One-pulse mode output
		45	(#) Synchronization circuit to control the timer with external signals and to interconnect
		46	several timers together.
		47	(#) Supports incremental encoder for positioning purposes
		48
		49	##### How to use this driver #####
		50	==============================================================================
		51	[..]
		52	(#) Initialize the TIM low level resources by implementing the following functions
		53	depending on the selected feature:
		54	(++) Time Base : HAL_TIM_Base_MspInit()
		55	(++) Input Capture : HAL_TIM_IC_MspInit()
		56	(++) Output Compare : HAL_TIM_OC_MspInit()
		57	(++) PWM generation : HAL_TIM_PWM_MspInit()
		58	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
		59	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
		60
		61	(#) Initialize the TIM low level resources :
		62	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
		63	(##) TIM pins configuration
		64	(+++) Enable the clock for the TIM GPIOs using the following function:
		65	__HAL_RCC_GPIOx_CLK_ENABLE();
		66	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
		67
		68	(#) The external Clock can be configured, if needed (the default clock is the
		69	internal clock from the APBx), using the following function:
		70	HAL_TIM_ConfigClockSource, the clock configuration should be done before
		71	any start function.
		72
		73	(#) Configure the TIM in the desired functioning mode using one of the
		74	Initialization function of this driver:
		75	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
		76	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
		77	Output Compare signal.
		78	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
		79	PWM signal.
		80	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
		81	external signal.
		82	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
		83	in One Pulse Mode.
		84	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
		85
		86	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
		87	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
		88	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
		89	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
		90	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
		91	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
		92	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
		93
		94	(#) The DMA Burst is managed with the two following functions:
		95	HAL_TIM_DMABurst_WriteStart()
		96	HAL_TIM_DMABurst_ReadStart()
		97
		98	* Callback registration *
		99	=============================================
		100
		101	[..]
		102	The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
		103	allows the user to configure dynamically the driver callbacks.
		104
		105	[..]
		106	Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
		107	@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
		108	the Callback ID and a pointer to the user callback function.
		109
		110	[..]
		111	Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
		112	weak function.
		113	@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
		114	and the Callback ID.
		115
		116	[..]
		117	These functions allow to register/unregister following callbacks:
		118	(+) Base_MspInitCallback : TIM Base Msp Init Callback.
		119	(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
		120	(+) IC_MspInitCallback : TIM IC Msp Init Callback.
		121	(+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
		122	(+) OC_MspInitCallback : TIM OC Msp Init Callback.
		123	(+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
		124	(+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
		125	(+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
		126	(+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
		127	(+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
		128	(+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
		129	(+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
		130	(+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
		131	(+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
		132	(+) PeriodElapsedCallback : TIM Period Elapsed Callback.
		133	(+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
		134	(+) TriggerCallback : TIM Trigger Callback.
		135	(+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
		136	(+) IC_CaptureCallback : TIM Input Capture Callback.
		137	(+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
		138	(+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
		139	(+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
		140	(+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
		141	(+) ErrorCallback : TIM Error Callback.
		142	(+) CommutationCallback : TIM Commutation Callback.
		143	(+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
		144	(+) BreakCallback : TIM Break Callback.
		145
		146	[..]
		147	By default, after the Init and when the state is HAL_TIM_STATE_RESET
		148	all interrupt callbacks are set to the corresponding weak functions:
		149	examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
		150
		151	[..]
		152	Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
		153	functionalities in the Init / DeInit only when these callbacks are null
		154	(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
		155	keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
		156
		157	[..]
		158	Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
		159	Exception done MspInit / MspDeInit that can be registered / unregistered
		160	in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
		161	thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
		162	In that case first register the MspInit/MspDeInit user callbacks
		163	using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
		164
		165	[..]
		166	When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
		167	not defined, the callback registration feature is not available and all callbacks
		168	are set to the corresponding weak functions.
		169
		170	@endverbatim
		171	******************************************************************************
		172	* @attention
		173	*
		174	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		175	* All rights reserved.</center></h2>
		176	*
		177	* This software component is licensed by ST under BSD 3-Clause license,
		178	* the "License"; You may not use this file except in compliance with the
		179	* License. You may obtain a copy of the License at:
		180	* opensource.org/licenses/BSD-3-Clause
		181	*
		182	******************************************************************************
		183	*/
		184
		185	/* Includes ------------------------------------------------------------------*/
		186	#include "stm32f0xx_hal.h"
		187
		188	/** @addtogroup STM32F0xx_HAL_Driver
		189	* @{
		190	*/
		191
		192	/** @defgroup TIM TIM
		193	* @brief TIM HAL module driver
		194	* @{
		195	*/
		196
		197	#ifdef HAL_TIM_MODULE_ENABLED
		198
		199	/* Private typedef -----------------------------------------------------------*/
		200	/* Private define ------------------------------------------------------------*/
		201	/* Private macro -------------------------------------------------------------*/
		202	/* Private variables ---------------------------------------------------------*/
		203	/* Private function prototypes -----------------------------------------------*/
		204	/** @addtogroup TIM_Private_Functions
		205	* @{
		206	*/
		207	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		208	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		209	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		210	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
		211	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		212	uint32_t TIM_ICFilter);
		213	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
		214	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		215	uint32_t TIM_ICFilter);
		216	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		217	uint32_t TIM_ICFilter);
		218	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
		219	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
		220	static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
		221	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
		222	static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
		223	static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
		224	TIM_SlaveConfigTypeDef *sSlaveConfig);
		225	/**
		226	* @}
		227	*/
		228	/* Exported functions --------------------------------------------------------*/
		229
		230	/** @defgroup TIM_Exported_Functions TIM Exported Functions
		231	* @{
		232	*/
		233
		234	/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
		235	* @brief Time Base functions
		236	*
		237	@verbatim
		238	==============================================================================
		239	##### Time Base functions #####
		240	==============================================================================
		241	[..]
		242	This section provides functions allowing to:
		243	(+) Initialize and configure the TIM base.
		244	(+) De-initialize the TIM base.
		245	(+) Start the Time Base.
		246	(+) Stop the Time Base.
		247	(+) Start the Time Base and enable interrupt.
		248	(+) Stop the Time Base and disable interrupt.
		249	(+) Start the Time Base and enable DMA transfer.
		250	(+) Stop the Time Base and disable DMA transfer.
		251
		252	@endverbatim
		253	* @{
		254	*/
		255	/**
		256	* @brief Initializes the TIM Time base Unit according to the specified
		257	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
		258	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		259	* requires a timer reset to avoid unexpected direction
		260	* due to DIR bit readonly in center aligned mode.
		261	* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
		262	* @param htim TIM Base handle
		263	* @retval HAL status
		264	*/
		265	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
		266	{
		267	/* Check the TIM handle allocation */
		268	if (htim == NULL)
		269	{
		270	return HAL_ERROR;
		271	}
		272
		273	/* Check the parameters */
		274	assert_param(IS_TIM_INSTANCE(htim->Instance));
		275	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		276	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		277	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		278
		279	if (htim->State == HAL_TIM_STATE_RESET)
		280	{
		281	/* Allocate lock resource and initialize it */
		282	htim->Lock = HAL_UNLOCKED;
		283
		284	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		285	/* Reset interrupt callbacks to legacy weak callbacks */
		286	TIM_ResetCallback(htim);
		287
		288	if (htim->Base_MspInitCallback == NULL)
		289	{
		290	htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
		291	}
		292	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		293	htim->Base_MspInitCallback(htim);
		294	#else
		295	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		296	HAL_TIM_Base_MspInit(htim);
		297	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		298	}
		299
		300	/* Set the TIM state */
		301	htim->State = HAL_TIM_STATE_BUSY;
		302
		303	/* Set the Time Base configuration */
		304	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		305
		306	/* Initialize the TIM state*/
		307	htim->State = HAL_TIM_STATE_READY;
		308
		309	return HAL_OK;
		310	}
		311
		312	/**
		313	* @brief DeInitializes the TIM Base peripheral
		314	* @param htim TIM Base handle
		315	* @retval HAL status
		316	*/
		317	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
		318	{
		319	/* Check the parameters */
		320	assert_param(IS_TIM_INSTANCE(htim->Instance));
		321
		322	htim->State = HAL_TIM_STATE_BUSY;
		323
		324	/* Disable the TIM Peripheral Clock */
		325	__HAL_TIM_DISABLE(htim);
		326
		327	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		328	if (htim->Base_MspDeInitCallback == NULL)
		329	{
		330	htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
		331	}
		332	/* DeInit the low level hardware */
		333	htim->Base_MspDeInitCallback(htim);
		334	#else
		335	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		336	HAL_TIM_Base_MspDeInit(htim);
		337	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		338
		339	/* Change TIM state */
		340	htim->State = HAL_TIM_STATE_RESET;
		341
		342	/* Release Lock */
		343	__HAL_UNLOCK(htim);
		344
		345	return HAL_OK;
		346	}
		347
		348	/**
		349	* @brief Initializes the TIM Base MSP.
		350	* @param htim TIM Base handle
		351	* @retval None
		352	*/
		353	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
		354	{
		355	/* Prevent unused argument(s) compilation warning */
		356	UNUSED(htim);
		357
		358	/* NOTE : This function should not be modified, when the callback is needed,
		359	the HAL_TIM_Base_MspInit could be implemented in the user file
		360	*/
		361	}
		362
		363	/**
		364	* @brief DeInitializes TIM Base MSP.
		365	* @param htim TIM Base handle
		366	* @retval None
		367	*/
		368	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
		369	{
		370	/* Prevent unused argument(s) compilation warning */
		371	UNUSED(htim);
		372
		373	/* NOTE : This function should not be modified, when the callback is needed,
		374	the HAL_TIM_Base_MspDeInit could be implemented in the user file
		375	*/
		376	}
		377
		378
		379	/**
		380	* @brief Starts the TIM Base generation.
		381	* @param htim TIM Base handle
		382	* @retval HAL status
		383	*/
		384	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
		385	{
		386	uint32_t tmpsmcr;
		387
		388	/* Check the parameters */
		389	assert_param(IS_TIM_INSTANCE(htim->Instance));
		390
		391	/* Set the TIM state */
		392	htim->State = HAL_TIM_STATE_BUSY;
		393
		394	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		395	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		396	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		397	{
		398	__HAL_TIM_ENABLE(htim);
		399	}
		400
		401	/* Change the TIM state*/
		402	htim->State = HAL_TIM_STATE_READY;
		403
		404	/* Return function status */
		405	return HAL_OK;
		406	}
		407
		408	/**
		409	* @brief Stops the TIM Base generation.
		410	* @param htim TIM Base handle
		411	* @retval HAL status
		412	*/
		413	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
		414	{
		415	/* Check the parameters */
		416	assert_param(IS_TIM_INSTANCE(htim->Instance));
		417
		418	/* Set the TIM state */
		419	htim->State = HAL_TIM_STATE_BUSY;
		420
		421	/* Disable the Peripheral */
		422	__HAL_TIM_DISABLE(htim);
		423
		424	/* Change the TIM state*/
		425	htim->State = HAL_TIM_STATE_READY;
		426
		427	/* Return function status */
		428	return HAL_OK;
		429	}
		430
		431	/**
		432	* @brief Starts the TIM Base generation in interrupt mode.
		433	* @param htim TIM Base handle
		434	* @retval HAL status
		435	*/
		436	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
		437	{
		438	uint32_t tmpsmcr;
		439
		440	/* Check the parameters */
		441	assert_param(IS_TIM_INSTANCE(htim->Instance));
		442
		443	/* Enable the TIM Update interrupt */
		444	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
		445
		446	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		447	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		448	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		449	{
		450	__HAL_TIM_ENABLE(htim);
		451	}
		452
		453	/* Return function status */
		454	return HAL_OK;
		455	}
		456
		457	/**
		458	* @brief Stops the TIM Base generation in interrupt mode.
		459	* @param htim TIM Base handle
		460	* @retval HAL status
		461	*/
		462	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
		463	{
		464	/* Check the parameters */
		465	assert_param(IS_TIM_INSTANCE(htim->Instance));
		466	/* Disable the TIM Update interrupt */
		467	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
		468
		469	/* Disable the Peripheral */
		470	__HAL_TIM_DISABLE(htim);
		471
		472	/* Return function status */
		473	return HAL_OK;
		474	}
		475
		476	/**
		477	* @brief Starts the TIM Base generation in DMA mode.
		478	* @param htim TIM Base handle
		479	* @param pData The source Buffer address.
		480	* @param Length The length of data to be transferred from memory to peripheral.
		481	* @retval HAL status
		482	*/
		483	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
		484	{
		485	uint32_t tmpsmcr;
		486
		487	/* Check the parameters */
		488	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
		489
		490	if (htim->State == HAL_TIM_STATE_BUSY)
		491	{
		492	return HAL_BUSY;
		493	}
		494	else if (htim->State == HAL_TIM_STATE_READY)
		495	{
		496	if ((pData == NULL) && (Length > 0U))
		497	{
		498	return HAL_ERROR;
		499	}
		500	else
		501	{
		502	htim->State = HAL_TIM_STATE_BUSY;
		503	}
		504	}
		505	else
		506	{
		507	/* nothing to do */
		508	}
		509
		510	/* Set the DMA Period elapsed callbacks */
		511	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		512	htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
		513
		514	/* Set the DMA error callback */
		515	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		516
		517	/* Enable the DMA channel */
		518	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
		519	{
		520	return HAL_ERROR;
		521	}
		522
		523	/* Enable the TIM Update DMA request */
		524	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
		525
		526	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		527	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		528	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		529	{
		530	__HAL_TIM_ENABLE(htim);
		531	}
		532
		533	/* Return function status */
		534	return HAL_OK;
		535	}
		536
		537	/**
		538	* @brief Stops the TIM Base generation in DMA mode.
		539	* @param htim TIM Base handle
		540	* @retval HAL status
		541	*/
		542	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
		543	{
		544	/* Check the parameters */
		545	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
		546
		547	/* Disable the TIM Update DMA request */
		548	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
		549
		550	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
		551
		552	/* Disable the Peripheral */
		553	__HAL_TIM_DISABLE(htim);
		554
		555	/* Change the htim state */
		556	htim->State = HAL_TIM_STATE_READY;
		557
		558	/* Return function status */
		559	return HAL_OK;
		560	}
		561
		562	/**
		563	* @}
		564	*/
		565
		566	/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		567	* @brief TIM Output Compare functions
		568	*
		569	@verbatim
		570	==============================================================================
		571	##### TIM Output Compare functions #####
		572	==============================================================================
		573	[..]
		574	This section provides functions allowing to:
		575	(+) Initialize and configure the TIM Output Compare.
		576	(+) De-initialize the TIM Output Compare.
		577	(+) Start the TIM Output Compare.
		578	(+) Stop the TIM Output Compare.
		579	(+) Start the TIM Output Compare and enable interrupt.
		580	(+) Stop the TIM Output Compare and disable interrupt.
		581	(+) Start the TIM Output Compare and enable DMA transfer.
		582	(+) Stop the TIM Output Compare and disable DMA transfer.
		583
		584	@endverbatim
		585	* @{
		586	*/
		587	/**
		588	* @brief Initializes the TIM Output Compare according to the specified
		589	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		590	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		591	* requires a timer reset to avoid unexpected direction
		592	* due to DIR bit readonly in center aligned mode.
		593	* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
		594	* @param htim TIM Output Compare handle
		595	* @retval HAL status
		596	*/
		597	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
		598	{
		599	/* Check the TIM handle allocation */
		600	if (htim == NULL)
		601	{
		602	return HAL_ERROR;
		603	}
		604
		605	/* Check the parameters */
		606	assert_param(IS_TIM_INSTANCE(htim->Instance));
		607	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		608	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		609	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		610
		611	if (htim->State == HAL_TIM_STATE_RESET)
		612	{
		613	/* Allocate lock resource and initialize it */
		614	htim->Lock = HAL_UNLOCKED;
		615
		616	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		617	/* Reset interrupt callbacks to legacy weak callbacks */
		618	TIM_ResetCallback(htim);
		619
		620	if (htim->OC_MspInitCallback == NULL)
		621	{
		622	htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
		623	}
		624	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		625	htim->OC_MspInitCallback(htim);
		626	#else
		627	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		628	HAL_TIM_OC_MspInit(htim);
		629	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		630	}
		631
		632	/* Set the TIM state */
		633	htim->State = HAL_TIM_STATE_BUSY;
		634
		635	/* Init the base time for the Output Compare */
		636	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		637
		638	/* Initialize the TIM state*/
		639	htim->State = HAL_TIM_STATE_READY;
		640
		641	return HAL_OK;
		642	}
		643
		644	/**
		645	* @brief DeInitializes the TIM peripheral
		646	* @param htim TIM Output Compare handle
		647	* @retval HAL status
		648	*/
		649	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
		650	{
		651	/* Check the parameters */
		652	assert_param(IS_TIM_INSTANCE(htim->Instance));
		653
		654	htim->State = HAL_TIM_STATE_BUSY;
		655
		656	/* Disable the TIM Peripheral Clock */
		657	__HAL_TIM_DISABLE(htim);
		658
		659	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		660	if (htim->OC_MspDeInitCallback == NULL)
		661	{
		662	htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
		663	}
		664	/* DeInit the low level hardware */
		665	htim->OC_MspDeInitCallback(htim);
		666	#else
		667	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		668	HAL_TIM_OC_MspDeInit(htim);
		669	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		670
		671	/* Change TIM state */
		672	htim->State = HAL_TIM_STATE_RESET;
		673
		674	/* Release Lock */
		675	__HAL_UNLOCK(htim);
		676
		677	return HAL_OK;
		678	}
		679
		680	/**
		681	* @brief Initializes the TIM Output Compare MSP.
		682	* @param htim TIM Output Compare handle
		683	* @retval None
		684	*/
		685	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
		686	{
		687	/* Prevent unused argument(s) compilation warning */
		688	UNUSED(htim);
		689
		690	/* NOTE : This function should not be modified, when the callback is needed,
		691	the HAL_TIM_OC_MspInit could be implemented in the user file
		692	*/
		693	}
		694
		695	/**
		696	* @brief DeInitializes TIM Output Compare MSP.
		697	* @param htim TIM Output Compare handle
		698	* @retval None
		699	*/
		700	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
		701	{
		702	/* Prevent unused argument(s) compilation warning */
		703	UNUSED(htim);
		704
		705	/* NOTE : This function should not be modified, when the callback is needed,
		706	the HAL_TIM_OC_MspDeInit could be implemented in the user file
		707	*/
		708	}
		709
		710	/**
		711	* @brief Starts the TIM Output Compare signal generation.
		712	* @param htim TIM Output Compare handle
		713	* @param Channel TIM Channel to be enabled
		714	* This parameter can be one of the following values:
		715	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		716	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		717	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		718	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		719	* @retval HAL status
		720	*/
		721	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		722	{
		723	uint32_t tmpsmcr;
		724
		725	/* Check the parameters */
		726	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		727
		728	/* Enable the Output compare channel */
		729	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		730
		731	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		732	{
		733	/* Enable the main output */
		734	__HAL_TIM_MOE_ENABLE(htim);
		735	}
		736
		737	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		738	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		739	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		740	{
		741	__HAL_TIM_ENABLE(htim);
		742	}
		743
		744	/* Return function status */
		745	return HAL_OK;
		746	}
		747
		748	/**
		749	* @brief Stops the TIM Output Compare signal generation.
		750	* @param htim TIM Output Compare handle
		751	* @param Channel TIM Channel to be disabled
		752	* This parameter can be one of the following values:
		753	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		754	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		755	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		756	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		757	* @retval HAL status
		758	*/
		759	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		760	{
		761	/* Check the parameters */
		762	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		763
		764	/* Disable the Output compare channel */
		765	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		766
		767	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		768	{
		769	/* Disable the Main Output */
		770	__HAL_TIM_MOE_DISABLE(htim);
		771	}
		772
		773	/* Disable the Peripheral */
		774	__HAL_TIM_DISABLE(htim);
		775
		776	/* Return function status */
		777	return HAL_OK;
		778	}
		779
		780	/**
		781	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
		782	* @param htim TIM Output Compare handle
		783	* @param Channel TIM Channel to be enabled
		784	* This parameter can be one of the following values:
		785	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		786	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		787	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		788	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		789	* @retval HAL status
		790	*/
		791	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		792	{
		793	uint32_t tmpsmcr;
		794
		795	/* Check the parameters */
		796	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		797
		798	switch (Channel)
		799	{
		800	case TIM_CHANNEL_1:
		801	{
		802	/* Enable the TIM Capture/Compare 1 interrupt */
		803	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		804	break;
		805	}
		806
		807	case TIM_CHANNEL_2:
		808	{
		809	/* Enable the TIM Capture/Compare 2 interrupt */
		810	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		811	break;
		812	}
		813
		814	case TIM_CHANNEL_3:
		815	{
		816	/* Enable the TIM Capture/Compare 3 interrupt */
		817	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		818	break;
		819	}
		820
		821	case TIM_CHANNEL_4:
		822	{
		823	/* Enable the TIM Capture/Compare 4 interrupt */
		824	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		825	break;
		826	}
		827
		828	default:
		829	break;
		830	}
		831
		832	/* Enable the Output compare channel */
		833	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		834
		835	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		836	{
		837	/* Enable the main output */
		838	__HAL_TIM_MOE_ENABLE(htim);
		839	}
		840
		841	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		842	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		843	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		844	{
		845	__HAL_TIM_ENABLE(htim);
		846	}
		847
		848	/* Return function status */
		849	return HAL_OK;
		850	}
		851
		852	/**
		853	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
		854	* @param htim TIM Output Compare handle
		855	* @param Channel TIM Channel to be disabled
		856	* This parameter can be one of the following values:
		857	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		858	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		859	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		860	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		861	* @retval HAL status
		862	*/
		863	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		864	{
		865	/* Check the parameters */
		866	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		867
		868	switch (Channel)
		869	{
		870	case TIM_CHANNEL_1:
		871	{
		872	/* Disable the TIM Capture/Compare 1 interrupt */
		873	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		874	break;
		875	}
		876
		877	case TIM_CHANNEL_2:
		878	{
		879	/* Disable the TIM Capture/Compare 2 interrupt */
		880	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		881	break;
		882	}
		883
		884	case TIM_CHANNEL_3:
		885	{
		886	/* Disable the TIM Capture/Compare 3 interrupt */
		887	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		888	break;
		889	}
		890
		891	case TIM_CHANNEL_4:
		892	{
		893	/* Disable the TIM Capture/Compare 4 interrupt */
		894	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		895	break;
		896	}
		897
		898	default:
		899	break;
		900	}
		901
		902	/* Disable the Output compare channel */
		903	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		904
		905	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		906	{
		907	/* Disable the Main Output */
		908	__HAL_TIM_MOE_DISABLE(htim);
		909	}
		910
		911	/* Disable the Peripheral */
		912	__HAL_TIM_DISABLE(htim);
		913
		914	/* Return function status */
		915	return HAL_OK;
		916	}
		917
		918	/**
		919	* @brief Starts the TIM Output Compare signal generation in DMA mode.
		920	* @param htim TIM Output Compare handle
		921	* @param Channel TIM Channel to be enabled
		922	* This parameter can be one of the following values:
		923	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		924	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		925	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		926	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		927	* @param pData The source Buffer address.
		928	* @param Length The length of data to be transferred from memory to TIM peripheral
		929	* @retval HAL status
		930	*/
		931	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		932	{
		933	uint32_t tmpsmcr;
		934
		935	/* Check the parameters */
		936	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		937
		938	if (htim->State == HAL_TIM_STATE_BUSY)
		939	{
		940	return HAL_BUSY;
		941	}
		942	else if (htim->State == HAL_TIM_STATE_READY)
		943	{
		944	if ((pData == NULL) && (Length > 0U))
		945	{
		946	return HAL_ERROR;
		947	}
		948	else
		949	{
		950	htim->State = HAL_TIM_STATE_BUSY;
		951	}
		952	}
		953	else
		954	{
		955	/* nothing to do */
		956	}
		957
		958	switch (Channel)
		959	{
		960	case TIM_CHANNEL_1:
		961	{
		962	/* Set the DMA compare callbacks */
		963	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		964	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		965
		966	/* Set the DMA error callback */
		967	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		968
		969	/* Enable the DMA channel */
		970	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
		971	{
		972	return HAL_ERROR;
		973	}
		974
		975	/* Enable the TIM Capture/Compare 1 DMA request */
		976	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		977	break;
		978	}
		979
		980	case TIM_CHANNEL_2:
		981	{
		982	/* Set the DMA compare callbacks */
		983	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		984	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		985
		986	/* Set the DMA error callback */
		987	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		988
		989	/* Enable the DMA channel */
		990	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
		991	{
		992	return HAL_ERROR;
		993	}
		994
		995	/* Enable the TIM Capture/Compare 2 DMA request */
		996	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		997	break;
		998	}
		999
		1000	case TIM_CHANNEL_3:
		1001	{
		1002	/* Set the DMA compare callbacks */
		1003	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1004	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1005
		1006	/* Set the DMA error callback */
		1007	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		1008
		1009	/* Enable the DMA channel */
		1010	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
		1011	{
		1012	return HAL_ERROR;
		1013	}
		1014	/* Enable the TIM Capture/Compare 3 DMA request */
		1015	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		1016	break;
		1017	}
		1018
		1019	case TIM_CHANNEL_4:
		1020	{
		1021	/* Set the DMA compare callbacks */
		1022	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1023	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1024
		1025	/* Set the DMA error callback */
		1026	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		1027
		1028	/* Enable the DMA channel */
		1029	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
		1030	{
		1031	return HAL_ERROR;
		1032	}
		1033	/* Enable the TIM Capture/Compare 4 DMA request */
		1034	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		1035	break;
		1036	}
		1037
		1038	default:
		1039	break;
		1040	}
		1041
		1042	/* Enable the Output compare channel */
		1043	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1044
		1045	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1046	{
		1047	/* Enable the main output */
		1048	__HAL_TIM_MOE_ENABLE(htim);
		1049	}
		1050
		1051	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1052	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1053	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1054	{
		1055	__HAL_TIM_ENABLE(htim);
		1056	}
		1057
		1058	/* Return function status */
		1059	return HAL_OK;
		1060	}
		1061
		1062	/**
		1063	* @brief Stops the TIM Output Compare signal generation in DMA mode.
		1064	* @param htim TIM Output Compare handle
		1065	* @param Channel TIM Channel to be disabled
		1066	* This parameter can be one of the following values:
		1067	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1068	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1069	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1070	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1071	* @retval HAL status
		1072	*/
		1073	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		1074	{
		1075	/* Check the parameters */
		1076	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1077
		1078	switch (Channel)
		1079	{
		1080	case TIM_CHANNEL_1:
		1081	{
		1082	/* Disable the TIM Capture/Compare 1 DMA request */
		1083	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		1084	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		1085	break;
		1086	}
		1087
		1088	case TIM_CHANNEL_2:
		1089	{
		1090	/* Disable the TIM Capture/Compare 2 DMA request */
		1091	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		1092	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		1093	break;
		1094	}
		1095
		1096	case TIM_CHANNEL_3:
		1097	{
		1098	/* Disable the TIM Capture/Compare 3 DMA request */
		1099	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		1100	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		1101	break;
		1102	}
		1103
		1104	case TIM_CHANNEL_4:
		1105	{
		1106	/* Disable the TIM Capture/Compare 4 interrupt */
		1107	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		1108	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		1109	break;
		1110	}
		1111
		1112	default:
		1113	break;
		1114	}
		1115
		1116	/* Disable the Output compare channel */
		1117	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1118
		1119	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1120	{
		1121	/* Disable the Main Output */
		1122	__HAL_TIM_MOE_DISABLE(htim);
		1123	}
		1124
		1125	/* Disable the Peripheral */
		1126	__HAL_TIM_DISABLE(htim);
		1127
		1128	/* Change the htim state */
		1129	htim->State = HAL_TIM_STATE_READY;
		1130
		1131	/* Return function status */
		1132	return HAL_OK;
		1133	}
		1134
		1135	/**
		1136	* @}
		1137	*/
		1138
		1139	/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
		1140	* @brief TIM PWM functions
		1141	*
		1142	@verbatim
		1143	==============================================================================
		1144	##### TIM PWM functions #####
		1145	==============================================================================
		1146	[..]
		1147	This section provides functions allowing to:
		1148	(+) Initialize and configure the TIM PWM.
		1149	(+) De-initialize the TIM PWM.
		1150	(+) Start the TIM PWM.
		1151	(+) Stop the TIM PWM.
		1152	(+) Start the TIM PWM and enable interrupt.
		1153	(+) Stop the TIM PWM and disable interrupt.
		1154	(+) Start the TIM PWM and enable DMA transfer.
		1155	(+) Stop the TIM PWM and disable DMA transfer.
		1156
		1157	@endverbatim
		1158	* @{
		1159	*/
		1160	/**
		1161	* @brief Initializes the TIM PWM Time Base according to the specified
		1162	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		1163	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1164	* requires a timer reset to avoid unexpected direction
		1165	* due to DIR bit readonly in center aligned mode.
		1166	* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
		1167	* @param htim TIM PWM handle
		1168	* @retval HAL status
		1169	*/
		1170	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
		1171	{
		1172	/* Check the TIM handle allocation */
		1173	if (htim == NULL)
		1174	{
		1175	return HAL_ERROR;
		1176	}
		1177
		1178	/* Check the parameters */
		1179	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1180	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		1181	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		1182	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		1183
		1184	if (htim->State == HAL_TIM_STATE_RESET)
		1185	{
		1186	/* Allocate lock resource and initialize it */
		1187	htim->Lock = HAL_UNLOCKED;
		1188
		1189	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1190	/* Reset interrupt callbacks to legacy weak callbacks */
		1191	TIM_ResetCallback(htim);
		1192
		1193	if (htim->PWM_MspInitCallback == NULL)
		1194	{
		1195	htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
		1196	}
		1197	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		1198	htim->PWM_MspInitCallback(htim);
		1199	#else
		1200	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		1201	HAL_TIM_PWM_MspInit(htim);
		1202	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1203	}
		1204
		1205	/* Set the TIM state */
		1206	htim->State = HAL_TIM_STATE_BUSY;
		1207
		1208	/* Init the base time for the PWM */
		1209	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1210
		1211	/* Initialize the TIM state*/
		1212	htim->State = HAL_TIM_STATE_READY;
		1213
		1214	return HAL_OK;
		1215	}
		1216
		1217	/**
		1218	* @brief DeInitializes the TIM peripheral
		1219	* @param htim TIM PWM handle
		1220	* @retval HAL status
		1221	*/
		1222	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
		1223	{
		1224	/* Check the parameters */
		1225	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1226
		1227	htim->State = HAL_TIM_STATE_BUSY;
		1228
		1229	/* Disable the TIM Peripheral Clock */
		1230	__HAL_TIM_DISABLE(htim);
		1231
		1232	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1233	if (htim->PWM_MspDeInitCallback == NULL)
		1234	{
		1235	htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
		1236	}
		1237	/* DeInit the low level hardware */
		1238	htim->PWM_MspDeInitCallback(htim);
		1239	#else
		1240	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		1241	HAL_TIM_PWM_MspDeInit(htim);
		1242	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1243
		1244	/* Change TIM state */
		1245	htim->State = HAL_TIM_STATE_RESET;
		1246
		1247	/* Release Lock */
		1248	__HAL_UNLOCK(htim);
		1249
		1250	return HAL_OK;
		1251	}
		1252
		1253	/**
		1254	* @brief Initializes the TIM PWM MSP.
		1255	* @param htim TIM PWM handle
		1256	* @retval None
		1257	*/
		1258	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
		1259	{
		1260	/* Prevent unused argument(s) compilation warning */
		1261	UNUSED(htim);
		1262
		1263	/* NOTE : This function should not be modified, when the callback is needed,
		1264	the HAL_TIM_PWM_MspInit could be implemented in the user file
		1265	*/
		1266	}
		1267
		1268	/**
		1269	* @brief DeInitializes TIM PWM MSP.
		1270	* @param htim TIM PWM handle
		1271	* @retval None
		1272	*/
		1273	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
		1274	{
		1275	/* Prevent unused argument(s) compilation warning */
		1276	UNUSED(htim);
		1277
		1278	/* NOTE : This function should not be modified, when the callback is needed,
		1279	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
		1280	*/
		1281	}
		1282
		1283	/**
		1284	* @brief Starts the PWM signal generation.
		1285	* @param htim TIM handle
		1286	* @param Channel TIM Channels to be enabled
		1287	* This parameter can be one of the following values:
		1288	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1289	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1290	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1291	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1292	* @retval HAL status
		1293	*/
		1294	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		1295	{
		1296	uint32_t tmpsmcr;
		1297
		1298	/* Check the parameters */
		1299	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1300
		1301	/* Enable the Capture compare channel */
		1302	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1303
		1304	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1305	{
		1306	/* Enable the main output */
		1307	__HAL_TIM_MOE_ENABLE(htim);
		1308	}
		1309
		1310	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1311	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1312	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1313	{
		1314	__HAL_TIM_ENABLE(htim);
		1315	}
		1316
		1317	/* Return function status */
		1318	return HAL_OK;
		1319	}
		1320
		1321	/**
		1322	* @brief Stops the PWM signal generation.
		1323	* @param htim TIM PWM handle
		1324	* @param Channel TIM Channels to be disabled
		1325	* This parameter can be one of the following values:
		1326	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1327	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1328	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1329	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1330	* @retval HAL status
		1331	*/
		1332	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		1333	{
		1334	/* Check the parameters */
		1335	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1336
		1337	/* Disable the Capture compare channel */
		1338	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1339
		1340	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1341	{
		1342	/* Disable the Main Output */
		1343	__HAL_TIM_MOE_DISABLE(htim);
		1344	}
		1345
		1346	/* Disable the Peripheral */
		1347	__HAL_TIM_DISABLE(htim);
		1348
		1349	/* Change the htim state */
		1350	htim->State = HAL_TIM_STATE_READY;
		1351
		1352	/* Return function status */
		1353	return HAL_OK;
		1354	}
		1355
		1356	/**
		1357	* @brief Starts the PWM signal generation in interrupt mode.
		1358	* @param htim TIM PWM handle
		1359	* @param Channel TIM Channel to be enabled
		1360	* This parameter can be one of the following values:
		1361	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1362	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1363	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1364	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1365	* @retval HAL status
		1366	*/
		1367	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1368	{
		1369	uint32_t tmpsmcr;
		1370	/* Check the parameters */
		1371	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1372
		1373	switch (Channel)
		1374	{
		1375	case TIM_CHANNEL_1:
		1376	{
		1377	/* Enable the TIM Capture/Compare 1 interrupt */
		1378	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		1379	break;
		1380	}
		1381
		1382	case TIM_CHANNEL_2:
		1383	{
		1384	/* Enable the TIM Capture/Compare 2 interrupt */
		1385	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		1386	break;
		1387	}
		1388
		1389	case TIM_CHANNEL_3:
		1390	{
		1391	/* Enable the TIM Capture/Compare 3 interrupt */
		1392	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		1393	break;
		1394	}
		1395
		1396	case TIM_CHANNEL_4:
		1397	{
		1398	/* Enable the TIM Capture/Compare 4 interrupt */
		1399	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		1400	break;
		1401	}
		1402
		1403	default:
		1404	break;
		1405	}
		1406
		1407	/* Enable the Capture compare channel */
		1408	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1409
		1410	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1411	{
		1412	/* Enable the main output */
		1413	__HAL_TIM_MOE_ENABLE(htim);
		1414	}
		1415
		1416	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1417	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1418	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1419	{
		1420	__HAL_TIM_ENABLE(htim);
		1421	}
		1422
		1423	/* Return function status */
		1424	return HAL_OK;
		1425	}
		1426
		1427	/**
		1428	* @brief Stops the PWM signal generation in interrupt mode.
		1429	* @param htim TIM PWM handle
		1430	* @param Channel TIM Channels to be disabled
		1431	* This parameter can be one of the following values:
		1432	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1433	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1434	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1435	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1436	* @retval HAL status
		1437	*/
		1438	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1439	{
		1440	/* Check the parameters */
		1441	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1442
		1443	switch (Channel)
		1444	{
		1445	case TIM_CHANNEL_1:
		1446	{
		1447	/* Disable the TIM Capture/Compare 1 interrupt */
		1448	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		1449	break;
		1450	}
		1451
		1452	case TIM_CHANNEL_2:
		1453	{
		1454	/* Disable the TIM Capture/Compare 2 interrupt */
		1455	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		1456	break;
		1457	}
		1458
		1459	case TIM_CHANNEL_3:
		1460	{
		1461	/* Disable the TIM Capture/Compare 3 interrupt */
		1462	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		1463	break;
		1464	}
		1465
		1466	case TIM_CHANNEL_4:
		1467	{
		1468	/* Disable the TIM Capture/Compare 4 interrupt */
		1469	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		1470	break;
		1471	}
		1472
		1473	default:
		1474	break;
		1475	}
		1476
		1477	/* Disable the Capture compare channel */
		1478	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1479
		1480	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1481	{
		1482	/* Disable the Main Output */
		1483	__HAL_TIM_MOE_DISABLE(htim);
		1484	}
		1485
		1486	/* Disable the Peripheral */
		1487	__HAL_TIM_DISABLE(htim);
		1488
		1489	/* Return function status */
		1490	return HAL_OK;
		1491	}
		1492
		1493	/**
		1494	* @brief Starts the TIM PWM signal generation in DMA mode.
		1495	* @param htim TIM PWM handle
		1496	* @param Channel TIM Channels to be enabled
		1497	* This parameter can be one of the following values:
		1498	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1499	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1500	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1501	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1502	* @param pData The source Buffer address.
		1503	* @param Length The length of data to be transferred from memory to TIM peripheral
		1504	* @retval HAL status
		1505	*/
		1506	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		1507	{
		1508	uint32_t tmpsmcr;
		1509
		1510	/* Check the parameters */
		1511	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1512
		1513	if (htim->State == HAL_TIM_STATE_BUSY)
		1514	{
		1515	return HAL_BUSY;
		1516	}
		1517	else if (htim->State == HAL_TIM_STATE_READY)
		1518	{
		1519	if ((pData == NULL) && (Length > 0U))
		1520	{
		1521	return HAL_ERROR;
		1522	}
		1523	else
		1524	{
		1525	htim->State = HAL_TIM_STATE_BUSY;
		1526	}
		1527	}
		1528	else
		1529	{
		1530	/* nothing to do */
		1531	}
		1532
		1533	switch (Channel)
		1534	{
		1535	case TIM_CHANNEL_1:
		1536	{
		1537	/* Set the DMA compare callbacks */
		1538	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1539	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1540
		1541	/* Set the DMA error callback */
		1542	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		1543
		1544	/* Enable the DMA channel */
		1545	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
		1546	{
		1547	return HAL_ERROR;
		1548	}
		1549
		1550	/* Enable the TIM Capture/Compare 1 DMA request */
		1551	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		1552	break;
		1553	}
		1554
		1555	case TIM_CHANNEL_2:
		1556	{
		1557	/* Set the DMA compare callbacks */
		1558	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1559	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1560
		1561	/* Set the DMA error callback */
		1562	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		1563
		1564	/* Enable the DMA channel */
		1565	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
		1566	{
		1567	return HAL_ERROR;
		1568	}
		1569	/* Enable the TIM Capture/Compare 2 DMA request */
		1570	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		1571	break;
		1572	}
		1573
		1574	case TIM_CHANNEL_3:
		1575	{
		1576	/* Set the DMA compare callbacks */
		1577	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1578	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1579
		1580	/* Set the DMA error callback */
		1581	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		1582
		1583	/* Enable the DMA channel */
		1584	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
		1585	{
		1586	return HAL_ERROR;
		1587	}
		1588	/* Enable the TIM Output Capture/Compare 3 request */
		1589	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		1590	break;
		1591	}
		1592
		1593	case TIM_CHANNEL_4:
		1594	{
		1595	/* Set the DMA compare callbacks */
		1596	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		1597	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		1598
		1599	/* Set the DMA error callback */
		1600	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		1601
		1602	/* Enable the DMA channel */
		1603	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
		1604	{
		1605	return HAL_ERROR;
		1606	}
		1607	/* Enable the TIM Capture/Compare 4 DMA request */
		1608	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		1609	break;
		1610	}
		1611
		1612	default:
		1613	break;
		1614	}
		1615
		1616	/* Enable the Capture compare channel */
		1617	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1618
		1619	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1620	{
		1621	/* Enable the main output */
		1622	__HAL_TIM_MOE_ENABLE(htim);
		1623	}
		1624
		1625	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1626	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1627	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1628	{
		1629	__HAL_TIM_ENABLE(htim);
		1630	}
		1631
		1632	/* Return function status */
		1633	return HAL_OK;
		1634	}
		1635
		1636	/**
		1637	* @brief Stops the TIM PWM signal generation in DMA mode.
		1638	* @param htim TIM PWM handle
		1639	* @param Channel TIM Channels to be disabled
		1640	* This parameter can be one of the following values:
		1641	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1642	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1643	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1644	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1645	* @retval HAL status
		1646	*/
		1647	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		1648	{
		1649	/* Check the parameters */
		1650	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1651
		1652	switch (Channel)
		1653	{
		1654	case TIM_CHANNEL_1:
		1655	{
		1656	/* Disable the TIM Capture/Compare 1 DMA request */
		1657	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		1658	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		1659	break;
		1660	}
		1661
		1662	case TIM_CHANNEL_2:
		1663	{
		1664	/* Disable the TIM Capture/Compare 2 DMA request */
		1665	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		1666	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		1667	break;
		1668	}
		1669
		1670	case TIM_CHANNEL_3:
		1671	{
		1672	/* Disable the TIM Capture/Compare 3 DMA request */
		1673	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		1674	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		1675	break;
		1676	}
		1677
		1678	case TIM_CHANNEL_4:
		1679	{
		1680	/* Disable the TIM Capture/Compare 4 interrupt */
		1681	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		1682	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		1683	break;
		1684	}
		1685
		1686	default:
		1687	break;
		1688	}
		1689
		1690	/* Disable the Capture compare channel */
		1691	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1692
		1693	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		1694	{
		1695	/* Disable the Main Output */
		1696	__HAL_TIM_MOE_DISABLE(htim);
		1697	}
		1698
		1699	/* Disable the Peripheral */
		1700	__HAL_TIM_DISABLE(htim);
		1701
		1702	/* Change the htim state */
		1703	htim->State = HAL_TIM_STATE_READY;
		1704
		1705	/* Return function status */
		1706	return HAL_OK;
		1707	}
		1708
		1709	/**
		1710	* @}
		1711	*/
		1712
		1713	/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1714	* @brief TIM Input Capture functions
		1715	*
		1716	@verbatim
		1717	==============================================================================
		1718	##### TIM Input Capture functions #####
		1719	==============================================================================
		1720	[..]
		1721	This section provides functions allowing to:
		1722	(+) Initialize and configure the TIM Input Capture.
		1723	(+) De-initialize the TIM Input Capture.
		1724	(+) Start the TIM Input Capture.
		1725	(+) Stop the TIM Input Capture.
		1726	(+) Start the TIM Input Capture and enable interrupt.
		1727	(+) Stop the TIM Input Capture and disable interrupt.
		1728	(+) Start the TIM Input Capture and enable DMA transfer.
		1729	(+) Stop the TIM Input Capture and disable DMA transfer.
		1730
		1731	@endverbatim
		1732	* @{
		1733	*/
		1734	/**
		1735	* @brief Initializes the TIM Input Capture Time base according to the specified
		1736	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		1737	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1738	* requires a timer reset to avoid unexpected direction
		1739	* due to DIR bit readonly in center aligned mode.
		1740	* Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
		1741	* @param htim TIM Input Capture handle
		1742	* @retval HAL status
		1743	*/
		1744	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
		1745	{
		1746	/* Check the TIM handle allocation */
		1747	if (htim == NULL)
		1748	{
		1749	return HAL_ERROR;
		1750	}
		1751
		1752	/* Check the parameters */
		1753	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1754	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		1755	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		1756	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		1757
		1758	if (htim->State == HAL_TIM_STATE_RESET)
		1759	{
		1760	/* Allocate lock resource and initialize it */
		1761	htim->Lock = HAL_UNLOCKED;
		1762
		1763	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1764	/* Reset interrupt callbacks to legacy weak callbacks */
		1765	TIM_ResetCallback(htim);
		1766
		1767	if (htim->IC_MspInitCallback == NULL)
		1768	{
		1769	htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
		1770	}
		1771	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		1772	htim->IC_MspInitCallback(htim);
		1773	#else
		1774	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		1775	HAL_TIM_IC_MspInit(htim);
		1776	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1777	}
		1778
		1779	/* Set the TIM state */
		1780	htim->State = HAL_TIM_STATE_BUSY;
		1781
		1782	/* Init the base time for the input capture */
		1783	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		1784
		1785	/* Initialize the TIM state*/
		1786	htim->State = HAL_TIM_STATE_READY;
		1787
		1788	return HAL_OK;
		1789	}
		1790
		1791	/**
		1792	* @brief DeInitializes the TIM peripheral
		1793	* @param htim TIM Input Capture handle
		1794	* @retval HAL status
		1795	*/
		1796	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
		1797	{
		1798	/* Check the parameters */
		1799	assert_param(IS_TIM_INSTANCE(htim->Instance));
		1800
		1801	htim->State = HAL_TIM_STATE_BUSY;
		1802
		1803	/* Disable the TIM Peripheral Clock */
		1804	__HAL_TIM_DISABLE(htim);
		1805
		1806	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1807	if (htim->IC_MspDeInitCallback == NULL)
		1808	{
		1809	htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
		1810	}
		1811	/* DeInit the low level hardware */
		1812	htim->IC_MspDeInitCallback(htim);
		1813	#else
		1814	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
		1815	HAL_TIM_IC_MspDeInit(htim);
		1816	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1817
		1818	/* Change TIM state */
		1819	htim->State = HAL_TIM_STATE_RESET;
		1820
		1821	/* Release Lock */
		1822	__HAL_UNLOCK(htim);
		1823
		1824	return HAL_OK;
		1825	}
		1826
		1827	/**
		1828	* @brief Initializes the TIM Input Capture MSP.
		1829	* @param htim TIM Input Capture handle
		1830	* @retval None
		1831	*/
		1832	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
		1833	{
		1834	/* Prevent unused argument(s) compilation warning */
		1835	UNUSED(htim);
		1836
		1837	/* NOTE : This function should not be modified, when the callback is needed,
		1838	the HAL_TIM_IC_MspInit could be implemented in the user file
		1839	*/
		1840	}
		1841
		1842	/**
		1843	* @brief DeInitializes TIM Input Capture MSP.
		1844	* @param htim TIM handle
		1845	* @retval None
		1846	*/
		1847	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
		1848	{
		1849	/* Prevent unused argument(s) compilation warning */
		1850	UNUSED(htim);
		1851
		1852	/* NOTE : This function should not be modified, when the callback is needed,
		1853	the HAL_TIM_IC_MspDeInit could be implemented in the user file
		1854	*/
		1855	}
		1856
		1857	/**
		1858	* @brief Starts the TIM Input Capture measurement.
		1859	* @param htim TIM Input Capture handle
		1860	* @param Channel TIM Channels to be enabled
		1861	* This parameter can be one of the following values:
		1862	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1863	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1864	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1865	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1866	* @retval HAL status
		1867	*/
		1868	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		1869	{
		1870	uint32_t tmpsmcr;
		1871
		1872	/* Check the parameters */
		1873	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1874
		1875	/* Enable the Input Capture channel */
		1876	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1877
		1878	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1879	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1880	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1881	{
		1882	__HAL_TIM_ENABLE(htim);
		1883	}
		1884
		1885	/* Return function status */
		1886	return HAL_OK;
		1887	}
		1888
		1889	/**
		1890	* @brief Stops the TIM Input Capture measurement.
		1891	* @param htim TIM Input Capture handle
		1892	* @param Channel TIM Channels to be disabled
		1893	* This parameter can be one of the following values:
		1894	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1895	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1896	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1897	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1898	* @retval HAL status
		1899	*/
		1900	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		1901	{
		1902	/* Check the parameters */
		1903	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1904
		1905	/* Disable the Input Capture channel */
		1906	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		1907
		1908	/* Disable the Peripheral */
		1909	__HAL_TIM_DISABLE(htim);
		1910
		1911	/* Return function status */
		1912	return HAL_OK;
		1913	}
		1914
		1915	/**
		1916	* @brief Starts the TIM Input Capture measurement in interrupt mode.
		1917	* @param htim TIM Input Capture handle
		1918	* @param Channel TIM Channels to be enabled
		1919	* This parameter can be one of the following values:
		1920	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1921	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1922	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1923	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1924	* @retval HAL status
		1925	*/
		1926	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1927	{
		1928	uint32_t tmpsmcr;
		1929
		1930	/* Check the parameters */
		1931	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1932
		1933	switch (Channel)
		1934	{
		1935	case TIM_CHANNEL_1:
		1936	{
		1937	/* Enable the TIM Capture/Compare 1 interrupt */
		1938	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		1939	break;
		1940	}
		1941
		1942	case TIM_CHANNEL_2:
		1943	{
		1944	/* Enable the TIM Capture/Compare 2 interrupt */
		1945	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		1946	break;
		1947	}
		1948
		1949	case TIM_CHANNEL_3:
		1950	{
		1951	/* Enable the TIM Capture/Compare 3 interrupt */
		1952	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
		1953	break;
		1954	}
		1955
		1956	case TIM_CHANNEL_4:
		1957	{
		1958	/* Enable the TIM Capture/Compare 4 interrupt */
		1959	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
		1960	break;
		1961	}
		1962
		1963	default:
		1964	break;
		1965	}
		1966	/* Enable the Input Capture channel */
		1967	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		1968
		1969	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		1970	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		1971	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		1972	{
		1973	__HAL_TIM_ENABLE(htim);
		1974	}
		1975
		1976	/* Return function status */
		1977	return HAL_OK;
		1978	}
		1979
		1980	/**
		1981	* @brief Stops the TIM Input Capture measurement in interrupt mode.
		1982	* @param htim TIM Input Capture handle
		1983	* @param Channel TIM Channels to be disabled
		1984	* This parameter can be one of the following values:
		1985	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1986	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1987	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1988	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1989	* @retval HAL status
		1990	*/
		1991	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		1992	{
		1993	/* Check the parameters */
		1994	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		1995
		1996	switch (Channel)
		1997	{
		1998	case TIM_CHANNEL_1:
		1999	{
		2000	/* Disable the TIM Capture/Compare 1 interrupt */
		2001	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2002	break;
		2003	}
		2004
		2005	case TIM_CHANNEL_2:
		2006	{
		2007	/* Disable the TIM Capture/Compare 2 interrupt */
		2008	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2009	break;
		2010	}
		2011
		2012	case TIM_CHANNEL_3:
		2013	{
		2014	/* Disable the TIM Capture/Compare 3 interrupt */
		2015	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
		2016	break;
		2017	}
		2018
		2019	case TIM_CHANNEL_4:
		2020	{
		2021	/* Disable the TIM Capture/Compare 4 interrupt */
		2022	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
		2023	break;
		2024	}
		2025
		2026	default:
		2027	break;
		2028	}
		2029
		2030	/* Disable the Input Capture channel */
		2031	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		2032
		2033	/* Disable the Peripheral */
		2034	__HAL_TIM_DISABLE(htim);
		2035
		2036	/* Return function status */
		2037	return HAL_OK;
		2038	}
		2039
		2040	/**
		2041	* @brief Starts the TIM Input Capture measurement in DMA mode.
		2042	* @param htim TIM Input Capture handle
		2043	* @param Channel TIM Channels to be enabled
		2044	* This parameter can be one of the following values:
		2045	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2046	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2047	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		2048	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		2049	* @param pData The destination Buffer address.
		2050	* @param Length The length of data to be transferred from TIM peripheral to memory.
		2051	* @retval HAL status
		2052	*/
		2053	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
		2054	{
		2055	uint32_t tmpsmcr;
		2056
		2057	/* Check the parameters */
		2058	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		2059	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2060
		2061	if (htim->State == HAL_TIM_STATE_BUSY)
		2062	{
		2063	return HAL_BUSY;
		2064	}
		2065	else if (htim->State == HAL_TIM_STATE_READY)
		2066	{
		2067	if ((pData == NULL) && (Length > 0U))
		2068	{
		2069	return HAL_ERROR;
		2070	}
		2071	else
		2072	{
		2073	htim->State = HAL_TIM_STATE_BUSY;
		2074	}
		2075	}
		2076	else
		2077	{
		2078	/* nothing to do */
		2079	}
		2080
		2081	switch (Channel)
		2082	{
		2083	case TIM_CHANNEL_1:
		2084	{
		2085	/* Set the DMA capture callbacks */
		2086	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		2087	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2088
		2089	/* Set the DMA error callback */
		2090	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		2091
		2092	/* Enable the DMA channel */
		2093	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
		2094	{
		2095	return HAL_ERROR;
		2096	}
		2097	/* Enable the TIM Capture/Compare 1 DMA request */
		2098	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		2099	break;
		2100	}
		2101
		2102	case TIM_CHANNEL_2:
		2103	{
		2104	/* Set the DMA capture callbacks */
		2105	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		2106	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2107
		2108	/* Set the DMA error callback */
		2109	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		2110
		2111	/* Enable the DMA channel */
		2112	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
		2113	{
		2114	return HAL_ERROR;
		2115	}
		2116	/* Enable the TIM Capture/Compare 2 DMA request */
		2117	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		2118	break;
		2119	}
		2120
		2121	case TIM_CHANNEL_3:
		2122	{
		2123	/* Set the DMA capture callbacks */
		2124	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
		2125	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2126
		2127	/* Set the DMA error callback */
		2128	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		2129
		2130	/* Enable the DMA channel */
		2131	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
		2132	{
		2133	return HAL_ERROR;
		2134	}
		2135	/* Enable the TIM Capture/Compare 3 DMA request */
		2136	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
		2137	break;
		2138	}
		2139
		2140	case TIM_CHANNEL_4:
		2141	{
		2142	/* Set the DMA capture callbacks */
		2143	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
		2144	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2145
		2146	/* Set the DMA error callback */
		2147	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		2148
		2149	/* Enable the DMA channel */
		2150	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
		2151	{
		2152	return HAL_ERROR;
		2153	}
		2154	/* Enable the TIM Capture/Compare 4 DMA request */
		2155	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
		2156	break;
		2157	}
		2158
		2159	default:
		2160	break;
		2161	}
		2162
		2163	/* Enable the Input Capture channel */
		2164	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
		2165
		2166	/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
		2167	tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
		2168	if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
		2169	{
		2170	__HAL_TIM_ENABLE(htim);
		2171	}
		2172
		2173	/* Return function status */
		2174	return HAL_OK;
		2175	}
		2176
		2177	/**
		2178	* @brief Stops the TIM Input Capture measurement in DMA mode.
		2179	* @param htim TIM Input Capture handle
		2180	* @param Channel TIM Channels to be disabled
		2181	* This parameter can be one of the following values:
		2182	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2183	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2184	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		2185	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		2186	* @retval HAL status
		2187	*/
		2188	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		2189	{
		2190	/* Check the parameters */
		2191	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
		2192	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2193
		2194	switch (Channel)
		2195	{
		2196	case TIM_CHANNEL_1:
		2197	{
		2198	/* Disable the TIM Capture/Compare 1 DMA request */
		2199	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		2200	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		2201	break;
		2202	}
		2203
		2204	case TIM_CHANNEL_2:
		2205	{
		2206	/* Disable the TIM Capture/Compare 2 DMA request */
		2207	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		2208	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		2209	break;
		2210	}
		2211
		2212	case TIM_CHANNEL_3:
		2213	{
		2214	/* Disable the TIM Capture/Compare 3 DMA request */
		2215	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
		2216	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		2217	break;
		2218	}
		2219
		2220	case TIM_CHANNEL_4:
		2221	{
		2222	/* Disable the TIM Capture/Compare 4 DMA request */
		2223	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
		2224	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		2225	break;
		2226	}
		2227
		2228	default:
		2229	break;
		2230	}
		2231
		2232	/* Disable the Input Capture channel */
		2233	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
		2234
		2235	/* Disable the Peripheral */
		2236	__HAL_TIM_DISABLE(htim);
		2237
		2238	/* Change the htim state */
		2239	htim->State = HAL_TIM_STATE_READY;
		2240
		2241	/* Return function status */
		2242	return HAL_OK;
		2243	}
		2244	/**
		2245	* @}
		2246	*/
		2247
		2248	/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		2249	* @brief TIM One Pulse functions
		2250	*
		2251	@verbatim
		2252	==============================================================================
		2253	##### TIM One Pulse functions #####
		2254	==============================================================================
		2255	[..]
		2256	This section provides functions allowing to:
		2257	(+) Initialize and configure the TIM One Pulse.
		2258	(+) De-initialize the TIM One Pulse.
		2259	(+) Start the TIM One Pulse.
		2260	(+) Stop the TIM One Pulse.
		2261	(+) Start the TIM One Pulse and enable interrupt.
		2262	(+) Stop the TIM One Pulse and disable interrupt.
		2263	(+) Start the TIM One Pulse and enable DMA transfer.
		2264	(+) Stop the TIM One Pulse and disable DMA transfer.
		2265
		2266	@endverbatim
		2267	* @{
		2268	*/
		2269	/**
		2270	* @brief Initializes the TIM One Pulse Time Base according to the specified
		2271	* parameters in the TIM_HandleTypeDef and initializes the associated handle.
		2272	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		2273	* requires a timer reset to avoid unexpected direction
		2274	* due to DIR bit readonly in center aligned mode.
		2275	* Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
		2276	* @param htim TIM One Pulse handle
		2277	* @param OnePulseMode Select the One pulse mode.
		2278	* This parameter can be one of the following values:
		2279	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
		2280	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
		2281	* @retval HAL status
		2282	*/
		2283	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
		2284	{
		2285	/* Check the TIM handle allocation */
		2286	if (htim == NULL)
		2287	{
		2288	return HAL_ERROR;
		2289	}
		2290
		2291	/* Check the parameters */
		2292	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2293	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		2294	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		2295	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
		2296	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		2297
		2298	if (htim->State == HAL_TIM_STATE_RESET)
		2299	{
		2300	/* Allocate lock resource and initialize it */
		2301	htim->Lock = HAL_UNLOCKED;
		2302
		2303	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2304	/* Reset interrupt callbacks to legacy weak callbacks */
		2305	TIM_ResetCallback(htim);
		2306
		2307	if (htim->OnePulse_MspInitCallback == NULL)
		2308	{
		2309	htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
		2310	}
		2311	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		2312	htim->OnePulse_MspInitCallback(htim);
		2313	#else
		2314	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		2315	HAL_TIM_OnePulse_MspInit(htim);
		2316	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2317	}
		2318
		2319	/* Set the TIM state */
		2320	htim->State = HAL_TIM_STATE_BUSY;
		2321
		2322	/* Configure the Time base in the One Pulse Mode */
		2323	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		2324
		2325	/* Reset the OPM Bit */
		2326	htim->Instance->CR1 &= ~TIM_CR1_OPM;
		2327
		2328	/* Configure the OPM Mode */
		2329	htim->Instance->CR1 \|= OnePulseMode;
		2330
		2331	/* Initialize the TIM state*/
		2332	htim->State = HAL_TIM_STATE_READY;
		2333
		2334	return HAL_OK;
		2335	}
		2336
		2337	/**
		2338	* @brief DeInitializes the TIM One Pulse
		2339	* @param htim TIM One Pulse handle
		2340	* @retval HAL status
		2341	*/
		2342	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
		2343	{
		2344	/* Check the parameters */
		2345	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2346
		2347	htim->State = HAL_TIM_STATE_BUSY;
		2348
		2349	/* Disable the TIM Peripheral Clock */
		2350	__HAL_TIM_DISABLE(htim);
		2351
		2352	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2353	if (htim->OnePulse_MspDeInitCallback == NULL)
		2354	{
		2355	htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
		2356	}
		2357	/* DeInit the low level hardware */
		2358	htim->OnePulse_MspDeInitCallback(htim);
		2359	#else
		2360	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		2361	HAL_TIM_OnePulse_MspDeInit(htim);
		2362	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2363
		2364	/* Change TIM state */
		2365	htim->State = HAL_TIM_STATE_RESET;
		2366
		2367	/* Release Lock */
		2368	__HAL_UNLOCK(htim);
		2369
		2370	return HAL_OK;
		2371	}
		2372
		2373	/**
		2374	* @brief Initializes the TIM One Pulse MSP.
		2375	* @param htim TIM One Pulse handle
		2376	* @retval None
		2377	*/
		2378	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
		2379	{
		2380	/* Prevent unused argument(s) compilation warning */
		2381	UNUSED(htim);
		2382
		2383	/* NOTE : This function should not be modified, when the callback is needed,
		2384	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
		2385	*/
		2386	}
		2387
		2388	/**
		2389	* @brief DeInitializes TIM One Pulse MSP.
		2390	* @param htim TIM One Pulse handle
		2391	* @retval None
		2392	*/
		2393	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
		2394	{
		2395	/* Prevent unused argument(s) compilation warning */
		2396	UNUSED(htim);
		2397
		2398	/* NOTE : This function should not be modified, when the callback is needed,
		2399	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
		2400	*/
		2401	}
		2402
		2403	/**
		2404	* @brief Starts the TIM One Pulse signal generation.
		2405	* @param htim TIM One Pulse handle
		2406	* @param OutputChannel TIM Channels to be enabled
		2407	* This parameter can be one of the following values:
		2408	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2409	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2410	* @retval HAL status
		2411	*/
		2412	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2413	{
		2414	/* Prevent unused argument(s) compilation warning */
		2415	UNUSED(OutputChannel);
		2416
		2417	/* Enable the Capture compare and the Input Capture channels
		2418	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2419	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2420	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2421	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
		2422
		2423	No need to enable the counter, it's enabled automatically by hardware
		2424	(the counter starts in response to a stimulus and generate a pulse */
		2425
		2426	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2427	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2428
		2429	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2430	{
		2431	/* Enable the main output */
		2432	__HAL_TIM_MOE_ENABLE(htim);
		2433	}
		2434
		2435	/* Return function status */
		2436	return HAL_OK;
		2437	}
		2438
		2439	/**
		2440	* @brief Stops the TIM One Pulse signal generation.
		2441	* @param htim TIM One Pulse handle
		2442	* @param OutputChannel TIM Channels to be disable
		2443	* This parameter can be one of the following values:
		2444	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2445	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2446	* @retval HAL status
		2447	*/
		2448	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2449	{
		2450	/* Prevent unused argument(s) compilation warning */
		2451	UNUSED(OutputChannel);
		2452
		2453	/* Disable the Capture compare and the Input Capture channels
		2454	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2455	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2456	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2457	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
		2458
		2459	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2460	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2461
		2462	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2463	{
		2464	/* Disable the Main Output */
		2465	__HAL_TIM_MOE_DISABLE(htim);
		2466	}
		2467
		2468	/* Disable the Peripheral */
		2469	__HAL_TIM_DISABLE(htim);
		2470
		2471	/* Return function status */
		2472	return HAL_OK;
		2473	}
		2474
		2475	/**
		2476	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
		2477	* @param htim TIM One Pulse handle
		2478	* @param OutputChannel TIM Channels to be enabled
		2479	* This parameter can be one of the following values:
		2480	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2481	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2482	* @retval HAL status
		2483	*/
		2484	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2485	{
		2486	/* Prevent unused argument(s) compilation warning */
		2487	UNUSED(OutputChannel);
		2488
		2489	/* Enable the Capture compare and the Input Capture channels
		2490	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2491	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2492	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2493	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
		2494
		2495	No need to enable the counter, it's enabled automatically by hardware
		2496	(the counter starts in response to a stimulus and generate a pulse */
		2497
		2498	/* Enable the TIM Capture/Compare 1 interrupt */
		2499	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2500
		2501	/* Enable the TIM Capture/Compare 2 interrupt */
		2502	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2503
		2504	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2505	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2506
		2507	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2508	{
		2509	/* Enable the main output */
		2510	__HAL_TIM_MOE_ENABLE(htim);
		2511	}
		2512
		2513	/* Return function status */
		2514	return HAL_OK;
		2515	}
		2516
		2517	/**
		2518	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
		2519	* @param htim TIM One Pulse handle
		2520	* @param OutputChannel TIM Channels to be enabled
		2521	* This parameter can be one of the following values:
		2522	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2523	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2524	* @retval HAL status
		2525	*/
		2526	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
		2527	{
		2528	/* Prevent unused argument(s) compilation warning */
		2529	UNUSED(OutputChannel);
		2530
		2531	/* Disable the TIM Capture/Compare 1 interrupt */
		2532	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2533
		2534	/* Disable the TIM Capture/Compare 2 interrupt */
		2535	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2536
		2537	/* Disable the Capture compare and the Input Capture channels
		2538	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
		2539	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
		2540	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
		2541	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
		2542	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2543	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2544
		2545	if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
		2546	{
		2547	/* Disable the Main Output */
		2548	__HAL_TIM_MOE_DISABLE(htim);
		2549	}
		2550
		2551	/* Disable the Peripheral */
		2552	__HAL_TIM_DISABLE(htim);
		2553
		2554	/* Return function status */
		2555	return HAL_OK;
		2556	}
		2557
		2558	/**
		2559	* @}
		2560	*/
		2561
		2562	/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
		2563	* @brief TIM Encoder functions
		2564	*
		2565	@verbatim
		2566	==============================================================================
		2567	##### TIM Encoder functions #####
		2568	==============================================================================
		2569	[..]
		2570	This section provides functions allowing to:
		2571	(+) Initialize and configure the TIM Encoder.
		2572	(+) De-initialize the TIM Encoder.
		2573	(+) Start the TIM Encoder.
		2574	(+) Stop the TIM Encoder.
		2575	(+) Start the TIM Encoder and enable interrupt.
		2576	(+) Stop the TIM Encoder and disable interrupt.
		2577	(+) Start the TIM Encoder and enable DMA transfer.
		2578	(+) Stop the TIM Encoder and disable DMA transfer.
		2579
		2580	@endverbatim
		2581	* @{
		2582	*/
		2583	/**
		2584	* @brief Initializes the TIM Encoder Interface and initialize the associated handle.
		2585	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		2586	* requires a timer reset to avoid unexpected direction
		2587	* due to DIR bit readonly in center aligned mode.
		2588	* Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
		2589	* @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
		2590	* Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
		2591	* using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
		2592	* @param htim TIM Encoder Interface handle
		2593	* @param sConfig TIM Encoder Interface configuration structure
		2594	* @retval HAL status
		2595	*/
		2596	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
		2597	{
		2598	uint32_t tmpsmcr;
		2599	uint32_t tmpccmr1;
		2600	uint32_t tmpccer;
		2601
		2602	/* Check the TIM handle allocation */
		2603	if (htim == NULL)
		2604	{
		2605	return HAL_ERROR;
		2606	}
		2607
		2608	/* Check the parameters */
		2609	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
		2610	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
		2611	assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
		2612	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2613	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
		2614	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
		2615	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
		2616	assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
		2617	assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
		2618	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
		2619	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
		2620	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
		2621	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
		2622
		2623	if (htim->State == HAL_TIM_STATE_RESET)
		2624	{
		2625	/* Allocate lock resource and initialize it */
		2626	htim->Lock = HAL_UNLOCKED;
		2627
		2628	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2629	/* Reset interrupt callbacks to legacy weak callbacks */
		2630	TIM_ResetCallback(htim);
		2631
		2632	if (htim->Encoder_MspInitCallback == NULL)
		2633	{
		2634	htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
		2635	}
		2636	/* Init the low level hardware : GPIO, CLOCK, NVIC */
		2637	htim->Encoder_MspInitCallback(htim);
		2638	#else
		2639	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
		2640	HAL_TIM_Encoder_MspInit(htim);
		2641	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2642	}
		2643
		2644	/* Set the TIM state */
		2645	htim->State = HAL_TIM_STATE_BUSY;
		2646
		2647	/* Reset the SMS and ECE bits */
		2648	htim->Instance->SMCR &= ~(TIM_SMCR_SMS \| TIM_SMCR_ECE);
		2649
		2650	/* Configure the Time base in the Encoder Mode */
		2651	TIM_Base_SetConfig(htim->Instance, &htim->Init);
		2652
		2653	/* Get the TIMx SMCR register value */
		2654	tmpsmcr = htim->Instance->SMCR;
		2655
		2656	/* Get the TIMx CCMR1 register value */
		2657	tmpccmr1 = htim->Instance->CCMR1;
		2658
		2659	/* Get the TIMx CCER register value */
		2660	tmpccer = htim->Instance->CCER;
		2661
		2662	/* Set the encoder Mode */
		2663	tmpsmcr \|= sConfig->EncoderMode;
		2664
		2665	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
		2666	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
		2667	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
		2668
		2669	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
		2670	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
		2671	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
		2672	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
		2673	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
		2674
		2675	/* Set the TI1 and the TI2 Polarities */
		2676	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
		2677	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
		2678	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
		2679
		2680	/* Write to TIMx SMCR */
		2681	htim->Instance->SMCR = tmpsmcr;
		2682
		2683	/* Write to TIMx CCMR1 */
		2684	htim->Instance->CCMR1 = tmpccmr1;
		2685
		2686	/* Write to TIMx CCER */
		2687	htim->Instance->CCER = tmpccer;
		2688
		2689	/* Initialize the TIM state*/
		2690	htim->State = HAL_TIM_STATE_READY;
		2691
		2692	return HAL_OK;
		2693	}
		2694
		2695
		2696	/**
		2697	* @brief DeInitializes the TIM Encoder interface
		2698	* @param htim TIM Encoder Interface handle
		2699	* @retval HAL status
		2700	*/
		2701	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
		2702	{
		2703	/* Check the parameters */
		2704	assert_param(IS_TIM_INSTANCE(htim->Instance));
		2705
		2706	htim->State = HAL_TIM_STATE_BUSY;
		2707
		2708	/* Disable the TIM Peripheral Clock */
		2709	__HAL_TIM_DISABLE(htim);
		2710
		2711	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2712	if (htim->Encoder_MspDeInitCallback == NULL)
		2713	{
		2714	htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
		2715	}
		2716	/* DeInit the low level hardware */
		2717	htim->Encoder_MspDeInitCallback(htim);
		2718	#else
		2719	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
		2720	HAL_TIM_Encoder_MspDeInit(htim);
		2721	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2722
		2723	/* Change TIM state */
		2724	htim->State = HAL_TIM_STATE_RESET;
		2725
		2726	/* Release Lock */
		2727	__HAL_UNLOCK(htim);
		2728
		2729	return HAL_OK;
		2730	}
		2731
		2732	/**
		2733	* @brief Initializes the TIM Encoder Interface MSP.
		2734	* @param htim TIM Encoder Interface handle
		2735	* @retval None
		2736	*/
		2737	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
		2738	{
		2739	/* Prevent unused argument(s) compilation warning */
		2740	UNUSED(htim);
		2741
		2742	/* NOTE : This function should not be modified, when the callback is needed,
		2743	the HAL_TIM_Encoder_MspInit could be implemented in the user file
		2744	*/
		2745	}
		2746
		2747	/**
		2748	* @brief DeInitializes TIM Encoder Interface MSP.
		2749	* @param htim TIM Encoder Interface handle
		2750	* @retval None
		2751	*/
		2752	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
		2753	{
		2754	/* Prevent unused argument(s) compilation warning */
		2755	UNUSED(htim);
		2756
		2757	/* NOTE : This function should not be modified, when the callback is needed,
		2758	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
		2759	*/
		2760	}
		2761
		2762	/**
		2763	* @brief Starts the TIM Encoder Interface.
		2764	* @param htim TIM Encoder Interface handle
		2765	* @param Channel TIM Channels to be enabled
		2766	* This parameter can be one of the following values:
		2767	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2768	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2769	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2770	* @retval HAL status
		2771	*/
		2772	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
		2773	{
		2774	/* Check the parameters */
		2775	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2776
		2777	/* Enable the encoder interface channels */
		2778	switch (Channel)
		2779	{
		2780	case TIM_CHANNEL_1:
		2781	{
		2782	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2783	break;
		2784	}
		2785
		2786	case TIM_CHANNEL_2:
		2787	{
		2788	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2789	break;
		2790	}
		2791
		2792	default :
		2793	{
		2794	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2795	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2796	break;
		2797	}
		2798	}
		2799	/* Enable the Peripheral */
		2800	__HAL_TIM_ENABLE(htim);
		2801
		2802	/* Return function status */
		2803	return HAL_OK;
		2804	}
		2805
		2806	/**
		2807	* @brief Stops the TIM Encoder Interface.
		2808	* @param htim TIM Encoder Interface handle
		2809	* @param Channel TIM Channels to be disabled
		2810	* This parameter can be one of the following values:
		2811	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2812	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2813	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2814	* @retval HAL status
		2815	*/
		2816	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
		2817	{
		2818	/* Check the parameters */
		2819	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2820
		2821	/* Disable the Input Capture channels 1 and 2
		2822	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2823	switch (Channel)
		2824	{
		2825	case TIM_CHANNEL_1:
		2826	{
		2827	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2828	break;
		2829	}
		2830
		2831	case TIM_CHANNEL_2:
		2832	{
		2833	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2834	break;
		2835	}
		2836
		2837	default :
		2838	{
		2839	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2840	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2841	break;
		2842	}
		2843	}
		2844
		2845	/* Disable the Peripheral */
		2846	__HAL_TIM_DISABLE(htim);
		2847
		2848	/* Return function status */
		2849	return HAL_OK;
		2850	}
		2851
		2852	/**
		2853	* @brief Starts the TIM Encoder Interface in interrupt mode.
		2854	* @param htim TIM Encoder Interface handle
		2855	* @param Channel TIM Channels to be enabled
		2856	* This parameter can be one of the following values:
		2857	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2858	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2859	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2860	* @retval HAL status
		2861	*/
		2862	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		2863	{
		2864	/* Check the parameters */
		2865	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2866
		2867	/* Enable the encoder interface channels */
		2868	/* Enable the capture compare Interrupts 1 and/or 2 */
		2869	switch (Channel)
		2870	{
		2871	case TIM_CHANNEL_1:
		2872	{
		2873	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2874	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2875	break;
		2876	}
		2877
		2878	case TIM_CHANNEL_2:
		2879	{
		2880	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2881	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2882	break;
		2883	}
		2884
		2885	default :
		2886	{
		2887	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		2888	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		2889	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
		2890	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
		2891	break;
		2892	}
		2893	}
		2894
		2895	/* Enable the Peripheral */
		2896	__HAL_TIM_ENABLE(htim);
		2897
		2898	/* Return function status */
		2899	return HAL_OK;
		2900	}
		2901
		2902	/**
		2903	* @brief Stops the TIM Encoder Interface in interrupt mode.
		2904	* @param htim TIM Encoder Interface handle
		2905	* @param Channel TIM Channels to be disabled
		2906	* This parameter can be one of the following values:
		2907	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2908	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2909	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2910	* @retval HAL status
		2911	*/
		2912	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
		2913	{
		2914	/* Check the parameters */
		2915	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		2916
		2917	/* Disable the Input Capture channels 1 and 2
		2918	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		2919	if (Channel == TIM_CHANNEL_1)
		2920	{
		2921	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2922
		2923	/* Disable the capture compare Interrupts 1 */
		2924	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2925	}
		2926	else if (Channel == TIM_CHANNEL_2)
		2927	{
		2928	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2929
		2930	/* Disable the capture compare Interrupts 2 */
		2931	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2932	}
		2933	else
		2934	{
		2935	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		2936	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		2937
		2938	/* Disable the capture compare Interrupts 1 and 2 */
		2939	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
		2940	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
		2941	}
		2942
		2943	/* Disable the Peripheral */
		2944	__HAL_TIM_DISABLE(htim);
		2945
		2946	/* Change the htim state */
		2947	htim->State = HAL_TIM_STATE_READY;
		2948
		2949	/* Return function status */
		2950	return HAL_OK;
		2951	}
		2952
		2953	/**
		2954	* @brief Starts the TIM Encoder Interface in DMA mode.
		2955	* @param htim TIM Encoder Interface handle
		2956	* @param Channel TIM Channels to be enabled
		2957	* This parameter can be one of the following values:
		2958	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		2959	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		2960	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		2961	* @param pData1 The destination Buffer address for IC1.
		2962	* @param pData2 The destination Buffer address for IC2.
		2963	* @param Length The length of data to be transferred from TIM peripheral to memory.
		2964	* @retval HAL status
		2965	*/
		2966	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		2967	uint32_t *pData2, uint16_t Length)
		2968	{
		2969	/* Check the parameters */
		2970	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		2971
		2972	if (htim->State == HAL_TIM_STATE_BUSY)
		2973	{
		2974	return HAL_BUSY;
		2975	}
		2976	else if (htim->State == HAL_TIM_STATE_READY)
		2977	{
		2978	if ((((pData1 == NULL) \|\| (pData2 == NULL))) && (Length > 0U))
		2979	{
		2980	return HAL_ERROR;
		2981	}
		2982	else
		2983	{
		2984	htim->State = HAL_TIM_STATE_BUSY;
		2985	}
		2986	}
		2987	else
		2988	{
		2989	/* nothing to do */
		2990	}
		2991
		2992	switch (Channel)
		2993	{
		2994	case TIM_CHANNEL_1:
		2995	{
		2996	/* Set the DMA capture callbacks */
		2997	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		2998	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		2999
		3000	/* Set the DMA error callback */
		3001	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3002
		3003	/* Enable the DMA channel */
		3004	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
		3005	{
		3006	return HAL_ERROR;
		3007	}
		3008	/* Enable the TIM Input Capture DMA request */
		3009	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		3010
		3011	/* Enable the Peripheral */
		3012	__HAL_TIM_ENABLE(htim);
		3013
		3014	/* Enable the Capture compare channel */
		3015	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		3016	break;
		3017	}
		3018
		3019	case TIM_CHANNEL_2:
		3020	{
		3021	/* Set the DMA capture callbacks */
		3022	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		3023	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		3024
		3025	/* Set the DMA error callback */
		3026	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
		3027	/* Enable the DMA channel */
		3028	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
		3029	{
		3030	return HAL_ERROR;
		3031	}
		3032	/* Enable the TIM Input Capture DMA request */
		3033	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		3034
		3035	/* Enable the Peripheral */
		3036	__HAL_TIM_ENABLE(htim);
		3037
		3038	/* Enable the Capture compare channel */
		3039	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		3040	break;
		3041	}
		3042
		3043	case TIM_CHANNEL_ALL:
		3044	{
		3045	/* Set the DMA capture callbacks */
		3046	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		3047	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		3048
		3049	/* Set the DMA error callback */
		3050	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3051
		3052	/* Enable the DMA channel */
		3053	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
		3054	{
		3055	return HAL_ERROR;
		3056	}
		3057
		3058	/* Set the DMA capture callbacks */
		3059	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		3060	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		3061
		3062	/* Set the DMA error callback */
		3063	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		3064
		3065	/* Enable the DMA channel */
		3066	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
		3067	{
		3068	return HAL_ERROR;
		3069	}
		3070	/* Enable the Peripheral */
		3071	__HAL_TIM_ENABLE(htim);
		3072
		3073	/* Enable the Capture compare channel */
		3074	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
		3075	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
		3076
		3077	/* Enable the TIM Input Capture DMA request */
		3078	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
		3079	/* Enable the TIM Input Capture DMA request */
		3080	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
		3081	break;
		3082	}
		3083
		3084	default:
		3085	break;
		3086	}
		3087	/* Return function status */
		3088	return HAL_OK;
		3089	}
		3090
		3091	/**
		3092	* @brief Stops the TIM Encoder Interface in DMA mode.
		3093	* @param htim TIM Encoder Interface handle
		3094	* @param Channel TIM Channels to be enabled
		3095	* This parameter can be one of the following values:
		3096	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3097	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3098	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
		3099	* @retval HAL status
		3100	*/
		3101	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
		3102	{
		3103	/* Check the parameters */
		3104	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
		3105
		3106	/* Disable the Input Capture channels 1 and 2
		3107	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
		3108	if (Channel == TIM_CHANNEL_1)
		3109	{
		3110	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		3111
		3112	/* Disable the capture compare DMA Request 1 */
		3113	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		3114	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		3115	}
		3116	else if (Channel == TIM_CHANNEL_2)
		3117	{
		3118	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		3119
		3120	/* Disable the capture compare DMA Request 2 */
		3121	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		3122	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		3123	}
		3124	else
		3125	{
		3126	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
		3127	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
		3128
		3129	/* Disable the capture compare DMA Request 1 and 2 */
		3130	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
		3131	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
		3132	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		3133	(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		3134	}
		3135
		3136	/* Disable the Peripheral */
		3137	__HAL_TIM_DISABLE(htim);
		3138
		3139	/* Change the htim state */
		3140	htim->State = HAL_TIM_STATE_READY;
		3141
		3142	/* Return function status */
		3143	return HAL_OK;
		3144	}
		3145
		3146	/**
		3147	* @}
		3148	*/
		3149	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		3150	* @brief TIM IRQ handler management
		3151	*
		3152	@verbatim
		3153	==============================================================================
		3154	##### IRQ handler management #####
		3155	==============================================================================
		3156	[..]
		3157	This section provides Timer IRQ handler function.
		3158
		3159	@endverbatim
		3160	* @{
		3161	*/
		3162	/**
		3163	* @brief This function handles TIM interrupts requests.
		3164	* @param htim TIM handle
		3165	* @retval None
		3166	*/
		3167	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
		3168	{
		3169	/* Capture compare 1 event */
		3170	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
		3171	{
		3172	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
		3173	{
		3174	{
		3175	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
		3176	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		3177
		3178	/* Input capture event */
		3179	if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
		3180	{
		3181	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3182	htim->IC_CaptureCallback(htim);
		3183	#else
		3184	HAL_TIM_IC_CaptureCallback(htim);
		3185	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3186	}
		3187	/* Output compare event */
		3188	else
		3189	{
		3190	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3191	htim->OC_DelayElapsedCallback(htim);
		3192	htim->PWM_PulseFinishedCallback(htim);
		3193	#else
		3194	HAL_TIM_OC_DelayElapsedCallback(htim);
		3195	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3196	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3197	}
		3198	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3199	}
		3200	}
		3201	}
		3202	/* Capture compare 2 event */
		3203	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
		3204	{
		3205	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
		3206	{
		3207	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
		3208	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		3209	/* Input capture event */
		3210	if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
		3211	{
		3212	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3213	htim->IC_CaptureCallback(htim);
		3214	#else
		3215	HAL_TIM_IC_CaptureCallback(htim);
		3216	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3217	}
		3218	/* Output compare event */
		3219	else
		3220	{
		3221	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3222	htim->OC_DelayElapsedCallback(htim);
		3223	htim->PWM_PulseFinishedCallback(htim);
		3224	#else
		3225	HAL_TIM_OC_DelayElapsedCallback(htim);
		3226	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3227	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3228	}
		3229	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3230	}
		3231	}
		3232	/* Capture compare 3 event */
		3233	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
		3234	{
		3235	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
		3236	{
		3237	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
		3238	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		3239	/* Input capture event */
		3240	if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
		3241	{
		3242	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3243	htim->IC_CaptureCallback(htim);
		3244	#else
		3245	HAL_TIM_IC_CaptureCallback(htim);
		3246	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3247	}
		3248	/* Output compare event */
		3249	else
		3250	{
		3251	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3252	htim->OC_DelayElapsedCallback(htim);
		3253	htim->PWM_PulseFinishedCallback(htim);
		3254	#else
		3255	HAL_TIM_OC_DelayElapsedCallback(htim);
		3256	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3257	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3258	}
		3259	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3260	}
		3261	}
		3262	/* Capture compare 4 event */
		3263	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
		3264	{
		3265	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
		3266	{
		3267	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
		3268	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		3269	/* Input capture event */
		3270	if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
		3271	{
		3272	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3273	htim->IC_CaptureCallback(htim);
		3274	#else
		3275	HAL_TIM_IC_CaptureCallback(htim);
		3276	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3277	}
		3278	/* Output compare event */
		3279	else
		3280	{
		3281	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3282	htim->OC_DelayElapsedCallback(htim);
		3283	htim->PWM_PulseFinishedCallback(htim);
		3284	#else
		3285	HAL_TIM_OC_DelayElapsedCallback(htim);
		3286	HAL_TIM_PWM_PulseFinishedCallback(htim);
		3287	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3288	}
		3289	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		3290	}
		3291	}
		3292	/* TIM Update event */
		3293	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
		3294	{
		3295	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
		3296	{
		3297	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
		3298	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3299	htim->PeriodElapsedCallback(htim);
		3300	#else
		3301	HAL_TIM_PeriodElapsedCallback(htim);
		3302	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3303	}
		3304	}
		3305	/* TIM Break input event */
		3306	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
		3307	{
		3308	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
		3309	{
		3310	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
		3311	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3312	htim->BreakCallback(htim);
		3313	#else
		3314	HAL_TIMEx_BreakCallback(htim);
		3315	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3316	}
		3317	}
		3318	/* TIM Trigger detection event */
		3319	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
		3320	{
		3321	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
		3322	{
		3323	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
		3324	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3325	htim->TriggerCallback(htim);
		3326	#else
		3327	HAL_TIM_TriggerCallback(htim);
		3328	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3329	}
		3330	}
		3331	/* TIM commutation event */
		3332	if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
		3333	{
		3334	if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
		3335	{
		3336	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
		3337	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		3338	htim->CommutationCallback(htim);
		3339	#else
		3340	HAL_TIMEx_CommutCallback(htim);
		3341	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		3342	}
		3343	}
		3344	}
		3345
		3346	/**
		3347	* @}
		3348	*/
		3349
		3350	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		3351	* @brief TIM Peripheral Control functions
		3352	*
		3353	@verbatim
		3354	==============================================================================
		3355	##### Peripheral Control functions #####
		3356	==============================================================================
		3357	[..]
		3358	This section provides functions allowing to:
		3359	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
		3360	(+) Configure External Clock source.
		3361	(+) Configure Complementary channels, break features and dead time.
		3362	(+) Configure Master and the Slave synchronization.
		3363	(+) Configure the DMA Burst Mode.
		3364
		3365	@endverbatim
		3366	* @{
		3367	*/
		3368
		3369	/**
		3370	* @brief Initializes the TIM Output Compare Channels according to the specified
		3371	* parameters in the TIM_OC_InitTypeDef.
		3372	* @param htim TIM Output Compare handle
		3373	* @param sConfig TIM Output Compare configuration structure
		3374	* @param Channel TIM Channels to configure
		3375	* This parameter can be one of the following values:
		3376	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3377	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3378	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3379	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3380	* @retval HAL status
		3381	*/
		3382	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
		3383	TIM_OC_InitTypeDef *sConfig,
		3384	uint32_t Channel)
		3385	{
		3386	/* Check the parameters */
		3387	assert_param(IS_TIM_CHANNELS(Channel));
		3388	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
		3389	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
		3390
		3391	/* Process Locked */
		3392	__HAL_LOCK(htim);
		3393
		3394	htim->State = HAL_TIM_STATE_BUSY;
		3395
		3396	switch (Channel)
		3397	{
		3398	case TIM_CHANNEL_1:
		3399	{
		3400	/* Check the parameters */
		3401	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3402
		3403	/* Configure the TIM Channel 1 in Output Compare */
		3404	TIM_OC1_SetConfig(htim->Instance, sConfig);
		3405	break;
		3406	}
		3407
		3408	case TIM_CHANNEL_2:
		3409	{
		3410	/* Check the parameters */
		3411	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3412
		3413	/* Configure the TIM Channel 2 in Output Compare */
		3414	TIM_OC2_SetConfig(htim->Instance, sConfig);
		3415	break;
		3416	}
		3417
		3418	case TIM_CHANNEL_3:
		3419	{
		3420	/* Check the parameters */
		3421	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3422
		3423	/* Configure the TIM Channel 3 in Output Compare */
		3424	TIM_OC3_SetConfig(htim->Instance, sConfig);
		3425	break;
		3426	}
		3427
		3428	case TIM_CHANNEL_4:
		3429	{
		3430	/* Check the parameters */
		3431	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3432
		3433	/* Configure the TIM Channel 4 in Output Compare */
		3434	TIM_OC4_SetConfig(htim->Instance, sConfig);
		3435	break;
		3436	}
		3437
		3438	default:
		3439	break;
		3440	}
		3441
		3442	htim->State = HAL_TIM_STATE_READY;
		3443
		3444	__HAL_UNLOCK(htim);
		3445
		3446	return HAL_OK;
		3447	}
		3448
		3449	/**
		3450	* @brief Initializes the TIM Input Capture Channels according to the specified
		3451	* parameters in the TIM_IC_InitTypeDef.
		3452	* @param htim TIM IC handle
		3453	* @param sConfig TIM Input Capture configuration structure
		3454	* @param Channel TIM Channel to configure
		3455	* This parameter can be one of the following values:
		3456	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3457	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3458	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3459	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3460	* @retval HAL status
		3461	*/
		3462	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
		3463	{
		3464	/* Check the parameters */
		3465	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3466	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
		3467	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
		3468	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
		3469	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
		3470
		3471	/* Process Locked */
		3472	__HAL_LOCK(htim);
		3473
		3474	htim->State = HAL_TIM_STATE_BUSY;
		3475
		3476	if (Channel == TIM_CHANNEL_1)
		3477	{
		3478	/* TI1 Configuration */
		3479	TIM_TI1_SetConfig(htim->Instance,
		3480	sConfig->ICPolarity,
		3481	sConfig->ICSelection,
		3482	sConfig->ICFilter);
		3483
		3484	/* Reset the IC1PSC Bits */
		3485	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
		3486
		3487	/* Set the IC1PSC value */
		3488	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
		3489	}
		3490	else if (Channel == TIM_CHANNEL_2)
		3491	{
		3492	/* TI2 Configuration */
		3493	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3494
		3495	TIM_TI2_SetConfig(htim->Instance,
		3496	sConfig->ICPolarity,
		3497	sConfig->ICSelection,
		3498	sConfig->ICFilter);
		3499
		3500	/* Reset the IC2PSC Bits */
		3501	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
		3502
		3503	/* Set the IC2PSC value */
		3504	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
		3505	}
		3506	else if (Channel == TIM_CHANNEL_3)
		3507	{
		3508	/* TI3 Configuration */
		3509	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3510
		3511	TIM_TI3_SetConfig(htim->Instance,
		3512	sConfig->ICPolarity,
		3513	sConfig->ICSelection,
		3514	sConfig->ICFilter);
		3515
		3516	/* Reset the IC3PSC Bits */
		3517	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
		3518
		3519	/* Set the IC3PSC value */
		3520	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
		3521	}
		3522	else
		3523	{
		3524	/* TI4 Configuration */
		3525	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3526
		3527	TIM_TI4_SetConfig(htim->Instance,
		3528	sConfig->ICPolarity,
		3529	sConfig->ICSelection,
		3530	sConfig->ICFilter);
		3531
		3532	/* Reset the IC4PSC Bits */
		3533	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
		3534
		3535	/* Set the IC4PSC value */
		3536	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
		3537	}
		3538
		3539	htim->State = HAL_TIM_STATE_READY;
		3540
		3541	__HAL_UNLOCK(htim);
		3542
		3543	return HAL_OK;
		3544	}
		3545
		3546	/**
		3547	* @brief Initializes the TIM PWM channels according to the specified
		3548	* parameters in the TIM_OC_InitTypeDef.
		3549	* @param htim TIM PWM handle
		3550	* @param sConfig TIM PWM configuration structure
		3551	* @param Channel TIM Channels to be configured
		3552	* This parameter can be one of the following values:
		3553	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3554	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3555	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		3556	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		3557	* @retval HAL status
		3558	*/
		3559	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
		3560	TIM_OC_InitTypeDef *sConfig,
		3561	uint32_t Channel)
		3562	{
		3563	/* Check the parameters */
		3564	assert_param(IS_TIM_CHANNELS(Channel));
		3565	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
		3566	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
		3567	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
		3568
		3569	/* Process Locked */
		3570	__HAL_LOCK(htim);
		3571
		3572	htim->State = HAL_TIM_STATE_BUSY;
		3573
		3574	switch (Channel)
		3575	{
		3576	case TIM_CHANNEL_1:
		3577	{
		3578	/* Check the parameters */
		3579	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3580
		3581	/* Configure the Channel 1 in PWM mode */
		3582	TIM_OC1_SetConfig(htim->Instance, sConfig);
		3583
		3584	/* Set the Preload enable bit for channel1 */
		3585	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
		3586
		3587	/* Configure the Output Fast mode */
		3588	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
		3589	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
		3590	break;
		3591	}
		3592
		3593	case TIM_CHANNEL_2:
		3594	{
		3595	/* Check the parameters */
		3596	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3597
		3598	/* Configure the Channel 2 in PWM mode */
		3599	TIM_OC2_SetConfig(htim->Instance, sConfig);
		3600
		3601	/* Set the Preload enable bit for channel2 */
		3602	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
		3603
		3604	/* Configure the Output Fast mode */
		3605	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
		3606	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8U;
		3607	break;
		3608	}
		3609
		3610	case TIM_CHANNEL_3:
		3611	{
		3612	/* Check the parameters */
		3613	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		3614
		3615	/* Configure the Channel 3 in PWM mode */
		3616	TIM_OC3_SetConfig(htim->Instance, sConfig);
		3617
		3618	/* Set the Preload enable bit for channel3 */
		3619	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
		3620
		3621	/* Configure the Output Fast mode */
		3622	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
		3623	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
		3624	break;
		3625	}
		3626
		3627	case TIM_CHANNEL_4:
		3628	{
		3629	/* Check the parameters */
		3630	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		3631
		3632	/* Configure the Channel 4 in PWM mode */
		3633	TIM_OC4_SetConfig(htim->Instance, sConfig);
		3634
		3635	/* Set the Preload enable bit for channel4 */
		3636	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
		3637
		3638	/* Configure the Output Fast mode */
		3639	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
		3640	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8U;
		3641	break;
		3642	}
		3643
		3644	default:
		3645	break;
		3646	}
		3647
		3648	htim->State = HAL_TIM_STATE_READY;
		3649
		3650	__HAL_UNLOCK(htim);
		3651
		3652	return HAL_OK;
		3653	}
		3654
		3655	/**
		3656	* @brief Initializes the TIM One Pulse Channels according to the specified
		3657	* parameters in the TIM_OnePulse_InitTypeDef.
		3658	* @param htim TIM One Pulse handle
		3659	* @param sConfig TIM One Pulse configuration structure
		3660	* @param OutputChannel TIM output channel to configure
		3661	* This parameter can be one of the following values:
		3662	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3663	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3664	* @param InputChannel TIM input Channel to configure
		3665	* This parameter can be one of the following values:
		3666	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		3667	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		3668	* @note To output a waveform with a minimum delay user can enable the fast
		3669	* mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
		3670	* output is forced in response to the edge detection on TIx input,
		3671	* without taking in account the comparison.
		3672	* @retval HAL status
		3673	*/
		3674	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		3675	uint32_t OutputChannel, uint32_t InputChannel)
		3676	{
		3677	TIM_OC_InitTypeDef temp1;
		3678
		3679	/* Check the parameters */
		3680	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
		3681	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
		3682
		3683	if (OutputChannel != InputChannel)
		3684	{
		3685	/* Process Locked */
		3686	__HAL_LOCK(htim);
		3687
		3688	htim->State = HAL_TIM_STATE_BUSY;
		3689
		3690	/* Extract the Output compare configuration from sConfig structure */
		3691	temp1.OCMode = sConfig->OCMode;
		3692	temp1.Pulse = sConfig->Pulse;
		3693	temp1.OCPolarity = sConfig->OCPolarity;
		3694	temp1.OCNPolarity = sConfig->OCNPolarity;
		3695	temp1.OCIdleState = sConfig->OCIdleState;
		3696	temp1.OCNIdleState = sConfig->OCNIdleState;
		3697
		3698	switch (OutputChannel)
		3699	{
		3700	case TIM_CHANNEL_1:
		3701	{
		3702	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3703
		3704	TIM_OC1_SetConfig(htim->Instance, &temp1);
		3705	break;
		3706	}
		3707	case TIM_CHANNEL_2:
		3708	{
		3709	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3710
		3711	TIM_OC2_SetConfig(htim->Instance, &temp1);
		3712	break;
		3713	}
		3714	default:
		3715	break;
		3716	}
		3717
		3718	switch (InputChannel)
		3719	{
		3720	case TIM_CHANNEL_1:
		3721	{
		3722	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		3723
		3724	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
		3725	sConfig->ICSelection, sConfig->ICFilter);
		3726
		3727	/* Reset the IC1PSC Bits */
		3728	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
		3729
		3730	/* Select the Trigger source */
		3731	htim->Instance->SMCR &= ~TIM_SMCR_TS;
		3732	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
		3733
		3734	/* Select the Slave Mode */
		3735	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3736	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
		3737	break;
		3738	}
		3739	case TIM_CHANNEL_2:
		3740	{
		3741	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		3742
		3743	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
		3744	sConfig->ICSelection, sConfig->ICFilter);
		3745
		3746	/* Reset the IC2PSC Bits */
		3747	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
		3748
		3749	/* Select the Trigger source */
		3750	htim->Instance->SMCR &= ~TIM_SMCR_TS;
		3751	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
		3752
		3753	/* Select the Slave Mode */
		3754	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
		3755	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
		3756	break;
		3757	}
		3758
		3759	default:
		3760	break;
		3761	}
		3762
		3763	htim->State = HAL_TIM_STATE_READY;
		3764
		3765	__HAL_UNLOCK(htim);
		3766
		3767	return HAL_OK;
		3768	}
		3769	else
		3770	{
		3771	return HAL_ERROR;
		3772	}
		3773	}
		3774
		3775	/**
		3776	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
		3777	* @param htim TIM handle
		3778	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
		3779	* This parameter can be one of the following values:
		3780	* @arg TIM_DMABASE_CR1
		3781	* @arg TIM_DMABASE_CR2
		3782	* @arg TIM_DMABASE_SMCR
		3783	* @arg TIM_DMABASE_DIER
		3784	* @arg TIM_DMABASE_SR
		3785	* @arg TIM_DMABASE_EGR
		3786	* @arg TIM_DMABASE_CCMR1
		3787	* @arg TIM_DMABASE_CCMR2
		3788	* @arg TIM_DMABASE_CCER
		3789	* @arg TIM_DMABASE_CNT
		3790	* @arg TIM_DMABASE_PSC
		3791	* @arg TIM_DMABASE_ARR
		3792	* @arg TIM_DMABASE_RCR
		3793	* @arg TIM_DMABASE_CCR1
		3794	* @arg TIM_DMABASE_CCR2
		3795	* @arg TIM_DMABASE_CCR3
		3796	* @arg TIM_DMABASE_CCR4
		3797	* @arg TIM_DMABASE_BDTR
		3798	* @param BurstRequestSrc TIM DMA Request sources
		3799	* This parameter can be one of the following values:
		3800	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		3801	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		3802	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		3803	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		3804	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		3805	* @arg TIM_DMA_COM: TIM Commutation DMA source
		3806	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		3807	* @param BurstBuffer The Buffer address.
		3808	* @param BurstLength DMA Burst length. This parameter can be one value
		3809	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		3810	* @note This function should be used only when BurstLength is equal to DMA data transfer length.
		3811	* @retval HAL status
		3812	*/
		3813	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		3814	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
		3815	{
		3816	return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
		3817	((BurstLength) >> 8U) + 1U);
		3818	}
		3819
		3820	/**
		3821	* @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
		3822	* @param htim TIM handle
		3823	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
		3824	* This parameter can be one of the following values:
		3825	* @arg TIM_DMABASE_CR1
		3826	* @arg TIM_DMABASE_CR2
		3827	* @arg TIM_DMABASE_SMCR
		3828	* @arg TIM_DMABASE_DIER
		3829	* @arg TIM_DMABASE_SR
		3830	* @arg TIM_DMABASE_EGR
		3831	* @arg TIM_DMABASE_CCMR1
		3832	* @arg TIM_DMABASE_CCMR2
		3833	* @arg TIM_DMABASE_CCER
		3834	* @arg TIM_DMABASE_CNT
		3835	* @arg TIM_DMABASE_PSC
		3836	* @arg TIM_DMABASE_ARR
		3837	* @arg TIM_DMABASE_RCR
		3838	* @arg TIM_DMABASE_CCR1
		3839	* @arg TIM_DMABASE_CCR2
		3840	* @arg TIM_DMABASE_CCR3
		3841	* @arg TIM_DMABASE_CCR4
		3842	* @arg TIM_DMABASE_BDTR
		3843	* @param BurstRequestSrc TIM DMA Request sources
		3844	* This parameter can be one of the following values:
		3845	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		3846	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		3847	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		3848	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		3849	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		3850	* @arg TIM_DMA_COM: TIM Commutation DMA source
		3851	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		3852	* @param BurstBuffer The Buffer address.
		3853	* @param BurstLength DMA Burst length. This parameter can be one value
		3854	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		3855	* @param DataLength Data length. This parameter can be one value
		3856	* between 1 and 0xFFFF.
		3857	* @retval HAL status
		3858	*/
		3859	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		3860	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
		3861	uint32_t BurstLength, uint32_t DataLength)
		3862	{
		3863	/* Check the parameters */
		3864	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
		3865	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
		3866	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		3867	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
		3868	assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
		3869
		3870	if (htim->State == HAL_TIM_STATE_BUSY)
		3871	{
		3872	return HAL_BUSY;
		3873	}
		3874	else if (htim->State == HAL_TIM_STATE_READY)
		3875	{
		3876	if ((BurstBuffer == NULL) && (BurstLength > 0U))
		3877	{
		3878	return HAL_ERROR;
		3879	}
		3880	else
		3881	{
		3882	htim->State = HAL_TIM_STATE_BUSY;
		3883	}
		3884	}
		3885	else
		3886	{
		3887	/* nothing to do */
		3888	}
		3889	switch (BurstRequestSrc)
		3890	{
		3891	case TIM_DMA_UPDATE:
		3892	{
		3893	/* Set the DMA Period elapsed callbacks */
		3894	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		3895	htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
		3896
		3897	/* Set the DMA error callback */
		3898	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		3899
		3900	/* Enable the DMA channel */
		3901	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
		3902	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		3903	{
		3904	return HAL_ERROR;
		3905	}
		3906	break;
		3907	}
		3908	case TIM_DMA_CC1:
		3909	{
		3910	/* Set the DMA compare callbacks */
		3911	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3912	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3913
		3914	/* Set the DMA error callback */
		3915	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		3916
		3917	/* Enable the DMA channel */
		3918	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
		3919	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		3920	{
		3921	return HAL_ERROR;
		3922	}
		3923	break;
		3924	}
		3925	case TIM_DMA_CC2:
		3926	{
		3927	/* Set the DMA compare callbacks */
		3928	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3929	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3930
		3931	/* Set the DMA error callback */
		3932	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		3933
		3934	/* Enable the DMA channel */
		3935	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
		3936	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		3937	{
		3938	return HAL_ERROR;
		3939	}
		3940	break;
		3941	}
		3942	case TIM_DMA_CC3:
		3943	{
		3944	/* Set the DMA compare callbacks */
		3945	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3946	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3947
		3948	/* Set the DMA error callback */
		3949	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		3950
		3951	/* Enable the DMA channel */
		3952	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
		3953	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		3954	{
		3955	return HAL_ERROR;
		3956	}
		3957	break;
		3958	}
		3959	case TIM_DMA_CC4:
		3960	{
		3961	/* Set the DMA compare callbacks */
		3962	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
		3963	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
		3964
		3965	/* Set the DMA error callback */
		3966	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		3967
		3968	/* Enable the DMA channel */
		3969	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
		3970	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		3971	{
		3972	return HAL_ERROR;
		3973	}
		3974	break;
		3975	}
		3976	case TIM_DMA_COM:
		3977	{
		3978	/* Set the DMA commutation callbacks */
		3979	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
		3980	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
		3981
		3982	/* Set the DMA error callback */
		3983	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
		3984
		3985	/* Enable the DMA channel */
		3986	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
		3987	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		3988	{
		3989	return HAL_ERROR;
		3990	}
		3991	break;
		3992	}
		3993	case TIM_DMA_TRIGGER:
		3994	{
		3995	/* Set the DMA trigger callbacks */
		3996	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
		3997	htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
		3998
		3999	/* Set the DMA error callback */
		4000	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
		4001
		4002	/* Enable the DMA channel */
		4003	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
		4004	(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
		4005	{
		4006	return HAL_ERROR;
		4007	}
		4008	break;
		4009	}
		4010	default:
		4011	break;
		4012	}
		4013
		4014	/* Configure the DMA Burst Mode */
		4015	htim->Instance->DCR = (BurstBaseAddress \| BurstLength);
		4016	/* Enable the TIM DMA Request */
		4017	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
		4018
		4019	htim->State = HAL_TIM_STATE_READY;
		4020
		4021	/* Return function status */
		4022	return HAL_OK;
		4023	}
		4024
		4025	/**
		4026	* @brief Stops the TIM DMA Burst mode
		4027	* @param htim TIM handle
		4028	* @param BurstRequestSrc TIM DMA Request sources to disable
		4029	* @retval HAL status
		4030	*/
		4031	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
		4032	{
		4033	HAL_StatusTypeDef status = HAL_OK;
		4034	/* Check the parameters */
		4035	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		4036
		4037	/* Abort the DMA transfer (at least disable the DMA channel) */
		4038	switch (BurstRequestSrc)
		4039	{
		4040	case TIM_DMA_UPDATE:
		4041	{
		4042	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
		4043	break;
		4044	}
		4045	case TIM_DMA_CC1:
		4046	{
		4047	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		4048	break;
		4049	}
		4050	case TIM_DMA_CC2:
		4051	{
		4052	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		4053	break;
		4054	}
		4055	case TIM_DMA_CC3:
		4056	{
		4057	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		4058	break;
		4059	}
		4060	case TIM_DMA_CC4:
		4061	{
		4062	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		4063	break;
		4064	}
		4065	case TIM_DMA_COM:
		4066	{
		4067	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
		4068	break;
		4069	}
		4070	case TIM_DMA_TRIGGER:
		4071	{
		4072	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
		4073	break;
		4074	}
		4075	default:
		4076	break;
		4077	}
		4078
		4079	if (HAL_OK == status)
		4080	{
		4081	/* Disable the TIM Update DMA request */
		4082	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
		4083	}
		4084
		4085	/* Return function status */
		4086	return status;
		4087	}
		4088
		4089	/**
		4090	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
		4091	* @param htim TIM handle
		4092	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
		4093	* This parameter can be one of the following values:
		4094	* @arg TIM_DMABASE_CR1
		4095	* @arg TIM_DMABASE_CR2
		4096	* @arg TIM_DMABASE_SMCR
		4097	* @arg TIM_DMABASE_DIER
		4098	* @arg TIM_DMABASE_SR
		4099	* @arg TIM_DMABASE_EGR
		4100	* @arg TIM_DMABASE_CCMR1
		4101	* @arg TIM_DMABASE_CCMR2
		4102	* @arg TIM_DMABASE_CCER
		4103	* @arg TIM_DMABASE_CNT
		4104	* @arg TIM_DMABASE_PSC
		4105	* @arg TIM_DMABASE_ARR
		4106	* @arg TIM_DMABASE_RCR
		4107	* @arg TIM_DMABASE_CCR1
		4108	* @arg TIM_DMABASE_CCR2
		4109	* @arg TIM_DMABASE_CCR3
		4110	* @arg TIM_DMABASE_CCR4
		4111	* @arg TIM_DMABASE_BDTR
		4112	* @param BurstRequestSrc TIM DMA Request sources
		4113	* This parameter can be one of the following values:
		4114	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		4115	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		4116	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		4117	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		4118	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		4119	* @arg TIM_DMA_COM: TIM Commutation DMA source
		4120	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		4121	* @param BurstBuffer The Buffer address.
		4122	* @param BurstLength DMA Burst length. This parameter can be one value
		4123	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		4124	* @note This function should be used only when BurstLength is equal to DMA data transfer length.
		4125	* @retval HAL status
		4126	*/
		4127	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		4128	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
		4129	{
		4130	return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
		4131	((BurstLength) >> 8U) + 1U);
		4132	}
		4133
		4134	/**
		4135	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
		4136	* @param htim TIM handle
		4137	* @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
		4138	* This parameter can be one of the following values:
		4139	* @arg TIM_DMABASE_CR1
		4140	* @arg TIM_DMABASE_CR2
		4141	* @arg TIM_DMABASE_SMCR
		4142	* @arg TIM_DMABASE_DIER
		4143	* @arg TIM_DMABASE_SR
		4144	* @arg TIM_DMABASE_EGR
		4145	* @arg TIM_DMABASE_CCMR1
		4146	* @arg TIM_DMABASE_CCMR2
		4147	* @arg TIM_DMABASE_CCER
		4148	* @arg TIM_DMABASE_CNT
		4149	* @arg TIM_DMABASE_PSC
		4150	* @arg TIM_DMABASE_ARR
		4151	* @arg TIM_DMABASE_RCR
		4152	* @arg TIM_DMABASE_CCR1
		4153	* @arg TIM_DMABASE_CCR2
		4154	* @arg TIM_DMABASE_CCR3
		4155	* @arg TIM_DMABASE_CCR4
		4156	* @arg TIM_DMABASE_BDTR
		4157	* @param BurstRequestSrc TIM DMA Request sources
		4158	* This parameter can be one of the following values:
		4159	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
		4160	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
		4161	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
		4162	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
		4163	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
		4164	* @arg TIM_DMA_COM: TIM Commutation DMA source
		4165	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
		4166	* @param BurstBuffer The Buffer address.
		4167	* @param BurstLength DMA Burst length. This parameter can be one value
		4168	* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
		4169	* @param DataLength Data length. This parameter can be one value
		4170	* between 1 and 0xFFFF.
		4171	* @retval HAL status
		4172	*/
		4173	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		4174	uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
		4175	uint32_t BurstLength, uint32_t DataLength)
		4176	{
		4177	/* Check the parameters */
		4178	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
		4179	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
		4180	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		4181	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
		4182	assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
		4183
		4184	if (htim->State == HAL_TIM_STATE_BUSY)
		4185	{
		4186	return HAL_BUSY;
		4187	}
		4188	else if (htim->State == HAL_TIM_STATE_READY)
		4189	{
		4190	if ((BurstBuffer == NULL) && (BurstLength > 0U))
		4191	{
		4192	return HAL_ERROR;
		4193	}
		4194	else
		4195	{
		4196	htim->State = HAL_TIM_STATE_BUSY;
		4197	}
		4198	}
		4199	else
		4200	{
		4201	/* nothing to do */
		4202	}
		4203	switch (BurstRequestSrc)
		4204	{
		4205	case TIM_DMA_UPDATE:
		4206	{
		4207	/* Set the DMA Period elapsed callbacks */
		4208	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
		4209	htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
		4210
		4211	/* Set the DMA error callback */
		4212	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
		4213
		4214	/* Enable the DMA channel */
		4215	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4216	DataLength) != HAL_OK)
		4217	{
		4218	return HAL_ERROR;
		4219	}
		4220	break;
		4221	}
		4222	case TIM_DMA_CC1:
		4223	{
		4224	/* Set the DMA capture callbacks */
		4225	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
		4226	htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4227
		4228	/* Set the DMA error callback */
		4229	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
		4230
		4231	/* Enable the DMA channel */
		4232	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4233	DataLength) != HAL_OK)
		4234	{
		4235	return HAL_ERROR;
		4236	}
		4237	break;
		4238	}
		4239	case TIM_DMA_CC2:
		4240	{
		4241	/* Set the DMA capture callbacks */
		4242	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
		4243	htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4244
		4245	/* Set the DMA error callback */
		4246	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
		4247
		4248	/* Enable the DMA channel */
		4249	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4250	DataLength) != HAL_OK)
		4251	{
		4252	return HAL_ERROR;
		4253	}
		4254	break;
		4255	}
		4256	case TIM_DMA_CC3:
		4257	{
		4258	/* Set the DMA capture callbacks */
		4259	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
		4260	htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4261
		4262	/* Set the DMA error callback */
		4263	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
		4264
		4265	/* Enable the DMA channel */
		4266	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4267	DataLength) != HAL_OK)
		4268	{
		4269	return HAL_ERROR;
		4270	}
		4271	break;
		4272	}
		4273	case TIM_DMA_CC4:
		4274	{
		4275	/* Set the DMA capture callbacks */
		4276	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
		4277	htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
		4278
		4279	/* Set the DMA error callback */
		4280	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
		4281
		4282	/* Enable the DMA channel */
		4283	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4284	DataLength) != HAL_OK)
		4285	{
		4286	return HAL_ERROR;
		4287	}
		4288	break;
		4289	}
		4290	case TIM_DMA_COM:
		4291	{
		4292	/* Set the DMA commutation callbacks */
		4293	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
		4294	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
		4295
		4296	/* Set the DMA error callback */
		4297	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
		4298
		4299	/* Enable the DMA channel */
		4300	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4301	DataLength) != HAL_OK)
		4302	{
		4303	return HAL_ERROR;
		4304	}
		4305	break;
		4306	}
		4307	case TIM_DMA_TRIGGER:
		4308	{
		4309	/* Set the DMA trigger callbacks */
		4310	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
		4311	htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
		4312
		4313	/* Set the DMA error callback */
		4314	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
		4315
		4316	/* Enable the DMA channel */
		4317	if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
		4318	DataLength) != HAL_OK)
		4319	{
		4320	return HAL_ERROR;
		4321	}
		4322	break;
		4323	}
		4324	default:
		4325	break;
		4326	}
		4327
		4328	/* Configure the DMA Burst Mode */
		4329	htim->Instance->DCR = (BurstBaseAddress \| BurstLength);
		4330
		4331	/* Enable the TIM DMA Request */
		4332	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
		4333
		4334	htim->State = HAL_TIM_STATE_READY;
		4335
		4336	/* Return function status */
		4337	return HAL_OK;
		4338	}
		4339
		4340	/**
		4341	* @brief Stop the DMA burst reading
		4342	* @param htim TIM handle
		4343	* @param BurstRequestSrc TIM DMA Request sources to disable.
		4344	* @retval HAL status
		4345	*/
		4346	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
		4347	{
		4348	HAL_StatusTypeDef status = HAL_OK;
		4349	/* Check the parameters */
		4350	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
		4351
		4352	/* Abort the DMA transfer (at least disable the DMA channel) */
		4353	switch (BurstRequestSrc)
		4354	{
		4355	case TIM_DMA_UPDATE:
		4356	{
		4357	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
		4358	break;
		4359	}
		4360	case TIM_DMA_CC1:
		4361	{
		4362	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
		4363	break;
		4364	}
		4365	case TIM_DMA_CC2:
		4366	{
		4367	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
		4368	break;
		4369	}
		4370	case TIM_DMA_CC3:
		4371	{
		4372	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
		4373	break;
		4374	}
		4375	case TIM_DMA_CC4:
		4376	{
		4377	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
		4378	break;
		4379	}
		4380	case TIM_DMA_COM:
		4381	{
		4382	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
		4383	break;
		4384	}
		4385	case TIM_DMA_TRIGGER:
		4386	{
		4387	status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
		4388	break;
		4389	}
		4390	default:
		4391	break;
		4392	}
		4393
		4394	if (HAL_OK == status)
		4395	{
		4396	/* Disable the TIM Update DMA request */
		4397	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
		4398	}
		4399
		4400	/* Return function status */
		4401	return status;
		4402	}
		4403
		4404	/**
		4405	* @brief Generate a software event
		4406	* @param htim TIM handle
		4407	* @param EventSource specifies the event source.
		4408	* This parameter can be one of the following values:
		4409	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
		4410	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
		4411	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
		4412	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
		4413	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
		4414	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
		4415	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
		4416	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
		4417	* @note Basic timers can only generate an update event.
		4418	* @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
		4419	* @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
		4420	* supporting a break input.
		4421	* @retval HAL status
		4422	*/
		4423
		4424	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
		4425	{
		4426	/* Check the parameters */
		4427	assert_param(IS_TIM_INSTANCE(htim->Instance));
		4428	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
		4429
		4430	/* Process Locked */
		4431	__HAL_LOCK(htim);
		4432
		4433	/* Change the TIM state */
		4434	htim->State = HAL_TIM_STATE_BUSY;
		4435
		4436	/* Set the event sources */
		4437	htim->Instance->EGR = EventSource;
		4438
		4439	/* Change the TIM state */
		4440	htim->State = HAL_TIM_STATE_READY;
		4441
		4442	__HAL_UNLOCK(htim);
		4443
		4444	/* Return function status */
		4445	return HAL_OK;
		4446	}
		4447
		4448	/**
		4449	* @brief Configures the OCRef clear feature
		4450	* @param htim TIM handle
		4451	* @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
		4452	* contains the OCREF clear feature and parameters for the TIM peripheral.
		4453	* @param Channel specifies the TIM Channel
		4454	* This parameter can be one of the following values:
		4455	* @arg TIM_CHANNEL_1: TIM Channel 1
		4456	* @arg TIM_CHANNEL_2: TIM Channel 2
		4457	* @arg TIM_CHANNEL_3: TIM Channel 3
		4458	* @arg TIM_CHANNEL_4: TIM Channel 4
		4459	* @retval HAL status
		4460	*/
		4461	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
		4462	TIM_ClearInputConfigTypeDef *sClearInputConfig,
		4463	uint32_t Channel)
		4464	{
		4465	/* Check the parameters */
		4466	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
		4467	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
		4468
		4469	/* Process Locked */
		4470	__HAL_LOCK(htim);
		4471
		4472	htim->State = HAL_TIM_STATE_BUSY;
		4473
		4474	switch (sClearInputConfig->ClearInputSource)
		4475	{
		4476	case TIM_CLEARINPUTSOURCE_NONE:
		4477	{
		4478	/* Clear the OCREF clear selection bit and the the ETR Bits */
		4479	CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS \| TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP));
		4480	break;
		4481	}
		4482	case TIM_CLEARINPUTSOURCE_OCREFCLR:
		4483	{
		4484	/* Clear the OCREF clear selection bit */
		4485	CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
		4486	}
		4487	break;
		4488
		4489	case TIM_CLEARINPUTSOURCE_ETR:
		4490	{
		4491	/* Check the parameters */
		4492	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
		4493	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
		4494	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
		4495
		4496	/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
		4497	if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
		4498	{
		4499	htim->State = HAL_TIM_STATE_READY;
		4500	__HAL_UNLOCK(htim);
		4501	return HAL_ERROR;
		4502	}
		4503
		4504	TIM_ETR_SetConfig(htim->Instance,
		4505	sClearInputConfig->ClearInputPrescaler,
		4506	sClearInputConfig->ClearInputPolarity,
		4507	sClearInputConfig->ClearInputFilter);
		4508
		4509	/* Set the OCREF clear selection bit */
		4510	SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
		4511	break;
		4512	}
		4513
		4514	default:
		4515	break;
		4516	}
		4517
		4518	switch (Channel)
		4519	{
		4520	case TIM_CHANNEL_1:
		4521	{
		4522	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4523	{
		4524	/* Enable the OCREF clear feature for Channel 1 */
		4525	SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
		4526	}
		4527	else
		4528	{
		4529	/* Disable the OCREF clear feature for Channel 1 */
		4530	CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
		4531	}
		4532	break;
		4533	}
		4534	case TIM_CHANNEL_2:
		4535	{
		4536	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4537	{
		4538	/* Enable the OCREF clear feature for Channel 2 */
		4539	SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
		4540	}
		4541	else
		4542	{
		4543	/* Disable the OCREF clear feature for Channel 2 */
		4544	CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
		4545	}
		4546	break;
		4547	}
		4548	case TIM_CHANNEL_3:
		4549	{
		4550	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4551	{
		4552	/* Enable the OCREF clear feature for Channel 3 */
		4553	SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
		4554	}
		4555	else
		4556	{
		4557	/* Disable the OCREF clear feature for Channel 3 */
		4558	CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
		4559	}
		4560	break;
		4561	}
		4562	case TIM_CHANNEL_4:
		4563	{
		4564	if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
		4565	{
		4566	/* Enable the OCREF clear feature for Channel 4 */
		4567	SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
		4568	}
		4569	else
		4570	{
		4571	/* Disable the OCREF clear feature for Channel 4 */
		4572	CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
		4573	}
		4574	break;
		4575	}
		4576	default:
		4577	break;
		4578	}
		4579
		4580	htim->State = HAL_TIM_STATE_READY;
		4581
		4582	__HAL_UNLOCK(htim);
		4583
		4584	return HAL_OK;
		4585	}
		4586
		4587	/**
		4588	* @brief Configures the clock source to be used
		4589	* @param htim TIM handle
		4590	* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
		4591	* contains the clock source information for the TIM peripheral.
		4592	* @retval HAL status
		4593	*/
		4594	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
		4595	{
		4596	uint32_t tmpsmcr;
		4597
		4598	/* Process Locked */
		4599	__HAL_LOCK(htim);
		4600
		4601	htim->State = HAL_TIM_STATE_BUSY;
		4602
		4603	/* Check the parameters */
		4604	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
		4605
		4606	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
		4607	tmpsmcr = htim->Instance->SMCR;
		4608	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
		4609	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		4610	htim->Instance->SMCR = tmpsmcr;
		4611
		4612	switch (sClockSourceConfig->ClockSource)
		4613	{
		4614	case TIM_CLOCKSOURCE_INTERNAL:
		4615	{
		4616	assert_param(IS_TIM_INSTANCE(htim->Instance));
		4617	break;
		4618	}
		4619
		4620	case TIM_CLOCKSOURCE_ETRMODE1:
		4621	{
		4622	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
		4623	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
		4624
		4625	/* Check ETR input conditioning related parameters */
		4626	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
		4627	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4628	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4629
		4630	/* Configure the ETR Clock source */
		4631	TIM_ETR_SetConfig(htim->Instance,
		4632	sClockSourceConfig->ClockPrescaler,
		4633	sClockSourceConfig->ClockPolarity,
		4634	sClockSourceConfig->ClockFilter);
		4635
		4636	/* Select the External clock mode1 and the ETRF trigger */
		4637	tmpsmcr = htim->Instance->SMCR;
		4638	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
		4639	/* Write to TIMx SMCR */
		4640	htim->Instance->SMCR = tmpsmcr;
		4641	break;
		4642	}
		4643
		4644	case TIM_CLOCKSOURCE_ETRMODE2:
		4645	{
		4646	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
		4647	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
		4648
		4649	/* Check ETR input conditioning related parameters */
		4650	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
		4651	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4652	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4653
		4654	/* Configure the ETR Clock source */
		4655	TIM_ETR_SetConfig(htim->Instance,
		4656	sClockSourceConfig->ClockPrescaler,
		4657	sClockSourceConfig->ClockPolarity,
		4658	sClockSourceConfig->ClockFilter);
		4659	/* Enable the External clock mode2 */
		4660	htim->Instance->SMCR \|= TIM_SMCR_ECE;
		4661	break;
		4662	}
		4663
		4664	case TIM_CLOCKSOURCE_TI1:
		4665	{
		4666	/* Check whether or not the timer instance supports external clock mode 1 */
		4667	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		4668
		4669	/* Check TI1 input conditioning related parameters */
		4670	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4671	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4672
		4673	TIM_TI1_ConfigInputStage(htim->Instance,
		4674	sClockSourceConfig->ClockPolarity,
		4675	sClockSourceConfig->ClockFilter);
		4676	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
		4677	break;
		4678	}
		4679
		4680	case TIM_CLOCKSOURCE_TI2:
		4681	{
		4682	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
		4683	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		4684
		4685	/* Check TI2 input conditioning related parameters */
		4686	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4687	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4688
		4689	TIM_TI2_ConfigInputStage(htim->Instance,
		4690	sClockSourceConfig->ClockPolarity,
		4691	sClockSourceConfig->ClockFilter);
		4692	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
		4693	break;
		4694	}
		4695
		4696	case TIM_CLOCKSOURCE_TI1ED:
		4697	{
		4698	/* Check whether or not the timer instance supports external clock mode 1 */
		4699	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
		4700
		4701	/* Check TI1 input conditioning related parameters */
		4702	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
		4703	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
		4704
		4705	TIM_TI1_ConfigInputStage(htim->Instance,
		4706	sClockSourceConfig->ClockPolarity,
		4707	sClockSourceConfig->ClockFilter);
		4708	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
		4709	break;
		4710	}
		4711
		4712	case TIM_CLOCKSOURCE_ITR0:
		4713	case TIM_CLOCKSOURCE_ITR1:
		4714	case TIM_CLOCKSOURCE_ITR2:
		4715	case TIM_CLOCKSOURCE_ITR3:
		4716	{
		4717	/* Check whether or not the timer instance supports internal trigger input */
		4718	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
		4719
		4720	TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
		4721	break;
		4722	}
		4723
		4724	default:
		4725	break;
		4726	}
		4727	htim->State = HAL_TIM_STATE_READY;
		4728
		4729	__HAL_UNLOCK(htim);
		4730
		4731	return HAL_OK;
		4732	}
		4733
		4734	/**
		4735	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
		4736	* or a XOR combination between CH1_input, CH2_input & CH3_input
		4737	* @param htim TIM handle.
		4738	* @param TI1_Selection Indicate whether or not channel 1 is connected to the
		4739	* output of a XOR gate.
		4740	* This parameter can be one of the following values:
		4741	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
		4742	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
		4743	* pins are connected to the TI1 input (XOR combination)
		4744	* @retval HAL status
		4745	*/
		4746	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
		4747	{
		4748	uint32_t tmpcr2;
		4749
		4750	/* Check the parameters */
		4751	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
		4752	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
		4753
		4754	/* Get the TIMx CR2 register value */
		4755	tmpcr2 = htim->Instance->CR2;
		4756
		4757	/* Reset the TI1 selection */
		4758	tmpcr2 &= ~TIM_CR2_TI1S;
		4759
		4760	/* Set the TI1 selection */
		4761	tmpcr2 \|= TI1_Selection;
		4762
		4763	/* Write to TIMxCR2 */
		4764	htim->Instance->CR2 = tmpcr2;
		4765
		4766	return HAL_OK;
		4767	}
		4768
		4769	/**
		4770	* @brief Configures the TIM in Slave mode
		4771	* @param htim TIM handle.
		4772	* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
		4773	* contains the selected trigger (internal trigger input, filtered
		4774	* timer input or external trigger input) and the Slave mode
		4775	* (Disable, Reset, Gated, Trigger, External clock mode 1).
		4776	* @retval HAL status
		4777	*/
		4778	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
		4779	{
		4780	/* Check the parameters */
		4781	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
		4782	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
		4783	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
		4784
		4785	__HAL_LOCK(htim);
		4786
		4787	htim->State = HAL_TIM_STATE_BUSY;
		4788
		4789	if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
		4790	{
		4791	htim->State = HAL_TIM_STATE_READY;
		4792	__HAL_UNLOCK(htim);
		4793	return HAL_ERROR;
		4794	}
		4795
		4796	/* Disable Trigger Interrupt */
		4797	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
		4798
		4799	/* Disable Trigger DMA request */
		4800	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
		4801
		4802	htim->State = HAL_TIM_STATE_READY;
		4803
		4804	__HAL_UNLOCK(htim);
		4805
		4806	return HAL_OK;
		4807	}
		4808
		4809	/**
		4810	* @brief Configures the TIM in Slave mode in interrupt mode
		4811	* @param htim TIM handle.
		4812	* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
		4813	* contains the selected trigger (internal trigger input, filtered
		4814	* timer input or external trigger input) and the Slave mode
		4815	* (Disable, Reset, Gated, Trigger, External clock mode 1).
		4816	* @retval HAL status
		4817	*/
		4818	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
		4819	TIM_SlaveConfigTypeDef *sSlaveConfig)
		4820	{
		4821	/* Check the parameters */
		4822	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
		4823	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
		4824	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
		4825
		4826	__HAL_LOCK(htim);
		4827
		4828	htim->State = HAL_TIM_STATE_BUSY;
		4829
		4830	if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
		4831	{
		4832	htim->State = HAL_TIM_STATE_READY;
		4833	__HAL_UNLOCK(htim);
		4834	return HAL_ERROR;
		4835	}
		4836
		4837	/* Enable Trigger Interrupt */
		4838	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
		4839
		4840	/* Disable Trigger DMA request */
		4841	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
		4842
		4843	htim->State = HAL_TIM_STATE_READY;
		4844
		4845	__HAL_UNLOCK(htim);
		4846
		4847	return HAL_OK;
		4848	}
		4849
		4850	/**
		4851	* @brief Read the captured value from Capture Compare unit
		4852	* @param htim TIM handle.
		4853	* @param Channel TIM Channels to be enabled
		4854	* This parameter can be one of the following values:
		4855	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		4856	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		4857	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		4858	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		4859	* @retval Captured value
		4860	*/
		4861	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
		4862	{
		4863	uint32_t tmpreg = 0U;
		4864
		4865	switch (Channel)
		4866	{
		4867	case TIM_CHANNEL_1:
		4868	{
		4869	/* Check the parameters */
		4870	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		4871
		4872	/* Return the capture 1 value */
		4873	tmpreg = htim->Instance->CCR1;
		4874
		4875	break;
		4876	}
		4877	case TIM_CHANNEL_2:
		4878	{
		4879	/* Check the parameters */
		4880	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		4881
		4882	/* Return the capture 2 value */
		4883	tmpreg = htim->Instance->CCR2;
		4884
		4885	break;
		4886	}
		4887
		4888	case TIM_CHANNEL_3:
		4889	{
		4890	/* Check the parameters */
		4891	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
		4892
		4893	/* Return the capture 3 value */
		4894	tmpreg = htim->Instance->CCR3;
		4895
		4896	break;
		4897	}
		4898
		4899	case TIM_CHANNEL_4:
		4900	{
		4901	/* Check the parameters */
		4902	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
		4903
		4904	/* Return the capture 4 value */
		4905	tmpreg = htim->Instance->CCR4;
		4906
		4907	break;
		4908	}
		4909
		4910	default:
		4911	break;
		4912	}
		4913
		4914	return tmpreg;
		4915	}
		4916
		4917	/**
		4918	* @}
		4919	*/
		4920
		4921	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		4922	* @brief TIM Callbacks functions
		4923	*
		4924	@verbatim
		4925	==============================================================================
		4926	##### TIM Callbacks functions #####
		4927	==============================================================================
		4928	[..]
		4929	This section provides TIM callback functions:
		4930	(+) TIM Period elapsed callback
		4931	(+) TIM Output Compare callback
		4932	(+) TIM Input capture callback
		4933	(+) TIM Trigger callback
		4934	(+) TIM Error callback
		4935
		4936	@endverbatim
		4937	* @{
		4938	*/
		4939
		4940	/**
		4941	* @brief Period elapsed callback in non-blocking mode
		4942	* @param htim TIM handle
		4943	* @retval None
		4944	*/
		4945	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
		4946	{
		4947	/* Prevent unused argument(s) compilation warning */
		4948	UNUSED(htim);
		4949
		4950	/* NOTE : This function should not be modified, when the callback is needed,
		4951	the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
		4952	*/
		4953	}
		4954
		4955	/**
		4956	* @brief Period elapsed half complete callback in non-blocking mode
		4957	* @param htim TIM handle
		4958	* @retval None
		4959	*/
		4960	__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
		4961	{
		4962	/* Prevent unused argument(s) compilation warning */
		4963	UNUSED(htim);
		4964
		4965	/* NOTE : This function should not be modified, when the callback is needed,
		4966	the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
		4967	*/
		4968	}
		4969
		4970	/**
		4971	* @brief Output Compare callback in non-blocking mode
		4972	* @param htim TIM OC handle
		4973	* @retval None
		4974	*/
		4975	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
		4976	{
		4977	/* Prevent unused argument(s) compilation warning */
		4978	UNUSED(htim);
		4979
		4980	/* NOTE : This function should not be modified, when the callback is needed,
		4981	the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
		4982	*/
		4983	}
		4984
		4985	/**
		4986	* @brief Input Capture callback in non-blocking mode
		4987	* @param htim TIM IC handle
		4988	* @retval None
		4989	*/
		4990	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
		4991	{
		4992	/* Prevent unused argument(s) compilation warning */
		4993	UNUSED(htim);
		4994
		4995	/* NOTE : This function should not be modified, when the callback is needed,
		4996	the HAL_TIM_IC_CaptureCallback could be implemented in the user file
		4997	*/
		4998	}
		4999
		5000	/**
		5001	* @brief Input Capture half complete callback in non-blocking mode
		5002	* @param htim TIM IC handle
		5003	* @retval None
		5004	*/
		5005	__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
		5006	{
		5007	/* Prevent unused argument(s) compilation warning */
		5008	UNUSED(htim);
		5009
		5010	/* NOTE : This function should not be modified, when the callback is needed,
		5011	the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
		5012	*/
		5013	}
		5014
		5015	/**
		5016	* @brief PWM Pulse finished callback in non-blocking mode
		5017	* @param htim TIM handle
		5018	* @retval None
		5019	*/
		5020	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
		5021	{
		5022	/* Prevent unused argument(s) compilation warning */
		5023	UNUSED(htim);
		5024
		5025	/* NOTE : This function should not be modified, when the callback is needed,
		5026	the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
		5027	*/
		5028	}
		5029
		5030	/**
		5031	* @brief PWM Pulse finished half complete callback in non-blocking mode
		5032	* @param htim TIM handle
		5033	* @retval None
		5034	*/
		5035	__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
		5036	{
		5037	/* Prevent unused argument(s) compilation warning */
		5038	UNUSED(htim);
		5039
		5040	/* NOTE : This function should not be modified, when the callback is needed,
		5041	the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
		5042	*/
		5043	}
		5044
		5045	/**
		5046	* @brief Hall Trigger detection callback in non-blocking mode
		5047	* @param htim TIM handle
		5048	* @retval None
		5049	*/
		5050	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
		5051	{
		5052	/* Prevent unused argument(s) compilation warning */
		5053	UNUSED(htim);
		5054
		5055	/* NOTE : This function should not be modified, when the callback is needed,
		5056	the HAL_TIM_TriggerCallback could be implemented in the user file
		5057	*/
		5058	}
		5059
		5060	/**
		5061	* @brief Hall Trigger detection half complete callback in non-blocking mode
		5062	* @param htim TIM handle
		5063	* @retval None
		5064	*/
		5065	__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
		5066	{
		5067	/* Prevent unused argument(s) compilation warning */
		5068	UNUSED(htim);
		5069
		5070	/* NOTE : This function should not be modified, when the callback is needed,
		5071	the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
		5072	*/
		5073	}
		5074
		5075	/**
		5076	* @brief Timer error callback in non-blocking mode
		5077	* @param htim TIM handle
		5078	* @retval None
		5079	*/
		5080	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
		5081	{
		5082	/* Prevent unused argument(s) compilation warning */
		5083	UNUSED(htim);
		5084
		5085	/* NOTE : This function should not be modified, when the callback is needed,
		5086	the HAL_TIM_ErrorCallback could be implemented in the user file
		5087	*/
		5088	}
		5089
		5090	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5091	/**
		5092	* @brief Register a User TIM callback to be used instead of the weak predefined callback
		5093	* @param htim tim handle
		5094	* @param CallbackID ID of the callback to be registered
		5095	* This parameter can be one of the following values:
		5096	* @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
		5097	* @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
		5098	* @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
		5099	* @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
		5100	* @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
		5101	* @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
		5102	* @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
		5103	* @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
		5104	* @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
		5105	* @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
		5106	* @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
		5107	* @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
		5108	* @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
		5109	* @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
		5110	* @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
		5111	* @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
		5112	* @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
		5113	* @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
		5114	* @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
		5115	* @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
		5116	* @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
		5117	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
		5118	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
		5119	* @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
		5120	* @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
		5121	* @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
		5122	* @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
		5123	* @param pCallback pointer to the callback function
		5124	* @retval status
		5125	*/
		5126	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		5127	pTIM_CallbackTypeDef pCallback)
		5128	{
		5129	HAL_StatusTypeDef status = HAL_OK;
		5130
		5131	if (pCallback == NULL)
		5132	{
		5133	return HAL_ERROR;
		5134	}
		5135	/* Process locked */
		5136	__HAL_LOCK(htim);
		5137
		5138	if (htim->State == HAL_TIM_STATE_READY)
		5139	{
		5140	switch (CallbackID)
		5141	{
		5142	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5143	htim->Base_MspInitCallback = pCallback;
		5144	break;
		5145
		5146	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5147	htim->Base_MspDeInitCallback = pCallback;
		5148	break;
		5149
		5150	case HAL_TIM_IC_MSPINIT_CB_ID :
		5151	htim->IC_MspInitCallback = pCallback;
		5152	break;
		5153
		5154	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5155	htim->IC_MspDeInitCallback = pCallback;
		5156	break;
		5157
		5158	case HAL_TIM_OC_MSPINIT_CB_ID :
		5159	htim->OC_MspInitCallback = pCallback;
		5160	break;
		5161
		5162	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5163	htim->OC_MspDeInitCallback = pCallback;
		5164	break;
		5165
		5166	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5167	htim->PWM_MspInitCallback = pCallback;
		5168	break;
		5169
		5170	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5171	htim->PWM_MspDeInitCallback = pCallback;
		5172	break;
		5173
		5174	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5175	htim->OnePulse_MspInitCallback = pCallback;
		5176	break;
		5177
		5178	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5179	htim->OnePulse_MspDeInitCallback = pCallback;
		5180	break;
		5181
		5182	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5183	htim->Encoder_MspInitCallback = pCallback;
		5184	break;
		5185
		5186	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5187	htim->Encoder_MspDeInitCallback = pCallback;
		5188	break;
		5189
		5190	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5191	htim->HallSensor_MspInitCallback = pCallback;
		5192	break;
		5193
		5194	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5195	htim->HallSensor_MspDeInitCallback = pCallback;
		5196	break;
		5197
		5198	case HAL_TIM_PERIOD_ELAPSED_CB_ID :
		5199	htim->PeriodElapsedCallback = pCallback;
		5200	break;
		5201
		5202	case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
		5203	htim->PeriodElapsedHalfCpltCallback = pCallback;
		5204	break;
		5205
		5206	case HAL_TIM_TRIGGER_CB_ID :
		5207	htim->TriggerCallback = pCallback;
		5208	break;
		5209
		5210	case HAL_TIM_TRIGGER_HALF_CB_ID :
		5211	htim->TriggerHalfCpltCallback = pCallback;
		5212	break;
		5213
		5214	case HAL_TIM_IC_CAPTURE_CB_ID :
		5215	htim->IC_CaptureCallback = pCallback;
		5216	break;
		5217
		5218	case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
		5219	htim->IC_CaptureHalfCpltCallback = pCallback;
		5220	break;
		5221
		5222	case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
		5223	htim->OC_DelayElapsedCallback = pCallback;
		5224	break;
		5225
		5226	case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
		5227	htim->PWM_PulseFinishedCallback = pCallback;
		5228	break;
		5229
		5230	case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
		5231	htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
		5232	break;
		5233
		5234	case HAL_TIM_ERROR_CB_ID :
		5235	htim->ErrorCallback = pCallback;
		5236	break;
		5237
		5238	case HAL_TIM_COMMUTATION_CB_ID :
		5239	htim->CommutationCallback = pCallback;
		5240	break;
		5241
		5242	case HAL_TIM_COMMUTATION_HALF_CB_ID :
		5243	htim->CommutationHalfCpltCallback = pCallback;
		5244	break;
		5245
		5246	case HAL_TIM_BREAK_CB_ID :
		5247	htim->BreakCallback = pCallback;
		5248	break;
		5249
		5250	default :
		5251	/* Return error status */
		5252	status = HAL_ERROR;
		5253	break;
		5254	}
		5255	}
		5256	else if (htim->State == HAL_TIM_STATE_RESET)
		5257	{
		5258	switch (CallbackID)
		5259	{
		5260	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5261	htim->Base_MspInitCallback = pCallback;
		5262	break;
		5263
		5264	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5265	htim->Base_MspDeInitCallback = pCallback;
		5266	break;
		5267
		5268	case HAL_TIM_IC_MSPINIT_CB_ID :
		5269	htim->IC_MspInitCallback = pCallback;
		5270	break;
		5271
		5272	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5273	htim->IC_MspDeInitCallback = pCallback;
		5274	break;
		5275
		5276	case HAL_TIM_OC_MSPINIT_CB_ID :
		5277	htim->OC_MspInitCallback = pCallback;
		5278	break;
		5279
		5280	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5281	htim->OC_MspDeInitCallback = pCallback;
		5282	break;
		5283
		5284	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5285	htim->PWM_MspInitCallback = pCallback;
		5286	break;
		5287
		5288	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5289	htim->PWM_MspDeInitCallback = pCallback;
		5290	break;
		5291
		5292	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5293	htim->OnePulse_MspInitCallback = pCallback;
		5294	break;
		5295
		5296	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5297	htim->OnePulse_MspDeInitCallback = pCallback;
		5298	break;
		5299
		5300	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5301	htim->Encoder_MspInitCallback = pCallback;
		5302	break;
		5303
		5304	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5305	htim->Encoder_MspDeInitCallback = pCallback;
		5306	break;
		5307
		5308	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5309	htim->HallSensor_MspInitCallback = pCallback;
		5310	break;
		5311
		5312	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5313	htim->HallSensor_MspDeInitCallback = pCallback;
		5314	break;
		5315
		5316	default :
		5317	/* Return error status */
		5318	status = HAL_ERROR;
		5319	break;
		5320	}
		5321	}
		5322	else
		5323	{
		5324	/* Return error status */
		5325	status = HAL_ERROR;
		5326	}
		5327
		5328	/* Release Lock */
		5329	__HAL_UNLOCK(htim);
		5330
		5331	return status;
		5332	}
		5333
		5334	/**
		5335	* @brief Unregister a TIM callback
		5336	* TIM callback is redirected to the weak predefined callback
		5337	* @param htim tim handle
		5338	* @param CallbackID ID of the callback to be unregistered
		5339	* This parameter can be one of the following values:
		5340	* @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
		5341	* @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
		5342	* @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
		5343	* @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
		5344	* @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
		5345	* @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
		5346	* @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
		5347	* @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
		5348	* @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
		5349	* @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
		5350	* @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
		5351	* @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
		5352	* @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
		5353	* @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
		5354	* @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
		5355	* @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
		5356	* @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
		5357	* @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
		5358	* @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
		5359	* @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
		5360	* @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
		5361	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
		5362	* @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
		5363	* @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
		5364	* @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
		5365	* @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
		5366	* @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
		5367	* @retval status
		5368	*/
		5369	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
		5370	{
		5371	HAL_StatusTypeDef status = HAL_OK;
		5372
		5373	/* Process locked */
		5374	__HAL_LOCK(htim);
		5375
		5376	if (htim->State == HAL_TIM_STATE_READY)
		5377	{
		5378	switch (CallbackID)
		5379	{
		5380	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5381	htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
		5382	break;
		5383
		5384	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5385	htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
		5386	break;
		5387
		5388	case HAL_TIM_IC_MSPINIT_CB_ID :
		5389	htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
		5390	break;
		5391
		5392	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5393	htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
		5394	break;
		5395
		5396	case HAL_TIM_OC_MSPINIT_CB_ID :
		5397	htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
		5398	break;
		5399
		5400	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5401	htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
		5402	break;
		5403
		5404	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5405	htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
		5406	break;
		5407
		5408	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5409	htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
		5410	break;
		5411
		5412	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5413	htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
		5414	break;
		5415
		5416	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5417	htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
		5418	break;
		5419
		5420	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5421	htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
		5422	break;
		5423
		5424	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5425	htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
		5426	break;
		5427
		5428	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5429	htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
		5430	break;
		5431
		5432	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5433	htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
		5434	break;
		5435
		5436	case HAL_TIM_PERIOD_ELAPSED_CB_ID :
		5437	htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
		5438	break;
		5439
		5440	case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
		5441	htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
		5442	break;
		5443
		5444	case HAL_TIM_TRIGGER_CB_ID :
		5445	htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
		5446	break;
		5447
		5448	case HAL_TIM_TRIGGER_HALF_CB_ID :
		5449	htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
		5450	break;
		5451
		5452	case HAL_TIM_IC_CAPTURE_CB_ID :
		5453	htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
		5454	break;
		5455
		5456	case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
		5457	htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
		5458	break;
		5459
		5460	case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
		5461	htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
		5462	break;
		5463
		5464	case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
		5465	htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
		5466	break;
		5467
		5468	case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
		5469	htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
		5470	break;
		5471
		5472	case HAL_TIM_ERROR_CB_ID :
		5473	htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
		5474	break;
		5475
		5476	case HAL_TIM_COMMUTATION_CB_ID :
		5477	htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
		5478	break;
		5479
		5480	case HAL_TIM_COMMUTATION_HALF_CB_ID :
		5481	htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
		5482	break;
		5483
		5484	case HAL_TIM_BREAK_CB_ID :
		5485	htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
		5486	break;
		5487
		5488	default :
		5489	/* Return error status */
		5490	status = HAL_ERROR;
		5491	break;
		5492	}
		5493	}
		5494	else if (htim->State == HAL_TIM_STATE_RESET)
		5495	{
		5496	switch (CallbackID)
		5497	{
		5498	case HAL_TIM_BASE_MSPINIT_CB_ID :
		5499	htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
		5500	break;
		5501
		5502	case HAL_TIM_BASE_MSPDEINIT_CB_ID :
		5503	htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
		5504	break;
		5505
		5506	case HAL_TIM_IC_MSPINIT_CB_ID :
		5507	htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
		5508	break;
		5509
		5510	case HAL_TIM_IC_MSPDEINIT_CB_ID :
		5511	htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
		5512	break;
		5513
		5514	case HAL_TIM_OC_MSPINIT_CB_ID :
		5515	htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
		5516	break;
		5517
		5518	case HAL_TIM_OC_MSPDEINIT_CB_ID :
		5519	htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
		5520	break;
		5521
		5522	case HAL_TIM_PWM_MSPINIT_CB_ID :
		5523	htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
		5524	break;
		5525
		5526	case HAL_TIM_PWM_MSPDEINIT_CB_ID :
		5527	htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
		5528	break;
		5529
		5530	case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
		5531	htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
		5532	break;
		5533
		5534	case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
		5535	htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
		5536	break;
		5537
		5538	case HAL_TIM_ENCODER_MSPINIT_CB_ID :
		5539	htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
		5540	break;
		5541
		5542	case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
		5543	htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
		5544	break;
		5545
		5546	case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
		5547	htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
		5548	break;
		5549
		5550	case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
		5551	htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
		5552	break;
		5553
		5554	default :
		5555	/* Return error status */
		5556	status = HAL_ERROR;
		5557	break;
		5558	}
		5559	}
		5560	else
		5561	{
		5562	/* Return error status */
		5563	status = HAL_ERROR;
		5564	}
		5565
		5566	/* Release Lock */
		5567	__HAL_UNLOCK(htim);
		5568
		5569	return status;
		5570	}
		5571	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5572
		5573	/**
		5574	* @}
		5575	*/
		5576
		5577	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		5578	* @brief TIM Peripheral State functions
		5579	*
		5580	@verbatim
		5581	==============================================================================
		5582	##### Peripheral State functions #####
		5583	==============================================================================
		5584	[..]
		5585	This subsection permits to get in run-time the status of the peripheral
		5586	and the data flow.
		5587
		5588	@endverbatim
		5589	* @{
		5590	*/
		5591
		5592	/**
		5593	* @brief Return the TIM Base handle state.
		5594	* @param htim TIM Base handle
		5595	* @retval HAL state
		5596	*/
		5597	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
		5598	{
		5599	return htim->State;
		5600	}
		5601
		5602	/**
		5603	* @brief Return the TIM OC handle state.
		5604	* @param htim TIM Output Compare handle
		5605	* @retval HAL state
		5606	*/
		5607	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
		5608	{
		5609	return htim->State;
		5610	}
		5611
		5612	/**
		5613	* @brief Return the TIM PWM handle state.
		5614	* @param htim TIM handle
		5615	* @retval HAL state
		5616	*/
		5617	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
		5618	{
		5619	return htim->State;
		5620	}
		5621
		5622	/**
		5623	* @brief Return the TIM Input Capture handle state.
		5624	* @param htim TIM IC handle
		5625	* @retval HAL state
		5626	*/
		5627	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
		5628	{
		5629	return htim->State;
		5630	}
		5631
		5632	/**
		5633	* @brief Return the TIM One Pulse Mode handle state.
		5634	* @param htim TIM OPM handle
		5635	* @retval HAL state
		5636	*/
		5637	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
		5638	{
		5639	return htim->State;
		5640	}
		5641
		5642	/**
		5643	* @brief Return the TIM Encoder Mode handle state.
		5644	* @param htim TIM Encoder Interface handle
		5645	* @retval HAL state
		5646	*/
		5647	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
		5648	{
		5649	return htim->State;
		5650	}
		5651
		5652	/**
		5653	* @}
		5654	*/
		5655
		5656	/**
		5657	* @}
		5658	*/
		5659
		5660	/** @defgroup TIM_Private_Functions TIM Private Functions
		5661	* @{
		5662	*/
		5663
		5664	/**
		5665	* @brief TIM DMA error callback
		5666	* @param hdma pointer to DMA handle.
		5667	* @retval None
		5668	*/
		5669	void TIM_DMAError(DMA_HandleTypeDef *hdma)
		5670	{
		5671	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5672
		5673	htim->State = HAL_TIM_STATE_READY;
		5674
		5675	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5676	htim->ErrorCallback(htim);
		5677	#else
		5678	HAL_TIM_ErrorCallback(htim);
		5679	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5680	}
		5681
		5682	/**
		5683	* @brief TIM DMA Delay Pulse complete callback.
		5684	* @param hdma pointer to DMA handle.
		5685	* @retval None
		5686	*/
		5687	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
		5688	{
		5689	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5690
		5691	htim->State = HAL_TIM_STATE_READY;
		5692
		5693	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5694	{
		5695	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5696	}
		5697	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5698	{
		5699	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5700	}
		5701	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5702	{
		5703	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5704	}
		5705	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5706	{
		5707	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5708	}
		5709	else
		5710	{
		5711	/* nothing to do */
		5712	}
		5713
		5714	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5715	htim->PWM_PulseFinishedCallback(htim);
		5716	#else
		5717	HAL_TIM_PWM_PulseFinishedCallback(htim);
		5718	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5719
		5720	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5721	}
		5722
		5723	/**
		5724	* @brief TIM DMA Delay Pulse half complete callback.
		5725	* @param hdma pointer to DMA handle.
		5726	* @retval None
		5727	*/
		5728	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
		5729	{
		5730	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5731
		5732	htim->State = HAL_TIM_STATE_READY;
		5733
		5734	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5735	{
		5736	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5737	}
		5738	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5739	{
		5740	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5741	}
		5742	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5743	{
		5744	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5745	}
		5746	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5747	{
		5748	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5749	}
		5750	else
		5751	{
		5752	/* nothing to do */
		5753	}
		5754
		5755	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5756	htim->PWM_PulseFinishedHalfCpltCallback(htim);
		5757	#else
		5758	HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
		5759	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5760
		5761	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5762	}
		5763
		5764	/**
		5765	* @brief TIM DMA Capture complete callback.
		5766	* @param hdma pointer to DMA handle.
		5767	* @retval None
		5768	*/
		5769	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
		5770	{
		5771	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5772
		5773	htim->State = HAL_TIM_STATE_READY;
		5774
		5775	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5776	{
		5777	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5778	}
		5779	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5780	{
		5781	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5782	}
		5783	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5784	{
		5785	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5786	}
		5787	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5788	{
		5789	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5790	}
		5791	else
		5792	{
		5793	/* nothing to do */
		5794	}
		5795
		5796	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5797	htim->IC_CaptureCallback(htim);
		5798	#else
		5799	HAL_TIM_IC_CaptureCallback(htim);
		5800	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5801
		5802	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5803	}
		5804
		5805	/**
		5806	* @brief TIM DMA Capture half complete callback.
		5807	* @param hdma pointer to DMA handle.
		5808	* @retval None
		5809	*/
		5810	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
		5811	{
		5812	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5813
		5814	htim->State = HAL_TIM_STATE_READY;
		5815
		5816	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
		5817	{
		5818	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
		5819	}
		5820	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
		5821	{
		5822	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
		5823	}
		5824	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
		5825	{
		5826	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
		5827	}
		5828	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
		5829	{
		5830	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
		5831	}
		5832	else
		5833	{
		5834	/* nothing to do */
		5835	}
		5836
		5837	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5838	htim->IC_CaptureHalfCpltCallback(htim);
		5839	#else
		5840	HAL_TIM_IC_CaptureHalfCpltCallback(htim);
		5841	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5842
		5843	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
		5844	}
		5845
		5846	/**
		5847	* @brief TIM DMA Period Elapse complete callback.
		5848	* @param hdma pointer to DMA handle.
		5849	* @retval None
		5850	*/
		5851	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
		5852	{
		5853	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5854
		5855	htim->State = HAL_TIM_STATE_READY;
		5856
		5857	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5858	htim->PeriodElapsedCallback(htim);
		5859	#else
		5860	HAL_TIM_PeriodElapsedCallback(htim);
		5861	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5862	}
		5863
		5864	/**
		5865	* @brief TIM DMA Period Elapse half complete callback.
		5866	* @param hdma pointer to DMA handle.
		5867	* @retval None
		5868	*/
		5869	static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
		5870	{
		5871	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5872
		5873	htim->State = HAL_TIM_STATE_READY;
		5874
		5875	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5876	htim->PeriodElapsedHalfCpltCallback(htim);
		5877	#else
		5878	HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
		5879	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5880	}
		5881
		5882	/**
		5883	* @brief TIM DMA Trigger callback.
		5884	* @param hdma pointer to DMA handle.
		5885	* @retval None
		5886	*/
		5887	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
		5888	{
		5889	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5890
		5891	htim->State = HAL_TIM_STATE_READY;
		5892
		5893	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5894	htim->TriggerCallback(htim);
		5895	#else
		5896	HAL_TIM_TriggerCallback(htim);
		5897	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5898	}
		5899
		5900	/**
		5901	* @brief TIM DMA Trigger half complete callback.
		5902	* @param hdma pointer to DMA handle.
		5903	* @retval None
		5904	*/
		5905	static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
		5906	{
		5907	TIM_HandleTypeDef htim = (TIM_HandleTypeDef )((DMA_HandleTypeDef *)hdma)->Parent;
		5908
		5909	htim->State = HAL_TIM_STATE_READY;
		5910
		5911	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		5912	htim->TriggerHalfCpltCallback(htim);
		5913	#else
		5914	HAL_TIM_TriggerHalfCpltCallback(htim);
		5915	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		5916	}
		5917
		5918	/**
		5919	* @brief Time Base configuration
		5920	* @param TIMx TIM peripheral
		5921	* @param Structure TIM Base configuration structure
		5922	* @retval None
		5923	*/
		5924	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
		5925	{
		5926	uint32_t tmpcr1;
		5927	tmpcr1 = TIMx->CR1;
		5928
		5929	/* Set TIM Time Base Unit parameters ---------------------------------------*/
		5930	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
		5931	{
		5932	/* Select the Counter Mode */
		5933	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
		5934	tmpcr1 \|= Structure->CounterMode;
		5935	}
		5936
		5937	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
		5938	{
		5939	/* Set the clock division */
		5940	tmpcr1 &= ~TIM_CR1_CKD;
		5941	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
		5942	}
		5943
		5944	/* Set the auto-reload preload */
		5945	MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
		5946
		5947	TIMx->CR1 = tmpcr1;
		5948
		5949	/* Set the Autoreload value */
		5950	TIMx->ARR = (uint32_t)Structure->Period ;
		5951
		5952	/* Set the Prescaler value */
		5953	TIMx->PSC = Structure->Prescaler;
		5954
		5955	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
		5956	{
		5957	/* Set the Repetition Counter value */
		5958	TIMx->RCR = Structure->RepetitionCounter;
		5959	}
		5960
		5961	/* Generate an update event to reload the Prescaler
		5962	and the repetition counter (only for advanced timer) value immediately */
		5963	TIMx->EGR = TIM_EGR_UG;
		5964	}
		5965
		5966	/**
		5967	* @brief Timer Output Compare 1 configuration
		5968	* @param TIMx to select the TIM peripheral
		5969	* @param OC_Config The ouput configuration structure
		5970	* @retval None
		5971	*/
		5972	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		5973	{
		5974	uint32_t tmpccmrx;
		5975	uint32_t tmpccer;
		5976	uint32_t tmpcr2;
		5977
		5978	/* Disable the Channel 1: Reset the CC1E Bit */
		5979	TIMx->CCER &= ~TIM_CCER_CC1E;
		5980
		5981	/* Get the TIMx CCER register value */
		5982	tmpccer = TIMx->CCER;
		5983	/* Get the TIMx CR2 register value */
		5984	tmpcr2 = TIMx->CR2;
		5985
		5986	/* Get the TIMx CCMR1 register value */
		5987	tmpccmrx = TIMx->CCMR1;
		5988
		5989	/* Reset the Output Compare Mode Bits */
		5990	tmpccmrx &= ~TIM_CCMR1_OC1M;
		5991	tmpccmrx &= ~TIM_CCMR1_CC1S;
		5992	/* Select the Output Compare Mode */
		5993	tmpccmrx \|= OC_Config->OCMode;
		5994
		5995	/* Reset the Output Polarity level */
		5996	tmpccer &= ~TIM_CCER_CC1P;
		5997	/* Set the Output Compare Polarity */
		5998	tmpccer \|= OC_Config->OCPolarity;
		5999
		6000	if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
		6001	{
		6002	/* Check parameters */
		6003	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		6004
		6005	/* Reset the Output N Polarity level */
		6006	tmpccer &= ~TIM_CCER_CC1NP;
		6007	/* Set the Output N Polarity */
		6008	tmpccer \|= OC_Config->OCNPolarity;
		6009	/* Reset the Output N State */
		6010	tmpccer &= ~TIM_CCER_CC1NE;
		6011	}
		6012
		6013	if (IS_TIM_BREAK_INSTANCE(TIMx))
		6014	{
		6015	/* Check parameters */
		6016	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		6017	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		6018
		6019	/* Reset the Output Compare and Output Compare N IDLE State */
		6020	tmpcr2 &= ~TIM_CR2_OIS1;
		6021	tmpcr2 &= ~TIM_CR2_OIS1N;
		6022	/* Set the Output Idle state */
		6023	tmpcr2 \|= OC_Config->OCIdleState;
		6024	/* Set the Output N Idle state */
		6025	tmpcr2 \|= OC_Config->OCNIdleState;
		6026	}
		6027
		6028	/* Write to TIMx CR2 */
		6029	TIMx->CR2 = tmpcr2;
		6030
		6031	/* Write to TIMx CCMR1 */
		6032	TIMx->CCMR1 = tmpccmrx;
		6033
		6034	/* Set the Capture Compare Register value */
		6035	TIMx->CCR1 = OC_Config->Pulse;
		6036
		6037	/* Write to TIMx CCER */
		6038	TIMx->CCER = tmpccer;
		6039	}
		6040
		6041	/**
		6042	* @brief Timer Output Compare 2 configuration
		6043	* @param TIMx to select the TIM peripheral
		6044	* @param OC_Config The ouput configuration structure
		6045	* @retval None
		6046	*/
		6047	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		6048	{
		6049	uint32_t tmpccmrx;
		6050	uint32_t tmpccer;
		6051	uint32_t tmpcr2;
		6052
		6053	/* Disable the Channel 2: Reset the CC2E Bit */
		6054	TIMx->CCER &= ~TIM_CCER_CC2E;
		6055
		6056	/* Get the TIMx CCER register value */
		6057	tmpccer = TIMx->CCER;
		6058	/* Get the TIMx CR2 register value */
		6059	tmpcr2 = TIMx->CR2;
		6060
		6061	/* Get the TIMx CCMR1 register value */
		6062	tmpccmrx = TIMx->CCMR1;
		6063
		6064	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		6065	tmpccmrx &= ~TIM_CCMR1_OC2M;
		6066	tmpccmrx &= ~TIM_CCMR1_CC2S;
		6067
		6068	/* Select the Output Compare Mode */
		6069	tmpccmrx \|= (OC_Config->OCMode << 8U);
		6070
		6071	/* Reset the Output Polarity level */
		6072	tmpccer &= ~TIM_CCER_CC2P;
		6073	/* Set the Output Compare Polarity */
		6074	tmpccer \|= (OC_Config->OCPolarity << 4U);
		6075
		6076	if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
		6077	{
		6078	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		6079
		6080	/* Reset the Output N Polarity level */
		6081	tmpccer &= ~TIM_CCER_CC2NP;
		6082	/* Set the Output N Polarity */
		6083	tmpccer \|= (OC_Config->OCNPolarity << 4U);
		6084	/* Reset the Output N State */
		6085	tmpccer &= ~TIM_CCER_CC2NE;
		6086
		6087	}
		6088
		6089	if (IS_TIM_BREAK_INSTANCE(TIMx))
		6090	{
		6091	/* Check parameters */
		6092	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		6093	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		6094
		6095	/* Reset the Output Compare and Output Compare N IDLE State */
		6096	tmpcr2 &= ~TIM_CR2_OIS2;
		6097	tmpcr2 &= ~TIM_CR2_OIS2N;
		6098	/* Set the Output Idle state */
		6099	tmpcr2 \|= (OC_Config->OCIdleState << 2U);
		6100	/* Set the Output N Idle state */
		6101	tmpcr2 \|= (OC_Config->OCNIdleState << 2U);
		6102	}
		6103
		6104	/* Write to TIMx CR2 */
		6105	TIMx->CR2 = tmpcr2;
		6106
		6107	/* Write to TIMx CCMR1 */
		6108	TIMx->CCMR1 = tmpccmrx;
		6109
		6110	/* Set the Capture Compare Register value */
		6111	TIMx->CCR2 = OC_Config->Pulse;
		6112
		6113	/* Write to TIMx CCER */
		6114	TIMx->CCER = tmpccer;
		6115	}
		6116
		6117	/**
		6118	* @brief Timer Output Compare 3 configuration
		6119	* @param TIMx to select the TIM peripheral
		6120	* @param OC_Config The ouput configuration structure
		6121	* @retval None
		6122	*/
		6123	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		6124	{
		6125	uint32_t tmpccmrx;
		6126	uint32_t tmpccer;
		6127	uint32_t tmpcr2;
		6128
		6129	/* Disable the Channel 3: Reset the CC2E Bit */
		6130	TIMx->CCER &= ~TIM_CCER_CC3E;
		6131
		6132	/* Get the TIMx CCER register value */
		6133	tmpccer = TIMx->CCER;
		6134	/* Get the TIMx CR2 register value */
		6135	tmpcr2 = TIMx->CR2;
		6136
		6137	/* Get the TIMx CCMR2 register value */
		6138	tmpccmrx = TIMx->CCMR2;
		6139
		6140	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		6141	tmpccmrx &= ~TIM_CCMR2_OC3M;
		6142	tmpccmrx &= ~TIM_CCMR2_CC3S;
		6143	/* Select the Output Compare Mode */
		6144	tmpccmrx \|= OC_Config->OCMode;
		6145
		6146	/* Reset the Output Polarity level */
		6147	tmpccer &= ~TIM_CCER_CC3P;
		6148	/* Set the Output Compare Polarity */
		6149	tmpccer \|= (OC_Config->OCPolarity << 8U);
		6150
		6151	if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
		6152	{
		6153	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
		6154
		6155	/* Reset the Output N Polarity level */
		6156	tmpccer &= ~TIM_CCER_CC3NP;
		6157	/* Set the Output N Polarity */
		6158	tmpccer \|= (OC_Config->OCNPolarity << 8U);
		6159	/* Reset the Output N State */
		6160	tmpccer &= ~TIM_CCER_CC3NE;
		6161	}
		6162
		6163	if (IS_TIM_BREAK_INSTANCE(TIMx))
		6164	{
		6165	/* Check parameters */
		6166	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
		6167	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		6168
		6169	/* Reset the Output Compare and Output Compare N IDLE State */
		6170	tmpcr2 &= ~TIM_CR2_OIS3;
		6171	tmpcr2 &= ~TIM_CR2_OIS3N;
		6172	/* Set the Output Idle state */
		6173	tmpcr2 \|= (OC_Config->OCIdleState << 4U);
		6174	/* Set the Output N Idle state */
		6175	tmpcr2 \|= (OC_Config->OCNIdleState << 4U);
		6176	}
		6177
		6178	/* Write to TIMx CR2 */
		6179	TIMx->CR2 = tmpcr2;
		6180
		6181	/* Write to TIMx CCMR2 */
		6182	TIMx->CCMR2 = tmpccmrx;
		6183
		6184	/* Set the Capture Compare Register value */
		6185	TIMx->CCR3 = OC_Config->Pulse;
		6186
		6187	/* Write to TIMx CCER */
		6188	TIMx->CCER = tmpccer;
		6189	}
		6190
		6191	/**
		6192	* @brief Timer Output Compare 4 configuration
		6193	* @param TIMx to select the TIM peripheral
		6194	* @param OC_Config The ouput configuration structure
		6195	* @retval None
		6196	*/
		6197	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
		6198	{
		6199	uint32_t tmpccmrx;
		6200	uint32_t tmpccer;
		6201	uint32_t tmpcr2;
		6202
		6203	/* Disable the Channel 4: Reset the CC4E Bit */
		6204	TIMx->CCER &= ~TIM_CCER_CC4E;
		6205
		6206	/* Get the TIMx CCER register value */
		6207	tmpccer = TIMx->CCER;
		6208	/* Get the TIMx CR2 register value */
		6209	tmpcr2 = TIMx->CR2;
		6210
		6211	/* Get the TIMx CCMR2 register value */
		6212	tmpccmrx = TIMx->CCMR2;
		6213
		6214	/* Reset the Output Compare mode and Capture/Compare selection Bits */
		6215	tmpccmrx &= ~TIM_CCMR2_OC4M;
		6216	tmpccmrx &= ~TIM_CCMR2_CC4S;
		6217
		6218	/* Select the Output Compare Mode */
		6219	tmpccmrx \|= (OC_Config->OCMode << 8U);
		6220
		6221	/* Reset the Output Polarity level */
		6222	tmpccer &= ~TIM_CCER_CC4P;
		6223	/* Set the Output Compare Polarity */
		6224	tmpccer \|= (OC_Config->OCPolarity << 12U);
		6225
		6226	if (IS_TIM_BREAK_INSTANCE(TIMx))
		6227	{
		6228	/* Check parameters */
		6229	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
		6230
		6231	/* Reset the Output Compare IDLE State */
		6232	tmpcr2 &= ~TIM_CR2_OIS4;
		6233
		6234	/* Set the Output Idle state */
		6235	tmpcr2 \|= (OC_Config->OCIdleState << 6U);
		6236	}
		6237
		6238	/* Write to TIMx CR2 */
		6239	TIMx->CR2 = tmpcr2;
		6240
		6241	/* Write to TIMx CCMR2 */
		6242	TIMx->CCMR2 = tmpccmrx;
		6243
		6244	/* Set the Capture Compare Register value */
		6245	TIMx->CCR4 = OC_Config->Pulse;
		6246
		6247	/* Write to TIMx CCER */
		6248	TIMx->CCER = tmpccer;
		6249	}
		6250
		6251	/**
		6252	* @brief Slave Timer configuration function
		6253	* @param htim TIM handle
		6254	* @param sSlaveConfig Slave timer configuration
		6255	* @retval None
		6256	*/
		6257	static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
		6258	TIM_SlaveConfigTypeDef *sSlaveConfig)
		6259	{
		6260	uint32_t tmpsmcr;
		6261	uint32_t tmpccmr1;
		6262	uint32_t tmpccer;
		6263
		6264	/* Get the TIMx SMCR register value */
		6265	tmpsmcr = htim->Instance->SMCR;
		6266
		6267	/* Reset the Trigger Selection Bits */
		6268	tmpsmcr &= ~TIM_SMCR_TS;
		6269	/* Set the Input Trigger source */
		6270	tmpsmcr \|= sSlaveConfig->InputTrigger;
		6271
		6272	/* Reset the slave mode Bits */
		6273	tmpsmcr &= ~TIM_SMCR_SMS;
		6274	/* Set the slave mode */
		6275	tmpsmcr \|= sSlaveConfig->SlaveMode;
		6276
		6277	/* Write to TIMx SMCR */
		6278	htim->Instance->SMCR = tmpsmcr;
		6279
		6280	/* Configure the trigger prescaler, filter, and polarity */
		6281	switch (sSlaveConfig->InputTrigger)
		6282	{
		6283	case TIM_TS_ETRF:
		6284	{
		6285	/* Check the parameters */
		6286	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
		6287	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
		6288	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		6289	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6290	/* Configure the ETR Trigger source */
		6291	TIM_ETR_SetConfig(htim->Instance,
		6292	sSlaveConfig->TriggerPrescaler,
		6293	sSlaveConfig->TriggerPolarity,
		6294	sSlaveConfig->TriggerFilter);
		6295	break;
		6296	}
		6297
		6298	case TIM_TS_TI1F_ED:
		6299	{
		6300	/* Check the parameters */
		6301	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		6302	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6303
		6304	if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
		6305	{
		6306	return HAL_ERROR;
		6307	}
		6308
		6309	/* Disable the Channel 1: Reset the CC1E Bit */
		6310	tmpccer = htim->Instance->CCER;
		6311	htim->Instance->CCER &= ~TIM_CCER_CC1E;
		6312	tmpccmr1 = htim->Instance->CCMR1;
		6313
		6314	/* Set the filter */
		6315	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		6316	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4U);
		6317
		6318	/* Write to TIMx CCMR1 and CCER registers */
		6319	htim->Instance->CCMR1 = tmpccmr1;
		6320	htim->Instance->CCER = tmpccer;
		6321	break;
		6322	}
		6323
		6324	case TIM_TS_TI1FP1:
		6325	{
		6326	/* Check the parameters */
		6327	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
		6328	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		6329	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6330
		6331	/* Configure TI1 Filter and Polarity */
		6332	TIM_TI1_ConfigInputStage(htim->Instance,
		6333	sSlaveConfig->TriggerPolarity,
		6334	sSlaveConfig->TriggerFilter);
		6335	break;
		6336	}
		6337
		6338	case TIM_TS_TI2FP2:
		6339	{
		6340	/* Check the parameters */
		6341	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		6342	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
		6343	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
		6344
		6345	/* Configure TI2 Filter and Polarity */
		6346	TIM_TI2_ConfigInputStage(htim->Instance,
		6347	sSlaveConfig->TriggerPolarity,
		6348	sSlaveConfig->TriggerFilter);
		6349	break;
		6350	}
		6351
		6352	case TIM_TS_ITR0:
		6353	case TIM_TS_ITR1:
		6354	case TIM_TS_ITR2:
		6355	case TIM_TS_ITR3:
		6356	{
		6357	/* Check the parameter */
		6358	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
		6359	break;
		6360	}
		6361
		6362	default:
		6363	break;
		6364	}
		6365	return HAL_OK;
		6366	}
		6367
		6368	/**
		6369	* @brief Configure the TI1 as Input.
		6370	* @param TIMx to select the TIM peripheral.
		6371	* @param TIM_ICPolarity The Input Polarity.
		6372	* This parameter can be one of the following values:
		6373	* @arg TIM_ICPOLARITY_RISING
		6374	* @arg TIM_ICPOLARITY_FALLING
		6375	* @arg TIM_ICPOLARITY_BOTHEDGE
		6376	* @param TIM_ICSelection specifies the input to be used.
		6377	* This parameter can be one of the following values:
		6378	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
		6379	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
		6380	* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
		6381	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6382	* This parameter must be a value between 0x00 and 0x0F.
		6383	* @retval None
		6384	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
		6385	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
		6386	* protected against un-initialized filter and polarity values.
		6387	*/
		6388	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6389	uint32_t TIM_ICFilter)
		6390	{
		6391	uint32_t tmpccmr1;
		6392	uint32_t tmpccer;
		6393
		6394	/* Disable the Channel 1: Reset the CC1E Bit */
		6395	TIMx->CCER &= ~TIM_CCER_CC1E;
		6396	tmpccmr1 = TIMx->CCMR1;
		6397	tmpccer = TIMx->CCER;
		6398
		6399	/* Select the Input */
		6400	if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
		6401	{
		6402	tmpccmr1 &= ~TIM_CCMR1_CC1S;
		6403	tmpccmr1 \|= TIM_ICSelection;
		6404	}
		6405	else
		6406	{
		6407	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
		6408	}
		6409
		6410	/* Set the filter */
		6411	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		6412	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
		6413
		6414	/* Select the Polarity and set the CC1E Bit */
		6415	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
		6416	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
		6417
		6418	/* Write to TIMx CCMR1 and CCER registers */
		6419	TIMx->CCMR1 = tmpccmr1;
		6420	TIMx->CCER = tmpccer;
		6421	}
		6422
		6423	/**
		6424	* @brief Configure the Polarity and Filter for TI1.
		6425	* @param TIMx to select the TIM peripheral.
		6426	* @param TIM_ICPolarity The Input Polarity.
		6427	* This parameter can be one of the following values:
		6428	* @arg TIM_ICPOLARITY_RISING
		6429	* @arg TIM_ICPOLARITY_FALLING
		6430	* @arg TIM_ICPOLARITY_BOTHEDGE
		6431	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6432	* This parameter must be a value between 0x00 and 0x0F.
		6433	* @retval None
		6434	*/
		6435	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
		6436	{
		6437	uint32_t tmpccmr1;
		6438	uint32_t tmpccer;
		6439
		6440	/* Disable the Channel 1: Reset the CC1E Bit */
		6441	tmpccer = TIMx->CCER;
		6442	TIMx->CCER &= ~TIM_CCER_CC1E;
		6443	tmpccmr1 = TIMx->CCMR1;
		6444
		6445	/* Set the filter */
		6446	tmpccmr1 &= ~TIM_CCMR1_IC1F;
		6447	tmpccmr1 \|= (TIM_ICFilter << 4U);
		6448
		6449	/* Select the Polarity and set the CC1E Bit */
		6450	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
		6451	tmpccer \|= TIM_ICPolarity;
		6452
		6453	/* Write to TIMx CCMR1 and CCER registers */
		6454	TIMx->CCMR1 = tmpccmr1;
		6455	TIMx->CCER = tmpccer;
		6456	}
		6457
		6458	/**
		6459	* @brief Configure the TI2 as Input.
		6460	* @param TIMx to select the TIM peripheral
		6461	* @param TIM_ICPolarity The Input Polarity.
		6462	* This parameter can be one of the following values:
		6463	* @arg TIM_ICPOLARITY_RISING
		6464	* @arg TIM_ICPOLARITY_FALLING
		6465	* @arg TIM_ICPOLARITY_BOTHEDGE
		6466	* @param TIM_ICSelection specifies the input to be used.
		6467	* This parameter can be one of the following values:
		6468	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
		6469	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
		6470	* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
		6471	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6472	* This parameter must be a value between 0x00 and 0x0F.
		6473	* @retval None
		6474	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
		6475	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
		6476	* protected against un-initialized filter and polarity values.
		6477	*/
		6478	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6479	uint32_t TIM_ICFilter)
		6480	{
		6481	uint32_t tmpccmr1;
		6482	uint32_t tmpccer;
		6483
		6484	/* Disable the Channel 2: Reset the CC2E Bit */
		6485	TIMx->CCER &= ~TIM_CCER_CC2E;
		6486	tmpccmr1 = TIMx->CCMR1;
		6487	tmpccer = TIMx->CCER;
		6488
		6489	/* Select the Input */
		6490	tmpccmr1 &= ~TIM_CCMR1_CC2S;
		6491	tmpccmr1 \|= (TIM_ICSelection << 8U);
		6492
		6493	/* Set the filter */
		6494	tmpccmr1 &= ~TIM_CCMR1_IC2F;
		6495	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
		6496
		6497	/* Select the Polarity and set the CC2E Bit */
		6498	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
		6499	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
		6500
		6501	/* Write to TIMx CCMR1 and CCER registers */
		6502	TIMx->CCMR1 = tmpccmr1 ;
		6503	TIMx->CCER = tmpccer;
		6504	}
		6505
		6506	/**
		6507	* @brief Configure the Polarity and Filter for TI2.
		6508	* @param TIMx to select the TIM peripheral.
		6509	* @param TIM_ICPolarity The Input Polarity.
		6510	* This parameter can be one of the following values:
		6511	* @arg TIM_ICPOLARITY_RISING
		6512	* @arg TIM_ICPOLARITY_FALLING
		6513	* @arg TIM_ICPOLARITY_BOTHEDGE
		6514	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6515	* This parameter must be a value between 0x00 and 0x0F.
		6516	* @retval None
		6517	*/
		6518	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
		6519	{
		6520	uint32_t tmpccmr1;
		6521	uint32_t tmpccer;
		6522
		6523	/* Disable the Channel 2: Reset the CC2E Bit */
		6524	TIMx->CCER &= ~TIM_CCER_CC2E;
		6525	tmpccmr1 = TIMx->CCMR1;
		6526	tmpccer = TIMx->CCER;
		6527
		6528	/* Set the filter */
		6529	tmpccmr1 &= ~TIM_CCMR1_IC2F;
		6530	tmpccmr1 \|= (TIM_ICFilter << 12U);
		6531
		6532	/* Select the Polarity and set the CC2E Bit */
		6533	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
		6534	tmpccer \|= (TIM_ICPolarity << 4U);
		6535
		6536	/* Write to TIMx CCMR1 and CCER registers */
		6537	TIMx->CCMR1 = tmpccmr1 ;
		6538	TIMx->CCER = tmpccer;
		6539	}
		6540
		6541	/**
		6542	* @brief Configure the TI3 as Input.
		6543	* @param TIMx to select the TIM peripheral
		6544	* @param TIM_ICPolarity The Input Polarity.
		6545	* This parameter can be one of the following values:
		6546	* @arg TIM_ICPOLARITY_RISING
		6547	* @arg TIM_ICPOLARITY_FALLING
		6548	* @arg TIM_ICPOLARITY_BOTHEDGE
		6549	* @param TIM_ICSelection specifies the input to be used.
		6550	* This parameter can be one of the following values:
		6551	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
		6552	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
		6553	* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
		6554	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6555	* This parameter must be a value between 0x00 and 0x0F.
		6556	* @retval None
		6557	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
		6558	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
		6559	* protected against un-initialized filter and polarity values.
		6560	*/
		6561	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6562	uint32_t TIM_ICFilter)
		6563	{
		6564	uint32_t tmpccmr2;
		6565	uint32_t tmpccer;
		6566
		6567	/* Disable the Channel 3: Reset the CC3E Bit */
		6568	TIMx->CCER &= ~TIM_CCER_CC3E;
		6569	tmpccmr2 = TIMx->CCMR2;
		6570	tmpccer = TIMx->CCER;
		6571
		6572	/* Select the Input */
		6573	tmpccmr2 &= ~TIM_CCMR2_CC3S;
		6574	tmpccmr2 \|= TIM_ICSelection;
		6575
		6576	/* Set the filter */
		6577	tmpccmr2 &= ~TIM_CCMR2_IC3F;
		6578	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
		6579
		6580	/* Select the Polarity and set the CC3E Bit */
		6581	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
		6582	tmpccer \|= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
		6583
		6584	/* Write to TIMx CCMR2 and CCER registers */
		6585	TIMx->CCMR2 = tmpccmr2;
		6586	TIMx->CCER = tmpccer;
		6587	}
		6588
		6589	/**
		6590	* @brief Configure the TI4 as Input.
		6591	* @param TIMx to select the TIM peripheral
		6592	* @param TIM_ICPolarity The Input Polarity.
		6593	* This parameter can be one of the following values:
		6594	* @arg TIM_ICPOLARITY_RISING
		6595	* @arg TIM_ICPOLARITY_FALLING
		6596	* @arg TIM_ICPOLARITY_BOTHEDGE
		6597	* @param TIM_ICSelection specifies the input to be used.
		6598	* This parameter can be one of the following values:
		6599	* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
		6600	* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
		6601	* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
		6602	* @param TIM_ICFilter Specifies the Input Capture Filter.
		6603	* This parameter must be a value between 0x00 and 0x0F.
		6604	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
		6605	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
		6606	* protected against un-initialized filter and polarity values.
		6607	* @retval None
		6608	*/
		6609	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
		6610	uint32_t TIM_ICFilter)
		6611	{
		6612	uint32_t tmpccmr2;
		6613	uint32_t tmpccer;
		6614
		6615	/* Disable the Channel 4: Reset the CC4E Bit */
		6616	TIMx->CCER &= ~TIM_CCER_CC4E;
		6617	tmpccmr2 = TIMx->CCMR2;
		6618	tmpccer = TIMx->CCER;
		6619
		6620	/* Select the Input */
		6621	tmpccmr2 &= ~TIM_CCMR2_CC4S;
		6622	tmpccmr2 \|= (TIM_ICSelection << 8U);
		6623
		6624	/* Set the filter */
		6625	tmpccmr2 &= ~TIM_CCMR2_IC4F;
		6626	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
		6627
		6628	/* Select the Polarity and set the CC4E Bit */
		6629	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
		6630	tmpccer \|= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
		6631
		6632	/* Write to TIMx CCMR2 and CCER registers */
		6633	TIMx->CCMR2 = tmpccmr2;
		6634	TIMx->CCER = tmpccer ;
		6635	}
		6636
		6637	/**
		6638	* @brief Selects the Input Trigger source
		6639	* @param TIMx to select the TIM peripheral
		6640	* @param InputTriggerSource The Input Trigger source.
		6641	* This parameter can be one of the following values:
		6642	* @arg TIM_TS_ITR0: Internal Trigger 0
		6643	* @arg TIM_TS_ITR1: Internal Trigger 1
		6644	* @arg TIM_TS_ITR2: Internal Trigger 2
		6645	* @arg TIM_TS_ITR3: Internal Trigger 3
		6646	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
		6647	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
		6648	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
		6649	* @arg TIM_TS_ETRF: External Trigger input
		6650	* @retval None
		6651	*/
		6652	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
		6653	{
		6654	uint32_t tmpsmcr;
		6655
		6656	/* Get the TIMx SMCR register value */
		6657	tmpsmcr = TIMx->SMCR;
		6658	/* Reset the TS Bits */
		6659	tmpsmcr &= ~TIM_SMCR_TS;
		6660	/* Set the Input Trigger source and the slave mode*/
		6661	tmpsmcr \|= (InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1);
		6662	/* Write to TIMx SMCR */
		6663	TIMx->SMCR = tmpsmcr;
		6664	}
		6665	/**
		6666	* @brief Configures the TIMx External Trigger (ETR).
		6667	* @param TIMx to select the TIM peripheral
		6668	* @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
		6669	* This parameter can be one of the following values:
		6670	* @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
		6671	* @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
		6672	* @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
		6673	* @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
		6674	* @param TIM_ExtTRGPolarity The external Trigger Polarity.
		6675	* This parameter can be one of the following values:
		6676	* @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
		6677	* @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
		6678	* @param ExtTRGFilter External Trigger Filter.
		6679	* This parameter must be a value between 0x00 and 0x0F
		6680	* @retval None
		6681	*/
		6682	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
		6683	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
		6684	{
		6685	uint32_t tmpsmcr;
		6686
		6687	tmpsmcr = TIMx->SMCR;
		6688
		6689	/* Reset the ETR Bits */
		6690	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
		6691
		6692	/* Set the Prescaler, the Filter value and the Polarity */
		6693	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8U)));
		6694
		6695	/* Write to TIMx SMCR */
		6696	TIMx->SMCR = tmpsmcr;
		6697	}
		6698
		6699	/**
		6700	* @brief Enables or disables the TIM Capture Compare Channel x.
		6701	* @param TIMx to select the TIM peripheral
		6702	* @param Channel specifies the TIM Channel
		6703	* This parameter can be one of the following values:
		6704	* @arg TIM_CHANNEL_1: TIM Channel 1
		6705	* @arg TIM_CHANNEL_2: TIM Channel 2
		6706	* @arg TIM_CHANNEL_3: TIM Channel 3
		6707	* @arg TIM_CHANNEL_4: TIM Channel 4
		6708	* @param ChannelState specifies the TIM Channel CCxE bit new state.
		6709	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
		6710	* @retval None
		6711	*/
		6712	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
		6713	{
		6714	uint32_t tmp;
		6715
		6716	/* Check the parameters */
		6717	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
		6718	assert_param(IS_TIM_CHANNELS(Channel));
		6719
		6720	tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
		6721
		6722	/* Reset the CCxE Bit */
		6723	TIMx->CCER &= ~tmp;
		6724
		6725	/* Set or reset the CCxE Bit */
		6726	TIMx->CCER \|= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
		6727	}
		6728
		6729	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		6730	/**
		6731	* @brief Reset interrupt callbacks to the legacy weak callbacks.
		6732	* @param htim pointer to a TIM_HandleTypeDef structure that contains
		6733	* the configuration information for TIM module.
		6734	* @retval None
		6735	*/
		6736	void TIM_ResetCallback(TIM_HandleTypeDef *htim)
		6737	{
		6738	/* Reset the TIM callback to the legacy weak callbacks */
		6739	htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
		6740	htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
		6741	htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
		6742	htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
		6743	htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
		6744	htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
		6745	htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
		6746	htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
		6747	htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
		6748	htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
		6749	htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
		6750	htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
		6751	htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
		6752	}
		6753	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		6754
		6755	/**
		6756	* @}
		6757	*/
		6758
		6759	#endif /* HAL_TIM_MODULE_ENABLED */
		6760	/**
		6761	* @}
		6762	*/
		6763
		6764	/**
		6765	* @}
		6766	*/
		6767	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_tim.c – Rev 2