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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_hal_spi.c
		4	* @author MCD Application Team
		5	* @brief SPI HAL module driver.
		6	* This file provides firmware functions to manage the following
		7	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
		8	* + Initialization and de-initialization functions
		9	* + IO operation functions
		10	* + Peripheral Control functions
		11	* + Peripheral State functions
		12	*
		13	@verbatim
		14	==============================================================================
		15	##### How to use this driver #####
		16	==============================================================================
		17	[..]
		18	The SPI HAL driver can be used as follows:
		19
		20	(#) Declare a SPI_HandleTypeDef handle structure, for example:
		21	SPI_HandleTypeDef hspi;
		22
		23	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
		24	(##) Enable the SPIx interface clock
		25	(##) SPI pins configuration
		26	(+++) Enable the clock for the SPI GPIOs
		27	(+++) Configure these SPI pins as alternate function push-pull
		28	(##) NVIC configuration if you need to use interrupt process
		29	(+++) Configure the SPIx interrupt priority
		30	(+++) Enable the NVIC SPI IRQ handle
		31	(##) DMA Configuration if you need to use DMA process
		32	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
		33	(+++) Enable the DMAx clock
		34	(+++) Configure the DMA handle parameters
		35	(+++) Configure the DMA Tx or Rx Stream/Channel
		36	(+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
		37	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
		38
		39	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
		40	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
		41
		42	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
		43	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
		44	by calling the customized HAL_SPI_MspInit() API.
		45	[..]
		46	Circular mode restriction:
		47	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
		48	(##) Master 2Lines RxOnly
		49	(##) Master 1Line Rx
		50	(#) The CRC feature is not managed when the DMA circular mode is enabled
		51	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
		52	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
		53	[..]
		54	Master Receive mode restriction:
		55	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
		56	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
		57	does not initiate a new transfer the following procedure has to be respected:
		58	(##) HAL_SPI_DeInit()
		59	(##) HAL_SPI_Init()
		60	[..]
		61	Data buffer address alignment restriction:
		62	(#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer.
		63	But there is no support for unaligned accesses on the Cortex-M0 processor.
		64	So, if the user wants to transfer more than 1 byte, it shall ensure that 16-bit aligned address is used for:
		65	(##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT()
		66	(##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
		67	(#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
		68	and HAL_SPI_TransmitReceive_DMA().
		69	[..]
		70	Callback registration:
		71
		72	(#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
		73	allows the user to configure dynamically the driver callbacks.
		74	Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
		75
		76	Function HAL_SPI_RegisterCallback() allows to register following callbacks:
		77	(++) TxCpltCallback : SPI Tx Completed callback
		78	(++) RxCpltCallback : SPI Rx Completed callback
		79	(++) TxRxCpltCallback : SPI TxRx Completed callback
		80	(++) TxHalfCpltCallback : SPI Tx Half Completed callback
		81	(++) RxHalfCpltCallback : SPI Rx Half Completed callback
		82	(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
		83	(++) ErrorCallback : SPI Error callback
		84	(++) AbortCpltCallback : SPI Abort callback
		85	(++) MspInitCallback : SPI Msp Init callback
		86	(++) MspDeInitCallback : SPI Msp DeInit callback
		87	This function takes as parameters the HAL peripheral handle, the Callback ID
		88	and a pointer to the user callback function.
		89
		90
		91	(#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
		92	weak function.
		93	HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
		94	and the Callback ID.
		95	This function allows to reset following callbacks:
		96	(++) TxCpltCallback : SPI Tx Completed callback
		97	(++) RxCpltCallback : SPI Rx Completed callback
		98	(++) TxRxCpltCallback : SPI TxRx Completed callback
		99	(++) TxHalfCpltCallback : SPI Tx Half Completed callback
		100	(++) RxHalfCpltCallback : SPI Rx Half Completed callback
		101	(++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
		102	(++) ErrorCallback : SPI Error callback
		103	(++) AbortCpltCallback : SPI Abort callback
		104	(++) MspInitCallback : SPI Msp Init callback
		105	(++) MspDeInitCallback : SPI Msp DeInit callback
		106
		107	[..]
		108	By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
		109	all callbacks are set to the corresponding weak functions:
		110	examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
		111	Exception done for MspInit and MspDeInit functions that are
		112	reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
		113	these callbacks are null (not registered beforehand).
		114	If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
		115	keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
		116
		117	[..]
		118	Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
		119	Exception done MspInit/MspDeInit functions that can be registered/unregistered
		120	in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
		121	thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
		122	Then, the user first registers the MspInit/MspDeInit user callbacks
		123	using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
		124	or HAL_SPI_Init() function.
		125
		126	[..]
		127	When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
		128	not defined, the callback registering feature is not available
		129	and weak (surcharged) callbacks are used.
		130
		131	[..]
		132	Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
		133	the following table resume the max SPI frequency reached with data size 8bits/16bits,
		134	according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
		135
		136	@endverbatim
		137
		138	Additional table :
		139
		140	DataSize = SPI_DATASIZE_8BIT:
		141	+----------------------------------------------------------------------------------------------+
		142	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		143	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
		144	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		145	\|==============================================================================================\|
		146	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
		147	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		148	\| / \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
		149	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		150	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		151	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		152	\| \| Polling \| Fpclk/4 \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
		153	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		154	\| R \| Interrupt \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/4 \|
		155	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		156	\| \| DMA \| Fpclk/4 \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \|
		157	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		158	\| \| Polling \| Fpclk/8 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
		159	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		160	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/16 \| Fpclk/8 \|
		161	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		162	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
		163	+----------------------------------------------------------------------------------------------+
		164
		165	DataSize = SPI_DATASIZE_16BIT:
		166	+----------------------------------------------------------------------------------------------+
		167	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
		168	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
		169	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
		170	\|==============================================================================================\|
		171	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
		172	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		173	\| / \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
		174	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		175	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
		176	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		177	\| \| Polling \| Fpclk/4 \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
		178	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		179	\| R \| Interrupt \| Fpclk/8 \| Fpclk/16 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/4 \|
		180	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		181	\| \| DMA \| Fpclk/4 \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \|
		182	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
		183	\| \| Polling \| Fpclk/8 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
		184	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		185	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/16 \| Fpclk/8 \|
		186	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
		187	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
		188	+----------------------------------------------------------------------------------------------+
		189	@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
		190	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
		191	@note
		192	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
		193	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
		194	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
		195
		196	******************************************************************************
		197	* @attention
		198	*
		199	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		200	* All rights reserved.</center></h2>
		201	*
		202	* This software component is licensed by ST under BSD 3-Clause license,
		203	* the "License"; You may not use this file except in compliance with the
		204	* License. You may obtain a copy of the License at:
		205	* opensource.org/licenses/BSD-3-Clause
		206	*
		207	******************************************************************************
		208	*/
		209
		210	/* Includes ------------------------------------------------------------------*/
		211	#include "stm32f0xx_hal.h"
		212
		213	/** @addtogroup STM32F0xx_HAL_Driver
		214	* @{
		215	*/
		216
		217	/** @defgroup SPI SPI
		218	* @brief SPI HAL module driver
		219	* @{
		220	*/
		221	#ifdef HAL_SPI_MODULE_ENABLED
		222
		223	/* Private typedef -----------------------------------------------------------*/
		224	/* Private defines -----------------------------------------------------------*/
		225	/** @defgroup SPI_Private_Constants SPI Private Constants
		226	* @{
		227	*/
		228	#define SPI_DEFAULT_TIMEOUT 100U
		229	/**
		230	* @}
		231	*/
		232
		233	/* Private macros ------------------------------------------------------------*/
		234	/* Private variables ---------------------------------------------------------*/
		235	/* Private function prototypes -----------------------------------------------*/
		236	/** @defgroup SPI_Private_Functions SPI Private Functions
		237	* @{
		238	*/
		239	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
		240	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
		241	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		242	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
		243	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
		244	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
		245	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
		246	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
		247	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
		248	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
		249	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
		250	uint32_t Timeout, uint32_t Tickstart);
		251	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
		252	uint32_t Timeout, uint32_t Tickstart);
		253	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		254	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		255	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		256	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		257	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		258	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
		259	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		260	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
		261	#if (USE_SPI_CRC != 0U)
		262	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		263	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		264	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
		265	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
		266	#endif /* USE_SPI_CRC */
		267	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
		268	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
		269	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
		270	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
		271	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
		272	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		273	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
		274	/**
		275	* @}
		276	*/
		277
		278	/* Exported functions --------------------------------------------------------*/
		279	/** @defgroup SPI_Exported_Functions SPI Exported Functions
		280	* @{
		281	*/
		282
		283	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
		284	* @brief Initialization and Configuration functions
		285	*
		286	@verbatim
		287	===============================================================================
		288	##### Initialization and de-initialization functions #####
		289	===============================================================================
		290	[..] This subsection provides a set of functions allowing to initialize and
		291	de-initialize the SPIx peripheral:
		292
		293	(+) User must implement HAL_SPI_MspInit() function in which he configures
		294	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
		295
		296	(+) Call the function HAL_SPI_Init() to configure the selected device with
		297	the selected configuration:
		298	(++) Mode
		299	(++) Direction
		300	(++) Data Size
		301	(++) Clock Polarity and Phase
		302	(++) NSS Management
		303	(++) BaudRate Prescaler
		304	(++) FirstBit
		305	(++) TIMode
		306	(++) CRC Calculation
		307	(++) CRC Polynomial if CRC enabled
		308	(++) CRC Length, used only with Data8 and Data16
		309	(++) FIFO reception threshold
		310
		311	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
		312	of the selected SPIx peripheral.
		313
		314	@endverbatim
		315	* @{
		316	*/
		317
		318	/**
		319	* @brief Initialize the SPI according to the specified parameters
		320	* in the SPI_InitTypeDef and initialize the associated handle.
		321	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		322	* the configuration information for SPI module.
		323	* @retval HAL status
		324	*/
		325	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
		326	{
		327	uint32_t frxth;
		328
		329	/* Check the SPI handle allocation */
		330	if (hspi == NULL)
		331	{
		332	return HAL_ERROR;
		333	}
		334
		335	/* Check the parameters */
		336	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		337	assert_param(IS_SPI_MODE(hspi->Init.Mode));
		338	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
		339	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
		340	assert_param(IS_SPI_NSS(hspi->Init.NSS));
		341	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
		342	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
		343	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
		344	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
		345	if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
		346	{
		347	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
		348	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
		349	}
		350	#if (USE_SPI_CRC != 0U)
		351	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
		352	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		353	{
		354	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
		355	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
		356	}
		357	#else
		358	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
		359	#endif /* USE_SPI_CRC */
		360
		361	if (hspi->State == HAL_SPI_STATE_RESET)
		362	{
		363	/* Allocate lock resource and initialize it */
		364	hspi->Lock = HAL_UNLOCKED;
		365
		366	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		367	/* Init the SPI Callback settings */
		368	hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
		369	hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
		370	hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
		371	hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
		372	hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
		373	hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
		374	hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
		375	hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
		376
		377	if (hspi->MspInitCallback == NULL)
		378	{
		379	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		380	}
		381
		382	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		383	hspi->MspInitCallback(hspi);
		384	#else
		385	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
		386	HAL_SPI_MspInit(hspi);
		387	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		388	}
		389
		390	hspi->State = HAL_SPI_STATE_BUSY;
		391
		392	/* Disable the selected SPI peripheral */
		393	__HAL_SPI_DISABLE(hspi);
		394
		395	/* Align by default the rs fifo threshold on the data size */
		396	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		397	{
		398	frxth = SPI_RXFIFO_THRESHOLD_HF;
		399	}
		400	else
		401	{
		402	frxth = SPI_RXFIFO_THRESHOLD_QF;
		403	}
		404
		405	/* CRC calculation is valid only for 16Bit and 8 Bit */
		406	if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
		407	{
		408	/* CRC must be disabled */
		409	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
		410	}
		411
		412	/* Align the CRC Length on the data size */
		413	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
		414	{
		415	/* CRC Length aligned on the data size : value set by default */
		416	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		417	{
		418	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
		419	}
		420	else
		421	{
		422	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
		423	}
		424	}
		425
		426	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
		427	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
		428	Communication speed, First bit and CRC calculation state */
		429	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \|
		430	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
		431	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation));
		432	#if (USE_SPI_CRC != 0U)
		433	/* Configure : CRC Length */
		434	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
		435	{
		436	hspi->Instance->CR1 \|= SPI_CR1_CRCL;
		437	}
		438	#endif /* USE_SPI_CRC */
		439
		440	/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
		441	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) \| hspi->Init.TIMode \|
		442	hspi->Init.NSSPMode \| hspi->Init.DataSize) \| frxth);
		443
		444	#if (USE_SPI_CRC != 0U)
		445	/---------------------------- SPIx CRCPOLY Configuration ------------------/
		446	/* Configure : CRC Polynomial */
		447	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		448	{
		449	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
		450	}
		451	#endif /* USE_SPI_CRC */
		452
		453	#if defined(SPI_I2SCFGR_I2SMOD)
		454	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
		455	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
		456	#endif /* SPI_I2SCFGR_I2SMOD */
		457
		458	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		459	hspi->State = HAL_SPI_STATE_READY;
		460
		461	return HAL_OK;
		462	}
		463
		464	/**
		465	* @brief De-Initialize the SPI peripheral.
		466	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		467	* the configuration information for SPI module.
		468	* @retval HAL status
		469	*/
		470	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
		471	{
		472	/* Check the SPI handle allocation */
		473	if (hspi == NULL)
		474	{
		475	return HAL_ERROR;
		476	}
		477
		478	/* Check SPI Instance parameter */
		479	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
		480
		481	hspi->State = HAL_SPI_STATE_BUSY;
		482
		483	/* Disable the SPI Peripheral Clock */
		484	__HAL_SPI_DISABLE(hspi);
		485
		486	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		487	if (hspi->MspDeInitCallback == NULL)
		488	{
		489	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		490	}
		491
		492	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		493	hspi->MspDeInitCallback(hspi);
		494	#else
		495	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
		496	HAL_SPI_MspDeInit(hspi);
		497	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		498
		499	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		500	hspi->State = HAL_SPI_STATE_RESET;
		501
		502	/* Release Lock */
		503	__HAL_UNLOCK(hspi);
		504
		505	return HAL_OK;
		506	}
		507
		508	/**
		509	* @brief Initialize the SPI MSP.
		510	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		511	* the configuration information for SPI module.
		512	* @retval None
		513	*/
		514	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
		515	{
		516	/* Prevent unused argument(s) compilation warning */
		517	UNUSED(hspi);
		518
		519	/* NOTE : This function should not be modified, when the callback is needed,
		520	the HAL_SPI_MspInit should be implemented in the user file
		521	*/
		522	}
		523
		524	/**
		525	* @brief De-Initialize the SPI MSP.
		526	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		527	* the configuration information for SPI module.
		528	* @retval None
		529	*/
		530	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
		531	{
		532	/* Prevent unused argument(s) compilation warning */
		533	UNUSED(hspi);
		534
		535	/* NOTE : This function should not be modified, when the callback is needed,
		536	the HAL_SPI_MspDeInit should be implemented in the user file
		537	*/
		538	}
		539
		540	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		541	/**
		542	* @brief Register a User SPI Callback
		543	* To be used instead of the weak predefined callback
		544	* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
		545	* the configuration information for the specified SPI.
		546	* @param CallbackID ID of the callback to be registered
		547	* @param pCallback pointer to the Callback function
		548	* @retval HAL status
		549	*/
		550	HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
		551	pSPI_CallbackTypeDef pCallback)
		552	{
		553	HAL_StatusTypeDef status = HAL_OK;
		554
		555	if (pCallback == NULL)
		556	{
		557	/* Update the error code */
		558	hspi->ErrorCode \|= HAL_SPI_ERROR_INVALID_CALLBACK;
		559
		560	return HAL_ERROR;
		561	}
		562	/* Process locked */
		563	__HAL_LOCK(hspi);
		564
		565	if (HAL_SPI_STATE_READY == hspi->State)
		566	{
		567	switch (CallbackID)
		568	{
		569	case HAL_SPI_TX_COMPLETE_CB_ID :
		570	hspi->TxCpltCallback = pCallback;
		571	break;
		572
		573	case HAL_SPI_RX_COMPLETE_CB_ID :
		574	hspi->RxCpltCallback = pCallback;
		575	break;
		576
		577	case HAL_SPI_TX_RX_COMPLETE_CB_ID :
		578	hspi->TxRxCpltCallback = pCallback;
		579	break;
		580
		581	case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
		582	hspi->TxHalfCpltCallback = pCallback;
		583	break;
		584
		585	case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
		586	hspi->RxHalfCpltCallback = pCallback;
		587	break;
		588
		589	case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
		590	hspi->TxRxHalfCpltCallback = pCallback;
		591	break;
		592
		593	case HAL_SPI_ERROR_CB_ID :
		594	hspi->ErrorCallback = pCallback;
		595	break;
		596
		597	case HAL_SPI_ABORT_CB_ID :
		598	hspi->AbortCpltCallback = pCallback;
		599	break;
		600
		601	case HAL_SPI_MSPINIT_CB_ID :
		602	hspi->MspInitCallback = pCallback;
		603	break;
		604
		605	case HAL_SPI_MSPDEINIT_CB_ID :
		606	hspi->MspDeInitCallback = pCallback;
		607	break;
		608
		609	default :
		610	/* Update the error code */
		611	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		612
		613	/* Return error status */
		614	status = HAL_ERROR;
		615	break;
		616	}
		617	}
		618	else if (HAL_SPI_STATE_RESET == hspi->State)
		619	{
		620	switch (CallbackID)
		621	{
		622	case HAL_SPI_MSPINIT_CB_ID :
		623	hspi->MspInitCallback = pCallback;
		624	break;
		625
		626	case HAL_SPI_MSPDEINIT_CB_ID :
		627	hspi->MspDeInitCallback = pCallback;
		628	break;
		629
		630	default :
		631	/* Update the error code */
		632	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		633
		634	/* Return error status */
		635	status = HAL_ERROR;
		636	break;
		637	}
		638	}
		639	else
		640	{
		641	/* Update the error code */
		642	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		643
		644	/* Return error status */
		645	status = HAL_ERROR;
		646	}
		647
		648	/* Release Lock */
		649	__HAL_UNLOCK(hspi);
		650	return status;
		651	}
		652
		653	/**
		654	* @brief Unregister an SPI Callback
		655	* SPI callback is redirected to the weak predefined callback
		656	* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
		657	* the configuration information for the specified SPI.
		658	* @param CallbackID ID of the callback to be unregistered
		659	* @retval HAL status
		660	*/
		661	HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
		662	{
		663	HAL_StatusTypeDef status = HAL_OK;
		664
		665	/* Process locked */
		666	__HAL_LOCK(hspi);
		667
		668	if (HAL_SPI_STATE_READY == hspi->State)
		669	{
		670	switch (CallbackID)
		671	{
		672	case HAL_SPI_TX_COMPLETE_CB_ID :
		673	hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
		674	break;
		675
		676	case HAL_SPI_RX_COMPLETE_CB_ID :
		677	hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
		678	break;
		679
		680	case HAL_SPI_TX_RX_COMPLETE_CB_ID :
		681	hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
		682	break;
		683
		684	case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
		685	hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
		686	break;
		687
		688	case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
		689	hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
		690	break;
		691
		692	case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
		693	hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
		694	break;
		695
		696	case HAL_SPI_ERROR_CB_ID :
		697	hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
		698	break;
		699
		700	case HAL_SPI_ABORT_CB_ID :
		701	hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
		702	break;
		703
		704	case HAL_SPI_MSPINIT_CB_ID :
		705	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		706	break;
		707
		708	case HAL_SPI_MSPDEINIT_CB_ID :
		709	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		710	break;
		711
		712	default :
		713	/* Update the error code */
		714	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		715
		716	/* Return error status */
		717	status = HAL_ERROR;
		718	break;
		719	}
		720	}
		721	else if (HAL_SPI_STATE_RESET == hspi->State)
		722	{
		723	switch (CallbackID)
		724	{
		725	case HAL_SPI_MSPINIT_CB_ID :
		726	hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
		727	break;
		728
		729	case HAL_SPI_MSPDEINIT_CB_ID :
		730	hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
		731	break;
		732
		733	default :
		734	/* Update the error code */
		735	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		736
		737	/* Return error status */
		738	status = HAL_ERROR;
		739	break;
		740	}
		741	}
		742	else
		743	{
		744	/* Update the error code */
		745	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
		746
		747	/* Return error status */
		748	status = HAL_ERROR;
		749	}
		750
		751	/* Release Lock */
		752	__HAL_UNLOCK(hspi);
		753	return status;
		754	}
		755	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		756	/**
		757	* @}
		758	*/
		759
		760	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
		761	* @brief Data transfers functions
		762	*
		763	@verbatim
		764	==============================================================================
		765	##### IO operation functions #####
		766	===============================================================================
		767	[..]
		768	This subsection provides a set of functions allowing to manage the SPI
		769	data transfers.
		770
		771	[..] The SPI supports master and slave mode :
		772
		773	(#) There are two modes of transfer:
		774	(++) Blocking mode: The communication is performed in polling mode.
		775	The HAL status of all data processing is returned by the same function
		776	after finishing transfer.
		777	(++) No-Blocking mode: The communication is performed using Interrupts
		778	or DMA, These APIs return the HAL status.
		779	The end of the data processing will be indicated through the
		780	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
		781	using DMA mode.
		782	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
		783	will be executed respectively at the end of the transmit or Receive process
		784	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
		785
		786	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
		787	exist for 1Line (simplex) and 2Lines (full duplex) modes.
		788
		789	@endverbatim
		790	* @{
		791	*/
		792
		793	/**
		794	* @brief Transmit an amount of data in blocking mode.
		795	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		796	* the configuration information for SPI module.
		797	* @param pData pointer to data buffer
		798	* @param Size amount of data to be sent
		799	* @param Timeout Timeout duration
		800	* @retval HAL status
		801	*/
		802	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		803	{
		804	uint32_t tickstart;
		805	HAL_StatusTypeDef errorcode = HAL_OK;
		806	uint16_t initial_TxXferCount;
		807
		808	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
		809	{
		810	/* in this case, 16-bit access is performed on Data
		811	So, check Data is 16-bit aligned address */
		812	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
		813	}
		814
		815	/* Check Direction parameter */
		816	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		817
		818	/* Process Locked */
		819	__HAL_LOCK(hspi);
		820
		821	/* Init tickstart for timeout management*/
		822	tickstart = HAL_GetTick();
		823	initial_TxXferCount = Size;
		824
		825	if (hspi->State != HAL_SPI_STATE_READY)
		826	{
		827	errorcode = HAL_BUSY;
		828	goto error;
		829	}
		830
		831	if ((pData == NULL) \|\| (Size == 0U))
		832	{
		833	errorcode = HAL_ERROR;
		834	goto error;
		835	}
		836
		837	/* Set the transaction information */
		838	hspi->State = HAL_SPI_STATE_BUSY_TX;
		839	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		840	hspi->pTxBuffPtr = (uint8_t *)pData;
		841	hspi->TxXferSize = Size;
		842	hspi->TxXferCount = Size;
		843
		844	/Init field not used in handle to zero /
		845	hspi->pRxBuffPtr = (uint8_t *)NULL;
		846	hspi->RxXferSize = 0U;
		847	hspi->RxXferCount = 0U;
		848	hspi->TxISR = NULL;
		849	hspi->RxISR = NULL;
		850
		851	/* Configure communication direction : 1Line */
		852	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		853	{
		854	SPI_1LINE_TX(hspi);
		855	}
		856
		857	#if (USE_SPI_CRC != 0U)
		858	/* Reset CRC Calculation */
		859	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		860	{
		861	SPI_RESET_CRC(hspi);
		862	}
		863	#endif /* USE_SPI_CRC */
		864
		865	/* Check if the SPI is already enabled */
		866	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		867	{
		868	/* Enable SPI peripheral */
		869	__HAL_SPI_ENABLE(hspi);
		870	}
		871
		872	/* Transmit data in 16 Bit mode */
		873	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		874	{
		875	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		876	{
		877	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		878	hspi->pTxBuffPtr += sizeof(uint16_t);
		879	hspi->TxXferCount--;
		880	}
		881	/* Transmit data in 16 Bit mode */
		882	while (hspi->TxXferCount > 0U)
		883	{
		884	/* Wait until TXE flag is set to send data */
		885	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		886	{
		887	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		888	hspi->pTxBuffPtr += sizeof(uint16_t);
		889	hspi->TxXferCount--;
		890	}
		891	else
		892	{
		893	/* Timeout management */
		894	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		895	{
		896	errorcode = HAL_TIMEOUT;
		897	goto error;
		898	}
		899	}
		900	}
		901	}
		902	/* Transmit data in 8 Bit mode */
		903	else
		904	{
		905	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		906	{
		907	if (hspi->TxXferCount > 1U)
		908	{
		909	/* write on the data register in packing mode */
		910	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		911	hspi->pTxBuffPtr += sizeof(uint16_t);
		912	hspi->TxXferCount -= 2U;
		913	}
		914	else
		915	{
		916	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		917	hspi->pTxBuffPtr ++;
		918	hspi->TxXferCount--;
		919	}
		920	}
		921	while (hspi->TxXferCount > 0U)
		922	{
		923	/* Wait until TXE flag is set to send data */
		924	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
		925	{
		926	if (hspi->TxXferCount > 1U)
		927	{
		928	/* write on the data register in packing mode */
		929	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		930	hspi->pTxBuffPtr += sizeof(uint16_t);
		931	hspi->TxXferCount -= 2U;
		932	}
		933	else
		934	{
		935	((__IO uint8_t )&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
		936	hspi->pTxBuffPtr++;
		937	hspi->TxXferCount--;
		938	}
		939	}
		940	else
		941	{
		942	/* Timeout management */
		943	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		944	{
		945	errorcode = HAL_TIMEOUT;
		946	goto error;
		947	}
		948	}
		949	}
		950	}
		951	#if (USE_SPI_CRC != 0U)
		952	/* Enable CRC Transmission */
		953	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		954	{
		955	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		956	}
		957	#endif /* USE_SPI_CRC */
		958
		959	/* Check the end of the transaction */
		960	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		961	{
		962	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		963	}
		964
		965	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		966	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		967	{
		968	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		969	}
		970
		971	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		972	{
		973	errorcode = HAL_ERROR;
		974	}
		975
		976	error:
		977	hspi->State = HAL_SPI_STATE_READY;
		978	/* Process Unlocked */
		979	__HAL_UNLOCK(hspi);
		980	return errorcode;
		981	}
		982
		983	/**
		984	* @brief Receive an amount of data in blocking mode.
		985	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		986	* the configuration information for SPI module.
		987	* @param pData pointer to data buffer
		988	* @param Size amount of data to be received
		989	* @param Timeout Timeout duration
		990	* @retval HAL status
		991	*/
		992	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
		993	{
		994	uint32_t tickstart;
		995	HAL_StatusTypeDef errorcode = HAL_OK;
		996
		997	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
		998	{
		999	/* in this case, 16-bit access is performed on Data
		1000	So, check Data is 16-bit aligned address */
		1001	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
		1002	}
		1003
		1004	if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
		1005	{
		1006	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1007	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1008	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
		1009	}
		1010
		1011	/* Process Locked */
		1012	__HAL_LOCK(hspi);
		1013
		1014	/* Init tickstart for timeout management*/
		1015	tickstart = HAL_GetTick();
		1016
		1017	if (hspi->State != HAL_SPI_STATE_READY)
		1018	{
		1019	errorcode = HAL_BUSY;
		1020	goto error;
		1021	}
		1022
		1023	if ((pData == NULL) \|\| (Size == 0U))
		1024	{
		1025	errorcode = HAL_ERROR;
		1026	goto error;
		1027	}
		1028
		1029	/* Set the transaction information */
		1030	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1031	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1032	hspi->pRxBuffPtr = (uint8_t *)pData;
		1033	hspi->RxXferSize = Size;
		1034	hspi->RxXferCount = Size;
		1035
		1036	/Init field not used in handle to zero /
		1037	hspi->pTxBuffPtr = (uint8_t *)NULL;
		1038	hspi->TxXferSize = 0U;
		1039	hspi->TxXferCount = 0U;
		1040	hspi->RxISR = NULL;
		1041	hspi->TxISR = NULL;
		1042
		1043	#if (USE_SPI_CRC != 0U)
		1044	/* Reset CRC Calculation */
		1045	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1046	{
		1047	SPI_RESET_CRC(hspi);
		1048	/* this is done to handle the CRCNEXT before the latest data */
		1049	hspi->RxXferCount--;
		1050	}
		1051	#endif /* USE_SPI_CRC */
		1052
		1053	/* Set the Rx Fifo threshold */
		1054	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1055	{
		1056	/* Set RX Fifo threshold according the reception data length: 16bit */
		1057	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1058	}
		1059	else
		1060	{
		1061	/* Set RX Fifo threshold according the reception data length: 8bit */
		1062	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1063	}
		1064
		1065	/* Configure communication direction: 1Line */
		1066	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1067	{
		1068	SPI_1LINE_RX(hspi);
		1069	}
		1070
		1071	/* Check if the SPI is already enabled */
		1072	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1073	{
		1074	/* Enable SPI peripheral */
		1075	__HAL_SPI_ENABLE(hspi);
		1076	}
		1077
		1078	/* Receive data in 8 Bit mode */
		1079	if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
		1080	{
		1081	/* Transfer loop */
		1082	while (hspi->RxXferCount > 0U)
		1083	{
		1084	/* Check the RXNE flag */
		1085	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		1086	{
		1087	/* read the received data */
		1088	(* (uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t *)&hspi->Instance->DR;
		1089	hspi->pRxBuffPtr += sizeof(uint8_t);
		1090	hspi->RxXferCount--;
		1091	}
		1092	else
		1093	{
		1094	/* Timeout management */
		1095	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		1096	{
		1097	errorcode = HAL_TIMEOUT;
		1098	goto error;
		1099	}
		1100	}
		1101	}
		1102	}
		1103	else
		1104	{
		1105	/* Transfer loop */
		1106	while (hspi->RxXferCount > 0U)
		1107	{
		1108	/* Check the RXNE flag */
		1109	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
		1110	{
		1111	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1112	hspi->pRxBuffPtr += sizeof(uint16_t);
		1113	hspi->RxXferCount--;
		1114	}
		1115	else
		1116	{
		1117	/* Timeout management */
		1118	if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) \|\| (Timeout == 0U))
		1119	{
		1120	errorcode = HAL_TIMEOUT;
		1121	goto error;
		1122	}
		1123	}
		1124	}
		1125	}
		1126
		1127	#if (USE_SPI_CRC != 0U)
		1128	/* Handle the CRC Transmission */
		1129	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1130	{
		1131	/* freeze the CRC before the latest data */
		1132	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1133
		1134	/* Read the latest data */
		1135	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1136	{
		1137	/* the latest data has not been received */
		1138	errorcode = HAL_TIMEOUT;
		1139	goto error;
		1140	}
		1141
		1142	/* Receive last data in 16 Bit mode */
		1143	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1144	{
		1145	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1146	}
		1147	/* Receive last data in 8 Bit mode */
		1148	else
		1149	{
		1150	((uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t )&hspi->Instance->DR;
		1151	}
		1152
		1153	/* Wait the CRC data */
		1154	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1155	{
		1156	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1157	errorcode = HAL_TIMEOUT;
		1158	goto error;
		1159	}
		1160
		1161	/* Read CRC to Flush DR and RXNE flag */
		1162	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		1163	{
		1164	/* Read 16bit CRC */
		1165	READ_REG(hspi->Instance->DR);
		1166	}
		1167	else
		1168	{
		1169	/* Read 8bit CRC */
		1170	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		1171
		1172	if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
		1173	{
		1174	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1175	{
		1176	/* Error on the CRC reception */
		1177	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1178	errorcode = HAL_TIMEOUT;
		1179	goto error;
		1180	}
		1181	/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
		1182	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		1183	}
		1184	}
		1185	}
		1186	#endif /* USE_SPI_CRC */
		1187
		1188	/* Check the end of the transaction */
		1189	if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		1190	{
		1191	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1192	}
		1193
		1194	#if (USE_SPI_CRC != 0U)
		1195	/* Check if CRC error occurred */
		1196	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
		1197	{
		1198	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1199	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1200	}
		1201	#endif /* USE_SPI_CRC */
		1202
		1203	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		1204	{
		1205	errorcode = HAL_ERROR;
		1206	}
		1207
		1208	error :
		1209	hspi->State = HAL_SPI_STATE_READY;
		1210	__HAL_UNLOCK(hspi);
		1211	return errorcode;
		1212	}
		1213
		1214	/**
		1215	* @brief Transmit and Receive an amount of data in blocking mode.
		1216	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1217	* the configuration information for SPI module.
		1218	* @param pTxData pointer to transmission data buffer
		1219	* @param pRxData pointer to reception data buffer
		1220	* @param Size amount of data to be sent and received
		1221	* @param Timeout Timeout duration
		1222	* @retval HAL status
		1223	*/
		1224	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
		1225	uint32_t Timeout)
		1226	{
		1227	uint16_t initial_TxXferCount;
		1228	uint16_t initial_RxXferCount;
		1229	uint32_t tmp_mode;
		1230	HAL_SPI_StateTypeDef tmp_state;
		1231	uint32_t tickstart;
		1232	#if (USE_SPI_CRC != 0U)
		1233	uint32_t spi_cr1;
		1234	uint32_t spi_cr2;
		1235	#endif /* USE_SPI_CRC */
		1236
		1237	/* Variable used to alternate Rx and Tx during transfer */
		1238	uint32_t txallowed = 1U;
		1239	HAL_StatusTypeDef errorcode = HAL_OK;
		1240
		1241	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
		1242	{
		1243	/* in this case, 16-bit access is performed on Data
		1244	So, check Data is 16-bit aligned address */
		1245	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
		1246	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
		1247	}
		1248
		1249	/* Check Direction parameter */
		1250	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1251
		1252	/* Process Locked */
		1253	__HAL_LOCK(hspi);
		1254
		1255	/* Init tickstart for timeout management*/
		1256	tickstart = HAL_GetTick();
		1257
		1258	/* Init temporary variables */
		1259	tmp_state = hspi->State;
		1260	tmp_mode = hspi->Init.Mode;
		1261	initial_TxXferCount = Size;
		1262	initial_RxXferCount = Size;
		1263	#if (USE_SPI_CRC != 0U)
		1264	spi_cr1 = READ_REG(hspi->Instance->CR1);
		1265	spi_cr2 = READ_REG(hspi->Instance->CR2);
		1266	#endif /* USE_SPI_CRC */
		1267
		1268	if (!((tmp_state == HAL_SPI_STATE_READY) \|\| \
		1269	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1270	{
		1271	errorcode = HAL_BUSY;
		1272	goto error;
		1273	}
		1274
		1275	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1276	{
		1277	errorcode = HAL_ERROR;
		1278	goto error;
		1279	}
		1280
		1281	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1282	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1283	{
		1284	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1285	}
		1286
		1287	/* Set the transaction information */
		1288	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1289	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1290	hspi->RxXferCount = Size;
		1291	hspi->RxXferSize = Size;
		1292	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1293	hspi->TxXferCount = Size;
		1294	hspi->TxXferSize = Size;
		1295
		1296	/Init field not used in handle to zero /
		1297	hspi->RxISR = NULL;
		1298	hspi->TxISR = NULL;
		1299
		1300	#if (USE_SPI_CRC != 0U)
		1301	/* Reset CRC Calculation */
		1302	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1303	{
		1304	SPI_RESET_CRC(hspi);
		1305	}
		1306	#endif /* USE_SPI_CRC */
		1307
		1308	/* Set the Rx Fifo threshold */
		1309	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (initial_RxXferCount > 1U))
		1310	{
		1311	/* Set fiforxthreshold according the reception data length: 16bit */
		1312	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1313	}
		1314	else
		1315	{
		1316	/* Set fiforxthreshold according the reception data length: 8bit */
		1317	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1318	}
		1319
		1320	/* Check if the SPI is already enabled */
		1321	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1322	{
		1323	/* Enable SPI peripheral */
		1324	__HAL_SPI_ENABLE(hspi);
		1325	}
		1326
		1327	/* Transmit and Receive data in 16 Bit mode */
		1328	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1329	{
		1330	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		1331	{
		1332	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1333	hspi->pTxBuffPtr += sizeof(uint16_t);
		1334	hspi->TxXferCount--;
		1335	}
		1336	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		1337	{
		1338	/* Check TXE flag */
		1339	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
		1340	{
		1341	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1342	hspi->pTxBuffPtr += sizeof(uint16_t);
		1343	hspi->TxXferCount--;
		1344	/* Next Data is a reception (Rx). Tx not allowed */
		1345	txallowed = 0U;
		1346
		1347	#if (USE_SPI_CRC != 0U)
		1348	/* Enable CRC Transmission */
		1349	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		1350	{
		1351	/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
		1352	if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
		1353	{
		1354	SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
		1355	}
		1356	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1357	}
		1358	#endif /* USE_SPI_CRC */
		1359	}
		1360
		1361	/* Check RXNE flag */
		1362	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
		1363	{
		1364	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1365	hspi->pRxBuffPtr += sizeof(uint16_t);
		1366	hspi->RxXferCount--;
		1367	/* Next Data is a Transmission (Tx). Tx is allowed */
		1368	txallowed = 1U;
		1369	}
		1370	if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
		1371	{
		1372	errorcode = HAL_TIMEOUT;
		1373	goto error;
		1374	}
		1375	}
		1376	}
		1377	/* Transmit and Receive data in 8 Bit mode */
		1378	else
		1379	{
		1380	if ((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (initial_TxXferCount == 0x01U))
		1381	{
		1382	if (hspi->TxXferCount > 1U)
		1383	{
		1384	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1385	hspi->pTxBuffPtr += sizeof(uint16_t);
		1386	hspi->TxXferCount -= 2U;
		1387	}
		1388	else
		1389	{
		1390	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		1391	hspi->pTxBuffPtr++;
		1392	hspi->TxXferCount--;
		1393	}
		1394	}
		1395	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
		1396	{
		1397	/* Check TXE flag */
		1398	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
		1399	{
		1400	if (hspi->TxXferCount > 1U)
		1401	{
		1402	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		1403	hspi->pTxBuffPtr += sizeof(uint16_t);
		1404	hspi->TxXferCount -= 2U;
		1405	}
		1406	else
		1407	{
		1408	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		1409	hspi->pTxBuffPtr++;
		1410	hspi->TxXferCount--;
		1411	}
		1412	/* Next Data is a reception (Rx). Tx not allowed */
		1413	txallowed = 0U;
		1414
		1415	#if (USE_SPI_CRC != 0U)
		1416	/* Enable CRC Transmission */
		1417	if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		1418	{
		1419	/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
		1420	if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
		1421	{
		1422	SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
		1423	}
		1424	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		1425	}
		1426	#endif /* USE_SPI_CRC */
		1427	}
		1428
		1429	/* Wait until RXNE flag is reset */
		1430	if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
		1431	{
		1432	if (hspi->RxXferCount > 1U)
		1433	{
		1434	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
		1435	hspi->pRxBuffPtr += sizeof(uint16_t);
		1436	hspi->RxXferCount -= 2U;
		1437	if (hspi->RxXferCount <= 1U)
		1438	{
		1439	/* Set RX Fifo threshold before to switch on 8 bit data size */
		1440	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1441	}
		1442	}
		1443	else
		1444	{
		1445	((uint8_t )hspi->pRxBuffPtr) = (__IO uint8_t )&hspi->Instance->DR;
		1446	hspi->pRxBuffPtr++;
		1447	hspi->RxXferCount--;
		1448	}
		1449	/* Next Data is a Transmission (Tx). Tx is allowed */
		1450	txallowed = 1U;
		1451	}
		1452	if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) \|\| (Timeout == 0U))
		1453	{
		1454	errorcode = HAL_TIMEOUT;
		1455	goto error;
		1456	}
		1457	}
		1458	}
		1459
		1460	#if (USE_SPI_CRC != 0U)
		1461	/* Read CRC from DR to close CRC calculation process */
		1462	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1463	{
		1464	/* Wait until TXE flag */
		1465	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1466	{
		1467	/* Error on the CRC reception */
		1468	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1469	errorcode = HAL_TIMEOUT;
		1470	goto error;
		1471	}
		1472	/* Read CRC */
		1473	if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
		1474	{
		1475	/* Read 16bit CRC */
		1476	READ_REG(hspi->Instance->DR);
		1477	}
		1478	else
		1479	{
		1480	/* Read 8bit CRC */
		1481	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		1482
		1483	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
		1484	{
		1485	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
		1486	{
		1487	/* Error on the CRC reception */
		1488	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1489	errorcode = HAL_TIMEOUT;
		1490	goto error;
		1491	}
		1492	/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
		1493	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		1494	}
		1495	}
		1496	}
		1497
		1498	/* Check if CRC error occurred */
		1499	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
		1500	{
		1501	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		1502	/* Clear CRC Flag */
		1503	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		1504
		1505	errorcode = HAL_ERROR;
		1506	}
		1507	#endif /* USE_SPI_CRC */
		1508
		1509	/* Check the end of the transaction */
		1510	if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
		1511	{
		1512	errorcode = HAL_ERROR;
		1513	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		1514	}
		1515
		1516	error :
		1517	hspi->State = HAL_SPI_STATE_READY;
		1518	__HAL_UNLOCK(hspi);
		1519	return errorcode;
		1520	}
		1521
		1522	/**
		1523	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
		1524	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1525	* the configuration information for SPI module.
		1526	* @param pData pointer to data buffer
		1527	* @param Size amount of data to be sent
		1528	* @retval HAL status
		1529	*/
		1530	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1531	{
		1532	HAL_StatusTypeDef errorcode = HAL_OK;
		1533
		1534	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
		1535	{
		1536	/* in this case, 16-bit access is performed on Data
		1537	So, check Data is 16-bit aligned address */
		1538	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
		1539	}
		1540
		1541	/* Check Direction parameter */
		1542	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1543
		1544	/* Process Locked */
		1545	__HAL_LOCK(hspi);
		1546
		1547	if ((pData == NULL) \|\| (Size == 0U))
		1548	{
		1549	errorcode = HAL_ERROR;
		1550	goto error;
		1551	}
		1552
		1553	if (hspi->State != HAL_SPI_STATE_READY)
		1554	{
		1555	errorcode = HAL_BUSY;
		1556	goto error;
		1557	}
		1558
		1559	/* Set the transaction information */
		1560	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1561	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1562	hspi->pTxBuffPtr = (uint8_t *)pData;
		1563	hspi->TxXferSize = Size;
		1564	hspi->TxXferCount = Size;
		1565
		1566	/* Init field not used in handle to zero */
		1567	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1568	hspi->RxXferSize = 0U;
		1569	hspi->RxXferCount = 0U;
		1570	hspi->RxISR = NULL;
		1571
		1572	/* Set the function for IT treatment */
		1573	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1574	{
		1575	hspi->TxISR = SPI_TxISR_16BIT;
		1576	}
		1577	else
		1578	{
		1579	hspi->TxISR = SPI_TxISR_8BIT;
		1580	}
		1581
		1582	/* Configure communication direction : 1Line */
		1583	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1584	{
		1585	SPI_1LINE_TX(hspi);
		1586	}
		1587
		1588	#if (USE_SPI_CRC != 0U)
		1589	/* Reset CRC Calculation */
		1590	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1591	{
		1592	SPI_RESET_CRC(hspi);
		1593	}
		1594	#endif /* USE_SPI_CRC */
		1595
		1596	/* Enable TXE and ERR interrupt */
		1597	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		1598
		1599
		1600	/* Check if the SPI is already enabled */
		1601	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1602	{
		1603	/* Enable SPI peripheral */
		1604	__HAL_SPI_ENABLE(hspi);
		1605	}
		1606
		1607	error :
		1608	__HAL_UNLOCK(hspi);
		1609	return errorcode;
		1610	}
		1611
		1612	/**
		1613	* @brief Receive an amount of data in non-blocking mode with Interrupt.
		1614	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1615	* the configuration information for SPI module.
		1616	* @param pData pointer to data buffer
		1617	* @param Size amount of data to be sent
		1618	* @retval HAL status
		1619	*/
		1620	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1621	{
		1622	HAL_StatusTypeDef errorcode = HAL_OK;
		1623
		1624	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
		1625	{
		1626	/* in this case, 16-bit access is performed on Data
		1627	So, check Data is 16-bit aligned address */
		1628	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
		1629	}
		1630
		1631	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1632	{
		1633	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1634	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1635	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
		1636	}
		1637
		1638	/* Process Locked */
		1639	__HAL_LOCK(hspi);
		1640
		1641	if (hspi->State != HAL_SPI_STATE_READY)
		1642	{
		1643	errorcode = HAL_BUSY;
		1644	goto error;
		1645	}
		1646
		1647	if ((pData == NULL) \|\| (Size == 0U))
		1648	{
		1649	errorcode = HAL_ERROR;
		1650	goto error;
		1651	}
		1652
		1653	/* Set the transaction information */
		1654	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1655	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1656	hspi->pRxBuffPtr = (uint8_t *)pData;
		1657	hspi->RxXferSize = Size;
		1658	hspi->RxXferCount = Size;
		1659
		1660	/* Init field not used in handle to zero */
		1661	hspi->pTxBuffPtr = (uint8_t *)NULL;
		1662	hspi->TxXferSize = 0U;
		1663	hspi->TxXferCount = 0U;
		1664	hspi->TxISR = NULL;
		1665
		1666	/* Check the data size to adapt Rx threshold and the set the function for IT treatment */
		1667	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1668	{
		1669	/* Set RX Fifo threshold according the reception data length: 16 bit */
		1670	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1671	hspi->RxISR = SPI_RxISR_16BIT;
		1672	}
		1673	else
		1674	{
		1675	/* Set RX Fifo threshold according the reception data length: 8 bit */
		1676	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1677	hspi->RxISR = SPI_RxISR_8BIT;
		1678	}
		1679
		1680	/* Configure communication direction : 1Line */
		1681	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1682	{
		1683	SPI_1LINE_RX(hspi);
		1684	}
		1685
		1686	#if (USE_SPI_CRC != 0U)
		1687	/* Reset CRC Calculation */
		1688	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1689	{
		1690	hspi->CRCSize = 1U;
		1691	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
		1692	{
		1693	hspi->CRCSize = 2U;
		1694	}
		1695	SPI_RESET_CRC(hspi);
		1696	}
		1697	else
		1698	{
		1699	hspi->CRCSize = 0U;
		1700	}
		1701	#endif /* USE_SPI_CRC */
		1702
		1703	/* Enable TXE and ERR interrupt */
		1704	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		1705
		1706	/* Note : The SPI must be enabled after unlocking current process
		1707	to avoid the risk of SPI interrupt handle execution before current
		1708	process unlock */
		1709
		1710	/* Check if the SPI is already enabled */
		1711	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1712	{
		1713	/* Enable SPI peripheral */
		1714	__HAL_SPI_ENABLE(hspi);
		1715	}
		1716
		1717	error :
		1718	/* Process Unlocked */
		1719	__HAL_UNLOCK(hspi);
		1720	return errorcode;
		1721	}
		1722
		1723	/**
		1724	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
		1725	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1726	* the configuration information for SPI module.
		1727	* @param pTxData pointer to transmission data buffer
		1728	* @param pRxData pointer to reception data buffer
		1729	* @param Size amount of data to be sent and received
		1730	* @retval HAL status
		1731	*/
		1732	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
		1733	{
		1734	uint32_t tmp_mode;
		1735	HAL_SPI_StateTypeDef tmp_state;
		1736	HAL_StatusTypeDef errorcode = HAL_OK;
		1737
		1738	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
		1739	{
		1740	/* in this case, 16-bit access is performed on Data
		1741	So, check Data is 16-bit aligned address */
		1742	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
		1743	assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
		1744	}
		1745
		1746	/* Check Direction parameter */
		1747	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		1748
		1749	/* Process locked */
		1750	__HAL_LOCK(hspi);
		1751
		1752	/* Init temporary variables */
		1753	tmp_state = hspi->State;
		1754	tmp_mode = hspi->Init.Mode;
		1755
		1756	if (!((tmp_state == HAL_SPI_STATE_READY) \|\| \
		1757	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		1758	{
		1759	errorcode = HAL_BUSY;
		1760	goto error;
		1761	}
		1762
		1763	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		1764	{
		1765	errorcode = HAL_ERROR;
		1766	goto error;
		1767	}
		1768
		1769	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		1770	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		1771	{
		1772	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		1773	}
		1774
		1775	/* Set the transaction information */
		1776	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1777	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		1778	hspi->TxXferSize = Size;
		1779	hspi->TxXferCount = Size;
		1780	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		1781	hspi->RxXferSize = Size;
		1782	hspi->RxXferCount = Size;
		1783
		1784	/* Set the function for IT treatment */
		1785	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		1786	{
		1787	hspi->RxISR = SPI_2linesRxISR_16BIT;
		1788	hspi->TxISR = SPI_2linesTxISR_16BIT;
		1789	}
		1790	else
		1791	{
		1792	hspi->RxISR = SPI_2linesRxISR_8BIT;
		1793	hspi->TxISR = SPI_2linesTxISR_8BIT;
		1794	}
		1795
		1796	#if (USE_SPI_CRC != 0U)
		1797	/* Reset CRC Calculation */
		1798	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1799	{
		1800	hspi->CRCSize = 1U;
		1801	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
		1802	{
		1803	hspi->CRCSize = 2U;
		1804	}
		1805	SPI_RESET_CRC(hspi);
		1806	}
		1807	else
		1808	{
		1809	hspi->CRCSize = 0U;
		1810	}
		1811	#endif /* USE_SPI_CRC */
		1812
		1813	/* Check if packing mode is enabled and if there is more than 2 data to receive */
		1814	if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (Size >= 2U))
		1815	{
		1816	/* Set RX Fifo threshold according the reception data length: 16 bit */
		1817	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1818	}
		1819	else
		1820	{
		1821	/* Set RX Fifo threshold according the reception data length: 8 bit */
		1822	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		1823	}
		1824
		1825	/* Enable TXE, RXNE and ERR interrupt */
		1826	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		1827
		1828	/* Check if the SPI is already enabled */
		1829	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1830	{
		1831	/* Enable SPI peripheral */
		1832	__HAL_SPI_ENABLE(hspi);
		1833	}
		1834
		1835	error :
		1836	/* Process Unlocked */
		1837	__HAL_UNLOCK(hspi);
		1838	return errorcode;
		1839	}
		1840
		1841	/**
		1842	* @brief Transmit an amount of data in non-blocking mode with DMA.
		1843	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1844	* the configuration information for SPI module.
		1845	* @param pData pointer to data buffer
		1846	* @param Size amount of data to be sent
		1847	* @retval HAL status
		1848	*/
		1849	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1850	{
		1851	HAL_StatusTypeDef errorcode = HAL_OK;
		1852
		1853	/* Check tx dma handle */
		1854	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1855
		1856	/* Check Direction parameter */
		1857	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
		1858
		1859	/* Process Locked */
		1860	__HAL_LOCK(hspi);
		1861
		1862	if (hspi->State != HAL_SPI_STATE_READY)
		1863	{
		1864	errorcode = HAL_BUSY;
		1865	goto error;
		1866	}
		1867
		1868	if ((pData == NULL) \|\| (Size == 0U))
		1869	{
		1870	errorcode = HAL_ERROR;
		1871	goto error;
		1872	}
		1873
		1874	/* Set the transaction information */
		1875	hspi->State = HAL_SPI_STATE_BUSY_TX;
		1876	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		1877	hspi->pTxBuffPtr = (uint8_t *)pData;
		1878	hspi->TxXferSize = Size;
		1879	hspi->TxXferCount = Size;
		1880
		1881	/* Init field not used in handle to zero */
		1882	hspi->pRxBuffPtr = (uint8_t *)NULL;
		1883	hspi->TxISR = NULL;
		1884	hspi->RxISR = NULL;
		1885	hspi->RxXferSize = 0U;
		1886	hspi->RxXferCount = 0U;
		1887
		1888	/* Configure communication direction : 1Line */
		1889	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		1890	{
		1891	SPI_1LINE_TX(hspi);
		1892	}
		1893
		1894	#if (USE_SPI_CRC != 0U)
		1895	/* Reset CRC Calculation */
		1896	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		1897	{
		1898	SPI_RESET_CRC(hspi);
		1899	}
		1900	#endif /* USE_SPI_CRC */
		1901
		1902	/* Set the SPI TxDMA Half transfer complete callback */
		1903	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
		1904
		1905	/* Set the SPI TxDMA transfer complete callback */
		1906	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
		1907
		1908	/* Set the DMA error callback */
		1909	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
		1910
		1911	/* Set the DMA AbortCpltCallback */
		1912	hspi->hdmatx->XferAbortCallback = NULL;
		1913
		1914	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
		1915	/* Packing mode is enabled only if the DMA setting is HALWORD */
		1916	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
		1917	{
		1918	/* Check the even/odd of the data size + crc if enabled */
		1919	if ((hspi->TxXferCount & 0x1U) == 0U)
		1920	{
		1921	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
		1922	hspi->TxXferCount = (hspi->TxXferCount >> 1U);
		1923	}
		1924	else
		1925	{
		1926	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
		1927	hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
		1928	}
		1929	}
		1930
		1931	/* Enable the Tx DMA Stream/Channel */
		1932	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
		1933	hspi->TxXferCount))
		1934	{
		1935	/* Update SPI error code */
		1936	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		1937	errorcode = HAL_ERROR;
		1938
		1939	hspi->State = HAL_SPI_STATE_READY;
		1940	goto error;
		1941	}
		1942
		1943	/* Check if the SPI is already enabled */
		1944	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		1945	{
		1946	/* Enable SPI peripheral */
		1947	__HAL_SPI_ENABLE(hspi);
		1948	}
		1949
		1950	/* Enable the SPI Error Interrupt Bit */
		1951	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		1952
		1953	/* Enable Tx DMA Request */
		1954	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		1955
		1956	error :
		1957	/* Process Unlocked */
		1958	__HAL_UNLOCK(hspi);
		1959	return errorcode;
		1960	}
		1961
		1962	/**
		1963	* @brief Receive an amount of data in non-blocking mode with DMA.
		1964	* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
		1965	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		1966	* the configuration information for SPI module.
		1967	* @param pData pointer to data buffer
		1968	* @note When the CRC feature is enabled the pData Length must be Size + 1.
		1969	* @param Size amount of data to be sent
		1970	* @retval HAL status
		1971	*/
		1972	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
		1973	{
		1974	HAL_StatusTypeDef errorcode = HAL_OK;
		1975
		1976	/* Check rx dma handle */
		1977	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
		1978
		1979	if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
		1980	{
		1981	hspi->State = HAL_SPI_STATE_BUSY_RX;
		1982
		1983	/* Check tx dma handle */
		1984	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		1985
		1986	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
		1987	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
		1988	}
		1989
		1990	/* Process Locked */
		1991	__HAL_LOCK(hspi);
		1992
		1993	if (hspi->State != HAL_SPI_STATE_READY)
		1994	{
		1995	errorcode = HAL_BUSY;
		1996	goto error;
		1997	}
		1998
		1999	if ((pData == NULL) \|\| (Size == 0U))
		2000	{
		2001	errorcode = HAL_ERROR;
		2002	goto error;
		2003	}
		2004
		2005	/* Set the transaction information */
		2006	hspi->State = HAL_SPI_STATE_BUSY_RX;
		2007	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2008	hspi->pRxBuffPtr = (uint8_t *)pData;
		2009	hspi->RxXferSize = Size;
		2010	hspi->RxXferCount = Size;
		2011
		2012	/Init field not used in handle to zero /
		2013	hspi->RxISR = NULL;
		2014	hspi->TxISR = NULL;
		2015	hspi->TxXferSize = 0U;
		2016	hspi->TxXferCount = 0U;
		2017
		2018	/* Configure communication direction : 1Line */
		2019	if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
		2020	{
		2021	SPI_1LINE_RX(hspi);
		2022	}
		2023
		2024	#if (USE_SPI_CRC != 0U)
		2025	/* Reset CRC Calculation */
		2026	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2027	{
		2028	SPI_RESET_CRC(hspi);
		2029	}
		2030	#endif /* USE_SPI_CRC */
		2031
		2032	#if defined (STM32F030x6) \|\| defined (STM32F030x8) \|\| defined (STM32F031x6)\|\| defined (STM32F038xx) \|\| defined (STM32F051x8) \|\| defined (STM32F058xx)
		2033	/* Packing mode management is enabled by the DMA settings */
		2034	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
		2035	{
		2036	/* Restriction the DMA data received is not allowed in this mode */
		2037	errorcode = HAL_ERROR;
		2038	goto error;
		2039	}
		2040	#endif
		2041
		2042	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
		2043	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		2044	{
		2045	/* Set RX Fifo threshold according the reception data length: 16bit */
		2046	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		2047	}
		2048	else
		2049	{
		2050	/* Set RX Fifo threshold according the reception data length: 8bit */
		2051	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		2052
		2053	if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
		2054	{
		2055	/* Set RX Fifo threshold according the reception data length: 16bit */
		2056	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		2057
		2058	if ((hspi->RxXferCount & 0x1U) == 0x0U)
		2059	{
		2060	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
		2061	hspi->RxXferCount = hspi->RxXferCount >> 1U;
		2062	}
		2063	else
		2064	{
		2065	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
		2066	hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
		2067	}
		2068	}
		2069	}
		2070
		2071	/* Set the SPI RxDMA Half transfer complete callback */
		2072	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		2073
		2074	/* Set the SPI Rx DMA transfer complete callback */
		2075	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		2076
		2077	/* Set the DMA error callback */
		2078	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		2079
		2080	/* Set the DMA AbortCpltCallback */
		2081	hspi->hdmarx->XferAbortCallback = NULL;
		2082
		2083	/* Enable the Rx DMA Stream/Channel */
		2084	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
		2085	hspi->RxXferCount))
		2086	{
		2087	/* Update SPI error code */
		2088	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2089	errorcode = HAL_ERROR;
		2090
		2091	hspi->State = HAL_SPI_STATE_READY;
		2092	goto error;
		2093	}
		2094
		2095	/* Check if the SPI is already enabled */
		2096	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		2097	{
		2098	/* Enable SPI peripheral */
		2099	__HAL_SPI_ENABLE(hspi);
		2100	}
		2101
		2102	/* Enable the SPI Error Interrupt Bit */
		2103	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		2104
		2105	/* Enable Rx DMA Request */
		2106	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		2107
		2108	error:
		2109	/* Process Unlocked */
		2110	__HAL_UNLOCK(hspi);
		2111	return errorcode;
		2112	}
		2113
		2114	/**
		2115	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
		2116	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2117	* the configuration information for SPI module.
		2118	* @param pTxData pointer to transmission data buffer
		2119	* @param pRxData pointer to reception data buffer
		2120	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
		2121	* @param Size amount of data to be sent
		2122	* @retval HAL status
		2123	*/
		2124	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData,
		2125	uint16_t Size)
		2126	{
		2127	uint32_t tmp_mode;
		2128	HAL_SPI_StateTypeDef tmp_state;
		2129	HAL_StatusTypeDef errorcode = HAL_OK;
		2130
		2131	/* Check rx & tx dma handles */
		2132	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
		2133	assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
		2134
		2135	/* Check Direction parameter */
		2136	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
		2137
		2138	/* Process locked */
		2139	__HAL_LOCK(hspi);
		2140
		2141	/* Init temporary variables */
		2142	tmp_state = hspi->State;
		2143	tmp_mode = hspi->Init.Mode;
		2144
		2145	if (!((tmp_state == HAL_SPI_STATE_READY) \|\|
		2146	((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
		2147	{
		2148	errorcode = HAL_BUSY;
		2149	goto error;
		2150	}
		2151
		2152	if ((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
		2153	{
		2154	errorcode = HAL_ERROR;
		2155	goto error;
		2156	}
		2157
		2158	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
		2159	if (hspi->State != HAL_SPI_STATE_BUSY_RX)
		2160	{
		2161	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
		2162	}
		2163
		2164	/* Set the transaction information */
		2165	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2166	hspi->pTxBuffPtr = (uint8_t *)pTxData;
		2167	hspi->TxXferSize = Size;
		2168	hspi->TxXferCount = Size;
		2169	hspi->pRxBuffPtr = (uint8_t *)pRxData;
		2170	hspi->RxXferSize = Size;
		2171	hspi->RxXferCount = Size;
		2172
		2173	/* Init field not used in handle to zero */
		2174	hspi->RxISR = NULL;
		2175	hspi->TxISR = NULL;
		2176
		2177	#if (USE_SPI_CRC != 0U)
		2178	/* Reset CRC Calculation */
		2179	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		2180	{
		2181	SPI_RESET_CRC(hspi);
		2182	}
		2183	#endif /* USE_SPI_CRC */
		2184
		2185	#if defined (STM32F030x6) \|\| defined (STM32F030x8) \|\| defined (STM32F031x6) \|\| defined (STM32F038xx) \|\| defined (STM32F051x8) \|\| defined (STM32F058xx)
		2186	/* Packing mode management is enabled by the DMA settings */
		2187	if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
		2188	{
		2189	/* Restriction the DMA data received is not allowed in this mode */
		2190	errorcode = HAL_ERROR;
		2191	goto error;
		2192	}
		2193	#endif
		2194
		2195	/* Reset the threshold bit */
		2196	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX \| SPI_CR2_LDMARX);
		2197
		2198	/* The packing mode management is enabled by the DMA settings according the spi data size */
		2199	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		2200	{
		2201	/* Set fiforxthreshold according the reception data length: 16bit */
		2202	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		2203	}
		2204	else
		2205	{
		2206	/* Set RX Fifo threshold according the reception data length: 8bit */
		2207	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		2208
		2209	if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
		2210	{
		2211	if ((hspi->TxXferSize & 0x1U) == 0x0U)
		2212	{
		2213	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
		2214	hspi->TxXferCount = hspi->TxXferCount >> 1U;
		2215	}
		2216	else
		2217	{
		2218	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
		2219	hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
		2220	}
		2221	}
		2222
		2223	if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
		2224	{
		2225	/* Set RX Fifo threshold according the reception data length: 16bit */
		2226	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		2227
		2228	if ((hspi->RxXferCount & 0x1U) == 0x0U)
		2229	{
		2230	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
		2231	hspi->RxXferCount = hspi->RxXferCount >> 1U;
		2232	}
		2233	else
		2234	{
		2235	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
		2236	hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
		2237	}
		2238	}
		2239	}
		2240
		2241	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
		2242	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
		2243	{
		2244	/* Set the SPI Rx DMA Half transfer complete callback */
		2245	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
		2246	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
		2247	}
		2248	else
		2249	{
		2250	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
		2251	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
		2252	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
		2253	}
		2254
		2255	/* Set the DMA error callback */
		2256	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
		2257
		2258	/* Set the DMA AbortCpltCallback */
		2259	hspi->hdmarx->XferAbortCallback = NULL;
		2260
		2261	/* Enable the Rx DMA Stream/Channel */
		2262	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
		2263	hspi->RxXferCount))
		2264	{
		2265	/* Update SPI error code */
		2266	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2267	errorcode = HAL_ERROR;
		2268
		2269	hspi->State = HAL_SPI_STATE_READY;
		2270	goto error;
		2271	}
		2272
		2273	/* Enable Rx DMA Request */
		2274	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		2275
		2276	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
		2277	is performed in DMA reception complete callback */
		2278	hspi->hdmatx->XferHalfCpltCallback = NULL;
		2279	hspi->hdmatx->XferCpltCallback = NULL;
		2280	hspi->hdmatx->XferErrorCallback = NULL;
		2281	hspi->hdmatx->XferAbortCallback = NULL;
		2282
		2283	/* Enable the Tx DMA Stream/Channel */
		2284	if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
		2285	hspi->TxXferCount))
		2286	{
		2287	/* Update SPI error code */
		2288	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2289	errorcode = HAL_ERROR;
		2290
		2291	hspi->State = HAL_SPI_STATE_READY;
		2292	goto error;
		2293	}
		2294
		2295	/* Check if the SPI is already enabled */
		2296	if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
		2297	{
		2298	/* Enable SPI peripheral */
		2299	__HAL_SPI_ENABLE(hspi);
		2300	}
		2301	/* Enable the SPI Error Interrupt Bit */
		2302	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
		2303
		2304	/* Enable Tx DMA Request */
		2305	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		2306
		2307	error :
		2308	/* Process Unlocked */
		2309	__HAL_UNLOCK(hspi);
		2310	return errorcode;
		2311	}
		2312
		2313	/**
		2314	* @brief Abort ongoing transfer (blocking mode).
		2315	* @param hspi SPI handle.
		2316	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		2317	* started in Interrupt or DMA mode.
		2318	* This procedure performs following operations :
		2319	* - Disable SPI Interrupts (depending of transfer direction)
		2320	* - Disable the DMA transfer in the peripheral register (if enabled)
		2321	* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
		2322	* - Set handle State to READY
		2323	* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
		2324	* @retval HAL status
		2325	*/
		2326	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
		2327	{
		2328	HAL_StatusTypeDef errorcode;
		2329	__IO uint32_t count;
		2330	__IO uint32_t resetcount;
		2331
		2332	/* Initialized local variable */
		2333	errorcode = HAL_OK;
		2334	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2335	count = resetcount;
		2336
		2337	/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
		2338	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		2339
		2340	/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
		2341	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		2342	{
		2343	hspi->TxISR = SPI_AbortTx_ISR;
		2344	/* Wait HAL_SPI_STATE_ABORT state */
		2345	do
		2346	{
		2347	if (count == 0U)
		2348	{
		2349	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2350	break;
		2351	}
		2352	count--;
		2353	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2354	/* Reset Timeout Counter */
		2355	count = resetcount;
		2356	}
		2357
		2358	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		2359	{
		2360	hspi->RxISR = SPI_AbortRx_ISR;
		2361	/* Wait HAL_SPI_STATE_ABORT state */
		2362	do
		2363	{
		2364	if (count == 0U)
		2365	{
		2366	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2367	break;
		2368	}
		2369	count--;
		2370	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2371	/* Reset Timeout Counter */
		2372	count = resetcount;
		2373	}
		2374
		2375	/* Disable the SPI DMA Tx request if enabled */
		2376	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2377	{
		2378	/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
		2379	if (hspi->hdmatx != NULL)
		2380	{
		2381	/* Set the SPI DMA Abort callback :
		2382	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		2383	hspi->hdmatx->XferAbortCallback = NULL;
		2384
		2385	/* Abort DMA Tx Handle linked to SPI Peripheral */
		2386	if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
		2387	{
		2388	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2389	}
		2390
		2391	/* Disable Tx DMA Request */
		2392	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
		2393
		2394	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		2395	{
		2396	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2397	}
		2398
		2399	/* Disable SPI Peripheral */
		2400	__HAL_SPI_DISABLE(hspi);
		2401
		2402	/* Empty the FRLVL fifo */
		2403	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		2404	{
		2405	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2406	}
		2407	}
		2408	}
		2409
		2410	/* Disable the SPI DMA Rx request if enabled */
		2411	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2412	{
		2413	/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
		2414	if (hspi->hdmarx != NULL)
		2415	{
		2416	/* Set the SPI DMA Abort callback :
		2417	will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
		2418	hspi->hdmarx->XferAbortCallback = NULL;
		2419
		2420	/* Abort DMA Rx Handle linked to SPI Peripheral */
		2421	if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
		2422	{
		2423	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2424	}
		2425
		2426	/* Disable peripheral */
		2427	__HAL_SPI_DISABLE(hspi);
		2428
		2429	/* Control the BSY flag */
		2430	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		2431	{
		2432	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2433	}
		2434
		2435	/* Empty the FRLVL fifo */
		2436	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		2437	{
		2438	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2439	}
		2440
		2441	/* Disable Rx DMA Request */
		2442	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
		2443	}
		2444	}
		2445	/* Reset Tx and Rx transfer counters */
		2446	hspi->RxXferCount = 0U;
		2447	hspi->TxXferCount = 0U;
		2448
		2449	/* Check error during Abort procedure */
		2450	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
		2451	{
		2452	/* return HAL_Error in case of error during Abort procedure */
		2453	errorcode = HAL_ERROR;
		2454	}
		2455	else
		2456	{
		2457	/* Reset errorCode */
		2458	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2459	}
		2460
		2461	/* Clear the Error flags in the SR register */
		2462	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2463	__HAL_SPI_CLEAR_FREFLAG(hspi);
		2464
		2465	/* Restore hspi->state to ready */
		2466	hspi->State = HAL_SPI_STATE_READY;
		2467
		2468	return errorcode;
		2469	}
		2470
		2471	/**
		2472	* @brief Abort ongoing transfer (Interrupt mode).
		2473	* @param hspi SPI handle.
		2474	* @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
		2475	* started in Interrupt or DMA mode.
		2476	* This procedure performs following operations :
		2477	* - Disable SPI Interrupts (depending of transfer direction)
		2478	* - Disable the DMA transfer in the peripheral register (if enabled)
		2479	* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
		2480	* - Set handle State to READY
		2481	* - At abort completion, call user abort complete callback
		2482	* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
		2483	* considered as completed only when user abort complete callback is executed (not when exiting function).
		2484	* @retval HAL status
		2485	*/
		2486	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
		2487	{
		2488	HAL_StatusTypeDef errorcode;
		2489	uint32_t abortcplt ;
		2490	__IO uint32_t count;
		2491	__IO uint32_t resetcount;
		2492
		2493	/* Initialized local variable */
		2494	errorcode = HAL_OK;
		2495	abortcplt = 1U;
		2496	resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		2497	count = resetcount;
		2498
		2499	/* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
		2500	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
		2501
		2502	/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
		2503	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
		2504	{
		2505	hspi->TxISR = SPI_AbortTx_ISR;
		2506	/* Wait HAL_SPI_STATE_ABORT state */
		2507	do
		2508	{
		2509	if (count == 0U)
		2510	{
		2511	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2512	break;
		2513	}
		2514	count--;
		2515	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2516	/* Reset Timeout Counter */
		2517	count = resetcount;
		2518	}
		2519
		2520	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		2521	{
		2522	hspi->RxISR = SPI_AbortRx_ISR;
		2523	/* Wait HAL_SPI_STATE_ABORT state */
		2524	do
		2525	{
		2526	if (count == 0U)
		2527	{
		2528	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2529	break;
		2530	}
		2531	count--;
		2532	} while (hspi->State != HAL_SPI_STATE_ABORT);
		2533	/* Reset Timeout Counter */
		2534	count = resetcount;
		2535	}
		2536
		2537	/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
		2538	before any call to DMA Abort functions */
		2539	/* DMA Tx Handle is valid */
		2540	if (hspi->hdmatx != NULL)
		2541	{
		2542	/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
		2543	Otherwise, set it to NULL */
		2544	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2545	{
		2546	hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
		2547	}
		2548	else
		2549	{
		2550	hspi->hdmatx->XferAbortCallback = NULL;
		2551	}
		2552	}
		2553	/* DMA Rx Handle is valid */
		2554	if (hspi->hdmarx != NULL)
		2555	{
		2556	/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
		2557	Otherwise, set it to NULL */
		2558	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2559	{
		2560	hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
		2561	}
		2562	else
		2563	{
		2564	hspi->hdmarx->XferAbortCallback = NULL;
		2565	}
		2566	}
		2567
		2568	/* Disable the SPI DMA Tx request if enabled */
		2569	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
		2570	{
		2571	/* Abort the SPI DMA Tx Stream/Channel */
		2572	if (hspi->hdmatx != NULL)
		2573	{
		2574	/* Abort DMA Tx Handle linked to SPI Peripheral */
		2575	if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
		2576	{
		2577	hspi->hdmatx->XferAbortCallback = NULL;
		2578	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2579	}
		2580	else
		2581	{
		2582	abortcplt = 0U;
		2583	}
		2584	}
		2585	}
		2586	/* Disable the SPI DMA Rx request if enabled */
		2587	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
		2588	{
		2589	/* Abort the SPI DMA Rx Stream/Channel */
		2590	if (hspi->hdmarx != NULL)
		2591	{
		2592	/* Abort DMA Rx Handle linked to SPI Peripheral */
		2593	if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
		2594	{
		2595	hspi->hdmarx->XferAbortCallback = NULL;
		2596	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		2597	}
		2598	else
		2599	{
		2600	abortcplt = 0U;
		2601	}
		2602	}
		2603	}
		2604
		2605	if (abortcplt == 1U)
		2606	{
		2607	/* Reset Tx and Rx transfer counters */
		2608	hspi->RxXferCount = 0U;
		2609	hspi->TxXferCount = 0U;
		2610
		2611	/* Check error during Abort procedure */
		2612	if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
		2613	{
		2614	/* return HAL_Error in case of error during Abort procedure */
		2615	errorcode = HAL_ERROR;
		2616	}
		2617	else
		2618	{
		2619	/* Reset errorCode */
		2620	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		2621	}
		2622
		2623	/* Clear the Error flags in the SR register */
		2624	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2625	__HAL_SPI_CLEAR_FREFLAG(hspi);
		2626
		2627	/* Restore hspi->State to Ready */
		2628	hspi->State = HAL_SPI_STATE_READY;
		2629
		2630	/* As no DMA to be aborted, call directly user Abort complete callback */
		2631	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2632	hspi->AbortCpltCallback(hspi);
		2633	#else
		2634	HAL_SPI_AbortCpltCallback(hspi);
		2635	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2636	}
		2637
		2638	return errorcode;
		2639	}
		2640
		2641	/**
		2642	* @brief Pause the DMA Transfer.
		2643	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2644	* the configuration information for the specified SPI module.
		2645	* @retval HAL status
		2646	*/
		2647	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
		2648	{
		2649	/* Process Locked */
		2650	__HAL_LOCK(hspi);
		2651
		2652	/* Disable the SPI DMA Tx & Rx requests */
		2653	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2654
		2655	/* Process Unlocked */
		2656	__HAL_UNLOCK(hspi);
		2657
		2658	return HAL_OK;
		2659	}
		2660
		2661	/**
		2662	* @brief Resume the DMA Transfer.
		2663	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2664	* the configuration information for the specified SPI module.
		2665	* @retval HAL status
		2666	*/
		2667	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
		2668	{
		2669	/* Process Locked */
		2670	__HAL_LOCK(hspi);
		2671
		2672	/* Enable the SPI DMA Tx & Rx requests */
		2673	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2674
		2675	/* Process Unlocked */
		2676	__HAL_UNLOCK(hspi);
		2677
		2678	return HAL_OK;
		2679	}
		2680
		2681	/**
		2682	* @brief Stop the DMA Transfer.
		2683	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2684	* the configuration information for the specified SPI module.
		2685	* @retval HAL status
		2686	*/
		2687	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
		2688	{
		2689	HAL_StatusTypeDef errorcode = HAL_OK;
		2690	/* The Lock is not implemented on this API to allow the user application
		2691	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
		2692	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
		2693	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
		2694	*/
		2695
		2696	/* Abort the SPI DMA tx Stream/Channel */
		2697	if (hspi->hdmatx != NULL)
		2698	{
		2699	if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
		2700	{
		2701	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2702	errorcode = HAL_ERROR;
		2703	}
		2704	}
		2705	/* Abort the SPI DMA rx Stream/Channel */
		2706	if (hspi->hdmarx != NULL)
		2707	{
		2708	if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
		2709	{
		2710	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		2711	errorcode = HAL_ERROR;
		2712	}
		2713	}
		2714
		2715	/* Disable the SPI DMA Tx & Rx requests */
		2716	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		2717	hspi->State = HAL_SPI_STATE_READY;
		2718	return errorcode;
		2719	}
		2720
		2721	/**
		2722	* @brief Handle SPI interrupt request.
		2723	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2724	* the configuration information for the specified SPI module.
		2725	* @retval None
		2726	*/
		2727	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
		2728	{
		2729	uint32_t itsource = hspi->Instance->CR2;
		2730	uint32_t itflag = hspi->Instance->SR;
		2731
		2732	/* SPI in mode Receiver ----------------------------------------------------*/
		2733	if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
		2734	(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
		2735	{
		2736	hspi->RxISR(hspi);
		2737	return;
		2738	}
		2739
		2740	/* SPI in mode Transmitter -------------------------------------------------*/
		2741	if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
		2742	{
		2743	hspi->TxISR(hspi);
		2744	return;
		2745	}
		2746
		2747	/* SPI in Error Treatment --------------------------------------------------*/
		2748	if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) \|\| (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
		2749	\|\| (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
		2750	{
		2751	/* SPI Overrun error interrupt occurred ----------------------------------*/
		2752	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
		2753	{
		2754	if (hspi->State != HAL_SPI_STATE_BUSY_TX)
		2755	{
		2756	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
		2757	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2758	}
		2759	else
		2760	{
		2761	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		2762	return;
		2763	}
		2764	}
		2765
		2766	/* SPI Mode Fault error interrupt occurred -------------------------------*/
		2767	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
		2768	{
		2769	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
		2770	__HAL_SPI_CLEAR_MODFFLAG(hspi);
		2771	}
		2772
		2773	/* SPI Frame error interrupt occurred ------------------------------------*/
		2774	if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
		2775	{
		2776	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
		2777	__HAL_SPI_CLEAR_FREFLAG(hspi);
		2778	}
		2779
		2780	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		2781	{
		2782	/* Disable all interrupts */
		2783	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
		2784
		2785	hspi->State = HAL_SPI_STATE_READY;
		2786	/* Disable the SPI DMA requests if enabled */
		2787	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) \|\| (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
		2788	{
		2789	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
		2790
		2791	/* Abort the SPI DMA Rx channel */
		2792	if (hspi->hdmarx != NULL)
		2793	{
		2794	/* Set the SPI DMA Abort callback :
		2795	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2796	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
		2797	if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
		2798	{
		2799	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2800	}
		2801	}
		2802	/* Abort the SPI DMA Tx channel */
		2803	if (hspi->hdmatx != NULL)
		2804	{
		2805	/* Set the SPI DMA Abort callback :
		2806	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
		2807	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
		2808	if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
		2809	{
		2810	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		2811	}
		2812	}
		2813	}
		2814	else
		2815	{
		2816	/* Call user error callback */
		2817	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		2818	hspi->ErrorCallback(hspi);
		2819	#else
		2820	HAL_SPI_ErrorCallback(hspi);
		2821	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		2822	}
		2823	}
		2824	return;
		2825	}
		2826	}
		2827
		2828	/**
		2829	* @brief Tx Transfer completed callback.
		2830	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2831	* the configuration information for SPI module.
		2832	* @retval None
		2833	*/
		2834	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
		2835	{
		2836	/* Prevent unused argument(s) compilation warning */
		2837	UNUSED(hspi);
		2838
		2839	/* NOTE : This function should not be modified, when the callback is needed,
		2840	the HAL_SPI_TxCpltCallback should be implemented in the user file
		2841	*/
		2842	}
		2843
		2844	/**
		2845	* @brief Rx Transfer completed callback.
		2846	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2847	* the configuration information for SPI module.
		2848	* @retval None
		2849	*/
		2850	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
		2851	{
		2852	/* Prevent unused argument(s) compilation warning */
		2853	UNUSED(hspi);
		2854
		2855	/* NOTE : This function should not be modified, when the callback is needed,
		2856	the HAL_SPI_RxCpltCallback should be implemented in the user file
		2857	*/
		2858	}
		2859
		2860	/**
		2861	* @brief Tx and Rx Transfer completed callback.
		2862	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2863	* the configuration information for SPI module.
		2864	* @retval None
		2865	*/
		2866	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
		2867	{
		2868	/* Prevent unused argument(s) compilation warning */
		2869	UNUSED(hspi);
		2870
		2871	/* NOTE : This function should not be modified, when the callback is needed,
		2872	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
		2873	*/
		2874	}
		2875
		2876	/**
		2877	* @brief Tx Half Transfer completed callback.
		2878	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2879	* the configuration information for SPI module.
		2880	* @retval None
		2881	*/
		2882	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2883	{
		2884	/* Prevent unused argument(s) compilation warning */
		2885	UNUSED(hspi);
		2886
		2887	/* NOTE : This function should not be modified, when the callback is needed,
		2888	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
		2889	*/
		2890	}
		2891
		2892	/**
		2893	* @brief Rx Half Transfer completed callback.
		2894	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2895	* the configuration information for SPI module.
		2896	* @retval None
		2897	*/
		2898	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2899	{
		2900	/* Prevent unused argument(s) compilation warning */
		2901	UNUSED(hspi);
		2902
		2903	/* NOTE : This function should not be modified, when the callback is needed,
		2904	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
		2905	*/
		2906	}
		2907
		2908	/**
		2909	* @brief Tx and Rx Half Transfer callback.
		2910	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2911	* the configuration information for SPI module.
		2912	* @retval None
		2913	*/
		2914	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
		2915	{
		2916	/* Prevent unused argument(s) compilation warning */
		2917	UNUSED(hspi);
		2918
		2919	/* NOTE : This function should not be modified, when the callback is needed,
		2920	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
		2921	*/
		2922	}
		2923
		2924	/**
		2925	* @brief SPI error callback.
		2926	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2927	* the configuration information for SPI module.
		2928	* @retval None
		2929	*/
		2930	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
		2931	{
		2932	/* Prevent unused argument(s) compilation warning */
		2933	UNUSED(hspi);
		2934
		2935	/* NOTE : This function should not be modified, when the callback is needed,
		2936	the HAL_SPI_ErrorCallback should be implemented in the user file
		2937	*/
		2938	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
		2939	and user can use HAL_SPI_GetError() API to check the latest error occurred
		2940	*/
		2941	}
		2942
		2943	/**
		2944	* @brief SPI Abort Complete callback.
		2945	* @param hspi SPI handle.
		2946	* @retval None
		2947	*/
		2948	__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
		2949	{
		2950	/* Prevent unused argument(s) compilation warning */
		2951	UNUSED(hspi);
		2952
		2953	/* NOTE : This function should not be modified, when the callback is needed,
		2954	the HAL_SPI_AbortCpltCallback can be implemented in the user file.
		2955	*/
		2956	}
		2957
		2958	/**
		2959	* @}
		2960	*/
		2961
		2962	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
		2963	* @brief SPI control functions
		2964	*
		2965	@verbatim
		2966	===============================================================================
		2967	##### Peripheral State and Errors functions #####
		2968	===============================================================================
		2969	[..]
		2970	This subsection provides a set of functions allowing to control the SPI.
		2971	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
		2972	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
		2973	@endverbatim
		2974	* @{
		2975	*/
		2976
		2977	/**
		2978	* @brief Return the SPI handle state.
		2979	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2980	* the configuration information for SPI module.
		2981	* @retval SPI state
		2982	*/
		2983	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
		2984	{
		2985	/* Return SPI handle state */
		2986	return hspi->State;
		2987	}
		2988
		2989	/**
		2990	* @brief Return the SPI error code.
		2991	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		2992	* the configuration information for SPI module.
		2993	* @retval SPI error code in bitmap format
		2994	*/
		2995	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
		2996	{
		2997	/* Return SPI ErrorCode */
		2998	return hspi->ErrorCode;
		2999	}
		3000
		3001	/**
		3002	* @}
		3003	*/
		3004
		3005	/**
		3006	* @}
		3007	*/
		3008
		3009	/** @addtogroup SPI_Private_Functions
		3010	* @brief Private functions
		3011	* @{
		3012	*/
		3013
		3014	/**
		3015	* @brief DMA SPI transmit process complete callback.
		3016	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3017	* the configuration information for the specified DMA module.
		3018	* @retval None
		3019	*/
		3020	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
		3021	{
		3022	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3023	uint32_t tickstart;
		3024
		3025	/* Init tickstart for timeout management*/
		3026	tickstart = HAL_GetTick();
		3027
		3028	/* DMA Normal Mode */
		3029	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		3030	{
		3031	/* Disable ERR interrupt */
		3032	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		3033
		3034	/* Disable Tx DMA Request */
		3035	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		3036
		3037	/* Check the end of the transaction */
		3038	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3039	{
		3040	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3041	}
		3042
		3043	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
		3044	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		3045	{
		3046	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3047	}
		3048
		3049	hspi->TxXferCount = 0U;
		3050	hspi->State = HAL_SPI_STATE_READY;
		3051
		3052	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		3053	{
		3054	/* Call user error callback */
		3055	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3056	hspi->ErrorCallback(hspi);
		3057	#else
		3058	HAL_SPI_ErrorCallback(hspi);
		3059	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3060	return;
		3061	}
		3062	}
		3063	/* Call user Tx complete callback */
		3064	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3065	hspi->TxCpltCallback(hspi);
		3066	#else
		3067	HAL_SPI_TxCpltCallback(hspi);
		3068	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3069	}
		3070
		3071	/**
		3072	* @brief DMA SPI receive process complete callback.
		3073	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3074	* the configuration information for the specified DMA module.
		3075	* @retval None
		3076	*/
		3077	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
		3078	{
		3079	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3080	uint32_t tickstart;
		3081
		3082	/* Init tickstart for timeout management*/
		3083	tickstart = HAL_GetTick();
		3084
		3085	/* DMA Normal Mode */
		3086	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		3087	{
		3088	/* Disable ERR interrupt */
		3089	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		3090
		3091	#if (USE_SPI_CRC != 0U)
		3092	/* CRC handling */
		3093	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3094	{
		3095	/* Wait until RXNE flag */
		3096	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3097	{
		3098	/* Error on the CRC reception */
		3099	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3100	}
		3101	/* Read CRC */
		3102	if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
		3103	{
		3104	/* Read 16bit CRC */
		3105	READ_REG(hspi->Instance->DR);
		3106	}
		3107	else
		3108	{
		3109	/* Read 8bit CRC */
		3110	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3111
		3112	if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
		3113	{
		3114	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3115	{
		3116	/* Error on the CRC reception */
		3117	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3118	}
		3119	/* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
		3120	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3121	}
		3122	}
		3123	}
		3124	#endif /* USE_SPI_CRC */
		3125
		3126	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
		3127	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		3128
		3129	/* Check the end of the transaction */
		3130	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3131	{
		3132	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
		3133	}
		3134
		3135	hspi->RxXferCount = 0U;
		3136	hspi->State = HAL_SPI_STATE_READY;
		3137
		3138	#if (USE_SPI_CRC != 0U)
		3139	/* Check if CRC error occurred */
		3140	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
		3141	{
		3142	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3143	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3144	}
		3145	#endif /* USE_SPI_CRC */
		3146
		3147	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		3148	{
		3149	/* Call user error callback */
		3150	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3151	hspi->ErrorCallback(hspi);
		3152	#else
		3153	HAL_SPI_ErrorCallback(hspi);
		3154	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3155	return;
		3156	}
		3157	}
		3158	/* Call user Rx complete callback */
		3159	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3160	hspi->RxCpltCallback(hspi);
		3161	#else
		3162	HAL_SPI_RxCpltCallback(hspi);
		3163	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3164	}
		3165
		3166	/**
		3167	* @brief DMA SPI transmit receive process complete callback.
		3168	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3169	* the configuration information for the specified DMA module.
		3170	* @retval None
		3171	*/
		3172	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		3173	{
		3174	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3175	uint32_t tickstart;
		3176
		3177	/* Init tickstart for timeout management*/
		3178	tickstart = HAL_GetTick();
		3179
		3180	/* DMA Normal Mode */
		3181	if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
		3182	{
		3183	/* Disable ERR interrupt */
		3184	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		3185
		3186	#if (USE_SPI_CRC != 0U)
		3187	/* CRC handling */
		3188	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3189	{
		3190	if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
		3191	{
		3192	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
		3193	tickstart) != HAL_OK)
		3194	{
		3195	/* Error on the CRC reception */
		3196	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3197	}
		3198	/* Read CRC to Flush DR and RXNE flag */
		3199	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3200	}
		3201	else
		3202	{
		3203	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3204	{
		3205	/* Error on the CRC reception */
		3206	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3207	}
		3208	/* Read CRC to Flush DR and RXNE flag */
		3209	READ_REG(hspi->Instance->DR);
		3210	}
		3211	}
		3212	#endif /* USE_SPI_CRC */
		3213
		3214	/* Check the end of the transaction */
		3215	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		3216	{
		3217	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3218	}
		3219
		3220	/* Disable Rx/Tx DMA Request */
		3221	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		3222
		3223	hspi->TxXferCount = 0U;
		3224	hspi->RxXferCount = 0U;
		3225	hspi->State = HAL_SPI_STATE_READY;
		3226
		3227	#if (USE_SPI_CRC != 0U)
		3228	/* Check if CRC error occurred */
		3229	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
		3230	{
		3231	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		3232	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		3233	}
		3234	#endif /* USE_SPI_CRC */
		3235
		3236	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		3237	{
		3238	/* Call user error callback */
		3239	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3240	hspi->ErrorCallback(hspi);
		3241	#else
		3242	HAL_SPI_ErrorCallback(hspi);
		3243	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3244	return;
		3245	}
		3246	}
		3247	/* Call user TxRx complete callback */
		3248	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3249	hspi->TxRxCpltCallback(hspi);
		3250	#else
		3251	HAL_SPI_TxRxCpltCallback(hspi);
		3252	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3253	}
		3254
		3255	/**
		3256	* @brief DMA SPI half transmit process complete callback.
		3257	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3258	* the configuration information for the specified DMA module.
		3259	* @retval None
		3260	*/
		3261	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
		3262	{
		3263	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3264
		3265	/* Call user Tx half complete callback */
		3266	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3267	hspi->TxHalfCpltCallback(hspi);
		3268	#else
		3269	HAL_SPI_TxHalfCpltCallback(hspi);
		3270	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3271	}
		3272
		3273	/**
		3274	* @brief DMA SPI half receive process complete callback
		3275	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3276	* the configuration information for the specified DMA module.
		3277	* @retval None
		3278	*/
		3279	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
		3280	{
		3281	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3282
		3283	/* Call user Rx half complete callback */
		3284	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3285	hspi->RxHalfCpltCallback(hspi);
		3286	#else
		3287	HAL_SPI_RxHalfCpltCallback(hspi);
		3288	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3289	}
		3290
		3291	/**
		3292	* @brief DMA SPI half transmit receive process complete callback.
		3293	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3294	* the configuration information for the specified DMA module.
		3295	* @retval None
		3296	*/
		3297	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
		3298	{
		3299	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3300
		3301	/* Call user TxRx half complete callback */
		3302	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3303	hspi->TxRxHalfCpltCallback(hspi);
		3304	#else
		3305	HAL_SPI_TxRxHalfCpltCallback(hspi);
		3306	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3307	}
		3308
		3309	/**
		3310	* @brief DMA SPI communication error callback.
		3311	* @param hdma pointer to a DMA_HandleTypeDef structure that contains
		3312	* the configuration information for the specified DMA module.
		3313	* @retval None
		3314	*/
		3315	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
		3316	{
		3317	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3318
		3319	/* Stop the disable DMA transfer on SPI side */
		3320	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
		3321
		3322	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
		3323	hspi->State = HAL_SPI_STATE_READY;
		3324	/* Call user error callback */
		3325	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3326	hspi->ErrorCallback(hspi);
		3327	#else
		3328	HAL_SPI_ErrorCallback(hspi);
		3329	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3330	}
		3331
		3332	/**
		3333	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
		3334	* (To be called at end of DMA Abort procedure following error occurrence).
		3335	* @param hdma DMA handle.
		3336	* @retval None
		3337	*/
		3338	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
		3339	{
		3340	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3341	hspi->RxXferCount = 0U;
		3342	hspi->TxXferCount = 0U;
		3343
		3344	/* Call user error callback */
		3345	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3346	hspi->ErrorCallback(hspi);
		3347	#else
		3348	HAL_SPI_ErrorCallback(hspi);
		3349	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3350	}
		3351
		3352	/**
		3353	* @brief DMA SPI Tx communication abort callback, when initiated by user
		3354	* (To be called at end of DMA Tx Abort procedure following user abort request).
		3355	* @note When this callback is executed, User Abort complete call back is called only if no
		3356	* Abort still ongoing for Rx DMA Handle.
		3357	* @param hdma DMA handle.
		3358	* @retval None
		3359	*/
		3360	static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
		3361	{
		3362	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3363
		3364	hspi->hdmatx->XferAbortCallback = NULL;
		3365
		3366	/* Disable Tx DMA Request */
		3367	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
		3368
		3369	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3370	{
		3371	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		3372	}
		3373
		3374	/* Disable SPI Peripheral */
		3375	__HAL_SPI_DISABLE(hspi);
		3376
		3377	/* Empty the FRLVL fifo */
		3378	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3379	{
		3380	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		3381	}
		3382
		3383	/* Check if an Abort process is still ongoing */
		3384	if (hspi->hdmarx != NULL)
		3385	{
		3386	if (hspi->hdmarx->XferAbortCallback != NULL)
		3387	{
		3388	return;
		3389	}
		3390	}
		3391
		3392	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
		3393	hspi->RxXferCount = 0U;
		3394	hspi->TxXferCount = 0U;
		3395
		3396	/* Check no error during Abort procedure */
		3397	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
		3398	{
		3399	/* Reset errorCode */
		3400	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		3401	}
		3402
		3403	/* Clear the Error flags in the SR register */
		3404	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3405	__HAL_SPI_CLEAR_FREFLAG(hspi);
		3406
		3407	/* Restore hspi->State to Ready */
		3408	hspi->State = HAL_SPI_STATE_READY;
		3409
		3410	/* Call user Abort complete callback */
		3411	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3412	hspi->AbortCpltCallback(hspi);
		3413	#else
		3414	HAL_SPI_AbortCpltCallback(hspi);
		3415	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3416	}
		3417
		3418	/**
		3419	* @brief DMA SPI Rx communication abort callback, when initiated by user
		3420	* (To be called at end of DMA Rx Abort procedure following user abort request).
		3421	* @note When this callback is executed, User Abort complete call back is called only if no
		3422	* Abort still ongoing for Tx DMA Handle.
		3423	* @param hdma DMA handle.
		3424	* @retval None
		3425	*/
		3426	static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
		3427	{
		3428	SPI_HandleTypeDef hspi = (SPI_HandleTypeDef )(((DMA_HandleTypeDef )hdma)->Parent); / Derogation MISRAC2012-Rule-11.5 */
		3429
		3430	/* Disable SPI Peripheral */
		3431	__HAL_SPI_DISABLE(hspi);
		3432
		3433	hspi->hdmarx->XferAbortCallback = NULL;
		3434
		3435	/* Disable Rx DMA Request */
		3436	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
		3437
		3438	/* Control the BSY flag */
		3439	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3440	{
		3441	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		3442	}
		3443
		3444	/* Empty the FRLVL fifo */
		3445	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		3446	{
		3447	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		3448	}
		3449
		3450	/* Check if an Abort process is still ongoing */
		3451	if (hspi->hdmatx != NULL)
		3452	{
		3453	if (hspi->hdmatx->XferAbortCallback != NULL)
		3454	{
		3455	return;
		3456	}
		3457	}
		3458
		3459	/* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
		3460	hspi->RxXferCount = 0U;
		3461	hspi->TxXferCount = 0U;
		3462
		3463	/* Check no error during Abort procedure */
		3464	if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
		3465	{
		3466	/* Reset errorCode */
		3467	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
		3468	}
		3469
		3470	/* Clear the Error flags in the SR register */
		3471	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		3472	__HAL_SPI_CLEAR_FREFLAG(hspi);
		3473
		3474	/* Restore hspi->State to Ready */
		3475	hspi->State = HAL_SPI_STATE_READY;
		3476
		3477	/* Call user Abort complete callback */
		3478	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		3479	hspi->AbortCpltCallback(hspi);
		3480	#else
		3481	HAL_SPI_AbortCpltCallback(hspi);
		3482	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		3483	}
		3484
		3485	/**
		3486	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		3487	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3488	* the configuration information for SPI module.
		3489	* @retval None
		3490	*/
		3491	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3492	{
		3493	/* Receive data in packing mode */
		3494	if (hspi->RxXferCount > 1U)
		3495	{
		3496	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3497	hspi->pRxBuffPtr += sizeof(uint16_t);
		3498	hspi->RxXferCount -= 2U;
		3499	if (hspi->RxXferCount == 1U)
		3500	{
		3501	/* Set RX Fifo threshold according the reception data length: 8bit */
		3502	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		3503	}
		3504	}
		3505	/* Receive data in 8 Bit mode */
		3506	else
		3507	{
		3508	hspi->pRxBuffPtr = ((__IO uint8_t *)&hspi->Instance->DR);
		3509	hspi->pRxBuffPtr++;
		3510	hspi->RxXferCount--;
		3511	}
		3512
		3513	/* Check end of the reception */
		3514	if (hspi->RxXferCount == 0U)
		3515	{
		3516	#if (USE_SPI_CRC != 0U)
		3517	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3518	{
		3519	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
		3520	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
		3521	return;
		3522	}
		3523	#endif /* USE_SPI_CRC */
		3524
		3525	/* Disable RXNE and ERR interrupt */
		3526	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3527
		3528	if (hspi->TxXferCount == 0U)
		3529	{
		3530	SPI_CloseRxTx_ISR(hspi);
		3531	}
		3532	}
		3533	}
		3534
		3535	#if (USE_SPI_CRC != 0U)
		3536	/**
		3537	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
		3538	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3539	* the configuration information for SPI module.
		3540	* @retval None
		3541	*/
		3542	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		3543	{
		3544	/* Read 8bit CRC to flush Data Regsiter */
		3545	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3546
		3547	hspi->CRCSize--;
		3548
		3549	/* Check end of the reception */
		3550	if (hspi->CRCSize == 0U)
		3551	{
		3552	/* Disable RXNE and ERR interrupt */
		3553	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3554
		3555	if (hspi->TxXferCount == 0U)
		3556	{
		3557	SPI_CloseRxTx_ISR(hspi);
		3558	}
		3559	}
		3560	}
		3561	#endif /* USE_SPI_CRC */
		3562
		3563	/**
		3564	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
		3565	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3566	* the configuration information for SPI module.
		3567	* @retval None
		3568	*/
		3569	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3570	{
		3571	/* Transmit data in packing Bit mode */
		3572	if (hspi->TxXferCount >= 2U)
		3573	{
		3574	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3575	hspi->pTxBuffPtr += sizeof(uint16_t);
		3576	hspi->TxXferCount -= 2U;
		3577	}
		3578	/* Transmit data in 8 Bit mode */
		3579	else
		3580	{
		3581	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		3582	hspi->pTxBuffPtr++;
		3583	hspi->TxXferCount--;
		3584	}
		3585
		3586	/* Check the end of the transmission */
		3587	if (hspi->TxXferCount == 0U)
		3588	{
		3589	#if (USE_SPI_CRC != 0U)
		3590	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3591	{
		3592	/* Set CRC Next Bit to send CRC */
		3593	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3594	/* Disable TXE interrupt */
		3595	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3596	return;
		3597	}
		3598	#endif /* USE_SPI_CRC */
		3599
		3600	/* Disable TXE interrupt */
		3601	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3602
		3603	if (hspi->RxXferCount == 0U)
		3604	{
		3605	SPI_CloseRxTx_ISR(hspi);
		3606	}
		3607	}
		3608	}
		3609
		3610	/**
		3611	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
		3612	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3613	* the configuration information for SPI module.
		3614	* @retval None
		3615	*/
		3616	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3617	{
		3618	/* Receive data in 16 Bit mode */
		3619	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3620	hspi->pRxBuffPtr += sizeof(uint16_t);
		3621	hspi->RxXferCount--;
		3622
		3623	if (hspi->RxXferCount == 0U)
		3624	{
		3625	#if (USE_SPI_CRC != 0U)
		3626	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3627	{
		3628	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
		3629	return;
		3630	}
		3631	#endif /* USE_SPI_CRC */
		3632
		3633	/* Disable RXNE interrupt */
		3634	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		3635
		3636	if (hspi->TxXferCount == 0U)
		3637	{
		3638	SPI_CloseRxTx_ISR(hspi);
		3639	}
		3640	}
		3641	}
		3642
		3643	#if (USE_SPI_CRC != 0U)
		3644	/**
		3645	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
		3646	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3647	* the configuration information for SPI module.
		3648	* @retval None
		3649	*/
		3650	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		3651	{
		3652	/* Read 16bit CRC to flush Data Regsiter */
		3653	READ_REG(hspi->Instance->DR);
		3654
		3655	/* Disable RXNE interrupt */
		3656	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
		3657
		3658	SPI_CloseRxTx_ISR(hspi);
		3659	}
		3660	#endif /* USE_SPI_CRC */
		3661
		3662	/**
		3663	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
		3664	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3665	* the configuration information for SPI module.
		3666	* @retval None
		3667	*/
		3668	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3669	{
		3670	/* Transmit data in 16 Bit mode */
		3671	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3672	hspi->pTxBuffPtr += sizeof(uint16_t);
		3673	hspi->TxXferCount--;
		3674
		3675	/* Enable CRC Transmission */
		3676	if (hspi->TxXferCount == 0U)
		3677	{
		3678	#if (USE_SPI_CRC != 0U)
		3679	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3680	{
		3681	/* Set CRC Next Bit to send CRC */
		3682	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3683	/* Disable TXE interrupt */
		3684	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3685	return;
		3686	}
		3687	#endif /* USE_SPI_CRC */
		3688
		3689	/* Disable TXE interrupt */
		3690	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
		3691
		3692	if (hspi->RxXferCount == 0U)
		3693	{
		3694	SPI_CloseRxTx_ISR(hspi);
		3695	}
		3696	}
		3697	}
		3698
		3699	#if (USE_SPI_CRC != 0U)
		3700	/**
		3701	* @brief Manage the CRC 8-bit receive in Interrupt context.
		3702	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3703	* the configuration information for SPI module.
		3704	* @retval None
		3705	*/
		3706	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
		3707	{
		3708	/* Read 8bit CRC to flush Data Register */
		3709	READ_REG((__IO uint8_t )&hspi->Instance->DR);
		3710
		3711	hspi->CRCSize--;
		3712
		3713	if (hspi->CRCSize == 0U)
		3714	{
		3715	SPI_CloseRx_ISR(hspi);
		3716	}
		3717	}
		3718	#endif /* USE_SPI_CRC */
		3719
		3720	/**
		3721	* @brief Manage the receive 8-bit in Interrupt context.
		3722	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3723	* the configuration information for SPI module.
		3724	* @retval None
		3725	*/
		3726	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3727	{
		3728	hspi->pRxBuffPtr = ((__IO uint8_t *)&hspi->Instance->DR);
		3729	hspi->pRxBuffPtr++;
		3730	hspi->RxXferCount--;
		3731
		3732	#if (USE_SPI_CRC != 0U)
		3733	/* Enable CRC Transmission */
		3734	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		3735	{
		3736	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3737	}
		3738	#endif /* USE_SPI_CRC */
		3739
		3740	if (hspi->RxXferCount == 0U)
		3741	{
		3742	#if (USE_SPI_CRC != 0U)
		3743	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3744	{
		3745	hspi->RxISR = SPI_RxISR_8BITCRC;
		3746	return;
		3747	}
		3748	#endif /* USE_SPI_CRC */
		3749	SPI_CloseRx_ISR(hspi);
		3750	}
		3751	}
		3752
		3753	#if (USE_SPI_CRC != 0U)
		3754	/**
		3755	* @brief Manage the CRC 16-bit receive in Interrupt context.
		3756	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3757	* the configuration information for SPI module.
		3758	* @retval None
		3759	*/
		3760	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
		3761	{
		3762	/* Read 16bit CRC to flush Data Register */
		3763	READ_REG(hspi->Instance->DR);
		3764
		3765	/* Disable RXNE and ERR interrupt */
		3766	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		3767
		3768	SPI_CloseRx_ISR(hspi);
		3769	}
		3770	#endif /* USE_SPI_CRC */
		3771
		3772	/**
		3773	* @brief Manage the 16-bit receive in Interrupt context.
		3774	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3775	* the configuration information for SPI module.
		3776	* @retval None
		3777	*/
		3778	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3779	{
		3780	((uint16_t )hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
		3781	hspi->pRxBuffPtr += sizeof(uint16_t);
		3782	hspi->RxXferCount--;
		3783
		3784	#if (USE_SPI_CRC != 0U)
		3785	/* Enable CRC Transmission */
		3786	if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
		3787	{
		3788	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3789	}
		3790	#endif /* USE_SPI_CRC */
		3791
		3792	if (hspi->RxXferCount == 0U)
		3793	{
		3794	#if (USE_SPI_CRC != 0U)
		3795	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3796	{
		3797	hspi->RxISR = SPI_RxISR_16BITCRC;
		3798	return;
		3799	}
		3800	#endif /* USE_SPI_CRC */
		3801	SPI_CloseRx_ISR(hspi);
		3802	}
		3803	}
		3804
		3805	/**
		3806	* @brief Handle the data 8-bit transmit in Interrupt mode.
		3807	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3808	* the configuration information for SPI module.
		3809	* @retval None
		3810	*/
		3811	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
		3812	{
		3813	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr);
		3814	hspi->pTxBuffPtr++;
		3815	hspi->TxXferCount--;
		3816
		3817	if (hspi->TxXferCount == 0U)
		3818	{
		3819	#if (USE_SPI_CRC != 0U)
		3820	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3821	{
		3822	/* Enable CRC Transmission */
		3823	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3824	}
		3825	#endif /* USE_SPI_CRC */
		3826	SPI_CloseTx_ISR(hspi);
		3827	}
		3828	}
		3829
		3830	/**
		3831	* @brief Handle the data 16-bit transmit in Interrupt mode.
		3832	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3833	* the configuration information for SPI module.
		3834	* @retval None
		3835	*/
		3836	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
		3837	{
		3838	/* Transmit data in 16 Bit mode */
		3839	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
		3840	hspi->pTxBuffPtr += sizeof(uint16_t);
		3841	hspi->TxXferCount--;
		3842
		3843	if (hspi->TxXferCount == 0U)
		3844	{
		3845	#if (USE_SPI_CRC != 0U)
		3846	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3847	{
		3848	/* Enable CRC Transmission */
		3849	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
		3850	}
		3851	#endif /* USE_SPI_CRC */
		3852	SPI_CloseTx_ISR(hspi);
		3853	}
		3854	}
		3855
		3856	/**
		3857	* @brief Handle SPI Communication Timeout.
		3858	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3859	* the configuration information for SPI module.
		3860	* @param Flag SPI flag to check
		3861	* @param State flag state to check
		3862	* @param Timeout Timeout duration
		3863	* @param Tickstart tick start value
		3864	* @retval HAL status
		3865	*/
		3866	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
		3867	uint32_t Timeout, uint32_t Tickstart)
		3868	{
		3869	while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
		3870	{
		3871	if (Timeout != HAL_MAX_DELAY)
		3872	{
		3873	if (((HAL_GetTick() - Tickstart) >= Timeout) \|\| (Timeout == 0U))
		3874	{
		3875	/* Disable the SPI and reset the CRC: the CRC value should be cleared
		3876	on both master and slave sides in order to resynchronize the master
		3877	and slave for their respective CRC calculation */
		3878
		3879	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
		3880	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		3881
		3882	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3883	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3884	{
		3885	/* Disable SPI peripheral */
		3886	__HAL_SPI_DISABLE(hspi);
		3887	}
		3888
		3889	/* Reset CRC Calculation */
		3890	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3891	{
		3892	SPI_RESET_CRC(hspi);
		3893	}
		3894
		3895	hspi->State = HAL_SPI_STATE_READY;
		3896
		3897	/* Process Unlocked */
		3898	__HAL_UNLOCK(hspi);
		3899
		3900	return HAL_TIMEOUT;
		3901	}
		3902	}
		3903	}
		3904
		3905	return HAL_OK;
		3906	}
		3907
		3908	/**
		3909	* @brief Handle SPI FIFO Communication Timeout.
		3910	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3911	* the configuration information for SPI module.
		3912	* @param Fifo Fifo to check
		3913	* @param State Fifo state to check
		3914	* @param Timeout Timeout duration
		3915	* @param Tickstart tick start value
		3916	* @retval HAL status
		3917	*/
		3918	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
		3919	uint32_t Timeout, uint32_t Tickstart)
		3920	{
		3921	while ((hspi->Instance->SR & Fifo) != State)
		3922	{
		3923	if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
		3924	{
		3925	/* Read 8bit CRC to flush Data Register */
		3926	READ_REG(((__IO uint8_t )&hspi->Instance->DR));
		3927	}
		3928
		3929	if (Timeout != HAL_MAX_DELAY)
		3930	{
		3931	if (((HAL_GetTick() - Tickstart) >= Timeout) \|\| (Timeout == 0U))
		3932	{
		3933	/* Disable the SPI and reset the CRC: the CRC value should be cleared
		3934	on both master and slave sides in order to resynchronize the master
		3935	and slave for their respective CRC calculation */
		3936
		3937	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
		3938	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
		3939
		3940	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3941	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3942	{
		3943	/* Disable SPI peripheral */
		3944	__HAL_SPI_DISABLE(hspi);
		3945	}
		3946
		3947	/* Reset CRC Calculation */
		3948	if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
		3949	{
		3950	SPI_RESET_CRC(hspi);
		3951	}
		3952
		3953	hspi->State = HAL_SPI_STATE_READY;
		3954
		3955	/* Process Unlocked */
		3956	__HAL_UNLOCK(hspi);
		3957
		3958	return HAL_TIMEOUT;
		3959	}
		3960	}
		3961	}
		3962
		3963	return HAL_OK;
		3964	}
		3965
		3966	/**
		3967	* @brief Handle the check of the RX transaction complete.
		3968	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		3969	* the configuration information for SPI module.
		3970	* @param Timeout Timeout duration
		3971	* @param Tickstart tick start value
		3972	* @retval HAL status
		3973	*/
		3974	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		3975	{
		3976	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3977	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3978	{
		3979	/* Disable SPI peripheral */
		3980	__HAL_SPI_DISABLE(hspi);
		3981	}
		3982
		3983	/* Control the BSY flag */
		3984	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		3985	{
		3986	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3987	return HAL_TIMEOUT;
		3988	}
		3989
		3990	if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
		3991	\|\| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
		3992	{
		3993	/* Empty the FRLVL fifo */
		3994	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
		3995	{
		3996	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		3997	return HAL_TIMEOUT;
		3998	}
		3999	}
		4000	return HAL_OK;
		4001	}
		4002
		4003	/**
		4004	* @brief Handle the check of the RXTX or TX transaction complete.
		4005	* @param hspi SPI handle
		4006	* @param Timeout Timeout duration
		4007	* @param Tickstart tick start value
		4008	* @retval HAL status
		4009	*/
		4010	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
		4011	{
		4012	/* Control if the TX fifo is empty */
		4013	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
		4014	{
		4015	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		4016	return HAL_TIMEOUT;
		4017	}
		4018
		4019	/* Control the BSY flag */
		4020	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
		4021	{
		4022	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		4023	return HAL_TIMEOUT;
		4024	}
		4025
		4026	/* Control if the RX fifo is empty */
		4027	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
		4028	{
		4029	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		4030	return HAL_TIMEOUT;
		4031	}
		4032
		4033	return HAL_OK;
		4034	}
		4035
		4036	/**
		4037	* @brief Handle the end of the RXTX transaction.
		4038	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		4039	* the configuration information for SPI module.
		4040	* @retval None
		4041	*/
		4042	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
		4043	{
		4044	uint32_t tickstart;
		4045
		4046	/* Init tickstart for timeout managment*/
		4047	tickstart = HAL_GetTick();
		4048
		4049	/* Disable ERR interrupt */
		4050	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
		4051
		4052	/* Check the end of the transaction */
		4053	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		4054	{
		4055	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		4056	}
		4057
		4058	#if (USE_SPI_CRC != 0U)
		4059	/* Check if CRC error occurred */
		4060	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		4061	{
		4062	hspi->State = HAL_SPI_STATE_READY;
		4063	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		4064	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		4065	/* Call user error callback */
		4066	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4067	hspi->ErrorCallback(hspi);
		4068	#else
		4069	HAL_SPI_ErrorCallback(hspi);
		4070	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4071	}
		4072	else
		4073	{
		4074	#endif /* USE_SPI_CRC */
		4075	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		4076	{
		4077	if (hspi->State == HAL_SPI_STATE_BUSY_RX)
		4078	{
		4079	hspi->State = HAL_SPI_STATE_READY;
		4080	/* Call user Rx complete callback */
		4081	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4082	hspi->RxCpltCallback(hspi);
		4083	#else
		4084	HAL_SPI_RxCpltCallback(hspi);
		4085	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4086	}
		4087	else
		4088	{
		4089	hspi->State = HAL_SPI_STATE_READY;
		4090	/* Call user TxRx complete callback */
		4091	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4092	hspi->TxRxCpltCallback(hspi);
		4093	#else
		4094	HAL_SPI_TxRxCpltCallback(hspi);
		4095	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4096	}
		4097	}
		4098	else
		4099	{
		4100	hspi->State = HAL_SPI_STATE_READY;
		4101	/* Call user error callback */
		4102	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4103	hspi->ErrorCallback(hspi);
		4104	#else
		4105	HAL_SPI_ErrorCallback(hspi);
		4106	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4107	}
		4108	#if (USE_SPI_CRC != 0U)
		4109	}
		4110	#endif /* USE_SPI_CRC */
		4111	}
		4112
		4113	/**
		4114	* @brief Handle the end of the RX transaction.
		4115	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		4116	* the configuration information for SPI module.
		4117	* @retval None
		4118	*/
		4119	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
		4120	{
		4121	/* Disable RXNE and ERR interrupt */
		4122	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
		4123
		4124	/* Check the end of the transaction */
		4125	if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4126	{
		4127	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		4128	}
		4129	hspi->State = HAL_SPI_STATE_READY;
		4130
		4131	#if (USE_SPI_CRC != 0U)
		4132	/* Check if CRC error occurred */
		4133	if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
		4134	{
		4135	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
		4136	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
		4137	/* Call user error callback */
		4138	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4139	hspi->ErrorCallback(hspi);
		4140	#else
		4141	HAL_SPI_ErrorCallback(hspi);
		4142	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4143	}
		4144	else
		4145	{
		4146	#endif /* USE_SPI_CRC */
		4147	if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
		4148	{
		4149	/* Call user Rx complete callback */
		4150	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4151	hspi->RxCpltCallback(hspi);
		4152	#else
		4153	HAL_SPI_RxCpltCallback(hspi);
		4154	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4155	}
		4156	else
		4157	{
		4158	/* Call user error callback */
		4159	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4160	hspi->ErrorCallback(hspi);
		4161	#else
		4162	HAL_SPI_ErrorCallback(hspi);
		4163	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4164	}
		4165	#if (USE_SPI_CRC != 0U)
		4166	}
		4167	#endif /* USE_SPI_CRC */
		4168	}
		4169
		4170	/**
		4171	* @brief Handle the end of the TX transaction.
		4172	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		4173	* the configuration information for SPI module.
		4174	* @retval None
		4175	*/
		4176	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
		4177	{
		4178	uint32_t tickstart;
		4179
		4180	/* Init tickstart for timeout management*/
		4181	tickstart = HAL_GetTick();
		4182
		4183	/* Disable TXE and ERR interrupt */
		4184	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
		4185
		4186	/* Check the end of the transaction */
		4187	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
		4188	{
		4189	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
		4190	}
		4191
		4192	/* Clear overrun flag in 2 Lines communication mode because received is not read */
		4193	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
		4194	{
		4195	__HAL_SPI_CLEAR_OVRFLAG(hspi);
		4196	}
		4197
		4198	hspi->State = HAL_SPI_STATE_READY;
		4199	if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
		4200	{
		4201	/* Call user error callback */
		4202	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4203	hspi->ErrorCallback(hspi);
		4204	#else
		4205	HAL_SPI_ErrorCallback(hspi);
		4206	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4207	}
		4208	else
		4209	{
		4210	/* Call user Rx complete callback */
		4211	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
		4212	hspi->TxCpltCallback(hspi);
		4213	#else
		4214	HAL_SPI_TxCpltCallback(hspi);
		4215	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
		4216	}
		4217	}
		4218
		4219	/**
		4220	* @brief Handle abort a Rx transaction.
		4221	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		4222	* the configuration information for SPI module.
		4223	* @retval None
		4224	*/
		4225	static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
		4226	{
		4227	__IO uint32_t count;
		4228
		4229	/* Disable SPI Peripheral */
		4230	__HAL_SPI_DISABLE(hspi);
		4231
		4232	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		4233
		4234	/* Disable RXNEIE interrupt */
		4235	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
		4236
		4237	/* Check RXNEIE is disabled */
		4238	do
		4239	{
		4240	if (count == 0U)
		4241	{
		4242	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		4243	break;
		4244	}
		4245	count--;
		4246	} while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
		4247
		4248	/* Control the BSY flag */
		4249	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4250	{
		4251	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		4252	}
		4253
		4254	/* Empty the FRLVL fifo */
		4255	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4256	{
		4257	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		4258	}
		4259
		4260	hspi->State = HAL_SPI_STATE_ABORT;
		4261	}
		4262
		4263	/**
		4264	* @brief Handle abort a Tx or Rx/Tx transaction.
		4265	* @param hspi pointer to a SPI_HandleTypeDef structure that contains
		4266	* the configuration information for SPI module.
		4267	* @retval None
		4268	*/
		4269	static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
		4270	{
		4271	__IO uint32_t count;
		4272
		4273	count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
		4274
		4275	/* Disable TXEIE interrupt */
		4276	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
		4277
		4278	/* Check TXEIE is disabled */
		4279	do
		4280	{
		4281	if (count == 0U)
		4282	{
		4283	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		4284	break;
		4285	}
		4286	count--;
		4287	} while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
		4288
		4289	if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4290	{
		4291	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		4292	}
		4293
		4294	/* Disable SPI Peripheral */
		4295	__HAL_SPI_DISABLE(hspi);
		4296
		4297	/* Empty the FRLVL fifo */
		4298	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4299	{
		4300	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		4301	}
		4302
		4303	/* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
		4304	if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
		4305	{
		4306	/* Disable RXNEIE interrupt */
		4307	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
		4308
		4309	/* Check RXNEIE is disabled */
		4310	do
		4311	{
		4312	if (count == 0U)
		4313	{
		4314	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
		4315	break;
		4316	}
		4317	count--;
		4318	} while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
		4319
		4320	/* Control the BSY flag */
		4321	if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4322	{
		4323	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		4324	}
		4325
		4326	/* Empty the FRLVL fifo */
		4327	if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
		4328	{
		4329	hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
		4330	}
		4331	}
		4332	hspi->State = HAL_SPI_STATE_ABORT;
		4333	}
		4334
		4335	/**
		4336	* @}
		4337	*/
		4338
		4339	#endif /* HAL_SPI_MODULE_ENABLED */
		4340
		4341	/**
		4342	* @}
		4343	*/
		4344
		4345	/**
		4346	* @}
		4347	*/
		4348
		4349	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_spi.c – Rev 2