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/**

  ******************************************************************************

  * @file    stm32f0xx_hal_rcc.c

  * @author  MCD Application Team

  * @brief   RCC HAL module driver.

  *          This file provides firmware functions to manage the following

  *          functionalities of the Reset and Clock Control (RCC) peripheral:

  *           + Initialization and de-initialization functions

  *           + Peripheral Control functions

  *      

  @verbatim                

  ==============================================================================

                      ##### RCC specific features #####

  ==============================================================================

    [..]  

      After reset the device is running from Internal High Speed oscillator

      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,

      and all peripherals are off except internal SRAM, Flash and JTAG.

      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;

          all peripherals mapped on these buses are running at HSI speed.

      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.

      (+) All GPIOs are in input floating state, except the JTAG pins which

          are assigned to be used for debug purpose.

    [..] Once the device started from reset, the user application has to:

      (+) Configure the clock source to be used to drive the System clock

          (if the application needs higher frequency/performance)

      (+) Configure the System clock frequency and Flash settings  

      (+) Configure the AHB and APB buses prescalers

      (+) Enable the clock for the peripheral(s) to be used

      (+) Configure the clock source(s) for peripherals whose clocks are not

          derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)

                      ##### RCC Limitations #####

  ==============================================================================

    [..]  

      A delay between an RCC peripheral clock enable and the effective peripheral

      enabling should be taken into account in order to manage the peripheral read/write

      from/to registers.

      (+) This delay depends on the peripheral mapping.

        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]  

      Workarounds:

      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

  @endverbatim

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.

  * All rights reserved.</center></h2>

  *

  * This software component is licensed by ST under BSD 3-Clause license,

  * the "License"; You may not use this file except in compliance with the

  * License. You may obtain a copy of the License at:

  *                        opensource.org/licenses/BSD-3-Clause

  *

  ******************************************************************************

  */

/* Includes ------------------------------------------------------------------*/

#include "stm32f0xx_hal.h"

/** @addtogroup STM32F0xx_HAL_Driver

  * @{

  */

/** @defgroup RCC RCC

* @brief RCC HAL module driver

  * @{

  */

#ifdef HAL_RCC_MODULE_ENABLED

/* Private typedef -----------------------------------------------------------*/

/* Private define ------------------------------------------------------------*/

/** @defgroup RCC_Private_Constants RCC Private Constants

 * @{

 */

/**

  * @}

  */

/* Private macro -------------------------------------------------------------*/

/** @defgroup RCC_Private_Macros RCC Private Macros

  * @{

  */

#define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()

#define MCO1_GPIO_PORT        GPIOA

#define MCO1_PIN              GPIO_PIN_8

/**

  * @}

  */

/* Private variables ---------------------------------------------------------*/

/** @defgroup RCC_Private_Variables RCC Private Variables

  * @{

  */

/**

  * @}

  */

/* Private function prototypes -----------------------------------------------*/

/* Exported functions ---------------------------------------------------------*/

/** @defgroup RCC_Exported_Functions RCC Exported Functions

  * @{

  */

/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions

  *  @brief    Initialization and Configuration functions

  *

  @verbatim    

  ===============================================================================

           ##### Initialization and de-initialization functions #####

  ===============================================================================

    [..]

      This section provides functions allowing to configure the internal/external oscillators

      (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK,

      AHB and APB1).

    [..] Internal/external clock and PLL configuration

      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through

          the PLL as System clock source.

          The HSI clock can be used also to clock the USART and I2C peripherals.

      (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock

          the ADC peripheral.

      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC

          clock source.

      (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or

          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.  

      (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:

       (++) The first output is used to generate the high speed system clock (up to 48 MHz)

       (++) The second output is used to generate the clock for the USB FS (48 MHz)

       (++) The third output may be used to generate the clock for the TIM, I2C and USART

            peripherals (up to 48 MHz)

      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()

          and if a HSE clock failure occurs(HSE used directly or through PLL as System

          clock source), the System clocks automatically switched to HSI and an interrupt

          is generated if enabled. The interrupt is linked to the Cortex-M0 NMI

          (Non-Maskable Interrupt) exception vector.  

      (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL

          clock (divided by 2) output on pin (such as PA8 pin).

    [..] System, AHB and APB buses clocks configuration

      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,

          HSE and PLL.

          The AHB clock (HCLK) is derived from System clock through configurable

          prescaler and used to clock the CPU, memory and peripherals mapped

          on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived

          from AHB clock through configurable prescalers and used to clock

          the peripherals mapped on these buses. You can use

          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:

        (++) The FLASH program/erase clock  which is always HSI 8MHz clock.

        (++) The USB 48 MHz clock which is derived from the PLL VCO clock.

        (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.

        (++) The I2C clock which can be derived as well from HSI 8MHz clock.

        (++) The ADC clock which is derived from PLL output.

        (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC

             (HSE divided by a programmable prescaler). The System clock (SYSCLK)

             frequency must be higher or equal to the RTC clock frequency.

        (++) IWDG clock which is always the LSI clock.

      (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,

          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.

      (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and

          prefetch is disabled.

  @endverbatim

  * @{

  */

/*

  Additional consideration on the SYSCLK based on Latency settings:

          +-----------------------------------------------+

          | Latency       | SYSCLK clock frequency (MHz)  |

          |---------------|-------------------------------|

          |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |

          |---------------|-------------------------------|

          |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |

          +-----------------------------------------------+

  */

/**

  * @brief  Resets the RCC clock configuration to the default reset state.

  * @note   The default reset state of the clock configuration is given below:

  *            - HSI ON and used as system clock source

  *            - HSE and PLL OFF

  *            - AHB, APB1 prescaler set to 1.

  *            - CSS and MCO1 OFF

  *            - All interrupts disabled

  *            - All interrupt and reset flags cleared

  * @note   This function does not modify the configuration of the

  *            - Peripheral clocks

  *            - LSI, LSE and RTC clocks

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_DeInit(void)

{

  uint32_t tickstart;

  /* Get Start Tick*/

  tickstart = HAL_GetTick();

  /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/

  SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);

  /* Wait till HSI is ready */

  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)

  {

    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */

  CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);

  /* Wait till HSI as SYSCLK status is enabled */

  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)

  {

    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Update the SystemCoreClock global variable for HSI as system clock source */

  SystemCoreClock = HSI_VALUE;

  /* Adapt Systick interrupt period */

  if (HAL_InitTick(uwTickPrio) != HAL_OK)

  {

    return HAL_ERROR;

  }

  /* Reset HSEON, CSSON, PLLON bits */

  CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);

  /* Reset HSEBYP bit */

  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);

  /* Get start tick */

  tickstart = HAL_GetTick();

  /* Wait till PLLRDY is cleared */

  while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)

  {

    if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)

    {

      return HAL_TIMEOUT;

    }

  }

  /* Reset CFGR register */

  CLEAR_REG(RCC->CFGR);

  /* Reset CFGR2 register */

  CLEAR_REG(RCC->CFGR2);

  /* Reset CFGR3 register */

  CLEAR_REG(RCC->CFGR3);

  /* Disable all interrupts */

  CLEAR_REG(RCC->CIR);

  /* Clear all reset flags */

  __HAL_RCC_CLEAR_RESET_FLAGS();

  return HAL_OK;

}

/**

  * @brief  Initializes the RCC Oscillators according to the specified parameters in the

  *         RCC_OscInitTypeDef.

  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that

  *         contains the configuration information for the RCC Oscillators.

  * @note   The PLL is not disabled when used as system clock.

  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not

  *         supported by this macro. User should request a transition to LSE Off

  *         first and then LSE On or LSE Bypass.

  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not

  *         supported by this macro. User should request a transition to HSE Off

  *         first and then HSE On or HSE Bypass.

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)

{

  uint32_t tickstart;

  uint32_t pll_config;

  uint32_t pll_config2;

  /* Check Null pointer */

  if(RCC_OscInitStruct == NULL)

  {

    return HAL_ERROR;

  }

  /* Check the parameters */

  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */

    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)

       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))

    {

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))

      {

        return HAL_ERROR;

      }

    }

    else

    {

      /* Set the new HSE configuration ---------------------------------------*/

      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);

       /* Check the HSE State */

      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)

      {

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSE is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)

        {

          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSE is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)

        {

           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*----------------------------- HSI Configuration --------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));

    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */

    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)

       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))

    {

      /* When HSI is used as system clock it will not disabled */

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))

      {

        return HAL_ERROR;

      }

      /* Otherwise, just the calibration is allowed */

      else

      {

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/

        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);

      }

    }

    else

    {

      /* Check the HSI State */

      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)

      {

       /* Enable the Internal High Speed oscillator (HSI). */

        __HAL_RCC_HSI_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)

        {

          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/

        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);

      }

      else

      {

        /* Disable the Internal High Speed oscillator (HSI). */

        __HAL_RCC_HSI_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)

        {

          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

  /*------------------------------ LSI Configuration -------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)

  {

    /* Check the parameters */

    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */

    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)

    {

      /* Enable the Internal Low Speed oscillator (LSI). */

      __HAL_RCC_LSI_ENABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSI is ready */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)

      {

        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    else

    {

      /* Disable the Internal Low Speed oscillator (LSI). */

      __HAL_RCC_LSI_DISABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSI is disabled */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)

      {

        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

  }

  /*------------------------------ LSE Configuration -------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)

  {

    FlagStatus       pwrclkchanged = RESET;

    /* Check the parameters */

    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */

    /* Requires to enable write access to Backup Domain of necessary */

    if(__HAL_RCC_PWR_IS_CLK_DISABLED())

    {

      __HAL_RCC_PWR_CLK_ENABLE();

      pwrclkchanged = SET;

    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))

    {

      /* Enable write access to Backup domain */

      SET_BIT(PWR->CR, PWR_CR_DBP);

      /* Wait for Backup domain Write protection disable */

      tickstart = HAL_GetTick();

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))

      {

        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    /* Set the new LSE configuration -----------------------------------------*/

    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);

    /* Check the LSE State */

    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)

    {

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSE is ready */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)

      {

        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    else

    {

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till LSE is disabled */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)

      {

        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

    /* Require to disable power clock if necessary */

    if(pwrclkchanged == SET)

    {

      __HAL_RCC_PWR_CLK_DISABLE();

    }

  }

  /*----------------------------- HSI14 Configuration --------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));

    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));

    /* Check the HSI14 State */

    if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)

    {

      /* Disable ADC control of the Internal High Speed oscillator HSI14 */

      __HAL_RCC_HSI14ADC_DISABLE();

      /* Enable the Internal High Speed oscillator (HSI). */

      __HAL_RCC_HSI14_ENABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till HSI is ready */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)

      {

        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }      

      }

      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */

      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);

    }

    else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)

    {

      /* Enable ADC control of the Internal High Speed oscillator HSI14 */

      __HAL_RCC_HSI14ADC_ENABLE();

      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */

      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);

    }

    else

    {

      /* Disable ADC control of the Internal High Speed oscillator HSI14 */

      __HAL_RCC_HSI14ADC_DISABLE();

      /* Disable the Internal High Speed oscillator (HSI). */

      __HAL_RCC_HSI14_DISABLE();

      /* Get Start Tick */

      tickstart = HAL_GetTick();

      /* Wait till HSI is ready */  

      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)

      {

        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)

        {

          return HAL_TIMEOUT;

        }

      }

    }

  }

#if defined(RCC_HSI48_SUPPORT)

  /*----------------------------- HSI48 Configuration --------------------------*/

  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)

  {

    /* Check the parameters */

    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

    /* When the HSI48 is used as system clock it is not allowed to be disabled */

    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||

       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))

    {

      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))

      {

        return HAL_ERROR;

      }

    }

    else

    {

      /* Check the HSI48 State */

      if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)

      {

        /* Enable the Internal High Speed oscillator (HSI48). */

        __HAL_RCC_HSI48_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI48 is ready */  

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)

        {

          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Disable the Internal High Speed oscillator (HSI48). */

        __HAL_RCC_HSI48_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till HSI48 is ready */  

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)

        {

          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

  }

#endif /* RCC_HSI48_SUPPORT */

  /*-------------------------------- PLL Configuration -----------------------*/

  /* Check the parameters */

  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));

  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)

  {

    /* Check if the PLL is used as system clock or not */

    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)

    {

      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)

      {

        /* Check the parameters */

        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));

        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));

        assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));

        /* Disable the main PLL. */

        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

        /* Configure the main PLL clock source, predivider and multiplication factor. */

        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,

                             RCC_OscInitStruct->PLL.PREDIV,

                             RCC_OscInitStruct->PLL.PLLMUL);

        /* Enable the main PLL. */

        __HAL_RCC_PLL_ENABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is ready */

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

      else

      {

        /* Disable the main PLL. */

        __HAL_RCC_PLL_DISABLE();

        /* Get Start Tick */

        tickstart = HAL_GetTick();

        /* Wait till PLL is disabled */  

        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)

        {

          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)

          {

            return HAL_TIMEOUT;

          }

        }

      }

    }

    else

    {

      /* Check if there is a request to disable the PLL used as System clock source */

      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)

      {

        return HAL_ERROR;

      }

      else

      {

        /* Do not return HAL_ERROR if request repeats the current configuration */

        pll_config  = RCC->CFGR;

        pll_config2 = RCC->CFGR2;

        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||

           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||

           (READ_BIT(pll_config,  RCC_CFGR_PLLMUL)  != RCC_OscInitStruct->PLL.PLLMUL))

        {

          return HAL_ERROR;

        }

      }

    }

  }

  return HAL_OK;

}

/**

  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified

  *         parameters in the RCC_ClkInitStruct.

  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that

  *         contains the configuration information for the RCC peripheral.

  * @param  FLatency FLASH Latency                  

  *          The value of this parameter depend on device used within the same series

  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency

  *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function

  *

  * @note   The HSI is used (enabled by hardware) as system clock source after

  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case

  *         of failure of the HSE used directly or indirectly as system clock

  *         (if the Clock Security System CSS is enabled).

  *          

  * @note   A switch from one clock source to another occurs only if the target

  *         clock source is ready (clock stable after start-up delay or PLL locked).

  *         If a clock source which is not yet ready is selected, the switch will

  *         occur when the clock source will be ready.

  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is

  *         currently used as system clock source.

  * @retval HAL status

  */

HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)

{

  uint32_t tickstart;

  /* Check Null pointer */

  if(RCC_ClkInitStruct == NULL)

  {

    return HAL_ERROR;

  }

  /* Check the parameters */

  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));

  assert_param(IS_FLASH_LATENCY(FLatency));

  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)

  must be correctly programmed according to the frequency of the CPU clock

    (HCLK) of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */

  if(FLatency > __HAL_FLASH_GET_LATENCY())

  {    

    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */

    __HAL_FLASH_SET_LATENCY(FLatency);

    /* Check that the new number of wait states is taken into account to access the Flash

    memory by reading the FLASH_ACR register */

    if(__HAL_FLASH_GET_LATENCY() != FLatency)

    {

      return HAL_ERROR;

    }

  }

  /*-------------------------- HCLK Configuration --------------------------*/

  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)

  {

    /* Set the highest APB divider in order to ensure that we do not go through

       a non-spec phase whatever we decrease or increase HCLK. */

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)

    {

      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);

    }

    /* Set the new HCLK clock divider */

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));

    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);

  }

  /*------------------------- SYSCLK Configuration ---------------------------*/

  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)

  {

    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)

    {

      /* Check the HSE ready flag */  

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)

      {

        return HAL_ERROR;

      }

    }

    /* PLL is selected as System Clock Source */

    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)

    {

      /* Check the PLL ready flag */  

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)

      {

        return HAL_ERROR;

      }

    }

#if defined(RCC_CFGR_SWS_HSI48)

    /* HSI48 is selected as System Clock Source */

    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)

    {

      /* Check the HSI48 ready flag */

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)

      {

        return HAL_ERROR;

      }

    }

#endif /* RCC_CFGR_SWS_HSI48 */

    /* HSI is selected as System Clock Source */

    else

    {

      /* Check the HSI ready flag */  

      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)

      {

        return HAL_ERROR;

      }

    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);

    /* Get Start Tick */

    tickstart = HAL_GetTick();

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))

    {

      if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)

      {

        return HAL_TIMEOUT;

      }

    }

  }

  /* Decreasing the number of wait states because of lower CPU frequency */

  if(FLatency < __HAL_FLASH_GET_LATENCY())

  {