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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_pwr.c |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief PWR HAL module driver. |
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| 6 | * This file provides firmware functions to manage the following |
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| 7 | * functionalities of the Power Controller (PWR) peripheral: |
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| 8 | * + Initialization/de-initialization function |
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| 9 | * + Peripheral Control function |
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| 10 | * |
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| 11 | @verbatim |
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| 12 | ****************************************************************************** |
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| 13 | * @attention |
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| 14 | * |
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| 15 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 16 | * All rights reserved.</center></h2> |
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| 17 | * |
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| 18 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 19 | * the "License"; You may not use this file except in compliance with the |
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| 20 | * License. You may obtain a copy of the License at: |
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| 21 | * opensource.org/licenses/BSD-3-Clause |
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| 22 | * |
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| 23 | ****************************************************************************** |
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| 24 | */ |
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| 25 | |||
| 26 | /* Includes ------------------------------------------------------------------*/ |
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| 27 | #include "stm32f0xx_hal.h" |
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| 28 | |||
| 29 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 30 | * @{ |
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| 31 | */ |
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| 32 | |||
| 33 | /** @defgroup PWR PWR |
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| 34 | * @brief PWR HAL module driver |
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| 35 | * @{ |
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| 36 | */ |
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| 37 | |||
| 38 | #ifdef HAL_PWR_MODULE_ENABLED |
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| 39 | |||
| 40 | /* Private typedef -----------------------------------------------------------*/ |
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| 41 | /* Private define ------------------------------------------------------------*/ |
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| 42 | /* Private macro -------------------------------------------------------------*/ |
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| 43 | /* Private variables ---------------------------------------------------------*/ |
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| 44 | /* Private function prototypes -----------------------------------------------*/ |
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| 45 | /* Private functions ---------------------------------------------------------*/ |
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| 46 | |||
| 47 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
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| 48 | * @{ |
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| 49 | */ |
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| 50 | |||
| 51 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
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| 52 | * @brief Initialization and de-initialization functions |
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| 53 | * |
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| 54 | @verbatim |
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| 55 | =============================================================================== |
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| 56 | ##### Initialization and de-initialization functions ##### |
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| 57 | =============================================================================== |
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| 58 | [..] |
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| 59 | After reset, the backup domain (RTC registers, RTC backup data |
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| 60 | registers) is protected against possible unwanted |
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| 61 | write accesses. |
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| 62 | To enable access to the RTC Domain and RTC registers, proceed as follows: |
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| 63 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
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| 64 | __HAL_RCC_PWR_CLK_ENABLE() macro. |
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| 65 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
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| 66 | |||
| 67 | @endverbatim |
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| 68 | * @{ |
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| 69 | */ |
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| 70 | |||
| 71 | /** |
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| 72 | * @brief Deinitializes the PWR peripheral registers to their default reset values. |
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| 73 | * @retval None |
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| 74 | */ |
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| 75 | void HAL_PWR_DeInit(void) |
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| 76 | { |
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| 77 | __HAL_RCC_PWR_FORCE_RESET(); |
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| 78 | __HAL_RCC_PWR_RELEASE_RESET(); |
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| 79 | } |
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| 80 | |||
| 81 | /** |
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| 82 | * @brief Enables access to the backup domain (RTC registers, RTC |
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| 83 | * backup data registers when present). |
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| 84 | * @note If the HSE divided by 32 is used as the RTC clock, the |
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| 85 | * Backup Domain Access should be kept enabled. |
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| 86 | * @retval None |
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| 87 | */ |
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| 88 | void HAL_PWR_EnableBkUpAccess(void) |
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| 89 | { |
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| 90 | PWR->CR |= (uint32_t)PWR_CR_DBP; |
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| 91 | } |
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| 92 | |||
| 93 | /** |
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| 94 | * @brief Disables access to the backup domain (RTC registers, RTC |
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| 95 | * backup data registers when present). |
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| 96 | * @note If the HSE divided by 32 is used as the RTC clock, the |
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| 97 | * Backup Domain Access should be kept enabled. |
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| 98 | * @retval None |
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| 99 | */ |
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| 100 | void HAL_PWR_DisableBkUpAccess(void) |
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| 101 | { |
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| 102 | PWR->CR &= ~((uint32_t)PWR_CR_DBP); |
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| 103 | } |
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| 104 | |||
| 105 | /** |
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| 106 | * @} |
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| 107 | */ |
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| 108 | |||
| 109 | /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
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| 110 | * @brief Low Power modes configuration functions |
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| 111 | * |
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| 112 | @verbatim |
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| 113 | |||
| 114 | =============================================================================== |
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| 115 | ##### Peripheral Control functions ##### |
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| 116 | =============================================================================== |
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| 117 | |||
| 118 | *** WakeUp pin configuration *** |
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| 119 | ================================ |
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| 120 | [..] |
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| 121 | (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is |
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| 122 | forced in input pull down configuration and is active on rising edges. |
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| 123 | (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. |
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| 124 | (++)WakeUp Pin 1 on PA.00. |
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| 125 | (++)WakeUp Pin 2 on PC.13. |
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| 126 | (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) |
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| 127 | (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) |
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| 128 | (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) |
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| 129 | (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) |
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| 130 | (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) |
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| 131 | (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) |
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| 132 | |||
| 133 | *** Low Power modes configuration *** |
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| 134 | ===================================== |
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| 135 | [..] |
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| 136 | The devices feature 3 low-power modes: |
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| 137 | (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. |
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| 138 | (+) Stop mode: all clocks are stopped, regulator running, regulator |
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| 139 | in low power mode |
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| 140 | (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). |
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| 141 | |||
| 142 | *** Sleep mode *** |
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| 143 | ================== |
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| 144 | [..] |
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| 145 | (+) Entry: |
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| 146 | The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
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| 147 | functions with |
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| 148 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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| 149 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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| 150 | |||
| 151 | (+) Exit: |
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| 152 | (++) Any peripheral interrupt acknowledged by the nested vectored interrupt |
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| 153 | controller (NVIC) can wake up the device from Sleep mode. |
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| 154 | |||
| 155 | *** Stop mode *** |
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| 156 | ================= |
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| 157 | [..] |
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| 158 | In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, |
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| 159 | and the HSE RC oscillators are disabled. Internal SRAM and register contents |
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| 160 | are preserved. |
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| 161 | The voltage regulator can be configured either in normal or low-power mode. |
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| 162 | To minimize the consumption. |
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| 163 | |||
| 164 | (+) Entry: |
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| 165 | The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) |
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| 166 | function with: |
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| 167 | (++) Main regulator ON. |
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| 168 | (++) Low Power regulator ON. |
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| 169 | (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction |
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| 170 | (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction |
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| 171 | (+) Exit: |
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| 172 | (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. |
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| 173 | (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, |
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| 174 | when programmed in wakeup mode (the peripheral must be |
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| 175 | programmed in wakeup mode and the corresponding interrupt vector |
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| 176 | must be enabled in the NVIC) |
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| 177 | |||
| 178 | *** Standby mode *** |
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| 179 | ==================== |
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| 180 | [..] |
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| 181 | The Standby mode allows to achieve the lowest power consumption. It is based |
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| 182 | on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. |
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| 183 | The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and |
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| 184 | the HSE oscillator are also switched off. SRAM and register contents are lost |
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| 185 | except for the RTC registers, RTC backup registers and Standby circuitry. |
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| 186 | The voltage regulator is OFF. |
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| 187 | |||
| 188 | (+) Entry: |
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| 189 | (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
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| 190 | (+) Exit: |
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| 191 | (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, |
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| 192 | tamper event, time-stamp event, external reset in NRST pin, IWDG reset. |
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| 193 | |||
| 194 | *** Auto-wakeup (AWU) from low-power mode *** |
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| 195 | ============================================= |
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| 196 | [..] |
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| 197 | The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC |
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| 198 | Wakeup event, a tamper event, a time-stamp event, or a comparator event, |
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| 199 | without depending on an external interrupt (Auto-wakeup mode). |
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| 200 | |||
| 201 | (+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
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| 202 | |||
| 203 | (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to |
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| 204 | configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. |
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| 205 | |||
| 206 | (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it |
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| 207 | is necessary to configure the RTC to detect the tamper or time stamp event using the |
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| 208 | HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. |
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| 209 | |||
| 210 | (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to |
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| 211 | configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. |
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| 212 | |||
| 213 | (+) Comparator auto-wakeup (AWU) from the Stop mode |
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| 214 | |||
| 215 | (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: |
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| 216 | (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) |
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| 217 | to be sensitive to to the selected edges (falling, rising or falling |
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| 218 | and rising) (Interrupt or Event modes) using the EXTI_Init() function. |
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| 219 | (+++) Configure the comparator to generate the event. |
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| 220 | @endverbatim |
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| 221 | * @{ |
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| 222 | */ |
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| 223 | |||
| 224 | /** |
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| 225 | * @brief Enables the WakeUp PINx functionality. |
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| 226 | * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. |
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| 227 | * This parameter can be value of : |
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| 228 | * @ref PWREx_WakeUp_Pins |
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| 229 | * @retval None |
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| 230 | */ |
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| 231 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
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| 232 | { |
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| 233 | /* Check the parameters */ |
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| 234 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
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| 235 | /* Enable the EWUPx pin */ |
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| 236 | SET_BIT(PWR->CSR, WakeUpPinx); |
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| 237 | } |
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| 238 | |||
| 239 | /** |
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| 240 | * @brief Disables the WakeUp PINx functionality. |
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| 241 | * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. |
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| 242 | * This parameter can be values of : |
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| 243 | * @ref PWREx_WakeUp_Pins |
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| 244 | * @retval None |
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| 245 | */ |
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| 246 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
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| 247 | { |
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| 248 | /* Check the parameters */ |
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| 249 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
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| 250 | /* Disable the EWUPx pin */ |
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| 251 | CLEAR_BIT(PWR->CSR, WakeUpPinx); |
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| 252 | } |
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| 253 | |||
| 254 | /** |
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| 255 | * @brief Enters Sleep mode. |
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| 256 | * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
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| 257 | * @param Regulator Specifies the regulator state in SLEEP mode. |
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| 258 | * On STM32F0 devices, this parameter is a dummy value and it is ignored |
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| 259 | * as regulator can't be modified in this mode. Parameter is kept for platform |
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| 260 | * compatibility. |
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| 261 | * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. |
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| 262 | * When WFI entry is used, tick interrupt have to be disabled if not desired as |
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| 263 | * the interrupt wake up source. |
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| 264 | * This parameter can be one of the following values: |
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| 265 | * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
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| 266 | * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
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| 267 | * @retval None |
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| 268 | */ |
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| 269 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
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| 270 | { |
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| 271 | /* Check the parameters */ |
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| 272 | assert_param(IS_PWR_REGULATOR(Regulator)); |
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| 273 | assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
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| 274 | |||
| 275 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
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| 276 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
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| 277 | |||
| 278 | /* Select SLEEP mode entry -------------------------------------------------*/ |
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| 279 | if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
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| 280 | { |
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| 281 | /* Request Wait For Interrupt */ |
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| 282 | __WFI(); |
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| 283 | } |
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| 284 | else |
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| 285 | { |
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| 286 | /* Request Wait For Event */ |
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| 287 | __SEV(); |
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| 288 | __WFE(); |
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| 289 | __WFE(); |
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| 290 | } |
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| 291 | } |
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| 292 | |||
| 293 | /** |
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| 294 | * @brief Enters STOP mode. |
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| 295 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
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| 296 | * @note When exiting Stop mode by issuing an interrupt or a wakeup event, |
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| 297 | * the HSI RC oscillator is selected as system clock. |
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| 298 | * @note When the voltage regulator operates in low power mode, an additional |
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| 299 | * startup delay is incurred when waking up from Stop mode. |
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| 300 | * By keeping the internal regulator ON during Stop mode, the consumption |
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| 301 | * is higher although the startup time is reduced. |
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| 302 | * @param Regulator Specifies the regulator state in STOP mode. |
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| 303 | * This parameter can be one of the following values: |
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| 304 | * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON |
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| 305 | * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON |
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| 306 | * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. |
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| 307 | * This parameter can be one of the following values: |
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| 308 | * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction |
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| 309 | * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction |
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| 310 | * @retval None |
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| 311 | */ |
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| 312 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
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| 313 | { |
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| 314 | uint32_t tmpreg = 0; |
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| 315 | |||
| 316 | /* Check the parameters */ |
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| 317 | assert_param(IS_PWR_REGULATOR(Regulator)); |
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| 318 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
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| 319 | |||
| 320 | /* Select the regulator state in STOP mode ---------------------------------*/ |
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| 321 | tmpreg = PWR->CR; |
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| 322 | |||
| 323 | /* Clear PDDS and LPDS bits */ |
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| 324 | tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); |
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| 325 | |||
| 326 | /* Set LPDS bit according to Regulator value */ |
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| 327 | tmpreg |= Regulator; |
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| 328 | |||
| 329 | /* Store the new value */ |
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| 330 | PWR->CR = tmpreg; |
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| 331 | |||
| 332 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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| 333 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
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| 334 | |||
| 335 | /* Select STOP mode entry --------------------------------------------------*/ |
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| 336 | if(STOPEntry == PWR_STOPENTRY_WFI) |
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| 337 | { |
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| 338 | /* Request Wait For Interrupt */ |
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| 339 | __WFI(); |
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| 340 | } |
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| 341 | else |
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| 342 | { |
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| 343 | /* Request Wait For Event */ |
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| 344 | __SEV(); |
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| 345 | __WFE(); |
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| 346 | __WFE(); |
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| 347 | } |
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| 348 | |||
| 349 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
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| 350 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
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| 351 | } |
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| 352 | |||
| 353 | /** |
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| 354 | * @brief Enters STANDBY mode. |
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| 355 | * @note In Standby mode, all I/O pins are high impedance except for: |
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| 356 | * - Reset pad (still available) |
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| 357 | * - RTC alternate function pins if configured for tamper, time-stamp, RTC |
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| 358 | * Alarm out, or RTC clock calibration out. |
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| 359 | * - WKUP pins if enabled. |
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| 360 | * STM32F0x8 devices, the Stop mode is available, but it is |
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| 361 | * aningless to distinguish between voltage regulator in Low power |
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| 362 | * mode and voltage regulator in Run mode because the regulator |
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| 363 | * not used and the core is supplied directly from an external source. |
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| 364 | * Consequently, the Standby mode is not available on those devices. |
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| 365 | * @retval None |
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| 366 | */ |
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| 367 | void HAL_PWR_EnterSTANDBYMode(void) |
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| 368 | { |
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| 369 | /* Select STANDBY mode */ |
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| 370 | PWR->CR |= (uint32_t)PWR_CR_PDDS; |
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| 371 | |||
| 372 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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| 373 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
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| 374 | |||
| 375 | /* This option is used to ensure that store operations are completed */ |
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| 376 | #if defined ( __CC_ARM) |
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| 377 | __force_stores(); |
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| 378 | #endif |
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| 379 | /* Request Wait For Interrupt */ |
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| 380 | __WFI(); |
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| 381 | } |
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| 382 | |||
| 383 | /** |
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| 384 | * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
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| 385 | * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
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| 386 | * re-enters SLEEP mode when an interruption handling is over. |
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| 387 | * Setting this bit is useful when the processor is expected to run only on |
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| 388 | * interruptions handling. |
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| 389 | * @retval None |
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| 390 | */ |
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| 391 | void HAL_PWR_EnableSleepOnExit(void) |
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| 392 | { |
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| 393 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
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| 394 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 395 | } |
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| 396 | |||
| 397 | |||
| 398 | /** |
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| 399 | * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
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| 400 | * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
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| 401 | * re-enters SLEEP mode when an interruption handling is over. |
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| 402 | * @retval None |
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| 403 | */ |
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| 404 | void HAL_PWR_DisableSleepOnExit(void) |
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| 405 | { |
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| 406 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
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| 407 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 408 | } |
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| 409 | |||
| 410 | |||
| 411 | |||
| 412 | /** |
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| 413 | * @brief Enables CORTEX M4 SEVONPEND bit. |
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| 414 | * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
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| 415 | * WFE to wake up when an interrupt moves from inactive to pended. |
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| 416 | * @retval None |
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| 417 | */ |
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| 418 | void HAL_PWR_EnableSEVOnPend(void) |
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| 419 | { |
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| 420 | /* Set SEVONPEND bit of Cortex System Control Register */ |
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| 421 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 422 | } |
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| 423 | |||
| 424 | |||
| 425 | /** |
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| 426 | * @brief Disables CORTEX M4 SEVONPEND bit. |
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| 427 | * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
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| 428 | * WFE to wake up when an interrupt moves from inactive to pended. |
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| 429 | * @retval None |
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| 430 | */ |
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| 431 | void HAL_PWR_DisableSEVOnPend(void) |
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| 432 | { |
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| 433 | /* Clear SEVONPEND bit of Cortex System Control Register */ |
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| 434 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 435 | } |
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| 436 | |||
| 437 | /** |
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| 438 | * @} |
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| 439 | */ |
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| 440 | |||
| 441 | /** |
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| 442 | * @} |
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| 443 | */ |
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| 444 | |||
| 445 | #endif /* HAL_PWR_MODULE_ENABLED */ |
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| 446 | /** |
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| 447 | * @} |
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| 448 | */ |
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| 449 | |||
| 450 | /** |
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| 451 | * @} |
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| 452 | */ |
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| 453 | |||
| 454 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |