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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f0xx_hal_adc.c |
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4 | * @author MCD Application Team |
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5 | * @brief This file provides firmware functions to manage the following |
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6 | * functionalities of the Analog to Digital Convertor (ADC) |
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7 | * peripheral: |
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8 | * + Initialization and de-initialization functions |
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9 | * ++ Initialization and Configuration of ADC |
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10 | * + Operation functions |
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11 | * ++ Start, stop, get result of conversions of regular |
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12 | * group, using 3 possible modes: polling, interruption or DMA. |
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13 | * + Control functions |
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14 | * ++ Channels configuration on regular group |
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15 | * ++ Analog Watchdog configuration |
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16 | * + State functions |
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17 | * ++ ADC state machine management |
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18 | * ++ Interrupts and flags management |
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19 | * Other functions (extended functions) are available in file |
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20 | * "stm32f0xx_hal_adc_ex.c". |
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21 | * |
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22 | @verbatim |
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23 | ============================================================================== |
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24 | ##### ADC peripheral features ##### |
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25 | ============================================================================== |
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26 | [..] |
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27 | (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution |
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28 | |||
29 | (+) Interrupt generation at the end of regular conversion and in case of |
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30 | analog watchdog or overrun events. |
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31 | |||
32 | (+) Single and continuous conversion modes. |
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33 | |||
34 | (+) Scan mode for conversion of several channels sequentially. |
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35 | |||
36 | (+) Data alignment with in-built data coherency. |
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37 | |||
38 | (+) Programmable sampling time (common for all channels) |
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39 | |||
40 | (+) ADC conversion of regular group. |
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41 | |||
42 | (+) External trigger (timer or EXTI) with configurable polarity |
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43 | |||
44 | (+) DMA request generation for transfer of conversions data of regular group. |
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45 | |||
46 | (+) ADC calibration |
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47 | |||
48 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
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49 | slower speed. |
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50 | |||
51 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
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52 | Vdda or to an external voltage reference). |
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53 | |||
54 | |||
55 | ##### How to use this driver ##### |
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56 | ============================================================================== |
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57 | [..] |
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58 | |||
59 | *** Configuration of top level parameters related to ADC *** |
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60 | ============================================================ |
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61 | [..] |
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62 | |||
63 | (#) Enable the ADC interface |
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64 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
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65 | Caution: On STM32F0, ADC clock frequency max is 14MHz (refer |
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66 | to device datasheet). |
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67 | Therefore, ADC clock prescaler must be configured in |
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68 | function of ADC clock source frequency to remain below |
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69 | this maximum frequency. |
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70 | |||
71 | (++) Two clock settings are mandatory: |
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72 | (+++) ADC clock (core clock, also possibly conversion clock). |
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73 | |||
74 | (+++) ADC clock (conversions clock). |
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75 | Two possible clock sources: synchronous clock derived from APB clock |
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76 | or asynchronous clock derived from ADC dedicated HSI RC oscillator |
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77 | 14MHz. |
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78 | If asynchronous clock is selected, parameter "HSI14State" must be set either: |
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79 | - to "...HSI14State = RCC_HSI14_ADC_CONTROL" to let the ADC control |
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80 | the HSI14 oscillator enable/disable (if not used to supply the main |
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81 | system clock): feature used if ADC mode LowPowerAutoPowerOff is |
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82 | enabled. |
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83 | - to "...HSI14State = RCC_HSI14_ON" to maintain the HSI14 oscillator |
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84 | always enabled: can be used to supply the main system clock. |
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85 | |||
86 | (+++) Example: |
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87 | Into HAL_ADC_MspInit() (recommended code location) or with |
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88 | other device clock parameters configuration: |
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89 | (+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory) |
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90 | |||
91 | HI14 enable or let under control of ADC: (optional: if asynchronous clock selected) |
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92 | (+++) RCC_OscInitTypeDef RCC_OscInitStructure; |
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93 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; |
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94 | (+++) RCC_OscInitStructure.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; |
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95 | (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_ADC_CONTROL; |
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96 | (+++) RCC_OscInitStructure.PLL... (optional if used for system clock) |
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97 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
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98 | |||
99 | (++) ADC clock source and clock prescaler are configured at ADC level with |
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100 | parameter "ClockPrescaler" using function HAL_ADC_Init(). |
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101 | |||
102 | (#) ADC pins configuration |
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103 | (++) Enable the clock for the ADC GPIOs |
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104 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
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105 | (++) Configure these ADC pins in analog mode |
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106 | using function HAL_GPIO_Init() |
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107 | |||
108 | (#) Optionally, in case of usage of ADC with interruptions: |
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109 | (++) Configure the NVIC for ADC |
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110 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
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111 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
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112 | into the function of corresponding ADC interruption vector |
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113 | ADCx_IRQHandler(). |
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114 | |||
115 | (#) Optionally, in case of usage of DMA: |
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116 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
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117 | using function HAL_DMA_Init(). |
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118 | (++) Configure the NVIC for DMA |
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119 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
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120 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
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121 | into the function of corresponding DMA interruption vector |
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122 | DMAx_Channelx_IRQHandler(). |
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123 | |||
124 | *** Configuration of ADC, group regular, channels parameters *** |
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125 | ================================================================ |
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126 | [..] |
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127 | |||
128 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
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129 | and regular group parameters (conversion trigger, sequencer, ...) |
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130 | using function HAL_ADC_Init(). |
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131 | |||
132 | (#) Configure the channels for regular group parameters (channel number, |
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133 | channel rank into sequencer, ..., into regular group) |
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134 | using function HAL_ADC_ConfigChannel(). |
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135 | |||
136 | (#) Optionally, configure the analog watchdog parameters (channels |
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137 | monitored, thresholds, ...) |
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138 | using function HAL_ADC_AnalogWDGConfig(). |
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139 | |||
140 | *** Execution of ADC conversions *** |
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141 | ==================================== |
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142 | [..] |
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143 | |||
144 | (#) Optionally, perform an automatic ADC calibration to improve the |
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145 | conversion accuracy |
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146 | using function HAL_ADCEx_Calibration_Start(). |
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147 | |||
148 | (#) ADC driver can be used among three modes: polling, interruption, |
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149 | transfer by DMA. |
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150 | |||
151 | (++) ADC conversion by polling: |
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152 | (+++) Activate the ADC peripheral and start conversions |
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153 | using function HAL_ADC_Start() |
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154 | (+++) Wait for ADC conversion completion |
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155 | using function HAL_ADC_PollForConversion() |
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156 | (+++) Retrieve conversion results |
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157 | using function HAL_ADC_GetValue() |
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158 | (+++) Stop conversion and disable the ADC peripheral |
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159 | using function HAL_ADC_Stop() |
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160 | |||
161 | (++) ADC conversion by interruption: |
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162 | (+++) Activate the ADC peripheral and start conversions |
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163 | using function HAL_ADC_Start_IT() |
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164 | (+++) Wait for ADC conversion completion by call of function |
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165 | HAL_ADC_ConvCpltCallback() |
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166 | (this function must be implemented in user program) |
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167 | (+++) Retrieve conversion results |
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168 | using function HAL_ADC_GetValue() |
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169 | (+++) Stop conversion and disable the ADC peripheral |
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170 | using function HAL_ADC_Stop_IT() |
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171 | |||
172 | (++) ADC conversion with transfer by DMA: |
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173 | (+++) Activate the ADC peripheral and start conversions |
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174 | using function HAL_ADC_Start_DMA() |
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175 | (+++) Wait for ADC conversion completion by call of function |
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176 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
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177 | (these functions must be implemented in user program) |
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178 | (+++) Conversion results are automatically transferred by DMA into |
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179 | destination variable address. |
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180 | (+++) Stop conversion and disable the ADC peripheral |
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181 | using function HAL_ADC_Stop_DMA() |
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182 | |||
183 | [..] |
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184 | |||
185 | (@) Callback functions must be implemented in user program: |
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186 | (+@) HAL_ADC_ErrorCallback() |
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187 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
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188 | (+@) HAL_ADC_ConvCpltCallback() |
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189 | (+@) HAL_ADC_ConvHalfCpltCallback |
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190 | |||
191 | *** Deinitialization of ADC *** |
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192 | ============================================================ |
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193 | [..] |
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194 | |||
195 | (#) Disable the ADC interface |
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196 | (++) ADC clock can be hard reset and disabled at RCC top level. |
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197 | (++) Hard reset of ADC peripherals |
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198 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
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199 | (++) ADC clock disable |
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200 | using the equivalent macro/functions as configuration step. |
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201 | (+++) Example: |
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202 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
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203 | other device clock parameters configuration: |
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204 | (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; |
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205 | (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) |
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206 | (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); |
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207 | |||
208 | (#) ADC pins configuration |
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209 | (++) Disable the clock for the ADC GPIOs |
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210 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
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211 | |||
212 | (#) Optionally, in case of usage of ADC with interruptions: |
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213 | (++) Disable the NVIC for ADC |
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214 | using function HAL_NVIC_DisableIRQ(ADCx_IRQn) |
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215 | |||
216 | (#) Optionally, in case of usage of DMA: |
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217 | (++) Deinitialize the DMA |
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218 | using function HAL_DMA_DeInit(). |
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219 | (++) Disable the NVIC for DMA |
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220 | using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) |
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221 | |||
222 | [..] |
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223 | |||
224 | *** Callback registration *** |
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225 | ============================================= |
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226 | [..] |
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227 | |||
228 | The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, |
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229 | allows the user to configure dynamically the driver callbacks. |
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230 | Use Functions @ref HAL_ADC_RegisterCallback() |
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231 | to register an interrupt callback. |
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232 | [..] |
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233 | |||
234 | Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: |
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235 | (+) ConvCpltCallback : ADC conversion complete callback |
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236 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
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237 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
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238 | (+) ErrorCallback : ADC error callback |
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239 | (+) MspInitCallback : ADC Msp Init callback |
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240 | (+) MspDeInitCallback : ADC Msp DeInit callback |
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241 | This function takes as parameters the HAL peripheral handle, the Callback ID |
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242 | and a pointer to the user callback function. |
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243 | [..] |
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244 | |||
245 | Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default |
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246 | weak function. |
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247 | [..] |
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248 | |||
249 | @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, |
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250 | and the Callback ID. |
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251 | This function allows to reset following callbacks: |
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252 | (+) ConvCpltCallback : ADC conversion complete callback |
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253 | (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback |
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254 | (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback |
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255 | (+) ErrorCallback : ADC error callback |
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256 | (+) MspInitCallback : ADC Msp Init callback |
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257 | (+) MspDeInitCallback : ADC Msp DeInit callback |
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258 | [..] |
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259 | |||
260 | By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET |
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261 | all callbacks are set to the corresponding weak functions: |
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262 | examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). |
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263 | Exception done for MspInit and MspDeInit functions that are |
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264 | reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when |
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265 | these callbacks are null (not registered beforehand). |
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266 | [..] |
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267 | |||
268 | If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() |
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269 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
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270 | [..] |
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271 | |||
272 | Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. |
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273 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
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274 | in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, |
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275 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
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276 | [..] |
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277 | |||
278 | Then, the user first registers the MspInit/MspDeInit user callbacks |
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279 | using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() |
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280 | or @ref HAL_ADC_Init() function. |
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281 | [..] |
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282 | |||
283 | When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or |
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284 | not defined, the callback registration feature is not available and all callbacks |
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285 | are set to the corresponding weak functions. |
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286 | |||
287 | @endverbatim |
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288 | ****************************************************************************** |
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289 | * @attention |
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290 | * |
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291 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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292 | * All rights reserved.</center></h2> |
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293 | * |
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294 | * This software component is licensed by ST under BSD 3-Clause license, |
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295 | * the "License"; You may not use this file except in compliance with the |
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296 | * License. You may obtain a copy of the License at: |
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297 | * opensource.org/licenses/BSD-3-Clause |
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298 | * |
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299 | ****************************************************************************** |
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300 | */ |
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301 | |||
302 | /* Includes ------------------------------------------------------------------*/ |
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303 | #include "stm32f0xx_hal.h" |
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304 | |||
305 | /** @addtogroup STM32F0xx_HAL_Driver |
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306 | * @{ |
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307 | */ |
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308 | |||
309 | /** @defgroup ADC ADC |
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310 | * @brief ADC HAL module driver |
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311 | * @{ |
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312 | */ |
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313 | |||
314 | #ifdef HAL_ADC_MODULE_ENABLED |
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315 | |||
316 | /* Private typedef -----------------------------------------------------------*/ |
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317 | /* Private define ------------------------------------------------------------*/ |
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318 | /** @defgroup ADC_Private_Constants ADC Private Constants |
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319 | * @{ |
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320 | */ |
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321 | |||
322 | /* Fixed timeout values for ADC calibration, enable settling time, disable */ |
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323 | /* settling time. */ |
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324 | /* Values defined to be higher than worst cases: low clock frequency, */ |
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325 | /* maximum prescaler. */ |
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326 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
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327 | /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ |
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328 | /* Unit: ms */ |
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329 | #define ADC_ENABLE_TIMEOUT ( 2U) |
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330 | #define ADC_DISABLE_TIMEOUT ( 2U) |
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331 | #define ADC_STOP_CONVERSION_TIMEOUT ( 2U) |
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332 | |||
333 | /* Delay for ADC stabilization time. */ |
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334 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
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335 | /* Unit: us */ |
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336 | #define ADC_STAB_DELAY_US ( 1U) |
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337 | |||
338 | /* Delay for temperature sensor stabilization time. */ |
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339 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
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340 | /* Unit: us */ |
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341 | #define ADC_TEMPSENSOR_DELAY_US ( 10U) |
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342 | |||
343 | /** |
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344 | * @} |
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345 | */ |
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346 | |||
347 | /* Private macro -------------------------------------------------------------*/ |
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348 | /* Private variables ---------------------------------------------------------*/ |
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349 | /* Private function prototypes -----------------------------------------------*/ |
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350 | /** @defgroup ADC_Private_Functions ADC Private Functions |
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351 | * @{ |
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352 | */ |
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353 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); |
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354 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); |
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355 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc); |
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356 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); |
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357 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); |
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358 | static void ADC_DMAError(DMA_HandleTypeDef *hdma); |
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359 | /** |
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360 | * @} |
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361 | */ |
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362 | |||
363 | /* Exported functions ---------------------------------------------------------*/ |
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364 | |||
365 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
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366 | * @{ |
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367 | */ |
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368 | |||
369 | /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions |
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370 | * @brief Initialization and Configuration functions |
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371 | * |
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372 | @verbatim |
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373 | =============================================================================== |
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374 | ##### Initialization and de-initialization functions ##### |
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375 | =============================================================================== |
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376 | [..] This section provides functions allowing to: |
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377 | (+) Initialize and configure the ADC. |
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378 | (+) De-initialize the ADC |
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379 | @endverbatim |
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380 | * @{ |
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381 | */ |
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382 | |||
383 | /** |
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384 | * @brief Initializes the ADC peripheral and regular group according to |
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385 | * parameters specified in structure "ADC_InitTypeDef". |
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386 | * @note As prerequisite, ADC clock must be configured at RCC top level |
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387 | * depending on both possible clock sources: APB clock of HSI clock. |
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388 | * See commented example code below that can be copied and uncommented |
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389 | * into HAL_ADC_MspInit(). |
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390 | * @note Possibility to update parameters on the fly: |
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391 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
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392 | * coming from ADC state reset. Following calls to this function can |
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393 | * be used to reconfigure some parameters of ADC_InitTypeDef |
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394 | * structure on the fly, without modifying MSP configuration. If ADC |
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395 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
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396 | * before HAL_ADC_Init(). |
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397 | * The setting of these parameters is conditioned to ADC state. |
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398 | * For parameters constraints, see comments of structure |
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399 | * "ADC_InitTypeDef". |
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400 | * @note This function configures the ADC within 2 scopes: scope of entire |
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401 | * ADC and scope of regular group. For parameters details, see comments |
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402 | * of structure "ADC_InitTypeDef". |
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403 | * @param hadc ADC handle |
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404 | * @retval HAL status |
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405 | */ |
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406 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
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407 | { |
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408 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
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409 | uint32_t tmpCFGR1 = 0U; |
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410 | |||
411 | /* Check ADC handle */ |
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412 | if(hadc == NULL) |
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413 | { |
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414 | return HAL_ERROR; |
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415 | } |
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416 | |||
417 | /* Check the parameters */ |
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418 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
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419 | assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); |
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420 | assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); |
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421 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
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422 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
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423 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
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424 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
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425 | assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); |
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426 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
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427 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); |
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428 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
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429 | assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); |
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430 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); |
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431 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); |
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432 | |||
433 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
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434 | /* at RCC top level depending on both possible clock sources: */ |
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435 | /* APB clock or HSI clock. */ |
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436 | /* Refer to header of this file for more details on clock enabling procedure*/ |
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437 | |||
438 | /* Actions performed only if ADC is coming from state reset: */ |
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439 | /* - Initialization of ADC MSP */ |
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440 | /* - ADC voltage regulator enable */ |
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441 | if (hadc->State == HAL_ADC_STATE_RESET) |
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442 | { |
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443 | /* Initialize ADC error code */ |
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444 | ADC_CLEAR_ERRORCODE(hadc); |
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445 | |||
446 | /* Allocate lock resource and initialize it */ |
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447 | hadc->Lock = HAL_UNLOCKED; |
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448 | |||
449 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
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450 | /* Init the ADC Callback settings */ |
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451 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ |
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452 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ |
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453 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ |
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454 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ |
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455 | |||
456 | if (hadc->MspInitCallback == NULL) |
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457 | { |
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458 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
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459 | } |
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460 | |||
461 | /* Init the low level hardware */ |
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462 | hadc->MspInitCallback(hadc); |
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463 | #else |
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464 | /* Init the low level hardware */ |
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465 | HAL_ADC_MspInit(hadc); |
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466 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
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467 | } |
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468 | |||
469 | /* Configuration of ADC parameters if previous preliminary actions are */ |
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470 | /* correctly completed. */ |
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471 | /* and if there is no conversion on going on regular group (ADC can be */ |
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472 | /* enabled anyway, in case of call of this function to update a parameter */ |
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473 | /* on the fly). */ |
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474 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && |
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475 | (tmp_hal_status == HAL_OK) && |
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476 | (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) |
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477 | { |
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478 | /* Set ADC state */ |
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479 | ADC_STATE_CLR_SET(hadc->State, |
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480 | HAL_ADC_STATE_REG_BUSY, |
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481 | HAL_ADC_STATE_BUSY_INTERNAL); |
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482 | |||
483 | /* Parameters update conditioned to ADC state: */ |
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484 | /* Parameters that can be updated only when ADC is disabled: */ |
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485 | /* - ADC clock mode */ |
||
486 | /* - ADC clock prescaler */ |
||
487 | /* - ADC resolution */ |
||
488 | if (ADC_IS_ENABLE(hadc) == RESET) |
||
489 | { |
||
490 | /* Some parameters of this register are not reset, since they are set */ |
||
491 | /* by other functions and must be kept in case of usage of this */ |
||
492 | /* function on the fly (update of a parameter of ADC_InitTypeDef */ |
||
493 | /* without needing to reconfigure all other ADC groups/channels */ |
||
494 | /* parameters): */ |
||
495 | /* - internal measurement paths: Vbat, temperature sensor, Vref */ |
||
496 | /* (set into HAL_ADC_ConfigChannel() ) */ |
||
497 | |||
498 | /* Configuration of ADC resolution */ |
||
499 | MODIFY_REG(hadc->Instance->CFGR1, |
||
500 | ADC_CFGR1_RES , |
||
501 | hadc->Init.Resolution ); |
||
502 | |||
503 | /* Configuration of ADC clock mode: clock source AHB or HSI with */ |
||
504 | /* selectable prescaler */ |
||
505 | MODIFY_REG(hadc->Instance->CFGR2 , |
||
506 | ADC_CFGR2_CKMODE , |
||
507 | hadc->Init.ClockPrescaler ); |
||
508 | } |
||
509 | |||
510 | /* Configuration of ADC: */ |
||
511 | /* - discontinuous mode */ |
||
512 | /* - LowPowerAutoWait mode */ |
||
513 | /* - LowPowerAutoPowerOff mode */ |
||
514 | /* - continuous conversion mode */ |
||
515 | /* - overrun */ |
||
516 | /* - external trigger to start conversion */ |
||
517 | /* - external trigger polarity */ |
||
518 | /* - data alignment */ |
||
519 | /* - resolution */ |
||
520 | /* - scan direction */ |
||
521 | /* - DMA continuous request */ |
||
522 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_DISCEN | |
||
523 | ADC_CFGR1_AUTOFF | |
||
524 | ADC_CFGR1_AUTDLY | |
||
525 | ADC_CFGR1_CONT | |
||
526 | ADC_CFGR1_OVRMOD | |
||
527 | ADC_CFGR1_EXTSEL | |
||
528 | ADC_CFGR1_EXTEN | |
||
529 | ADC_CFGR1_ALIGN | |
||
530 | ADC_CFGR1_SCANDIR | |
||
531 | ADC_CFGR1_DMACFG ); |
||
532 | |||
533 | tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | |
||
534 | ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | |
||
535 | ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | |
||
536 | ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | |
||
537 | hadc->Init.DataAlign | |
||
538 | ADC_SCANDIR(hadc->Init.ScanConvMode) | |
||
539 | ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); |
||
540 | |||
541 | /* Enable discontinuous mode only if continuous mode is disabled */ |
||
542 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
||
543 | { |
||
544 | if (hadc->Init.ContinuousConvMode == DISABLE) |
||
545 | { |
||
546 | /* Enable the selected ADC group regular discontinuous mode */ |
||
547 | tmpCFGR1 |= ADC_CFGR1_DISCEN; |
||
548 | } |
||
549 | else |
||
550 | { |
||
551 | /* ADC regular group discontinuous was intended to be enabled, */ |
||
552 | /* but ADC regular group modes continuous and sequencer discontinuous */ |
||
553 | /* cannot be enabled simultaneously. */ |
||
554 | |||
555 | /* Update ADC state machine to error */ |
||
556 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
557 | |||
558 | /* Set ADC error code to ADC IP internal error */ |
||
559 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
560 | } |
||
561 | } |
||
562 | |||
563 | /* Enable external trigger if trigger selection is different of software */ |
||
564 | /* start. */ |
||
565 | /* Note: This configuration keeps the hardware feature of parameter */ |
||
566 | /* ExternalTrigConvEdge "trigger edge none" equivalent to */ |
||
567 | /* software start. */ |
||
568 | if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) |
||
569 | { |
||
570 | tmpCFGR1 |= ( hadc->Init.ExternalTrigConv | |
||
571 | hadc->Init.ExternalTrigConvEdge ); |
||
572 | } |
||
573 | |||
574 | /* Update ADC configuration register with previous settings */ |
||
575 | hadc->Instance->CFGR1 |= tmpCFGR1; |
||
576 | |||
577 | /* Channel sampling time configuration */ |
||
578 | /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ |
||
579 | /* (obsolete): sampling time set in this function if parameter */ |
||
580 | /* "SamplingTimeCommon" has been set to a valid sampling time. */ |
||
581 | /* Otherwise, sampling time is set into ADC channel initialization */ |
||
582 | /* structure with parameter "SamplingTime" (obsolete). */ |
||
583 | if (IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
||
584 | { |
||
585 | /* Channel sampling time configuration */ |
||
586 | /* Clear the old sample time */ |
||
587 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); |
||
588 | |||
589 | /* Set the new sample time */ |
||
590 | hadc->Instance->SMPR |= ADC_SMPR_SET(hadc->Init.SamplingTimeCommon); |
||
591 | } |
||
592 | |||
593 | /* Check back that ADC registers have effectively been configured to */ |
||
594 | /* ensure of no potential problem of ADC core IP clocking. */ |
||
595 | /* Check through register CFGR1 (excluding analog watchdog configuration: */ |
||
596 | /* set into separate dedicated function, and bits of ADC resolution set */ |
||
597 | /* out of temporary variable 'tmpCFGR1'). */ |
||
598 | if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_RES)) |
||
599 | == tmpCFGR1) |
||
600 | { |
||
601 | /* Set ADC error code to none */ |
||
602 | ADC_CLEAR_ERRORCODE(hadc); |
||
603 | |||
604 | /* Set the ADC state */ |
||
605 | ADC_STATE_CLR_SET(hadc->State, |
||
606 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
607 | HAL_ADC_STATE_READY); |
||
608 | } |
||
609 | else |
||
610 | { |
||
611 | /* Update ADC state machine to error */ |
||
612 | ADC_STATE_CLR_SET(hadc->State, |
||
613 | HAL_ADC_STATE_BUSY_INTERNAL, |
||
614 | HAL_ADC_STATE_ERROR_INTERNAL); |
||
615 | |||
616 | /* Set ADC error code to ADC IP internal error */ |
||
617 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
618 | |||
619 | tmp_hal_status = HAL_ERROR; |
||
620 | } |
||
621 | |||
622 | } |
||
623 | else |
||
624 | { |
||
625 | /* Update ADC state machine to error */ |
||
626 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
627 | |||
628 | tmp_hal_status = HAL_ERROR; |
||
629 | } |
||
630 | |||
631 | /* Return function status */ |
||
632 | return tmp_hal_status; |
||
633 | } |
||
634 | |||
635 | |||
636 | /** |
||
637 | * @brief Deinitialize the ADC peripheral registers to their default reset |
||
638 | * values, with deinitialization of the ADC MSP. |
||
639 | * @note For devices with several ADCs: reset of ADC common registers is done |
||
640 | * only if all ADCs sharing the same common group are disabled. |
||
641 | * If this is not the case, reset of these common parameters reset is |
||
642 | * bypassed without error reporting: it can be the intended behaviour in |
||
643 | * case of reset of a single ADC while the other ADCs sharing the same |
||
644 | * common group is still running. |
||
645 | * @param hadc ADC handle |
||
646 | * @retval HAL status |
||
647 | */ |
||
648 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
||
649 | { |
||
650 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
651 | |||
652 | /* Check ADC handle */ |
||
653 | if(hadc == NULL) |
||
654 | { |
||
655 | return HAL_ERROR; |
||
656 | } |
||
657 | |||
658 | /* Check the parameters */ |
||
659 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
660 | |||
661 | /* Set ADC state */ |
||
662 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
||
663 | |||
664 | /* Stop potential conversion on going, on regular group */ |
||
665 | tmp_hal_status = ADC_ConversionStop(hadc); |
||
666 | |||
667 | /* Disable ADC peripheral if conversions are effectively stopped */ |
||
668 | if (tmp_hal_status == HAL_OK) |
||
669 | { |
||
670 | /* Disable the ADC peripheral */ |
||
671 | tmp_hal_status = ADC_Disable(hadc); |
||
672 | |||
673 | /* Check if ADC is effectively disabled */ |
||
674 | if (tmp_hal_status != HAL_ERROR) |
||
675 | { |
||
676 | /* Change ADC state */ |
||
677 | hadc->State = HAL_ADC_STATE_READY; |
||
678 | } |
||
679 | } |
||
680 | |||
681 | |||
682 | /* Configuration of ADC parameters if previous preliminary actions are */ |
||
683 | /* correctly completed. */ |
||
684 | if (tmp_hal_status != HAL_ERROR) |
||
685 | { |
||
686 | |||
687 | /* ========== Reset ADC registers ========== */ |
||
688 | /* Reset register IER */ |
||
689 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD | ADC_IT_OVR | |
||
690 | ADC_IT_EOS | ADC_IT_EOC | |
||
691 | ADC_IT_EOSMP | ADC_IT_RDY ) ); |
||
692 | |||
693 | /* Reset register ISR */ |
||
694 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_OVR | |
||
695 | ADC_FLAG_EOS | ADC_FLAG_EOC | |
||
696 | ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); |
||
697 | |||
698 | /* Reset register CR */ |
||
699 | /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ |
||
700 | /* "read-set": no direct reset applicable. */ |
||
701 | |||
702 | /* Reset register CFGR1 */ |
||
703 | hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN | |
||
704 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | |
||
705 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | |
||
706 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ); |
||
707 | |||
708 | /* Reset register CFGR2 */ |
||
709 | /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ |
||
710 | /* already done above. */ |
||
711 | hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; |
||
712 | |||
713 | /* Reset register SMPR */ |
||
714 | hadc->Instance->SMPR &= ~ADC_SMPR_SMP; |
||
715 | |||
716 | /* Reset register TR1 */ |
||
717 | hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); |
||
718 | |||
719 | /* Reset register CHSELR */ |
||
720 | hadc->Instance->CHSELR &= ~(ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 | |
||
721 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 | |
||
722 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 | |
||
723 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 | |
||
724 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ); |
||
725 | |||
726 | /* Reset register DR */ |
||
727 | /* bits in access mode read only, no direct reset applicable*/ |
||
728 | |||
729 | /* Reset register CCR */ |
||
730 | ADC->CCR &= ~(ADC_CCR_ALL); |
||
731 | |||
732 | /* ========== Hard reset ADC peripheral ========== */ |
||
733 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
||
734 | /* forced to a similar state after device power-on. */ |
||
735 | /* If needed, copy-paste and uncomment the following reset code into */ |
||
736 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
||
737 | /* */ |
||
738 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
||
739 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
||
740 | |||
741 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
742 | if (hadc->MspDeInitCallback == NULL) |
||
743 | { |
||
744 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
745 | } |
||
746 | |||
747 | /* DeInit the low level hardware */ |
||
748 | hadc->MspDeInitCallback(hadc); |
||
749 | #else |
||
750 | /* DeInit the low level hardware */ |
||
751 | HAL_ADC_MspDeInit(hadc); |
||
752 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
753 | |||
754 | /* Set ADC error code to none */ |
||
755 | ADC_CLEAR_ERRORCODE(hadc); |
||
756 | |||
757 | /* Set ADC state */ |
||
758 | hadc->State = HAL_ADC_STATE_RESET; |
||
759 | } |
||
760 | |||
761 | /* Process unlocked */ |
||
762 | __HAL_UNLOCK(hadc); |
||
763 | |||
764 | /* Return function status */ |
||
765 | return tmp_hal_status; |
||
766 | } |
||
767 | |||
768 | |||
769 | /** |
||
770 | * @brief Initializes the ADC MSP. |
||
771 | * @param hadc ADC handle |
||
772 | * @retval None |
||
773 | */ |
||
774 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
||
775 | { |
||
776 | /* Prevent unused argument(s) compilation warning */ |
||
777 | UNUSED(hadc); |
||
778 | |||
779 | /* NOTE : This function should not be modified. When the callback is needed, |
||
780 | function HAL_ADC_MspInit must be implemented in the user file. |
||
781 | */ |
||
782 | } |
||
783 | |||
784 | /** |
||
785 | * @brief DeInitializes the ADC MSP. |
||
786 | * @param hadc ADC handle |
||
787 | * @retval None |
||
788 | */ |
||
789 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
||
790 | { |
||
791 | /* Prevent unused argument(s) compilation warning */ |
||
792 | UNUSED(hadc); |
||
793 | |||
794 | /* NOTE : This function should not be modified. When the callback is needed, |
||
795 | function HAL_ADC_MspDeInit must be implemented in the user file. |
||
796 | */ |
||
797 | } |
||
798 | |||
799 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
800 | /** |
||
801 | * @brief Register a User ADC Callback |
||
802 | * To be used instead of the weak predefined callback |
||
803 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
804 | * the configuration information for the specified ADC. |
||
805 | * @param CallbackID ID of the callback to be registered |
||
806 | * This parameter can be one of the following values: |
||
807 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
808 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
809 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
810 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
811 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
812 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
813 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
814 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
815 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
816 | * @param pCallback pointer to the Callback function |
||
817 | * @retval HAL status |
||
818 | */ |
||
819 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) |
||
820 | { |
||
821 | HAL_StatusTypeDef status = HAL_OK; |
||
822 | |||
823 | if (pCallback == NULL) |
||
824 | { |
||
825 | /* Update the error code */ |
||
826 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
827 | |||
828 | return HAL_ERROR; |
||
829 | } |
||
830 | |||
831 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
832 | { |
||
833 | switch (CallbackID) |
||
834 | { |
||
835 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
836 | hadc->ConvCpltCallback = pCallback; |
||
837 | break; |
||
838 | |||
839 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
840 | hadc->ConvHalfCpltCallback = pCallback; |
||
841 | break; |
||
842 | |||
843 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
844 | hadc->LevelOutOfWindowCallback = pCallback; |
||
845 | break; |
||
846 | |||
847 | case HAL_ADC_ERROR_CB_ID : |
||
848 | hadc->ErrorCallback = pCallback; |
||
849 | break; |
||
850 | |||
851 | case HAL_ADC_MSPINIT_CB_ID : |
||
852 | hadc->MspInitCallback = pCallback; |
||
853 | break; |
||
854 | |||
855 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
856 | hadc->MspDeInitCallback = pCallback; |
||
857 | break; |
||
858 | |||
859 | default : |
||
860 | /* Update the error code */ |
||
861 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
862 | |||
863 | /* Return error status */ |
||
864 | status = HAL_ERROR; |
||
865 | break; |
||
866 | } |
||
867 | } |
||
868 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
869 | { |
||
870 | switch (CallbackID) |
||
871 | { |
||
872 | case HAL_ADC_MSPINIT_CB_ID : |
||
873 | hadc->MspInitCallback = pCallback; |
||
874 | break; |
||
875 | |||
876 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
877 | hadc->MspDeInitCallback = pCallback; |
||
878 | break; |
||
879 | |||
880 | default : |
||
881 | /* Update the error code */ |
||
882 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
883 | |||
884 | /* Return error status */ |
||
885 | status = HAL_ERROR; |
||
886 | break; |
||
887 | } |
||
888 | } |
||
889 | else |
||
890 | { |
||
891 | /* Update the error code */ |
||
892 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
893 | |||
894 | /* Return error status */ |
||
895 | status = HAL_ERROR; |
||
896 | } |
||
897 | |||
898 | return status; |
||
899 | } |
||
900 | |||
901 | /** |
||
902 | * @brief Unregister a ADC Callback |
||
903 | * ADC callback is redirected to the weak predefined callback |
||
904 | * @param hadc Pointer to a ADC_HandleTypeDef structure that contains |
||
905 | * the configuration information for the specified ADC. |
||
906 | * @param CallbackID ID of the callback to be unregistered |
||
907 | * This parameter can be one of the following values: |
||
908 | * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID |
||
909 | * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID |
||
910 | * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID |
||
911 | * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID |
||
912 | * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID |
||
913 | * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID |
||
914 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID |
||
915 | * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID |
||
916 | * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID |
||
917 | * @retval HAL status |
||
918 | */ |
||
919 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) |
||
920 | { |
||
921 | HAL_StatusTypeDef status = HAL_OK; |
||
922 | |||
923 | if ((hadc->State & HAL_ADC_STATE_READY) != 0) |
||
924 | { |
||
925 | switch (CallbackID) |
||
926 | { |
||
927 | case HAL_ADC_CONVERSION_COMPLETE_CB_ID : |
||
928 | hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; |
||
929 | break; |
||
930 | |||
931 | case HAL_ADC_CONVERSION_HALF_CB_ID : |
||
932 | hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; |
||
933 | break; |
||
934 | |||
935 | case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : |
||
936 | hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; |
||
937 | break; |
||
938 | |||
939 | case HAL_ADC_ERROR_CB_ID : |
||
940 | hadc->ErrorCallback = HAL_ADC_ErrorCallback; |
||
941 | break; |
||
942 | |||
943 | case HAL_ADC_MSPINIT_CB_ID : |
||
944 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
945 | break; |
||
946 | |||
947 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
948 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
949 | break; |
||
950 | |||
951 | default : |
||
952 | /* Update the error code */ |
||
953 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
954 | |||
955 | /* Return error status */ |
||
956 | status = HAL_ERROR; |
||
957 | break; |
||
958 | } |
||
959 | } |
||
960 | else if (HAL_ADC_STATE_RESET == hadc->State) |
||
961 | { |
||
962 | switch (CallbackID) |
||
963 | { |
||
964 | case HAL_ADC_MSPINIT_CB_ID : |
||
965 | hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ |
||
966 | break; |
||
967 | |||
968 | case HAL_ADC_MSPDEINIT_CB_ID : |
||
969 | hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ |
||
970 | break; |
||
971 | |||
972 | default : |
||
973 | /* Update the error code */ |
||
974 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
975 | |||
976 | /* Return error status */ |
||
977 | status = HAL_ERROR; |
||
978 | break; |
||
979 | } |
||
980 | } |
||
981 | else |
||
982 | { |
||
983 | /* Update the error code */ |
||
984 | hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; |
||
985 | |||
986 | /* Return error status */ |
||
987 | status = HAL_ERROR; |
||
988 | } |
||
989 | |||
990 | return status; |
||
991 | } |
||
992 | |||
993 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
994 | |||
995 | /** |
||
996 | * @} |
||
997 | */ |
||
998 | |||
999 | /** @defgroup ADC_Exported_Functions_Group2 IO operation functions |
||
1000 | * @brief IO operation functions |
||
1001 | * |
||
1002 | @verbatim |
||
1003 | =============================================================================== |
||
1004 | ##### IO operation functions ##### |
||
1005 | =============================================================================== |
||
1006 | [..] This section provides functions allowing to: |
||
1007 | (+) Start conversion of regular group. |
||
1008 | (+) Stop conversion of regular group. |
||
1009 | (+) Poll for conversion complete on regular group. |
||
1010 | (+) Poll for conversion event. |
||
1011 | (+) Get result of regular channel conversion. |
||
1012 | (+) Start conversion of regular group and enable interruptions. |
||
1013 | (+) Stop conversion of regular group and disable interruptions. |
||
1014 | (+) Handle ADC interrupt request |
||
1015 | (+) Start conversion of regular group and enable DMA transfer. |
||
1016 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
||
1017 | @endverbatim |
||
1018 | * @{ |
||
1019 | */ |
||
1020 | |||
1021 | /** |
||
1022 | * @brief Enables ADC, starts conversion of regular group. |
||
1023 | * Interruptions enabled in this function: None. |
||
1024 | * @param hadc ADC handle |
||
1025 | * @retval HAL status |
||
1026 | */ |
||
1027 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
||
1028 | { |
||
1029 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1030 | |||
1031 | /* Check the parameters */ |
||
1032 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1033 | |||
1034 | /* Perform ADC enable and conversion start if no conversion is on going */ |
||
1035 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
1036 | { |
||
1037 | /* Process locked */ |
||
1038 | __HAL_LOCK(hadc); |
||
1039 | |||
1040 | /* Enable the ADC peripheral */ |
||
1041 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
||
1042 | /* performed automatically by hardware. */ |
||
1043 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
||
1044 | { |
||
1045 | tmp_hal_status = ADC_Enable(hadc); |
||
1046 | } |
||
1047 | |||
1048 | /* Start conversion if ADC is effectively enabled */ |
||
1049 | if (tmp_hal_status == HAL_OK) |
||
1050 | { |
||
1051 | /* Set ADC state */ |
||
1052 | /* - Clear state bitfield related to regular group conversion results */ |
||
1053 | /* - Set state bitfield related to regular operation */ |
||
1054 | ADC_STATE_CLR_SET(hadc->State, |
||
1055 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
||
1056 | HAL_ADC_STATE_REG_BUSY); |
||
1057 | |||
1058 | /* Reset ADC all error code fields */ |
||
1059 | ADC_CLEAR_ERRORCODE(hadc); |
||
1060 | |||
1061 | /* Process unlocked */ |
||
1062 | /* Unlock before starting ADC conversions: in case of potential */ |
||
1063 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
1064 | __HAL_UNLOCK(hadc); |
||
1065 | |||
1066 | /* Clear regular group conversion flag and overrun flag */ |
||
1067 | /* (To ensure of no unknown state from potential previous ADC */ |
||
1068 | /* operations) */ |
||
1069 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
||
1070 | |||
1071 | /* Enable conversion of regular group. */ |
||
1072 | /* If software start has been selected, conversion starts immediately. */ |
||
1073 | /* If external trigger has been selected, conversion will start at next */ |
||
1074 | /* trigger event. */ |
||
1075 | hadc->Instance->CR |= ADC_CR_ADSTART; |
||
1076 | } |
||
1077 | } |
||
1078 | else |
||
1079 | { |
||
1080 | tmp_hal_status = HAL_BUSY; |
||
1081 | } |
||
1082 | |||
1083 | /* Return function status */ |
||
1084 | return tmp_hal_status; |
||
1085 | } |
||
1086 | |||
1087 | /** |
||
1088 | * @brief Stop ADC conversion of regular group, disable ADC peripheral. |
||
1089 | * @param hadc ADC handle |
||
1090 | * @retval HAL status. |
||
1091 | */ |
||
1092 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
||
1093 | { |
||
1094 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1095 | |||
1096 | /* Check the parameters */ |
||
1097 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1098 | |||
1099 | /* Process locked */ |
||
1100 | __HAL_LOCK(hadc); |
||
1101 | |||
1102 | /* 1. Stop potential conversion on going, on regular group */ |
||
1103 | tmp_hal_status = ADC_ConversionStop(hadc); |
||
1104 | |||
1105 | /* Disable ADC peripheral if conversions are effectively stopped */ |
||
1106 | if (tmp_hal_status == HAL_OK) |
||
1107 | { |
||
1108 | /* 2. Disable the ADC peripheral */ |
||
1109 | tmp_hal_status = ADC_Disable(hadc); |
||
1110 | |||
1111 | /* Check if ADC is effectively disabled */ |
||
1112 | if (tmp_hal_status == HAL_OK) |
||
1113 | { |
||
1114 | /* Set ADC state */ |
||
1115 | ADC_STATE_CLR_SET(hadc->State, |
||
1116 | HAL_ADC_STATE_REG_BUSY, |
||
1117 | HAL_ADC_STATE_READY); |
||
1118 | } |
||
1119 | } |
||
1120 | |||
1121 | /* Process unlocked */ |
||
1122 | __HAL_UNLOCK(hadc); |
||
1123 | |||
1124 | /* Return function status */ |
||
1125 | return tmp_hal_status; |
||
1126 | } |
||
1127 | |||
1128 | /** |
||
1129 | * @brief Wait for regular group conversion to be completed. |
||
1130 | * @note ADC conversion flags EOS (end of sequence) and EOC (end of |
||
1131 | * conversion) are cleared by this function, with an exception: |
||
1132 | * if low power feature "LowPowerAutoWait" is enabled, flags are |
||
1133 | * not cleared to not interfere with this feature until data register |
||
1134 | * is read using function HAL_ADC_GetValue(). |
||
1135 | * @note This function cannot be used in a particular setup: ADC configured |
||
1136 | * in DMA mode and polling for end of each conversion (ADC init |
||
1137 | * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). |
||
1138 | * In this case, DMA resets the flag EOC and polling cannot be |
||
1139 | * performed on each conversion. Nevertheless, polling can still |
||
1140 | * be performed on the complete sequence (ADC init |
||
1141 | * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). |
||
1142 | * @param hadc ADC handle |
||
1143 | * @param Timeout Timeout value in millisecond. |
||
1144 | * @retval HAL status |
||
1145 | */ |
||
1146 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
||
1147 | { |
||
1148 | uint32_t tickstart; |
||
1149 | uint32_t tmp_Flag_EOC; |
||
1150 | |||
1151 | /* Check the parameters */ |
||
1152 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1153 | |||
1154 | /* If end of conversion selected to end of sequence */ |
||
1155 | if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) |
||
1156 | { |
||
1157 | tmp_Flag_EOC = ADC_FLAG_EOS; |
||
1158 | } |
||
1159 | /* If end of conversion selected to end of each conversion */ |
||
1160 | else /* ADC_EOC_SINGLE_CONV */ |
||
1161 | { |
||
1162 | /* Verification that ADC configuration is compliant with polling for */ |
||
1163 | /* each conversion: */ |
||
1164 | /* Particular case is ADC configured in DMA mode and ADC sequencer with */ |
||
1165 | /* several ranks and polling for end of each conversion. */ |
||
1166 | /* For code simplicity sake, this particular case is generalized to */ |
||
1167 | /* ADC configured in DMA mode and and polling for end of each conversion. */ |
||
1168 | if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) |
||
1169 | { |
||
1170 | /* Update ADC state machine to error */ |
||
1171 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
1172 | |||
1173 | /* Process unlocked */ |
||
1174 | __HAL_UNLOCK(hadc); |
||
1175 | |||
1176 | return HAL_ERROR; |
||
1177 | } |
||
1178 | else |
||
1179 | { |
||
1180 | tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); |
||
1181 | } |
||
1182 | } |
||
1183 | |||
1184 | /* Get tick count */ |
||
1185 | tickstart = HAL_GetTick(); |
||
1186 | |||
1187 | /* Wait until End of Conversion flag is raised */ |
||
1188 | while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) |
||
1189 | { |
||
1190 | /* Check if timeout is disabled (set to infinite wait) */ |
||
1191 | if(Timeout != HAL_MAX_DELAY) |
||
1192 | { |
||
1193 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) |
||
1194 | { |
||
1195 | /* Update ADC state machine to timeout */ |
||
1196 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
1197 | |||
1198 | /* Process unlocked */ |
||
1199 | __HAL_UNLOCK(hadc); |
||
1200 | |||
1201 | return HAL_TIMEOUT; |
||
1202 | } |
||
1203 | } |
||
1204 | } |
||
1205 | |||
1206 | /* Update ADC state machine */ |
||
1207 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
1208 | |||
1209 | /* Determine whether any further conversion upcoming on group regular */ |
||
1210 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
1211 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
1212 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
||
1213 | { |
||
1214 | /* If End of Sequence is reached, disable interrupts */ |
||
1215 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
||
1216 | { |
||
1217 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
||
1218 | /* ADSTART==0 (no conversion on going) */ |
||
1219 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
1220 | { |
||
1221 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
1222 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
1223 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
||
1224 | /* by overrun IRQ process below. */ |
||
1225 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
||
1226 | |||
1227 | /* Set ADC state */ |
||
1228 | ADC_STATE_CLR_SET(hadc->State, |
||
1229 | HAL_ADC_STATE_REG_BUSY, |
||
1230 | HAL_ADC_STATE_READY); |
||
1231 | } |
||
1232 | else |
||
1233 | { |
||
1234 | /* Change ADC state to error state */ |
||
1235 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
1236 | |||
1237 | /* Set ADC error code to ADC IP internal error */ |
||
1238 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
1239 | } |
||
1240 | } |
||
1241 | } |
||
1242 | |||
1243 | /* Clear end of conversion flag of regular group if low power feature */ |
||
1244 | /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ |
||
1245 | /* until data register is read using function HAL_ADC_GetValue(). */ |
||
1246 | if (hadc->Init.LowPowerAutoWait == DISABLE) |
||
1247 | { |
||
1248 | /* Clear regular group conversion flag */ |
||
1249 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); |
||
1250 | } |
||
1251 | |||
1252 | /* Return ADC state */ |
||
1253 | return HAL_OK; |
||
1254 | } |
||
1255 | |||
1256 | /** |
||
1257 | * @brief Poll for conversion event. |
||
1258 | * @param hadc ADC handle |
||
1259 | * @param EventType the ADC event type. |
||
1260 | * This parameter can be one of the following values: |
||
1261 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event |
||
1262 | * @arg ADC_OVR_EVENT: ADC Overrun event |
||
1263 | * @param Timeout Timeout value in millisecond. |
||
1264 | * @retval HAL status |
||
1265 | */ |
||
1266 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
||
1267 | { |
||
1268 | uint32_t tickstart=0; |
||
1269 | |||
1270 | /* Check the parameters */ |
||
1271 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1272 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
||
1273 | |||
1274 | /* Get tick count */ |
||
1275 | tickstart = HAL_GetTick(); |
||
1276 | |||
1277 | /* Check selected event flag */ |
||
1278 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
||
1279 | { |
||
1280 | /* Check if timeout is disabled (set to infinite wait) */ |
||
1281 | if(Timeout != HAL_MAX_DELAY) |
||
1282 | { |
||
1283 | if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) |
||
1284 | { |
||
1285 | /* Update ADC state machine to timeout */ |
||
1286 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
||
1287 | |||
1288 | /* Process unlocked */ |
||
1289 | __HAL_UNLOCK(hadc); |
||
1290 | |||
1291 | return HAL_TIMEOUT; |
||
1292 | } |
||
1293 | } |
||
1294 | } |
||
1295 | |||
1296 | switch(EventType) |
||
1297 | { |
||
1298 | /* Analog watchdog (level out of window) event */ |
||
1299 | case ADC_AWD_EVENT: |
||
1300 | /* Set ADC state */ |
||
1301 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
1302 | |||
1303 | /* Clear ADC analog watchdog flag */ |
||
1304 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
1305 | break; |
||
1306 | |||
1307 | /* Overrun event */ |
||
1308 | default: /* Case ADC_OVR_EVENT */ |
||
1309 | /* If overrun is set to overwrite previous data, overrun event is not */ |
||
1310 | /* considered as an error. */ |
||
1311 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
||
1312 | /* overrun ") */ |
||
1313 | if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) |
||
1314 | { |
||
1315 | /* Set ADC state */ |
||
1316 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); |
||
1317 | |||
1318 | /* Set ADC error code to overrun */ |
||
1319 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
||
1320 | } |
||
1321 | |||
1322 | /* Clear ADC Overrun flag */ |
||
1323 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
1324 | break; |
||
1325 | } |
||
1326 | |||
1327 | /* Return ADC state */ |
||
1328 | return HAL_OK; |
||
1329 | } |
||
1330 | |||
1331 | /** |
||
1332 | * @brief Enables ADC, starts conversion of regular group with interruption. |
||
1333 | * Interruptions enabled in this function: |
||
1334 | * - EOC (end of conversion of regular group) or EOS (end of |
||
1335 | * sequence of regular group) depending on ADC initialization |
||
1336 | * parameter "EOCSelection" |
||
1337 | * - overrun (if available) |
||
1338 | * Each of these interruptions has its dedicated callback function. |
||
1339 | * @param hadc ADC handle |
||
1340 | * @retval HAL status |
||
1341 | */ |
||
1342 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
||
1343 | { |
||
1344 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1345 | |||
1346 | /* Check the parameters */ |
||
1347 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1348 | |||
1349 | /* Perform ADC enable and conversion start if no conversion is on going */ |
||
1350 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
1351 | { |
||
1352 | /* Process locked */ |
||
1353 | __HAL_LOCK(hadc); |
||
1354 | |||
1355 | /* Enable the ADC peripheral */ |
||
1356 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
||
1357 | /* performed automatically by hardware. */ |
||
1358 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
||
1359 | { |
||
1360 | tmp_hal_status = ADC_Enable(hadc); |
||
1361 | } |
||
1362 | |||
1363 | /* Start conversion if ADC is effectively enabled */ |
||
1364 | if (tmp_hal_status == HAL_OK) |
||
1365 | { |
||
1366 | /* Set ADC state */ |
||
1367 | /* - Clear state bitfield related to regular group conversion results */ |
||
1368 | /* - Set state bitfield related to regular operation */ |
||
1369 | ADC_STATE_CLR_SET(hadc->State, |
||
1370 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
||
1371 | HAL_ADC_STATE_REG_BUSY); |
||
1372 | |||
1373 | /* Reset ADC all error code fields */ |
||
1374 | ADC_CLEAR_ERRORCODE(hadc); |
||
1375 | |||
1376 | /* Process unlocked */ |
||
1377 | /* Unlock before starting ADC conversions: in case of potential */ |
||
1378 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
1379 | __HAL_UNLOCK(hadc); |
||
1380 | |||
1381 | /* Clear regular group conversion flag and overrun flag */ |
||
1382 | /* (To ensure of no unknown state from potential previous ADC */ |
||
1383 | /* operations) */ |
||
1384 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
||
1385 | |||
1386 | /* Enable ADC end of conversion interrupt */ |
||
1387 | /* Enable ADC overrun interrupt */ |
||
1388 | switch(hadc->Init.EOCSelection) |
||
1389 | { |
||
1390 | case ADC_EOC_SEQ_CONV: |
||
1391 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
||
1392 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR)); |
||
1393 | break; |
||
1394 | /* case ADC_EOC_SINGLE_CONV */ |
||
1395 | default: |
||
1396 | __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
||
1397 | break; |
||
1398 | } |
||
1399 | |||
1400 | /* Enable conversion of regular group. */ |
||
1401 | /* If software start has been selected, conversion starts immediately. */ |
||
1402 | /* If external trigger has been selected, conversion will start at next */ |
||
1403 | /* trigger event. */ |
||
1404 | hadc->Instance->CR |= ADC_CR_ADSTART; |
||
1405 | } |
||
1406 | } |
||
1407 | else |
||
1408 | { |
||
1409 | tmp_hal_status = HAL_BUSY; |
||
1410 | } |
||
1411 | |||
1412 | /* Return function status */ |
||
1413 | return tmp_hal_status; |
||
1414 | } |
||
1415 | |||
1416 | |||
1417 | /** |
||
1418 | * @brief Stop ADC conversion of regular group, disable interruption of |
||
1419 | * end-of-conversion, disable ADC peripheral. |
||
1420 | * @param hadc ADC handle |
||
1421 | * @retval HAL status. |
||
1422 | */ |
||
1423 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
||
1424 | { |
||
1425 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1426 | |||
1427 | /* Check the parameters */ |
||
1428 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1429 | |||
1430 | /* Process locked */ |
||
1431 | __HAL_LOCK(hadc); |
||
1432 | |||
1433 | /* 1. Stop potential conversion on going, on regular group */ |
||
1434 | tmp_hal_status = ADC_ConversionStop(hadc); |
||
1435 | |||
1436 | /* Disable ADC peripheral if conversions are effectively stopped */ |
||
1437 | if (tmp_hal_status == HAL_OK) |
||
1438 | { |
||
1439 | /* Disable ADC end of conversion interrupt for regular group */ |
||
1440 | /* Disable ADC overrun interrupt */ |
||
1441 | __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); |
||
1442 | |||
1443 | /* 2. Disable the ADC peripheral */ |
||
1444 | tmp_hal_status = ADC_Disable(hadc); |
||
1445 | |||
1446 | /* Check if ADC is effectively disabled */ |
||
1447 | if (tmp_hal_status == HAL_OK) |
||
1448 | { |
||
1449 | /* Set ADC state */ |
||
1450 | ADC_STATE_CLR_SET(hadc->State, |
||
1451 | HAL_ADC_STATE_REG_BUSY, |
||
1452 | HAL_ADC_STATE_READY); |
||
1453 | } |
||
1454 | } |
||
1455 | |||
1456 | /* Process unlocked */ |
||
1457 | __HAL_UNLOCK(hadc); |
||
1458 | |||
1459 | /* Return function status */ |
||
1460 | return tmp_hal_status; |
||
1461 | } |
||
1462 | |||
1463 | /** |
||
1464 | * @brief Enables ADC, starts conversion of regular group and transfers result |
||
1465 | * through DMA. |
||
1466 | * Interruptions enabled in this function: |
||
1467 | * - DMA transfer complete |
||
1468 | * - DMA half transfer |
||
1469 | * - overrun |
||
1470 | * Each of these interruptions has its dedicated callback function. |
||
1471 | * @param hadc ADC handle |
||
1472 | * @param pData The destination Buffer address. |
||
1473 | * @param Length The length of data to be transferred from ADC peripheral to memory. |
||
1474 | * @retval None |
||
1475 | */ |
||
1476 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
||
1477 | { |
||
1478 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1479 | |||
1480 | /* Check the parameters */ |
||
1481 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1482 | |||
1483 | /* Perform ADC enable and conversion start if no conversion is on going */ |
||
1484 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
1485 | { |
||
1486 | /* Process locked */ |
||
1487 | __HAL_LOCK(hadc); |
||
1488 | |||
1489 | /* Enable the ADC peripheral */ |
||
1490 | /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
||
1491 | /* performed automatically by hardware. */ |
||
1492 | if (hadc->Init.LowPowerAutoPowerOff != ENABLE) |
||
1493 | { |
||
1494 | tmp_hal_status = ADC_Enable(hadc); |
||
1495 | } |
||
1496 | |||
1497 | /* Start conversion if ADC is effectively enabled */ |
||
1498 | if (tmp_hal_status == HAL_OK) |
||
1499 | { |
||
1500 | /* Set ADC state */ |
||
1501 | /* - Clear state bitfield related to regular group conversion results */ |
||
1502 | /* - Set state bitfield related to regular operation */ |
||
1503 | ADC_STATE_CLR_SET(hadc->State, |
||
1504 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
||
1505 | HAL_ADC_STATE_REG_BUSY); |
||
1506 | |||
1507 | /* Reset ADC all error code fields */ |
||
1508 | ADC_CLEAR_ERRORCODE(hadc); |
||
1509 | |||
1510 | /* Process unlocked */ |
||
1511 | /* Unlock before starting ADC conversions: in case of potential */ |
||
1512 | /* interruption, to let the process to ADC IRQ Handler. */ |
||
1513 | __HAL_UNLOCK(hadc); |
||
1514 | |||
1515 | /* Set the DMA transfer complete callback */ |
||
1516 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
||
1517 | |||
1518 | /* Set the DMA half transfer complete callback */ |
||
1519 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
||
1520 | |||
1521 | /* Set the DMA error callback */ |
||
1522 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
||
1523 | |||
1524 | |||
1525 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
||
1526 | /* start (in case of SW start): */ |
||
1527 | |||
1528 | /* Clear regular group conversion flag and overrun flag */ |
||
1529 | /* (To ensure of no unknown state from potential previous ADC */ |
||
1530 | /* operations) */ |
||
1531 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); |
||
1532 | |||
1533 | /* Enable ADC overrun interrupt */ |
||
1534 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); |
||
1535 | |||
1536 | /* Enable ADC DMA mode */ |
||
1537 | hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; |
||
1538 | |||
1539 | /* Start the DMA channel */ |
||
1540 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
||
1541 | |||
1542 | /* Enable conversion of regular group. */ |
||
1543 | /* If software start has been selected, conversion starts immediately. */ |
||
1544 | /* If external trigger has been selected, conversion will start at next */ |
||
1545 | /* trigger event. */ |
||
1546 | hadc->Instance->CR |= ADC_CR_ADSTART; |
||
1547 | } |
||
1548 | } |
||
1549 | else |
||
1550 | { |
||
1551 | tmp_hal_status = HAL_BUSY; |
||
1552 | } |
||
1553 | |||
1554 | /* Return function status */ |
||
1555 | return tmp_hal_status; |
||
1556 | } |
||
1557 | |||
1558 | /** |
||
1559 | * @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable |
||
1560 | * ADC peripheral. |
||
1561 | * Each of these interruptions has its dedicated callback function. |
||
1562 | * @param hadc ADC handle |
||
1563 | * @retval HAL status. |
||
1564 | */ |
||
1565 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
||
1566 | { |
||
1567 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1568 | |||
1569 | /* Check the parameters */ |
||
1570 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1571 | |||
1572 | /* Process locked */ |
||
1573 | __HAL_LOCK(hadc); |
||
1574 | |||
1575 | /* 1. Stop potential conversion on going, on regular group */ |
||
1576 | tmp_hal_status = ADC_ConversionStop(hadc); |
||
1577 | |||
1578 | /* Disable ADC peripheral if conversions are effectively stopped */ |
||
1579 | if (tmp_hal_status == HAL_OK) |
||
1580 | { |
||
1581 | /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ |
||
1582 | hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN; |
||
1583 | |||
1584 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
||
1585 | /* while DMA transfer is on going) */ |
||
1586 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
||
1587 | |||
1588 | /* Check if DMA channel effectively disabled */ |
||
1589 | if (tmp_hal_status != HAL_OK) |
||
1590 | { |
||
1591 | /* Update ADC state machine to error */ |
||
1592 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
1593 | } |
||
1594 | |||
1595 | /* Disable ADC overrun interrupt */ |
||
1596 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); |
||
1597 | |||
1598 | /* 2. Disable the ADC peripheral */ |
||
1599 | /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ |
||
1600 | /* in memory a potential failing status. */ |
||
1601 | if (tmp_hal_status == HAL_OK) |
||
1602 | { |
||
1603 | tmp_hal_status = ADC_Disable(hadc); |
||
1604 | } |
||
1605 | else |
||
1606 | { |
||
1607 | ADC_Disable(hadc); |
||
1608 | } |
||
1609 | |||
1610 | /* Check if ADC is effectively disabled */ |
||
1611 | if (tmp_hal_status == HAL_OK) |
||
1612 | { |
||
1613 | /* Set ADC state */ |
||
1614 | ADC_STATE_CLR_SET(hadc->State, |
||
1615 | HAL_ADC_STATE_REG_BUSY, |
||
1616 | HAL_ADC_STATE_READY); |
||
1617 | } |
||
1618 | |||
1619 | } |
||
1620 | |||
1621 | /* Process unlocked */ |
||
1622 | __HAL_UNLOCK(hadc); |
||
1623 | |||
1624 | /* Return function status */ |
||
1625 | return tmp_hal_status; |
||
1626 | } |
||
1627 | |||
1628 | /** |
||
1629 | * @brief Get ADC regular group conversion result. |
||
1630 | * @note Reading register DR automatically clears ADC flag EOC |
||
1631 | * (ADC group regular end of unitary conversion). |
||
1632 | * @note This function does not clear ADC flag EOS |
||
1633 | * (ADC group regular end of sequence conversion). |
||
1634 | * Occurrence of flag EOS rising: |
||
1635 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
||
1636 | * to flag EOC. |
||
1637 | * - If sequencer is composed of several ranks, during the scan |
||
1638 | * sequence flag EOC only is raised, at the end of the scan sequence |
||
1639 | * both flags EOC and EOS are raised. |
||
1640 | * To clear this flag, either use function: |
||
1641 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
||
1642 | * model polling: @ref HAL_ADC_PollForConversion() |
||
1643 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
||
1644 | * @param hadc ADC handle |
||
1645 | * @retval ADC group regular conversion data |
||
1646 | */ |
||
1647 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
||
1648 | { |
||
1649 | /* Check the parameters */ |
||
1650 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1651 | |||
1652 | /* Note: EOC flag is not cleared here by software because automatically */ |
||
1653 | /* cleared by hardware when reading register DR. */ |
||
1654 | |||
1655 | /* Return ADC converted value */ |
||
1656 | return hadc->Instance->DR; |
||
1657 | } |
||
1658 | |||
1659 | /** |
||
1660 | * @brief Handles ADC interrupt request. |
||
1661 | * @param hadc ADC handle |
||
1662 | * @retval None |
||
1663 | */ |
||
1664 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
||
1665 | { |
||
1666 | /* Check the parameters */ |
||
1667 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1668 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
||
1669 | assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); |
||
1670 | |||
1671 | /* ========== Check End of Conversion flag for regular group ========== */ |
||
1672 | if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || |
||
1673 | (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) |
||
1674 | { |
||
1675 | /* Update state machine on conversion status if not in error state */ |
||
1676 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
||
1677 | { |
||
1678 | /* Set ADC state */ |
||
1679 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
1680 | } |
||
1681 | |||
1682 | /* Determine whether any further conversion upcoming on group regular */ |
||
1683 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
1684 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
1685 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
||
1686 | { |
||
1687 | /* If End of Sequence is reached, disable interrupts */ |
||
1688 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
||
1689 | { |
||
1690 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
||
1691 | /* ADSTART==0 (no conversion on going) */ |
||
1692 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
1693 | { |
||
1694 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
1695 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
1696 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
||
1697 | /* by overrun IRQ process below. */ |
||
1698 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
||
1699 | |||
1700 | /* Set ADC state */ |
||
1701 | ADC_STATE_CLR_SET(hadc->State, |
||
1702 | HAL_ADC_STATE_REG_BUSY, |
||
1703 | HAL_ADC_STATE_READY); |
||
1704 | } |
||
1705 | else |
||
1706 | { |
||
1707 | /* Change ADC state to error state */ |
||
1708 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
1709 | |||
1710 | /* Set ADC error code to ADC IP internal error */ |
||
1711 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
1712 | } |
||
1713 | } |
||
1714 | } |
||
1715 | |||
1716 | /* Note: into callback, to determine if conversion has been triggered */ |
||
1717 | /* from EOC or EOS, possibility to use: */ |
||
1718 | /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ |
||
1719 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1720 | hadc->ConvCpltCallback(hadc); |
||
1721 | #else |
||
1722 | HAL_ADC_ConvCpltCallback(hadc); |
||
1723 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1724 | |||
1725 | |||
1726 | /* Clear regular group conversion flag */ |
||
1727 | /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ |
||
1728 | /* conversion flags clear induces the release of the preserved data.*/ |
||
1729 | /* Therefore, if the preserved data value is needed, it must be */ |
||
1730 | /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ |
||
1731 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); |
||
1732 | } |
||
1733 | |||
1734 | /* ========== Check Analog watchdog flags ========== */ |
||
1735 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
||
1736 | { |
||
1737 | /* Set ADC state */ |
||
1738 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
||
1739 | |||
1740 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1741 | hadc->LevelOutOfWindowCallback(hadc); |
||
1742 | #else |
||
1743 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
||
1744 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1745 | |||
1746 | /* Clear ADC Analog watchdog flag */ |
||
1747 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
||
1748 | |||
1749 | } |
||
1750 | |||
1751 | |||
1752 | /* ========== Check Overrun flag ========== */ |
||
1753 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) |
||
1754 | { |
||
1755 | /* If overrun is set to overwrite previous data (default setting), */ |
||
1756 | /* overrun event is not considered as an error. */ |
||
1757 | /* (cf ref manual "Managing conversions without using the DMA and without */ |
||
1758 | /* overrun ") */ |
||
1759 | /* Exception for usage with DMA overrun event always considered as an */ |
||
1760 | /* error. */ |
||
1761 | if ((hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) || |
||
1762 | HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) ) |
||
1763 | { |
||
1764 | /* Set ADC error code to overrun */ |
||
1765 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); |
||
1766 | |||
1767 | /* Clear ADC overrun flag */ |
||
1768 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
1769 | |||
1770 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
1771 | hadc->ErrorCallback(hadc); |
||
1772 | #else |
||
1773 | HAL_ADC_ErrorCallback(hadc); |
||
1774 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
1775 | } |
||
1776 | |||
1777 | /* Clear the Overrun flag */ |
||
1778 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); |
||
1779 | } |
||
1780 | |||
1781 | } |
||
1782 | |||
1783 | |||
1784 | /** |
||
1785 | * @brief Conversion complete callback in non blocking mode |
||
1786 | * @param hadc ADC handle |
||
1787 | * @retval None |
||
1788 | */ |
||
1789 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
||
1790 | { |
||
1791 | /* Prevent unused argument(s) compilation warning */ |
||
1792 | UNUSED(hadc); |
||
1793 | |||
1794 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1795 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
||
1796 | */ |
||
1797 | } |
||
1798 | |||
1799 | /** |
||
1800 | * @brief Conversion DMA half-transfer callback in non blocking mode |
||
1801 | * @param hadc ADC handle |
||
1802 | * @retval None |
||
1803 | */ |
||
1804 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
||
1805 | { |
||
1806 | /* Prevent unused argument(s) compilation warning */ |
||
1807 | UNUSED(hadc); |
||
1808 | |||
1809 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1810 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
||
1811 | */ |
||
1812 | } |
||
1813 | |||
1814 | /** |
||
1815 | * @brief Analog watchdog callback in non blocking mode. |
||
1816 | * @param hadc ADC handle |
||
1817 | * @retval None |
||
1818 | */ |
||
1819 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
||
1820 | { |
||
1821 | /* Prevent unused argument(s) compilation warning */ |
||
1822 | UNUSED(hadc); |
||
1823 | |||
1824 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1825 | function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. |
||
1826 | */ |
||
1827 | } |
||
1828 | |||
1829 | /** |
||
1830 | * @brief ADC error callback in non blocking mode |
||
1831 | * (ADC conversion with interruption or transfer by DMA) |
||
1832 | * @param hadc ADC handle |
||
1833 | * @retval None |
||
1834 | */ |
||
1835 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
||
1836 | { |
||
1837 | /* Prevent unused argument(s) compilation warning */ |
||
1838 | UNUSED(hadc); |
||
1839 | |||
1840 | /* NOTE : This function should not be modified. When the callback is needed, |
||
1841 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
||
1842 | */ |
||
1843 | } |
||
1844 | |||
1845 | |||
1846 | /** |
||
1847 | * @} |
||
1848 | */ |
||
1849 | |||
1850 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
||
1851 | * @brief Peripheral Control functions |
||
1852 | * |
||
1853 | @verbatim |
||
1854 | =============================================================================== |
||
1855 | ##### Peripheral Control functions ##### |
||
1856 | =============================================================================== |
||
1857 | [..] This section provides functions allowing to: |
||
1858 | (+) Configure channels on regular group |
||
1859 | (+) Configure the analog watchdog |
||
1860 | |||
1861 | @endverbatim |
||
1862 | * @{ |
||
1863 | */ |
||
1864 | |||
1865 | /** |
||
1866 | * @brief Configures the the selected channel to be linked to the regular |
||
1867 | * group. |
||
1868 | * @note In case of usage of internal measurement channels: |
||
1869 | * VrefInt/Vbat/TempSensor. |
||
1870 | * Sampling time constraints must be respected (sampling time can be |
||
1871 | * adjusted in function of ADC clock frequency and sampling time |
||
1872 | * setting). |
||
1873 | * Refer to device datasheet for timings values, parameters TS_vrefint, |
||
1874 | * TS_vbat, TS_temp (values rough order: 5us to 17us). |
||
1875 | * These internal paths can be be disabled using function |
||
1876 | * HAL_ADC_DeInit(). |
||
1877 | * @note Possibility to update parameters on the fly: |
||
1878 | * This function initializes channel into regular group, following |
||
1879 | * calls to this function can be used to reconfigure some parameters |
||
1880 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
||
1881 | * the ADC. |
||
1882 | * The setting of these parameters is conditioned to ADC state. |
||
1883 | * For parameters constraints, see comments of structure |
||
1884 | * "ADC_ChannelConfTypeDef". |
||
1885 | * @param hadc ADC handle |
||
1886 | * @param sConfig Structure of ADC channel for regular group. |
||
1887 | * @retval HAL status |
||
1888 | */ |
||
1889 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
||
1890 | { |
||
1891 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
1892 | __IO uint32_t wait_loop_index = 0U; |
||
1893 | |||
1894 | /* Check the parameters */ |
||
1895 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
1896 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
||
1897 | assert_param(IS_ADC_RANK(sConfig->Rank)); |
||
1898 | |||
1899 | if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
||
1900 | { |
||
1901 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
||
1902 | } |
||
1903 | |||
1904 | /* Process locked */ |
||
1905 | __HAL_LOCK(hadc); |
||
1906 | |||
1907 | /* Parameters update conditioned to ADC state: */ |
||
1908 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
||
1909 | /* conversion on going on regular group: */ |
||
1910 | /* - Channel number */ |
||
1911 | /* - Channel sampling time */ |
||
1912 | /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
||
1913 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
1914 | { |
||
1915 | /* Configure channel: depending on rank setting, add it or remove it from */ |
||
1916 | /* ADC conversion sequencer. */ |
||
1917 | if (sConfig->Rank != ADC_RANK_NONE) |
||
1918 | { |
||
1919 | /* Regular sequence configuration */ |
||
1920 | /* Set the channel selection register from the selected channel */ |
||
1921 | hadc->Instance->CHSELR |= ADC_CHSELR_CHANNEL(sConfig->Channel); |
||
1922 | |||
1923 | /* Channel sampling time configuration */ |
||
1924 | /* Management of parameters "SamplingTimeCommon" and "SamplingTime" */ |
||
1925 | /* (obsolete): sampling time set in this function with */ |
||
1926 | /* parameter "SamplingTime" (obsolete) only if not already set into */ |
||
1927 | /* ADC initialization structure with parameter "SamplingTimeCommon". */ |
||
1928 | if (! IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon)) |
||
1929 | { |
||
1930 | /* Modify sampling time if needed (not needed in case of reoccurrence */ |
||
1931 | /* for several channels programmed consecutively into the sequencer) */ |
||
1932 | if (sConfig->SamplingTime != ADC_GET_SAMPLINGTIME(hadc)) |
||
1933 | { |
||
1934 | /* Channel sampling time configuration */ |
||
1935 | /* Clear the old sample time */ |
||
1936 | hadc->Instance->SMPR &= ~(ADC_SMPR_SMP); |
||
1937 | |||
1938 | /* Set the new sample time */ |
||
1939 | hadc->Instance->SMPR |= ADC_SMPR_SET(sConfig->SamplingTime); |
||
1940 | } |
||
1941 | } |
||
1942 | |||
1943 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
||
1944 | /* internal measurement paths enable: If internal channel selected, */ |
||
1945 | /* enable dedicated internal buffers and path. */ |
||
1946 | /* Note: these internal measurement paths can be disabled using */ |
||
1947 | /* HAL_ADC_DeInit() or removing the channel from sequencer with */ |
||
1948 | /* channel configuration parameter "Rank". */ |
||
1949 | if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) |
||
1950 | { |
||
1951 | /* If Channel_16 is selected, enable Temp. sensor measurement path. */ |
||
1952 | /* If Channel_17 is selected, enable VREFINT measurement path. */ |
||
1953 | /* If Channel_18 is selected, enable VBAT measurement path. */ |
||
1954 | ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); |
||
1955 | |||
1956 | /* If Temp. sensor is selected, wait for stabilization delay */ |
||
1957 | if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) |
||
1958 | { |
||
1959 | /* Delay for temperature sensor stabilization time */ |
||
1960 | /* Compute number of CPU cycles to wait for */ |
||
1961 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); |
||
1962 | while(wait_loop_index != 0U) |
||
1963 | { |
||
1964 | wait_loop_index--; |
||
1965 | } |
||
1966 | } |
||
1967 | } |
||
1968 | } |
||
1969 | else |
||
1970 | { |
||
1971 | /* Regular sequence configuration */ |
||
1972 | /* Reset the channel selection register from the selected channel */ |
||
1973 | hadc->Instance->CHSELR &= ~ADC_CHSELR_CHANNEL(sConfig->Channel); |
||
1974 | |||
1975 | /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ |
||
1976 | /* internal measurement paths disable: If internal channel selected, */ |
||
1977 | /* disable dedicated internal buffers and path. */ |
||
1978 | if(ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) |
||
1979 | { |
||
1980 | /* If Channel_16 is selected, disable Temp. sensor measurement path. */ |
||
1981 | /* If Channel_17 is selected, disable VREFINT measurement path. */ |
||
1982 | /* If Channel_18 is selected, disable VBAT measurement path. */ |
||
1983 | ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); |
||
1984 | } |
||
1985 | } |
||
1986 | |||
1987 | } |
||
1988 | |||
1989 | /* If a conversion is on going on regular group, no update on regular */ |
||
1990 | /* channel could be done on neither of the channel configuration structure */ |
||
1991 | /* parameters. */ |
||
1992 | else |
||
1993 | { |
||
1994 | /* Update ADC state machine to error */ |
||
1995 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
1996 | |||
1997 | tmp_hal_status = HAL_ERROR; |
||
1998 | } |
||
1999 | |||
2000 | /* Process unlocked */ |
||
2001 | __HAL_UNLOCK(hadc); |
||
2002 | |||
2003 | /* Return function status */ |
||
2004 | return tmp_hal_status; |
||
2005 | } |
||
2006 | |||
2007 | |||
2008 | /** |
||
2009 | * @brief Configures the analog watchdog. |
||
2010 | * @note Possibility to update parameters on the fly: |
||
2011 | * This function initializes the selected analog watchdog, following |
||
2012 | * calls to this function can be used to reconfigure some parameters |
||
2013 | * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting |
||
2014 | * the ADC. |
||
2015 | * The setting of these parameters is conditioned to ADC state. |
||
2016 | * For parameters constraints, see comments of structure |
||
2017 | * "ADC_AnalogWDGConfTypeDef". |
||
2018 | * @param hadc ADC handle |
||
2019 | * @param AnalogWDGConfig Structure of ADC analog watchdog configuration |
||
2020 | * @retval HAL status |
||
2021 | */ |
||
2022 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
||
2023 | { |
||
2024 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
||
2025 | |||
2026 | uint32_t tmpAWDHighThresholdShifted; |
||
2027 | uint32_t tmpAWDLowThresholdShifted; |
||
2028 | |||
2029 | /* Check the parameters */ |
||
2030 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
2031 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
||
2032 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
||
2033 | |||
2034 | /* Verify if threshold is within the selected ADC resolution */ |
||
2035 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); |
||
2036 | assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); |
||
2037 | |||
2038 | if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) |
||
2039 | { |
||
2040 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
||
2041 | } |
||
2042 | |||
2043 | /* Process locked */ |
||
2044 | __HAL_LOCK(hadc); |
||
2045 | |||
2046 | /* Parameters update conditioned to ADC state: */ |
||
2047 | /* Parameters that can be updated when ADC is disabled or enabled without */ |
||
2048 | /* conversion on going on regular group: */ |
||
2049 | /* - Analog watchdog channels */ |
||
2050 | /* - Analog watchdog thresholds */ |
||
2051 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
2052 | { |
||
2053 | /* Configuration of analog watchdog: */ |
||
2054 | /* - Set the analog watchdog enable mode: one or overall group of */ |
||
2055 | /* channels. */ |
||
2056 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
||
2057 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
||
2058 | hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | |
||
2059 | ADC_CFGR1_AWDEN | |
||
2060 | ADC_CFGR1_AWDCH ); |
||
2061 | |||
2062 | hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | |
||
2063 | ADC_CFGR_AWDCH(AnalogWDGConfig->Channel) ); |
||
2064 | |||
2065 | /* Shift the offset in function of the selected ADC resolution: Thresholds*/ |
||
2066 | /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ |
||
2067 | tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); |
||
2068 | tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); |
||
2069 | |||
2070 | /* Set the high and low thresholds */ |
||
2071 | hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT); |
||
2072 | hadc->Instance->TR |= ( ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | |
||
2073 | tmpAWDLowThresholdShifted ); |
||
2074 | |||
2075 | /* Clear the ADC Analog watchdog flag (in case of left enabled by */ |
||
2076 | /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ |
||
2077 | /* or HAL_ADC_PollForEvent(). */ |
||
2078 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD); |
||
2079 | |||
2080 | /* Configure ADC Analog watchdog interrupt */ |
||
2081 | if(AnalogWDGConfig->ITMode == ENABLE) |
||
2082 | { |
||
2083 | /* Enable the ADC Analog watchdog interrupt */ |
||
2084 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
||
2085 | } |
||
2086 | else |
||
2087 | { |
||
2088 | /* Disable the ADC Analog watchdog interrupt */ |
||
2089 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
||
2090 | } |
||
2091 | |||
2092 | } |
||
2093 | /* If a conversion is on going on regular group, no update could be done */ |
||
2094 | /* on neither of the AWD configuration structure parameters. */ |
||
2095 | else |
||
2096 | { |
||
2097 | /* Update ADC state machine to error */ |
||
2098 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
2099 | |||
2100 | tmp_hal_status = HAL_ERROR; |
||
2101 | } |
||
2102 | |||
2103 | |||
2104 | /* Process unlocked */ |
||
2105 | __HAL_UNLOCK(hadc); |
||
2106 | |||
2107 | /* Return function status */ |
||
2108 | return tmp_hal_status; |
||
2109 | } |
||
2110 | |||
2111 | |||
2112 | /** |
||
2113 | * @} |
||
2114 | */ |
||
2115 | |||
2116 | |||
2117 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
||
2118 | * @brief Peripheral State functions |
||
2119 | * |
||
2120 | @verbatim |
||
2121 | =============================================================================== |
||
2122 | ##### Peripheral State and Errors functions ##### |
||
2123 | =============================================================================== |
||
2124 | [..] |
||
2125 | This subsection provides functions to get in run-time the status of the |
||
2126 | peripheral. |
||
2127 | (+) Check the ADC state |
||
2128 | (+) Check the ADC error code |
||
2129 | |||
2130 | @endverbatim |
||
2131 | * @{ |
||
2132 | */ |
||
2133 | |||
2134 | /** |
||
2135 | * @brief Return the ADC state |
||
2136 | * @note ADC state machine is managed by bitfields, ADC status must be |
||
2137 | * compared with states bits. |
||
2138 | * For example: |
||
2139 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " |
||
2140 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " |
||
2141 | * @param hadc ADC handle |
||
2142 | * @retval HAL state |
||
2143 | */ |
||
2144 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
||
2145 | { |
||
2146 | /* Check the parameters */ |
||
2147 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
2148 | |||
2149 | /* Return ADC state */ |
||
2150 | return hadc->State; |
||
2151 | } |
||
2152 | |||
2153 | /** |
||
2154 | * @brief Return the ADC error code |
||
2155 | * @param hadc ADC handle |
||
2156 | * @retval ADC Error Code |
||
2157 | */ |
||
2158 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
||
2159 | { |
||
2160 | return hadc->ErrorCode; |
||
2161 | } |
||
2162 | |||
2163 | /** |
||
2164 | * @} |
||
2165 | */ |
||
2166 | |||
2167 | /** |
||
2168 | * @} |
||
2169 | */ |
||
2170 | |||
2171 | /** @defgroup ADC_Private_Functions ADC Private Functions |
||
2172 | * @{ |
||
2173 | */ |
||
2174 | |||
2175 | /** |
||
2176 | * @brief Enable the selected ADC. |
||
2177 | * @note Prerequisite condition to use this function: ADC must be disabled |
||
2178 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
||
2179 | * @note If low power mode AutoPowerOff is enabled, power-on/off phases are |
||
2180 | * performed automatically by hardware. |
||
2181 | * In this mode, this function is useless and must not be called because |
||
2182 | * flag ADC_FLAG_RDY is not usable. |
||
2183 | * Therefore, this function must be called under condition of |
||
2184 | * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". |
||
2185 | * @param hadc ADC handle |
||
2186 | * @retval HAL status. |
||
2187 | */ |
||
2188 | static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
||
2189 | { |
||
2190 | uint32_t tickstart = 0U; |
||
2191 | __IO uint32_t wait_loop_index = 0U; |
||
2192 | |||
2193 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
||
2194 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
||
2195 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
||
2196 | /* causes: ADC clock not running, ...). */ |
||
2197 | if (ADC_IS_ENABLE(hadc) == RESET) |
||
2198 | { |
||
2199 | /* Check if conditions to enable the ADC are fulfilled */ |
||
2200 | if (ADC_ENABLING_CONDITIONS(hadc) == RESET) |
||
2201 | { |
||
2202 | /* Update ADC state machine to error */ |
||
2203 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2204 | |||
2205 | /* Set ADC error code to ADC IP internal error */ |
||
2206 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2207 | |||
2208 | return HAL_ERROR; |
||
2209 | } |
||
2210 | |||
2211 | /* Enable the ADC peripheral */ |
||
2212 | __HAL_ADC_ENABLE(hadc); |
||
2213 | |||
2214 | /* Delay for ADC stabilization time */ |
||
2215 | /* Compute number of CPU cycles to wait for */ |
||
2216 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
||
2217 | while(wait_loop_index != 0U) |
||
2218 | { |
||
2219 | wait_loop_index--; |
||
2220 | } |
||
2221 | |||
2222 | /* Get tick count */ |
||
2223 | tickstart = HAL_GetTick(); |
||
2224 | |||
2225 | /* Wait for ADC effectively enabled */ |
||
2226 | while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) |
||
2227 | { |
||
2228 | if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) |
||
2229 | { |
||
2230 | /* Update ADC state machine to error */ |
||
2231 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2232 | |||
2233 | /* Set ADC error code to ADC IP internal error */ |
||
2234 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2235 | |||
2236 | return HAL_ERROR; |
||
2237 | } |
||
2238 | } |
||
2239 | |||
2240 | } |
||
2241 | |||
2242 | /* Return HAL status */ |
||
2243 | return HAL_OK; |
||
2244 | } |
||
2245 | |||
2246 | /** |
||
2247 | * @brief Disable the selected ADC. |
||
2248 | * @note Prerequisite condition to use this function: ADC conversions must be |
||
2249 | * stopped. |
||
2250 | * @param hadc ADC handle |
||
2251 | * @retval HAL status. |
||
2252 | */ |
||
2253 | static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) |
||
2254 | { |
||
2255 | uint32_t tickstart = 0U; |
||
2256 | |||
2257 | /* Verification if ADC is not already disabled: */ |
||
2258 | /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ |
||
2259 | /* disabled. */ |
||
2260 | if (ADC_IS_ENABLE(hadc) != RESET) |
||
2261 | { |
||
2262 | /* Check if conditions to disable the ADC are fulfilled */ |
||
2263 | if (ADC_DISABLING_CONDITIONS(hadc) != RESET) |
||
2264 | { |
||
2265 | /* Disable the ADC peripheral */ |
||
2266 | __HAL_ADC_DISABLE(hadc); |
||
2267 | } |
||
2268 | else |
||
2269 | { |
||
2270 | /* Update ADC state machine to error */ |
||
2271 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2272 | |||
2273 | /* Set ADC error code to ADC IP internal error */ |
||
2274 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2275 | |||
2276 | return HAL_ERROR; |
||
2277 | } |
||
2278 | |||
2279 | /* Wait for ADC effectively disabled */ |
||
2280 | /* Get tick count */ |
||
2281 | tickstart = HAL_GetTick(); |
||
2282 | |||
2283 | while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) |
||
2284 | { |
||
2285 | if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) |
||
2286 | { |
||
2287 | /* Update ADC state machine to error */ |
||
2288 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2289 | |||
2290 | /* Set ADC error code to ADC IP internal error */ |
||
2291 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2292 | |||
2293 | return HAL_ERROR; |
||
2294 | } |
||
2295 | } |
||
2296 | } |
||
2297 | |||
2298 | /* Return HAL status */ |
||
2299 | return HAL_OK; |
||
2300 | } |
||
2301 | |||
2302 | |||
2303 | /** |
||
2304 | * @brief Stop ADC conversion. |
||
2305 | * @note Prerequisite condition to use this function: ADC conversions must be |
||
2306 | * stopped to disable the ADC. |
||
2307 | * @param hadc ADC handle |
||
2308 | * @retval HAL status. |
||
2309 | */ |
||
2310 | static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc) |
||
2311 | { |
||
2312 | uint32_t tickstart = 0U; |
||
2313 | |||
2314 | /* Check the parameters */ |
||
2315 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
||
2316 | |||
2317 | /* Verification if ADC is not already stopped on regular group to bypass */ |
||
2318 | /* this function if not needed. */ |
||
2319 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) |
||
2320 | { |
||
2321 | |||
2322 | /* Stop potential conversion on going on regular group */ |
||
2323 | /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ |
||
2324 | if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && |
||
2325 | HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) |
||
2326 | { |
||
2327 | /* Stop conversions on regular group */ |
||
2328 | hadc->Instance->CR |= ADC_CR_ADSTP; |
||
2329 | } |
||
2330 | |||
2331 | /* Wait for conversion effectively stopped */ |
||
2332 | /* Get tick count */ |
||
2333 | tickstart = HAL_GetTick(); |
||
2334 | |||
2335 | while((hadc->Instance->CR & ADC_CR_ADSTART) != RESET) |
||
2336 | { |
||
2337 | if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) |
||
2338 | { |
||
2339 | /* Update ADC state machine to error */ |
||
2340 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
||
2341 | |||
2342 | /* Set ADC error code to ADC IP internal error */ |
||
2343 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2344 | |||
2345 | return HAL_ERROR; |
||
2346 | } |
||
2347 | } |
||
2348 | |||
2349 | } |
||
2350 | |||
2351 | /* Return HAL status */ |
||
2352 | return HAL_OK; |
||
2353 | } |
||
2354 | |||
2355 | |||
2356 | /** |
||
2357 | * @brief DMA transfer complete callback. |
||
2358 | * @param hdma pointer to DMA handle. |
||
2359 | * @retval None |
||
2360 | */ |
||
2361 | static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
||
2362 | { |
||
2363 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
2364 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
2365 | |||
2366 | /* Update state machine on conversion status if not in error state */ |
||
2367 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
||
2368 | { |
||
2369 | /* Set ADC state */ |
||
2370 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
||
2371 | |||
2372 | /* Determine whether any further conversion upcoming on group regular */ |
||
2373 | /* by external trigger, continuous mode or scan sequence on going. */ |
||
2374 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
||
2375 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
||
2376 | { |
||
2377 | /* If End of Sequence is reached, disable interrupts */ |
||
2378 | if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) |
||
2379 | { |
||
2380 | /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ |
||
2381 | /* ADSTART==0 (no conversion on going) */ |
||
2382 | if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) |
||
2383 | { |
||
2384 | /* Disable ADC end of single conversion interrupt on group regular */ |
||
2385 | /* Note: Overrun interrupt was enabled with EOC interrupt in */ |
||
2386 | /* HAL_Start_IT(), but is not disabled here because can be used */ |
||
2387 | /* by overrun IRQ process below. */ |
||
2388 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); |
||
2389 | |||
2390 | /* Set ADC state */ |
||
2391 | ADC_STATE_CLR_SET(hadc->State, |
||
2392 | HAL_ADC_STATE_REG_BUSY, |
||
2393 | HAL_ADC_STATE_READY); |
||
2394 | } |
||
2395 | else |
||
2396 | { |
||
2397 | /* Change ADC state to error state */ |
||
2398 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
||
2399 | |||
2400 | /* Set ADC error code to ADC IP internal error */ |
||
2401 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
||
2402 | } |
||
2403 | } |
||
2404 | } |
||
2405 | |||
2406 | /* Conversion complete callback */ |
||
2407 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
2408 | hadc->ConvCpltCallback(hadc); |
||
2409 | #else |
||
2410 | HAL_ADC_ConvCpltCallback(hadc); |
||
2411 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
2412 | } |
||
2413 | else |
||
2414 | { |
||
2415 | /* Call DMA error callback */ |
||
2416 | hadc->DMA_Handle->XferErrorCallback(hdma); |
||
2417 | } |
||
2418 | |||
2419 | } |
||
2420 | |||
2421 | /** |
||
2422 | * @brief DMA half transfer complete callback. |
||
2423 | * @param hdma pointer to DMA handle. |
||
2424 | * @retval None |
||
2425 | */ |
||
2426 | static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
||
2427 | { |
||
2428 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
2429 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
2430 | |||
2431 | /* Half conversion callback */ |
||
2432 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
2433 | hadc->ConvHalfCpltCallback(hadc); |
||
2434 | #else |
||
2435 | HAL_ADC_ConvHalfCpltCallback(hadc); |
||
2436 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
2437 | } |
||
2438 | |||
2439 | /** |
||
2440 | * @brief DMA error callback |
||
2441 | * @param hdma pointer to DMA handle. |
||
2442 | * @retval None |
||
2443 | */ |
||
2444 | static void ADC_DMAError(DMA_HandleTypeDef *hdma) |
||
2445 | { |
||
2446 | /* Retrieve ADC handle corresponding to current DMA handle */ |
||
2447 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
||
2448 | |||
2449 | /* Set ADC state */ |
||
2450 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
||
2451 | |||
2452 | /* Set ADC error code to DMA error */ |
||
2453 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
||
2454 | |||
2455 | /* Error callback */ |
||
2456 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
2457 | hadc->ErrorCallback(hadc); |
||
2458 | #else |
||
2459 | HAL_ADC_ErrorCallback(hadc); |
||
2460 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
2461 | } |
||
2462 | |||
2463 | /** |
||
2464 | * @} |
||
2465 | */ |
||
2466 | |||
2467 | #endif /* HAL_ADC_MODULE_ENABLED */ |
||
2468 | /** |
||
2469 | * @} |
||
2470 | */ |
||
2471 | |||
2472 | /** |
||
2473 | * @} |
||
2474 | */ |
||
2475 | |||
2476 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |