WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32F0xx_LL_TIM_H
		22	#define __STM32F0xx_LL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f0xx.h"
		30
		31	/** @addtogroup STM32F0xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
		36
		37	/** @defgroup TIM_LL TIM
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		44	* @{
		45	*/
		46	static const uint8_t OFFSET_TAB_CCMRx[] =
		47	{
		48	0x00U, /* 0: TIMx_CH1 */
		49	0x00U, /* 1: TIMx_CH1N */
		50	0x00U, /* 2: TIMx_CH2 */
		51	0x00U, /* 3: TIMx_CH2N */
		52	0x04U, /* 4: TIMx_CH3 */
		53	0x04U, /* 5: TIMx_CH3N */
		54	0x04U /* 6: TIMx_CH4 */
		55	};
		56
		57	static const uint8_t SHIFT_TAB_OCxx[] =
		58	{
		59	0U, /* 0: OC1M, OC1FE, OC1PE */
		60	0U, /* 1: - NA */
		61	8U, /* 2: OC2M, OC2FE, OC2PE */
		62	0U, /* 3: - NA */
		63	0U, /* 4: OC3M, OC3FE, OC3PE */
		64	0U, /* 5: - NA */
		65	8U /* 6: OC4M, OC4FE, OC4PE */
		66	};
		67
		68	static const uint8_t SHIFT_TAB_ICxx[] =
		69	{
		70	0U, /* 0: CC1S, IC1PSC, IC1F */
		71	0U, /* 1: - NA */
		72	8U, /* 2: CC2S, IC2PSC, IC2F */
		73	0U, /* 3: - NA */
		74	0U, /* 4: CC3S, IC3PSC, IC3F */
		75	0U, /* 5: - NA */
		76	8U /* 6: CC4S, IC4PSC, IC4F */
		77	};
		78
		79	static const uint8_t SHIFT_TAB_CCxP[] =
		80	{
		81	0U, /* 0: CC1P */
		82	2U, /* 1: CC1NP */
		83	4U, /* 2: CC2P */
		84	6U, /* 3: CC2NP */
		85	8U, /* 4: CC3P */
		86	10U, /* 5: CC3NP */
		87	12U /* 6: CC4P */
		88	};
		89
		90	static const uint8_t SHIFT_TAB_OISx[] =
		91	{
		92	0U, /* 0: OIS1 */
		93	1U, /* 1: OIS1N */
		94	2U, /* 2: OIS2 */
		95	3U, /* 3: OIS2N */
		96	4U, /* 4: OIS3 */
		97	5U, /* 5: OIS3N */
		98	6U /* 6: OIS4 */
		99	};
		100	/**
		101	* @}
		102	*/
		103
		104	/* Private constants ---------------------------------------------------------*/
		105	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		106	* @{
		107	*/
		108
		109
		110	#define TIMx_OR_RMP_SHIFT 16U
		111	#define TIMx_OR_RMP_MASK 0x0000FFFFU
		112	#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
		113
		114	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
		115	#define DT_DELAY_1 ((uint8_t)0x7F)
		116	#define DT_DELAY_2 ((uint8_t)0x3F)
		117	#define DT_DELAY_3 ((uint8_t)0x1F)
		118	#define DT_DELAY_4 ((uint8_t)0x1F)
		119
		120	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
		121	#define DT_RANGE_1 ((uint8_t)0x00)
		122	#define DT_RANGE_2 ((uint8_t)0x80)
		123	#define DT_RANGE_3 ((uint8_t)0xC0)
		124	#define DT_RANGE_4 ((uint8_t)0xE0)
		125
		126
		127	/**
		128	* @}
		129	*/
		130
		131	/* Private macros ------------------------------------------------------------*/
		132	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		133	* @{
		134	*/
		135	/** @brief Convert channel id into channel index.
		136	* @param __CHANNEL__ This parameter can be one of the following values:
		137	* @arg @ref LL_TIM_CHANNEL_CH1
		138	* @arg @ref LL_TIM_CHANNEL_CH1N
		139	* @arg @ref LL_TIM_CHANNEL_CH2
		140	* @arg @ref LL_TIM_CHANNEL_CH2N
		141	* @arg @ref LL_TIM_CHANNEL_CH3
		142	* @arg @ref LL_TIM_CHANNEL_CH3N
		143	* @arg @ref LL_TIM_CHANNEL_CH4
		144	* @retval none
		145	*/
		146	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
		147	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		148	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
		149	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		150	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
		151	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
		152	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
		153
		154	/** @brief Calculate the deadtime sampling period(in ps).
		155	* @param __TIMCLK__ timer input clock frequency (in Hz).
		156	* @param __CKD__ This parameter can be one of the following values:
		157	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		158	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		159	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		160	* @retval none
		161	*/
		162	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
		163	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
		164	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
		165	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
		166	/**
		167	* @}
		168	*/
		169
		170
		171	/* Exported types ------------------------------------------------------------*/
		172	#if defined(USE_FULL_LL_DRIVER)
		173	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		174	* @{
		175	*/
		176
		177	/**
		178	* @brief TIM Time Base configuration structure definition.
		179	*/
		180	typedef struct
		181	{
		182	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		183	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		184
6	mjames	185	This feature can be modified afterwards using unitary function
		186	@ref LL_TIM_SetPrescaler().*/
2	mjames	187
		188	uint32_t CounterMode; /*!< Specifies the counter mode.
		189	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		190
6	mjames	191	This feature can be modified afterwards using unitary function
		192	@ref LL_TIM_SetCounterMode().*/
2	mjames	193
		194	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		195	Auto-Reload Register at the next update event.
		196	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
6	mjames	197	Some timer instances may support 32 bits counters. In that case this parameter must
		198	be a number between 0x0000 and 0xFFFFFFFF.
2	mjames	199
6	mjames	200	This feature can be modified afterwards using unitary function
		201	@ref LL_TIM_SetAutoReload().*/
2	mjames	202
		203	uint32_t ClockDivision; /*!< Specifies the clock division.
		204	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		205
6	mjames	206	This feature can be modified afterwards using unitary function
		207	@ref LL_TIM_SetClockDivision().*/
2	mjames	208
6	mjames	209	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
2	mjames	210	reaches zero, an update event is generated and counting restarts
		211	from the RCR value (N).
		212	This means in PWM mode that (N+1) corresponds to:
		213	- the number of PWM periods in edge-aligned mode
		214	- the number of half PWM period in center-aligned mode
6	mjames	215	GP timers: this parameter must be a number between Min_Data = 0x00 and
		216	Max_Data = 0xFF.
		217	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
		218	Max_Data = 0xFFFF.
2	mjames	219
6	mjames	220	This feature can be modified afterwards using unitary function
		221	@ref LL_TIM_SetRepetitionCounter().*/
2	mjames	222	} LL_TIM_InitTypeDef;
		223
		224	/**
		225	* @brief TIM Output Compare configuration structure definition.
		226	*/
		227	typedef struct
		228	{
		229	uint32_t OCMode; /*!< Specifies the output mode.
		230	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		231
6	mjames	232	This feature can be modified afterwards using unitary function
		233	@ref LL_TIM_OC_SetMode().*/
2	mjames	234
		235	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		236	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		237
6	mjames	238	This feature can be modified afterwards using unitary functions
		239	@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
2	mjames	240
		241	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
		242	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		243
6	mjames	244	This feature can be modified afterwards using unitary functions
		245	@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
2	mjames	246
		247	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		248	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		249
6	mjames	250	This feature can be modified afterwards using unitary function
		251	LL_TIM_OC_SetCompareCHx (x=1..6).*/
2	mjames	252
		253	uint32_t OCPolarity; /*!< Specifies the output polarity.
		254	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		255
6	mjames	256	This feature can be modified afterwards using unitary function
		257	@ref LL_TIM_OC_SetPolarity().*/
2	mjames	258
		259	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		260	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		261
6	mjames	262	This feature can be modified afterwards using unitary function
		263	@ref LL_TIM_OC_SetPolarity().*/
2	mjames	264
		265
		266	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		267	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		268
6	mjames	269	This feature can be modified afterwards using unitary function
		270	@ref LL_TIM_OC_SetIdleState().*/
2	mjames	271
		272	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		273	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		274
6	mjames	275	This feature can be modified afterwards using unitary function
		276	@ref LL_TIM_OC_SetIdleState().*/
2	mjames	277	} LL_TIM_OC_InitTypeDef;
		278
		279	/**
		280	* @brief TIM Input Capture configuration structure definition.
		281	*/
		282
		283	typedef struct
		284	{
		285
		286	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		287	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		288
6	mjames	289	This feature can be modified afterwards using unitary function
		290	@ref LL_TIM_IC_SetPolarity().*/
2	mjames	291
		292	uint32_t ICActiveInput; /*!< Specifies the input.
		293	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		294
6	mjames	295	This feature can be modified afterwards using unitary function
		296	@ref LL_TIM_IC_SetActiveInput().*/
2	mjames	297
		298	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		299	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		300
6	mjames	301	This feature can be modified afterwards using unitary function
		302	@ref LL_TIM_IC_SetPrescaler().*/
2	mjames	303
		304	uint32_t ICFilter; /*!< Specifies the input capture filter.
		305	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		306
6	mjames	307	This feature can be modified afterwards using unitary function
		308	@ref LL_TIM_IC_SetFilter().*/
2	mjames	309	} LL_TIM_IC_InitTypeDef;
		310
		311
		312	/**
		313	* @brief TIM Encoder interface configuration structure definition.
		314	*/
		315	typedef struct
		316	{
		317	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		318	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		319
6	mjames	320	This feature can be modified afterwards using unitary function
		321	@ref LL_TIM_SetEncoderMode().*/
2	mjames	322
		323	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		324	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		325
6	mjames	326	This feature can be modified afterwards using unitary function
		327	@ref LL_TIM_IC_SetPolarity().*/
2	mjames	328
		329	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		330	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		331
6	mjames	332	This feature can be modified afterwards using unitary function
		333	@ref LL_TIM_IC_SetActiveInput().*/
2	mjames	334
		335	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		336	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		337
6	mjames	338	This feature can be modified afterwards using unitary function
		339	@ref LL_TIM_IC_SetPrescaler().*/
2	mjames	340
		341	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		342	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		343
6	mjames	344	This feature can be modified afterwards using unitary function
		345	@ref LL_TIM_IC_SetFilter().*/
2	mjames	346
		347	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		348	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		349
6	mjames	350	This feature can be modified afterwards using unitary function
		351	@ref LL_TIM_IC_SetPolarity().*/
2	mjames	352
		353	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		354	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		355
6	mjames	356	This feature can be modified afterwards using unitary function
		357	@ref LL_TIM_IC_SetActiveInput().*/
2	mjames	358
		359	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		360	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		361
6	mjames	362	This feature can be modified afterwards using unitary function
		363	@ref LL_TIM_IC_SetPrescaler().*/
2	mjames	364
		365	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		366	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		367
6	mjames	368	This feature can be modified afterwards using unitary function
		369	@ref LL_TIM_IC_SetFilter().*/
2	mjames	370
		371	} LL_TIM_ENCODER_InitTypeDef;
		372
		373	/**
		374	* @brief TIM Hall sensor interface configuration structure definition.
		375	*/
		376	typedef struct
		377	{
		378
		379	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		380	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		381
6	mjames	382	This feature can be modified afterwards using unitary function
		383	@ref LL_TIM_IC_SetPolarity().*/
2	mjames	384
		385	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		386	Prescaler must be set to get a maximum counter period longer than the
		387	time interval between 2 consecutive changes on the Hall inputs.
		388	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		389
6	mjames	390	This feature can be modified afterwards using unitary function
		391	@ref LL_TIM_IC_SetPrescaler().*/
2	mjames	392
		393	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
6	mjames	394	This parameter can be a value of
		395	@ref TIM_LL_EC_IC_FILTER.
2	mjames	396
6	mjames	397	This feature can be modified afterwards using unitary function
		398	@ref LL_TIM_IC_SetFilter().*/
2	mjames	399
		400	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
		401	A positive pulse (TRGO event) is generated with a programmable delay every time
		402	a change occurs on the Hall inputs.
		403	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
		404
6	mjames	405	This feature can be modified afterwards using unitary function
		406	@ref LL_TIM_OC_SetCompareCH2().*/
2	mjames	407	} LL_TIM_HALLSENSOR_InitTypeDef;
		408
		409	/**
		410	* @brief BDTR (Break and Dead Time) structure definition
		411	*/
		412	typedef struct
		413	{
		414	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
		415	This parameter can be a value of @ref TIM_LL_EC_OSSR
		416
6	mjames	417	This feature can be modified afterwards using unitary function
		418	@ref LL_TIM_SetOffStates()
2	mjames	419
6	mjames	420	@note This bit-field cannot be modified as long as LOCK level 2 has been
		421	programmed. */
2	mjames	422
		423	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
		424	This parameter can be a value of @ref TIM_LL_EC_OSSI
		425
6	mjames	426	This feature can be modified afterwards using unitary function
		427	@ref LL_TIM_SetOffStates()
2	mjames	428
6	mjames	429	@note This bit-field cannot be modified as long as LOCK level 2 has been
		430	programmed. */
2	mjames	431
		432	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
		433	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
		434
6	mjames	435	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
		436	register has been written, their content is frozen until the next reset.*/
2	mjames	437
		438	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
		439	switching-on of the outputs.
		440	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		441
6	mjames	442	This feature can be modified afterwards using unitary function
		443	@ref LL_TIM_OC_SetDeadTime()
2	mjames	444
6	mjames	445	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
		446	programmed. */
2	mjames	447
		448	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
		449	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
		450
6	mjames	451	This feature can be modified afterwards using unitary functions
		452	@ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
2	mjames	453
6	mjames	454	@note This bit-field can not be modified as long as LOCK level 1 has been
		455	programmed. */
2	mjames	456
		457	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
		458	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
		459
6	mjames	460	This feature can be modified afterwards using unitary function
		461	@ref LL_TIM_ConfigBRK()
2	mjames	462
6	mjames	463	@note This bit-field can not be modified as long as LOCK level 1 has been
		464	programmed. */
2	mjames	465
		466	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
		467	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
		468
6	mjames	469	This feature can be modified afterwards using unitary functions
		470	@ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
2	mjames	471
6	mjames	472	@note This bit-field can not be modified as long as LOCK level 1 has been
		473	programmed. */
2	mjames	474	} LL_TIM_BDTR_InitTypeDef;
		475
		476	/**
		477	* @}
		478	*/
		479	#endif /* USE_FULL_LL_DRIVER */
		480
		481	/* Exported constants --------------------------------------------------------*/
		482	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		483	* @{
		484	*/
		485
		486	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		487	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		488	* @{
		489	*/
		490	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		491	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		492	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		493	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		494	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		495	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
		496	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		497	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
		498	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		499	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		500	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		501	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		502	/**
		503	* @}
		504	*/
		505
		506	#if defined(USE_FULL_LL_DRIVER)
		507	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
		508	* @{
		509	*/
		510	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
		511	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
		512	/**
		513	* @}
		514	*/
		515
		516	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
		517	* @{
		518	*/
		519	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		520	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
		521	/**
		522	* @}
		523	*/
		524	#endif /* USE_FULL_LL_DRIVER */
		525
		526	/** @defgroup TIM_LL_EC_IT IT Defines
		527	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		528	* @{
		529	*/
		530	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		531	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		532	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		533	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		534	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		535	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
		536	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		537	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
		538	/**
		539	* @}
		540	*/
		541
		542	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		543	* @{
		544	*/
		545	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		546	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		547	/**
		548	* @}
		549	*/
		550
		551	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		552	* @{
		553	*/
6	mjames	554	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		555	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
2	mjames	556	/**
		557	* @}
		558	*/
		559
		560	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		561	* @{
		562	*/
		563	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		564	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
6	mjames	565	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		566	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
2	mjames	567	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		568	/**
		569	* @}
		570	*/
		571
		572	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		573	* @{
		574	*/
		575	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		576	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		577	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		578	/**
		579	* @}
		580	*/
		581
		582	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		583	* @{
		584	*/
		585	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		586	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		587	/**
		588	* @}
		589	*/
		590
		591	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
		592	* @{
		593	*/
		594	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
		595	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
		596	/**
		597	* @}
		598	*/
		599
		600	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		601	* @{
		602	*/
		603	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		604	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		605	/**
		606	* @}
		607	*/
		608
		609	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
		610	* @{
		611	*/
		612	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
		613	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		614	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		615	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		616	/**
		617	* @}
		618	*/
		619
		620	/** @defgroup TIM_LL_EC_CHANNEL Channel
		621	* @{
		622	*/
		623	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		624	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
		625	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		626	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
		627	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		628	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
		629	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		630	/**
		631	* @}
		632	*/
		633
		634	#if defined(USE_FULL_LL_DRIVER)
		635	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		636	* @{
		637	*/
		638	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		639	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		640	/**
		641	* @}
		642	*/
		643	#endif /* USE_FULL_LL_DRIVER */
		644
		645	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		646	* @{
		647	*/
		648	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		649	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		650	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		651	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
		652	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
		653	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		654	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		655	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		656	/**
		657	* @}
		658	*/
		659
		660	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		661	* @{
		662	*/
		663	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		664	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		665	/**
		666	* @}
		667	*/
		668
		669	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
		670	* @{
		671	*/
		672	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
		673	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
		674	/**
		675	* @}
		676	*/
		677
		678
		679	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		680	* @{
		681	*/
		682	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		683	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		684	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		685	/**
		686	* @}
		687	*/
		688
		689	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		690	* @{
		691	*/
		692	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
		693	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		694	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		695	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		696	/**
		697	* @}
		698	*/
		699
		700	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		701	* @{
		702	*/
		703	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		704	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		705	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		706	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		707	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		708	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		709	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		710	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		711	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		712	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		713	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		714	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		715	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		716	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		717	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		718	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		719	/**
		720	* @}
		721	*/
		722
		723	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		724	* @{
		725	*/
		726	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		727	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		728	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
		729	/**
		730	* @}
		731	*/
		732
		733	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		734	* @{
		735	*/
		736	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
		737	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
		738	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		739	/**
		740	* @}
		741	*/
		742
		743	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		744	* @{
		745	*/
		746	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		747	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		748	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
		749	/**
		750	* @}
		751	*/
		752
		753	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		754	* @{
		755	*/
		756	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		757	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		758	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		759	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		760	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		761	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		762	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		763	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		764	/**
		765	* @}
		766	*/
		767
		768
		769	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		770	* @{
		771	*/
		772	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		773	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		774	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		775	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		776	/**
		777	* @}
		778	*/
		779
		780	/** @defgroup TIM_LL_EC_TS Trigger Selection
		781	* @{
		782	*/
		783	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		784	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		785	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		786	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		787	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		788	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		789	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		790	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
		791	/**
		792	* @}
		793	*/
		794
		795	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		796	* @{
		797	*/
		798	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		799	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		800	/**
		801	* @}
		802	*/
		803
		804	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		805	* @{
		806	*/
		807	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		808	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		809	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		810	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		811	/**
		812	* @}
		813	*/
		814
		815	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		816	* @{
		817	*/
		818	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		819	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		820	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		821	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		822	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		823	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		824	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		825	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		826	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		827	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		828	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		829	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		830	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		831	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		832	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		833	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		834	/**
		835	* @}
		836	*/
		837
		838
		839	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
		840	* @{
		841	*/
		842	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		843	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		844	/**
		845	* @}
		846	*/
		847
		848
		849
		850
		851	/** @defgroup TIM_LL_EC_OSSI OSSI
		852	* @{
		853	*/
		854	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		855	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
		856	/**
		857	* @}
		858	*/
		859
		860	/** @defgroup TIM_LL_EC_OSSR OSSR
		861	* @{
		862	*/
		863	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		864	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
		865	/**
		866	* @}
		867	*/
		868
		869
		870	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		871	* @{
		872	*/
		873	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		874	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		875	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		876	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		877	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		878	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		879	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		880	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		881	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		882	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		883	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		884	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		885	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
		886	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		887	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		888	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		889	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		890	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
		891	/**
		892	* @}
		893	*/
		894
		895	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		896	* @{
		897	*/
		898	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		899	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		900	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		901	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		902	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		903	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		904	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		905	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		906	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		907	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		908	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		909	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		910	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		911	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		912	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		913	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		914	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		915	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		916	/**
		917	* @}
		918	*/
		919
		920
		921	#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /!< TIM14_TI1 is connected to Ored GPIO /
		922	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC clock /
		923	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 clock /
		924	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
		925
		926
		927	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
		928	* @{
		929	*/
		930	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
		931	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
		932	/**
		933	* @}
		934	*/
		935
		936	/**
		937	* @}
		938	*/
		939
		940	/* Exported macro ------------------------------------------------------------*/
		941	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		942	* @{
		943	*/
		944
		945	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		946	* @{
		947	*/
		948	/**
		949	* @brief Write a value in TIM register.
		950	* @param __INSTANCE__ TIM Instance
		951	* @param __REG__ Register to be written
		952	* @param __VALUE__ Value to be written in the register
		953	* @retval None
		954	*/
		955	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
		956
		957	/**
		958	* @brief Read a value in TIM register.
		959	* @param __INSTANCE__ TIM Instance
		960	* @param __REG__ Register to be read
		961	* @retval Register value
		962	*/
		963	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
		964	/**
		965	* @}
		966	*/
		967
		968	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		969	* @{
		970	*/
		971
		972	/**
		973	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
		974	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
		975	* @param __TIMCLK__ timer input clock frequency (in Hz)
		976	* @param __CKD__ This parameter can be one of the following values:
		977	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		978	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		979	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		980	* @param __DT__ deadtime duration (in ns)
		981	* @retval DTG[0:7]
		982	*/
		983	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
6	mjames	984	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		985	(uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
		986	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		987	(uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
		988	(__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
		989	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		990	(uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
		991	(__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
		992	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
		993	(uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
		994	(__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
2	mjames	995	0U)
		996
		997	/**
		998	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		999	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		1000	* @param __TIMCLK__ timer input clock frequency (in Hz)
		1001	* @param __CNTCLK__ counter clock frequency (in Hz)
		1002	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		1003	*/
		1004	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
		1005	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
		1006
		1007	/**
		1008	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		1009	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		1010	* @param __TIMCLK__ timer input clock frequency (in Hz)
		1011	* @param __PSC__ prescaler
		1012	* @param __FREQ__ output signal frequency (in Hz)
		1013	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		1014	*/
		1015	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
		1016	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
		1017
		1018	/**
6	mjames	1019	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
		1020	* active/inactive delay.
2	mjames	1021	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		1022	* @param __TIMCLK__ timer input clock frequency (in Hz)
		1023	* @param __PSC__ prescaler
		1024	* @param __DELAY__ timer output compare active/inactive delay (in us)
		1025	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		1026	*/
		1027	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
		1028	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		1029	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
		1030
		1031	/**
6	mjames	1032	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
		1033	* (when the timer operates in one pulse mode).
2	mjames	1034	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		1035	* @param __TIMCLK__ timer input clock frequency (in Hz)
		1036	* @param __PSC__ prescaler
		1037	* @param __DELAY__ timer output compare active/inactive delay (in us)
		1038	* @param __PULSE__ pulse duration (in us)
		1039	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		1040	*/
		1041	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
		1042	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		1043	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
		1044
		1045	/**
		1046	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		1047	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		1048	* @param __ICPSC__ This parameter can be one of the following values:
		1049	* @arg @ref LL_TIM_ICPSC_DIV1
		1050	* @arg @ref LL_TIM_ICPSC_DIV2
		1051	* @arg @ref LL_TIM_ICPSC_DIV4
		1052	* @arg @ref LL_TIM_ICPSC_DIV8
		1053	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		1054	*/
		1055	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
		1056	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
		1057
		1058
		1059	/**
		1060	* @}
		1061	*/
		1062
		1063
		1064	/**
		1065	* @}
		1066	*/
		1067
		1068	/* Exported functions --------------------------------------------------------*/
		1069	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		1070	* @{
		1071	*/
		1072
		1073	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		1074	* @{
		1075	*/
		1076	/**
		1077	* @brief Enable timer counter.
		1078	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		1079	* @param TIMx Timer instance
		1080	* @retval None
		1081	*/
		1082	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		1083	{
		1084	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		1085	}
		1086
		1087	/**
		1088	* @brief Disable timer counter.
		1089	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		1090	* @param TIMx Timer instance
		1091	* @retval None
		1092	*/
		1093	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		1094	{
		1095	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		1096	}
		1097
		1098	/**
		1099	* @brief Indicates whether the timer counter is enabled.
		1100	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		1101	* @param TIMx Timer instance
		1102	* @retval State of bit (1 or 0).
		1103	*/
		1104	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		1105	{
		1106	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
		1107	}
		1108
		1109	/**
		1110	* @brief Enable update event generation.
		1111	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		1112	* @param TIMx Timer instance
		1113	* @retval None
		1114	*/
		1115	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		1116	{
		1117	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1118	}
		1119
		1120	/**
		1121	* @brief Disable update event generation.
		1122	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		1123	* @param TIMx Timer instance
		1124	* @retval None
		1125	*/
		1126	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		1127	{
		1128	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1129	}
		1130
		1131	/**
		1132	* @brief Indicates whether update event generation is enabled.
		1133	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		1134	* @param TIMx Timer instance
		1135	* @retval Inverted state of bit (0 or 1).
		1136	*/
		1137	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		1138	{
		1139	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
		1140	}
		1141
		1142	/**
		1143	* @brief Set update event source
		1144	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		1145	* generate an update interrupt or DMA request if enabled:
		1146	* - Counter overflow/underflow
		1147	* - Setting the UG bit
		1148	* - Update generation through the slave mode controller
		1149	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		1150	* overflow/underflow generates an update interrupt or DMA request if enabled.
		1151	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		1152	* @param TIMx Timer instance
		1153	* @param UpdateSource This parameter can be one of the following values:
		1154	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1155	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1156	* @retval None
		1157	*/
		1158	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		1159	{
		1160	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		1161	}
		1162
		1163	/**
		1164	* @brief Get actual event update source
		1165	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		1166	* @param TIMx Timer instance
		1167	* @retval Returned value can be one of the following values:
		1168	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1169	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1170	*/
		1171	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		1172	{
		1173	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		1174	}
		1175
		1176	/**
		1177	* @brief Set one pulse mode (one shot v.s. repetitive).
		1178	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		1179	* @param TIMx Timer instance
		1180	* @param OnePulseMode This parameter can be one of the following values:
		1181	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1182	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1183	* @retval None
		1184	*/
		1185	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		1186	{
		1187	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		1188	}
		1189
		1190	/**
		1191	* @brief Get actual one pulse mode.
		1192	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		1193	* @param TIMx Timer instance
		1194	* @retval Returned value can be one of the following values:
		1195	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1196	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1197	*/
		1198	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		1199	{
		1200	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		1201	}
		1202
		1203	/**
		1204	* @brief Set the timer counter counting mode.
		1205	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1206	* check whether or not the counter mode selection feature is supported
		1207	* by a timer instance.
		1208	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1209	* requires a timer reset to avoid unexpected direction
		1210	* due to DIR bit readonly in center aligned mode.
		1211	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		1212	* CR1 CMS LL_TIM_SetCounterMode
		1213	* @param TIMx Timer instance
		1214	* @param CounterMode This parameter can be one of the following values:
		1215	* @arg @ref LL_TIM_COUNTERMODE_UP
		1216	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1217	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1218	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1219	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1220	* @retval None
		1221	*/
		1222	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1223	{
		1224	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
		1225	}
		1226
		1227	/**
		1228	* @brief Get actual counter mode.
		1229	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1230	* check whether or not the counter mode selection feature is supported
		1231	* by a timer instance.
		1232	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1233	* CR1 CMS LL_TIM_GetCounterMode
		1234	* @param TIMx Timer instance
		1235	* @retval Returned value can be one of the following values:
		1236	* @arg @ref LL_TIM_COUNTERMODE_UP
		1237	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1238	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1239	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1240	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1241	*/
		1242	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1243	{
6	mjames	1244	uint32_t counter_mode;
		1245
		1246	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
		1247
		1248	if (counter_mode == 0U)
		1249	{
		1250	counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1251	}
		1252
		1253	return counter_mode;
2	mjames	1254	}
		1255
		1256	/**
		1257	* @brief Enable auto-reload (ARR) preload.
		1258	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1259	* @param TIMx Timer instance
		1260	* @retval None
		1261	*/
		1262	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1263	{
		1264	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1265	}
		1266
		1267	/**
		1268	* @brief Disable auto-reload (ARR) preload.
		1269	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1270	* @param TIMx Timer instance
		1271	* @retval None
		1272	*/
		1273	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1274	{
		1275	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1276	}
		1277
		1278	/**
		1279	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1280	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1281	* @param TIMx Timer instance
		1282	* @retval State of bit (1 or 0).
		1283	*/
		1284	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1285	{
		1286	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
		1287	}
		1288
		1289	/**
6	mjames	1290	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
		1291	* (when supported) and the digital filters.
2	mjames	1292	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1293	* whether or not the clock division feature is supported by the timer
		1294	* instance.
		1295	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1296	* @param TIMx Timer instance
		1297	* @param ClockDivision This parameter can be one of the following values:
		1298	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1299	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1300	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1301	* @retval None
		1302	*/
		1303	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1304	{
		1305	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1306	}
		1307
		1308	/**
6	mjames	1309	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
		1310	* generators (when supported) and the digital filters.
2	mjames	1311	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1312	* whether or not the clock division feature is supported by the timer
		1313	* instance.
		1314	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1315	* @param TIMx Timer instance
		1316	* @retval Returned value can be one of the following values:
		1317	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1318	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1319	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1320	*/
		1321	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1322	{
		1323	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1324	}
		1325
		1326	/**
		1327	* @brief Set the counter value.
		1328	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1329	* whether or not a timer instance supports a 32 bits counter.
		1330	* @rmtoll CNT CNT LL_TIM_SetCounter
		1331	* @param TIMx Timer instance
		1332	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1333	* @retval None
		1334	*/
		1335	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1336	{
		1337	WRITE_REG(TIMx->CNT, Counter);
		1338	}
		1339
		1340	/**
		1341	* @brief Get the counter value.
		1342	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1343	* whether or not a timer instance supports a 32 bits counter.
		1344	* @rmtoll CNT CNT LL_TIM_GetCounter
		1345	* @param TIMx Timer instance
		1346	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1347	*/
		1348	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1349	{
		1350	return (uint32_t)(READ_REG(TIMx->CNT));
		1351	}
		1352
		1353	/**
		1354	* @brief Get the current direction of the counter
		1355	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1356	* @param TIMx Timer instance
		1357	* @retval Returned value can be one of the following values:
		1358	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1359	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1360	*/
		1361	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1362	{
		1363	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1364	}
		1365
		1366	/**
		1367	* @brief Set the prescaler value.
		1368	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1369	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1370	* prescaler ratio is taken into account at the next update event.
		1371	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1372	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1373	* @param TIMx Timer instance
		1374	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1375	* @retval None
		1376	*/
		1377	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1378	{
		1379	WRITE_REG(TIMx->PSC, Prescaler);
		1380	}
		1381
		1382	/**
		1383	* @brief Get the prescaler value.
		1384	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1385	* @param TIMx Timer instance
		1386	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1387	*/
		1388	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1389	{
		1390	return (uint32_t)(READ_REG(TIMx->PSC));
		1391	}
		1392
		1393	/**
		1394	* @brief Set the auto-reload value.
		1395	* @note The counter is blocked while the auto-reload value is null.
		1396	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1397	* whether or not a timer instance supports a 32 bits counter.
		1398	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1399	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1400	* @param TIMx Timer instance
		1401	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1402	* @retval None
		1403	*/
		1404	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1405	{
		1406	WRITE_REG(TIMx->ARR, AutoReload);
		1407	}
		1408
		1409	/**
		1410	* @brief Get the auto-reload value.
		1411	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1412	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1413	* whether or not a timer instance supports a 32 bits counter.
		1414	* @param TIMx Timer instance
		1415	* @retval Auto-reload value
		1416	*/
		1417	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1418	{
		1419	return (uint32_t)(READ_REG(TIMx->ARR));
		1420	}
		1421
		1422	/**
		1423	* @brief Set the repetition counter value.
		1424	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1425	* whether or not a timer instance supports a repetition counter.
		1426	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
		1427	* @param TIMx Timer instance
6	mjames	1428	* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2	mjames	1429	* @retval None
		1430	*/
		1431	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
		1432	{
		1433	WRITE_REG(TIMx->RCR, RepetitionCounter);
		1434	}
		1435
		1436	/**
		1437	* @brief Get the repetition counter value.
		1438	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1439	* whether or not a timer instance supports a repetition counter.
		1440	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
		1441	* @param TIMx Timer instance
		1442	* @retval Repetition counter value
		1443	*/
		1444	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
		1445	{
		1446	return (uint32_t)(READ_REG(TIMx->RCR));
		1447	}
		1448
		1449	/**
		1450	* @}
		1451	*/
		1452
		1453	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1454	* @{
		1455	*/
		1456	/**
		1457	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1458	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
		1459	* they are updated only when a commutation event (COM) occurs.
		1460	* @note Only on channels that have a complementary output.
		1461	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1462	* whether or not a timer instance is able to generate a commutation event.
		1463	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
		1464	* @param TIMx Timer instance
		1465	* @retval None
		1466	*/
		1467	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
		1468	{
		1469	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1470	}
		1471
		1472	/**
		1473	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1474	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1475	* whether or not a timer instance is able to generate a commutation event.
		1476	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
		1477	* @param TIMx Timer instance
		1478	* @retval None
		1479	*/
		1480	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
		1481	{
		1482	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1483	}
		1484
		1485	/**
		1486	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
		1487	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1488	* whether or not a timer instance is able to generate a commutation event.
		1489	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
		1490	* @param TIMx Timer instance
		1491	* @param CCUpdateSource This parameter can be one of the following values:
		1492	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
		1493	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
		1494	* @retval None
		1495	*/
		1496	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
		1497	{
		1498	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
		1499	}
		1500
		1501	/**
		1502	* @brief Set the trigger of the capture/compare DMA request.
		1503	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1504	* @param TIMx Timer instance
		1505	* @param DMAReqTrigger This parameter can be one of the following values:
		1506	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1507	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1508	* @retval None
		1509	*/
		1510	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1511	{
		1512	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1513	}
		1514
		1515	/**
		1516	* @brief Get actual trigger of the capture/compare DMA request.
		1517	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1518	* @param TIMx Timer instance
		1519	* @retval Returned value can be one of the following values:
		1520	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1521	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1522	*/
		1523	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1524	{
		1525	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1526	}
		1527
		1528	/**
		1529	* @brief Set the lock level to freeze the
		1530	* configuration of several capture/compare parameters.
		1531	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		1532	* the lock mechanism is supported by a timer instance.
		1533	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
		1534	* @param TIMx Timer instance
		1535	* @param LockLevel This parameter can be one of the following values:
		1536	* @arg @ref LL_TIM_LOCKLEVEL_OFF
		1537	* @arg @ref LL_TIM_LOCKLEVEL_1
		1538	* @arg @ref LL_TIM_LOCKLEVEL_2
		1539	* @arg @ref LL_TIM_LOCKLEVEL_3
		1540	* @retval None
		1541	*/
		1542	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
		1543	{
		1544	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
		1545	}
		1546
		1547	/**
		1548	* @brief Enable capture/compare channels.
		1549	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1550	* CCER CC1NE LL_TIM_CC_EnableChannel\n
		1551	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1552	* CCER CC2NE LL_TIM_CC_EnableChannel\n
		1553	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1554	* CCER CC3NE LL_TIM_CC_EnableChannel\n
		1555	* CCER CC4E LL_TIM_CC_EnableChannel
		1556	* @param TIMx Timer instance
		1557	* @param Channels This parameter can be a combination of the following values:
		1558	* @arg @ref LL_TIM_CHANNEL_CH1
		1559	* @arg @ref LL_TIM_CHANNEL_CH1N
		1560	* @arg @ref LL_TIM_CHANNEL_CH2
		1561	* @arg @ref LL_TIM_CHANNEL_CH2N
		1562	* @arg @ref LL_TIM_CHANNEL_CH3
		1563	* @arg @ref LL_TIM_CHANNEL_CH3N
		1564	* @arg @ref LL_TIM_CHANNEL_CH4
		1565	* @retval None
		1566	*/
		1567	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1568	{
		1569	SET_BIT(TIMx->CCER, Channels);
		1570	}
		1571
		1572	/**
		1573	* @brief Disable capture/compare channels.
		1574	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1575	* CCER CC1NE LL_TIM_CC_DisableChannel\n
		1576	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1577	* CCER CC2NE LL_TIM_CC_DisableChannel\n
		1578	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1579	* CCER CC3NE LL_TIM_CC_DisableChannel\n
		1580	* CCER CC4E LL_TIM_CC_DisableChannel
		1581	* @param TIMx Timer instance
		1582	* @param Channels This parameter can be a combination of the following values:
		1583	* @arg @ref LL_TIM_CHANNEL_CH1
		1584	* @arg @ref LL_TIM_CHANNEL_CH1N
		1585	* @arg @ref LL_TIM_CHANNEL_CH2
		1586	* @arg @ref LL_TIM_CHANNEL_CH2N
		1587	* @arg @ref LL_TIM_CHANNEL_CH3
		1588	* @arg @ref LL_TIM_CHANNEL_CH3N
		1589	* @arg @ref LL_TIM_CHANNEL_CH4
		1590	* @retval None
		1591	*/
		1592	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1593	{
		1594	CLEAR_BIT(TIMx->CCER, Channels);
		1595	}
		1596
		1597	/**
		1598	* @brief Indicate whether channel(s) is(are) enabled.
		1599	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1600	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
		1601	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1602	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
		1603	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1604	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
		1605	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1606	* @param TIMx Timer instance
		1607	* @param Channels This parameter can be a combination of the following values:
		1608	* @arg @ref LL_TIM_CHANNEL_CH1
		1609	* @arg @ref LL_TIM_CHANNEL_CH1N
		1610	* @arg @ref LL_TIM_CHANNEL_CH2
		1611	* @arg @ref LL_TIM_CHANNEL_CH2N
		1612	* @arg @ref LL_TIM_CHANNEL_CH3
		1613	* @arg @ref LL_TIM_CHANNEL_CH3N
		1614	* @arg @ref LL_TIM_CHANNEL_CH4
		1615	* @retval State of bit (1 or 0).
		1616	*/
		1617	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1618	{
		1619	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
		1620	}
		1621
		1622	/**
		1623	* @}
		1624	*/
		1625
		1626	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1627	* @{
		1628	*/
		1629	/**
		1630	* @brief Configure an output channel.
		1631	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1632	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1633	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1634	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1635	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1636	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1637	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1638	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1639	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
		1640	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
		1641	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
		1642	* CR2 OIS4 LL_TIM_OC_ConfigOutput
		1643	* @param TIMx Timer instance
		1644	* @param Channel This parameter can be one of the following values:
		1645	* @arg @ref LL_TIM_CHANNEL_CH1
		1646	* @arg @ref LL_TIM_CHANNEL_CH2
		1647	* @arg @ref LL_TIM_CHANNEL_CH3
		1648	* @arg @ref LL_TIM_CHANNEL_CH4
		1649	* @param Configuration This parameter must be a combination of all the following values:
		1650	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1651	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
		1652	* @retval None
		1653	*/
		1654	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1655	{
6	mjames	1656	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1657	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1658	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1659	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1660	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1661	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
		1662	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
		1663	}
		1664
		1665	/**
		1666	* @brief Define the behavior of the output reference signal OCxREF from which
		1667	* OCx and OCxN (when relevant) are derived.
		1668	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1669	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1670	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1671	* CCMR2 OC4M LL_TIM_OC_SetMode
		1672	* @param TIMx Timer instance
		1673	* @param Channel This parameter can be one of the following values:
		1674	* @arg @ref LL_TIM_CHANNEL_CH1
		1675	* @arg @ref LL_TIM_CHANNEL_CH2
		1676	* @arg @ref LL_TIM_CHANNEL_CH3
		1677	* @arg @ref LL_TIM_CHANNEL_CH4
		1678	* @param Mode This parameter can be one of the following values:
		1679	* @arg @ref LL_TIM_OCMODE_FROZEN
		1680	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1681	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1682	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1683	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1684	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1685	* @arg @ref LL_TIM_OCMODE_PWM1
		1686	* @arg @ref LL_TIM_OCMODE_PWM2
		1687	* @retval None
		1688	*/
		1689	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1690	{
6	mjames	1691	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1692	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1693	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2	mjames	1694	}
		1695
		1696	/**
		1697	* @brief Get the output compare mode of an output channel.
		1698	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1699	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1700	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1701	* CCMR2 OC4M LL_TIM_OC_GetMode
		1702	* @param TIMx Timer instance
		1703	* @param Channel This parameter can be one of the following values:
		1704	* @arg @ref LL_TIM_CHANNEL_CH1
		1705	* @arg @ref LL_TIM_CHANNEL_CH2
		1706	* @arg @ref LL_TIM_CHANNEL_CH3
		1707	* @arg @ref LL_TIM_CHANNEL_CH4
		1708	* @retval Returned value can be one of the following values:
		1709	* @arg @ref LL_TIM_OCMODE_FROZEN
		1710	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1711	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1712	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1713	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1714	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1715	* @arg @ref LL_TIM_OCMODE_PWM1
		1716	* @arg @ref LL_TIM_OCMODE_PWM2
		1717	*/
		1718	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1719	{
6	mjames	1720	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1721	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1722	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2	mjames	1723	}
		1724
		1725	/**
		1726	* @brief Set the polarity of an output channel.
		1727	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1728	* CCER CC1NP LL_TIM_OC_SetPolarity\n
		1729	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1730	* CCER CC2NP LL_TIM_OC_SetPolarity\n
		1731	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1732	* CCER CC3NP LL_TIM_OC_SetPolarity\n
		1733	* CCER CC4P LL_TIM_OC_SetPolarity
		1734	* @param TIMx Timer instance
		1735	* @param Channel This parameter can be one of the following values:
		1736	* @arg @ref LL_TIM_CHANNEL_CH1
		1737	* @arg @ref LL_TIM_CHANNEL_CH1N
		1738	* @arg @ref LL_TIM_CHANNEL_CH2
		1739	* @arg @ref LL_TIM_CHANNEL_CH2N
		1740	* @arg @ref LL_TIM_CHANNEL_CH3
		1741	* @arg @ref LL_TIM_CHANNEL_CH3N
		1742	* @arg @ref LL_TIM_CHANNEL_CH4
		1743	* @param Polarity This parameter can be one of the following values:
		1744	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1745	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1746	* @retval None
		1747	*/
		1748	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1749	{
6	mjames	1750	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1751	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1752	}
		1753
		1754	/**
		1755	* @brief Get the polarity of an output channel.
		1756	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1757	* CCER CC1NP LL_TIM_OC_GetPolarity\n
		1758	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1759	* CCER CC2NP LL_TIM_OC_GetPolarity\n
		1760	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1761	* CCER CC3NP LL_TIM_OC_GetPolarity\n
		1762	* CCER CC4P LL_TIM_OC_GetPolarity
		1763	* @param TIMx Timer instance
		1764	* @param Channel This parameter can be one of the following values:
		1765	* @arg @ref LL_TIM_CHANNEL_CH1
		1766	* @arg @ref LL_TIM_CHANNEL_CH1N
		1767	* @arg @ref LL_TIM_CHANNEL_CH2
		1768	* @arg @ref LL_TIM_CHANNEL_CH2N
		1769	* @arg @ref LL_TIM_CHANNEL_CH3
		1770	* @arg @ref LL_TIM_CHANNEL_CH3N
		1771	* @arg @ref LL_TIM_CHANNEL_CH4
		1772	* @retval Returned value can be one of the following values:
		1773	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1774	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1775	*/
		1776	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1777	{
6	mjames	1778	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1779	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1780	}
		1781
		1782	/**
		1783	* @brief Set the IDLE state of an output channel
		1784	* @note This function is significant only for the timer instances
		1785	* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
		1786	* can be used to check whether or not a timer instance provides
		1787	* a break input.
		1788	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
		1789	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
		1790	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
		1791	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
		1792	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
		1793	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
		1794	* CR2 OIS4 LL_TIM_OC_SetIdleState
		1795	* @param TIMx Timer instance
		1796	* @param Channel This parameter can be one of the following values:
		1797	* @arg @ref LL_TIM_CHANNEL_CH1
		1798	* @arg @ref LL_TIM_CHANNEL_CH1N
		1799	* @arg @ref LL_TIM_CHANNEL_CH2
		1800	* @arg @ref LL_TIM_CHANNEL_CH2N
		1801	* @arg @ref LL_TIM_CHANNEL_CH3
		1802	* @arg @ref LL_TIM_CHANNEL_CH3N
		1803	* @arg @ref LL_TIM_CHANNEL_CH4
		1804	* @param IdleState This parameter can be one of the following values:
		1805	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1806	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1807	* @retval None
		1808	*/
		1809	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
		1810	{
6	mjames	1811	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1812	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
		1813	}
		1814
		1815	/**
		1816	* @brief Get the IDLE state of an output channel
		1817	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
		1818	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
		1819	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
		1820	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
		1821	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
		1822	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
		1823	* CR2 OIS4 LL_TIM_OC_GetIdleState
		1824	* @param TIMx Timer instance
		1825	* @param Channel This parameter can be one of the following values:
		1826	* @arg @ref LL_TIM_CHANNEL_CH1
		1827	* @arg @ref LL_TIM_CHANNEL_CH1N
		1828	* @arg @ref LL_TIM_CHANNEL_CH2
		1829	* @arg @ref LL_TIM_CHANNEL_CH2N
		1830	* @arg @ref LL_TIM_CHANNEL_CH3
		1831	* @arg @ref LL_TIM_CHANNEL_CH3N
		1832	* @arg @ref LL_TIM_CHANNEL_CH4
		1833	* @retval Returned value can be one of the following values:
		1834	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1835	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1836	*/
		1837	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
		1838	{
6	mjames	1839	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	1840	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
		1841	}
		1842
		1843	/**
		1844	* @brief Enable fast mode for the output channel.
		1845	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1846	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1847	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1848	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1849	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1850	* @param TIMx Timer instance
		1851	* @param Channel This parameter can be one of the following values:
		1852	* @arg @ref LL_TIM_CHANNEL_CH1
		1853	* @arg @ref LL_TIM_CHANNEL_CH2
		1854	* @arg @ref LL_TIM_CHANNEL_CH3
		1855	* @arg @ref LL_TIM_CHANNEL_CH4
		1856	* @retval None
		1857	*/
		1858	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1859	{
6	mjames	1860	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1861	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1862	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1863
		1864	}
		1865
		1866	/**
		1867	* @brief Disable fast mode for the output channel.
		1868	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1869	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1870	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1871	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1872	* @param TIMx Timer instance
		1873	* @param Channel This parameter can be one of the following values:
		1874	* @arg @ref LL_TIM_CHANNEL_CH1
		1875	* @arg @ref LL_TIM_CHANNEL_CH2
		1876	* @arg @ref LL_TIM_CHANNEL_CH3
		1877	* @arg @ref LL_TIM_CHANNEL_CH4
		1878	* @retval None
		1879	*/
		1880	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1881	{
6	mjames	1882	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1883	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1884	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1885
		1886	}
		1887
		1888	/**
		1889	* @brief Indicates whether fast mode is enabled for the output channel.
		1890	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1891	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1892	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1893	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1894	* @param TIMx Timer instance
		1895	* @param Channel This parameter can be one of the following values:
		1896	* @arg @ref LL_TIM_CHANNEL_CH1
		1897	* @arg @ref LL_TIM_CHANNEL_CH2
		1898	* @arg @ref LL_TIM_CHANNEL_CH3
		1899	* @arg @ref LL_TIM_CHANNEL_CH4
		1900	* @retval State of bit (1 or 0).
		1901	*/
		1902	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1903	{
6	mjames	1904	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1905	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1906	uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2	mjames	1907	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1908	}
		1909
		1910	/**
		1911	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1912	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1913	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1914	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1915	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1916	* @param TIMx Timer instance
		1917	* @param Channel This parameter can be one of the following values:
		1918	* @arg @ref LL_TIM_CHANNEL_CH1
		1919	* @arg @ref LL_TIM_CHANNEL_CH2
		1920	* @arg @ref LL_TIM_CHANNEL_CH3
		1921	* @arg @ref LL_TIM_CHANNEL_CH4
		1922	* @retval None
		1923	*/
		1924	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1925	{
6	mjames	1926	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1927	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1928	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1929	}
		1930
		1931	/**
		1932	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1933	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1934	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1935	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1936	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1937	* @param TIMx Timer instance
		1938	* @param Channel This parameter can be one of the following values:
		1939	* @arg @ref LL_TIM_CHANNEL_CH1
		1940	* @arg @ref LL_TIM_CHANNEL_CH2
		1941	* @arg @ref LL_TIM_CHANNEL_CH3
		1942	* @arg @ref LL_TIM_CHANNEL_CH4
		1943	* @retval None
		1944	*/
		1945	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1946	{
6	mjames	1947	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1948	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1949	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1950	}
		1951
		1952	/**
		1953	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1954	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1955	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1956	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1957	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1958	* @param TIMx Timer instance
		1959	* @param Channel This parameter can be one of the following values:
		1960	* @arg @ref LL_TIM_CHANNEL_CH1
		1961	* @arg @ref LL_TIM_CHANNEL_CH2
		1962	* @arg @ref LL_TIM_CHANNEL_CH3
		1963	* @arg @ref LL_TIM_CHANNEL_CH4
		1964	* @retval State of bit (1 or 0).
		1965	*/
		1966	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1967	{
6	mjames	1968	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1969	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1970	uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2	mjames	1971	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1972	}
		1973
		1974	/**
		1975	* @brief Enable clearing the output channel on an external event.
		1976	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1977	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1978	* or not a timer instance can clear the OCxREF signal on an external event.
		1979	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1980	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1981	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1982	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1983	* @param TIMx Timer instance
		1984	* @param Channel This parameter can be one of the following values:
		1985	* @arg @ref LL_TIM_CHANNEL_CH1
		1986	* @arg @ref LL_TIM_CHANNEL_CH2
		1987	* @arg @ref LL_TIM_CHANNEL_CH3
		1988	* @arg @ref LL_TIM_CHANNEL_CH4
		1989	* @retval None
		1990	*/
		1991	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1992	{
6	mjames	1993	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1994	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	1995	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1996	}
		1997
		1998	/**
		1999	* @brief Disable clearing the output channel on an external event.
		2000	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		2001	* or not a timer instance can clear the OCxREF signal on an external event.
		2002	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		2003	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		2004	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		2005	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		2006	* @param TIMx Timer instance
		2007	* @param Channel This parameter can be one of the following values:
		2008	* @arg @ref LL_TIM_CHANNEL_CH1
		2009	* @arg @ref LL_TIM_CHANNEL_CH2
		2010	* @arg @ref LL_TIM_CHANNEL_CH3
		2011	* @arg @ref LL_TIM_CHANNEL_CH4
		2012	* @retval None
		2013	*/
		2014	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		2015	{
6	mjames	2016	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2017	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2018	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		2019	}
		2020
		2021	/**
		2022	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		2023	* @note This function enables clearing the output channel on an external event.
		2024	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		2025	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		2026	* or not a timer instance can clear the OCxREF signal on an external event.
		2027	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		2028	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		2029	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		2030	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		2031	* @param TIMx Timer instance
		2032	* @param Channel This parameter can be one of the following values:
		2033	* @arg @ref LL_TIM_CHANNEL_CH1
		2034	* @arg @ref LL_TIM_CHANNEL_CH2
		2035	* @arg @ref LL_TIM_CHANNEL_CH3
		2036	* @arg @ref LL_TIM_CHANNEL_CH4
		2037	* @retval State of bit (1 or 0).
		2038	*/
		2039	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		2040	{
6	mjames	2041	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2042	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2043	uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2	mjames	2044	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		2045	}
		2046
		2047	/**
6	mjames	2048	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
		2049	* the Ocx and OCxN signals).
2	mjames	2050	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2051	* dead-time insertion feature is supported by a timer instance.
		2052	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
		2053	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
		2054	* @param TIMx Timer instance
		2055	* @param DeadTime between Min_Data=0 and Max_Data=255
		2056	* @retval None
		2057	*/
		2058	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
		2059	{
		2060	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
		2061	}
		2062
		2063	/**
		2064	* @brief Set compare value for output channel 1 (TIMx_CCR1).
		2065	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2066	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2067	* whether or not a timer instance supports a 32 bits counter.
		2068	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2069	* output channel 1 is supported by a timer instance.
		2070	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		2071	* @param TIMx Timer instance
		2072	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2073	* @retval None
		2074	*/
		2075	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2076	{
		2077	WRITE_REG(TIMx->CCR1, CompareValue);
		2078	}
		2079
		2080	/**
		2081	* @brief Set compare value for output channel 2 (TIMx_CCR2).
		2082	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2083	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2084	* whether or not a timer instance supports a 32 bits counter.
		2085	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2086	* output channel 2 is supported by a timer instance.
		2087	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		2088	* @param TIMx Timer instance
		2089	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2090	* @retval None
		2091	*/
		2092	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2093	{
		2094	WRITE_REG(TIMx->CCR2, CompareValue);
		2095	}
		2096
		2097	/**
		2098	* @brief Set compare value for output channel 3 (TIMx_CCR3).
		2099	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2100	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2101	* whether or not a timer instance supports a 32 bits counter.
		2102	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2103	* output channel is supported by a timer instance.
		2104	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		2105	* @param TIMx Timer instance
		2106	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2107	* @retval None
		2108	*/
		2109	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2110	{
		2111	WRITE_REG(TIMx->CCR3, CompareValue);
		2112	}
		2113
		2114	/**
		2115	* @brief Set compare value for output channel 4 (TIMx_CCR4).
		2116	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2117	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2118	* whether or not a timer instance supports a 32 bits counter.
		2119	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2120	* output channel 4 is supported by a timer instance.
		2121	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		2122	* @param TIMx Timer instance
		2123	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2124	* @retval None
		2125	*/
		2126	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2127	{
		2128	WRITE_REG(TIMx->CCR4, CompareValue);
		2129	}
		2130
		2131	/**
		2132	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
		2133	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2134	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2135	* whether or not a timer instance supports a 32 bits counter.
		2136	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2137	* output channel 1 is supported by a timer instance.
		2138	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		2139	* @param TIMx Timer instance
		2140	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2141	*/
		2142	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		2143	{
		2144	return (uint32_t)(READ_REG(TIMx->CCR1));
		2145	}
		2146
		2147	/**
		2148	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
		2149	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2150	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2151	* whether or not a timer instance supports a 32 bits counter.
		2152	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2153	* output channel 2 is supported by a timer instance.
		2154	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		2155	* @param TIMx Timer instance
		2156	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2157	*/
		2158	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		2159	{
		2160	return (uint32_t)(READ_REG(TIMx->CCR2));
		2161	}
		2162
		2163	/**
		2164	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
		2165	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2166	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2167	* whether or not a timer instance supports a 32 bits counter.
		2168	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2169	* output channel 3 is supported by a timer instance.
		2170	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		2171	* @param TIMx Timer instance
		2172	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2173	*/
		2174	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		2175	{
		2176	return (uint32_t)(READ_REG(TIMx->CCR3));
		2177	}
		2178
		2179	/**
		2180	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
		2181	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2182	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2183	* whether or not a timer instance supports a 32 bits counter.
		2184	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2185	* output channel 4 is supported by a timer instance.
		2186	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		2187	* @param TIMx Timer instance
		2188	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2189	*/
		2190	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		2191	{
		2192	return (uint32_t)(READ_REG(TIMx->CCR4));
		2193	}
		2194
		2195	/**
		2196	* @}
		2197	*/
		2198
		2199	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		2200	* @{
		2201	*/
		2202	/**
		2203	* @brief Configure input channel.
		2204	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		2205	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		2206	* CCMR1 IC1F LL_TIM_IC_Config\n
		2207	* CCMR1 CC2S LL_TIM_IC_Config\n
		2208	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		2209	* CCMR1 IC2F LL_TIM_IC_Config\n
		2210	* CCMR2 CC3S LL_TIM_IC_Config\n
		2211	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		2212	* CCMR2 IC3F LL_TIM_IC_Config\n
		2213	* CCMR2 CC4S LL_TIM_IC_Config\n
		2214	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		2215	* CCMR2 IC4F LL_TIM_IC_Config\n
		2216	* CCER CC1P LL_TIM_IC_Config\n
		2217	* CCER CC1NP LL_TIM_IC_Config\n
		2218	* CCER CC2P LL_TIM_IC_Config\n
		2219	* CCER CC2NP LL_TIM_IC_Config\n
		2220	* CCER CC3P LL_TIM_IC_Config\n
		2221	* CCER CC3NP LL_TIM_IC_Config\n
		2222	* CCER CC4P LL_TIM_IC_Config\n
		2223	* CCER CC4NP LL_TIM_IC_Config
		2224	* @param TIMx Timer instance
		2225	* @param Channel This parameter can be one of the following values:
		2226	* @arg @ref LL_TIM_CHANNEL_CH1
		2227	* @arg @ref LL_TIM_CHANNEL_CH2
		2228	* @arg @ref LL_TIM_CHANNEL_CH3
		2229	* @arg @ref LL_TIM_CHANNEL_CH4
		2230	* @param Configuration This parameter must be a combination of all the following values:
		2231	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		2232	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		2233	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		2234	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2235	* @retval None
		2236	*/
		2237	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		2238	{
6	mjames	2239	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2240	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2241	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
6	mjames	2242	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) \
		2243	<< SHIFT_TAB_ICxx[iChannel]);
2	mjames	2244	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2245	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		2246	}
		2247
		2248	/**
		2249	* @brief Set the active input.
		2250	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		2251	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		2252	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		2253	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		2254	* @param TIMx Timer instance
		2255	* @param Channel This parameter can be one of the following values:
		2256	* @arg @ref LL_TIM_CHANNEL_CH1
		2257	* @arg @ref LL_TIM_CHANNEL_CH2
		2258	* @arg @ref LL_TIM_CHANNEL_CH3
		2259	* @arg @ref LL_TIM_CHANNEL_CH4
		2260	* @param ICActiveInput This parameter can be one of the following values:
		2261	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2262	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2263	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2264	* @retval None
		2265	*/
		2266	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		2267	{
6	mjames	2268	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2269	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2270	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2271	}
		2272
		2273	/**
		2274	* @brief Get the current active input.
		2275	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		2276	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		2277	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		2278	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		2279	* @param TIMx Timer instance
		2280	* @param Channel This parameter can be one of the following values:
		2281	* @arg @ref LL_TIM_CHANNEL_CH1
		2282	* @arg @ref LL_TIM_CHANNEL_CH2
		2283	* @arg @ref LL_TIM_CHANNEL_CH3
		2284	* @arg @ref LL_TIM_CHANNEL_CH4
		2285	* @retval Returned value can be one of the following values:
		2286	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2287	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2288	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2289	*/
		2290	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		2291	{
6	mjames	2292	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2293	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2294	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2295	}
		2296
		2297	/**
		2298	* @brief Set the prescaler of input channel.
		2299	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		2300	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		2301	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		2302	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		2303	* @param TIMx Timer instance
		2304	* @param Channel This parameter can be one of the following values:
		2305	* @arg @ref LL_TIM_CHANNEL_CH1
		2306	* @arg @ref LL_TIM_CHANNEL_CH2
		2307	* @arg @ref LL_TIM_CHANNEL_CH3
		2308	* @arg @ref LL_TIM_CHANNEL_CH4
		2309	* @param ICPrescaler This parameter can be one of the following values:
		2310	* @arg @ref LL_TIM_ICPSC_DIV1
		2311	* @arg @ref LL_TIM_ICPSC_DIV2
		2312	* @arg @ref LL_TIM_ICPSC_DIV4
		2313	* @arg @ref LL_TIM_ICPSC_DIV8
		2314	* @retval None
		2315	*/
		2316	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		2317	{
6	mjames	2318	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2319	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2320	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2321	}
		2322
		2323	/**
		2324	* @brief Get the current prescaler value acting on an input channel.
		2325	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		2326	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		2327	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		2328	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		2329	* @param TIMx Timer instance
		2330	* @param Channel This parameter can be one of the following values:
		2331	* @arg @ref LL_TIM_CHANNEL_CH1
		2332	* @arg @ref LL_TIM_CHANNEL_CH2
		2333	* @arg @ref LL_TIM_CHANNEL_CH3
		2334	* @arg @ref LL_TIM_CHANNEL_CH4
		2335	* @retval Returned value can be one of the following values:
		2336	* @arg @ref LL_TIM_ICPSC_DIV1
		2337	* @arg @ref LL_TIM_ICPSC_DIV2
		2338	* @arg @ref LL_TIM_ICPSC_DIV4
		2339	* @arg @ref LL_TIM_ICPSC_DIV8
		2340	*/
		2341	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		2342	{
6	mjames	2343	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2344	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2345	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2346	}
		2347
		2348	/**
		2349	* @brief Set the input filter duration.
		2350	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		2351	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		2352	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		2353	* CCMR2 IC4F LL_TIM_IC_SetFilter
		2354	* @param TIMx Timer instance
		2355	* @param Channel This parameter can be one of the following values:
		2356	* @arg @ref LL_TIM_CHANNEL_CH1
		2357	* @arg @ref LL_TIM_CHANNEL_CH2
		2358	* @arg @ref LL_TIM_CHANNEL_CH3
		2359	* @arg @ref LL_TIM_CHANNEL_CH4
		2360	* @param ICFilter This parameter can be one of the following values:
		2361	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2362	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2363	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2364	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2365	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2366	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2367	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2368	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2369	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2370	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2371	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2372	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2373	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2374	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2375	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2376	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2377	* @retval None
		2378	*/
		2379	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		2380	{
6	mjames	2381	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2382	__IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2383	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2384	}
		2385
		2386	/**
		2387	* @brief Get the input filter duration.
		2388	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		2389	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		2390	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		2391	* CCMR2 IC4F LL_TIM_IC_GetFilter
		2392	* @param TIMx Timer instance
		2393	* @param Channel This parameter can be one of the following values:
		2394	* @arg @ref LL_TIM_CHANNEL_CH1
		2395	* @arg @ref LL_TIM_CHANNEL_CH2
		2396	* @arg @ref LL_TIM_CHANNEL_CH3
		2397	* @arg @ref LL_TIM_CHANNEL_CH4
		2398	* @retval Returned value can be one of the following values:
		2399	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2400	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2401	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2402	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2403	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2404	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2405	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2406	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2407	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2408	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2409	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2410	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2411	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2412	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2413	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2414	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2415	*/
		2416	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		2417	{
6	mjames	2418	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2419	const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2	mjames	2420	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2421	}
		2422
		2423	/**
		2424	* @brief Set the input channel polarity.
		2425	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		2426	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		2427	* CCER CC2P LL_TIM_IC_SetPolarity\n
		2428	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		2429	* CCER CC3P LL_TIM_IC_SetPolarity\n
		2430	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2431	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2432	* CCER CC4NP LL_TIM_IC_SetPolarity
		2433	* @param TIMx Timer instance
		2434	* @param Channel This parameter can be one of the following values:
		2435	* @arg @ref LL_TIM_CHANNEL_CH1
		2436	* @arg @ref LL_TIM_CHANNEL_CH2
		2437	* @arg @ref LL_TIM_CHANNEL_CH3
		2438	* @arg @ref LL_TIM_CHANNEL_CH4
		2439	* @param ICPolarity This parameter can be one of the following values:
		2440	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2441	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2442	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2443	* @retval None
		2444	*/
		2445	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2446	{
6	mjames	2447	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	2448	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2449	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2450	}
		2451
		2452	/**
		2453	* @brief Get the current input channel polarity.
		2454	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2455	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2456	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2457	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2458	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2459	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2460	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2461	* CCER CC4NP LL_TIM_IC_GetPolarity
		2462	* @param TIMx Timer instance
		2463	* @param Channel This parameter can be one of the following values:
		2464	* @arg @ref LL_TIM_CHANNEL_CH1
		2465	* @arg @ref LL_TIM_CHANNEL_CH2
		2466	* @arg @ref LL_TIM_CHANNEL_CH3
		2467	* @arg @ref LL_TIM_CHANNEL_CH4
		2468	* @retval Returned value can be one of the following values:
		2469	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2470	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2471	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2472	*/
		2473	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2474	{
6	mjames	2475	uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2	mjames	2476	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2477	SHIFT_TAB_CCxP[iChannel]);
		2478	}
		2479
		2480	/**
		2481	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
		2482	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2483	* a timer instance provides an XOR input.
		2484	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2485	* @param TIMx Timer instance
		2486	* @retval None
		2487	*/
		2488	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2489	{
		2490	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2491	}
		2492
		2493	/**
		2494	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
		2495	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2496	* a timer instance provides an XOR input.
		2497	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2498	* @param TIMx Timer instance
		2499	* @retval None
		2500	*/
		2501	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2502	{
		2503	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2504	}
		2505
		2506	/**
		2507	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
		2508	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2509	* a timer instance provides an XOR input.
		2510	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2511	* @param TIMx Timer instance
		2512	* @retval State of bit (1 or 0).
		2513	*/
		2514	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2515	{
		2516	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
		2517	}
		2518
		2519	/**
		2520	* @brief Get captured value for input channel 1.
		2521	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2522	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2523	* whether or not a timer instance supports a 32 bits counter.
		2524	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2525	* input channel 1 is supported by a timer instance.
		2526	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2527	* @param TIMx Timer instance
		2528	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2529	*/
		2530	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2531	{
		2532	return (uint32_t)(READ_REG(TIMx->CCR1));
		2533	}
		2534
		2535	/**
		2536	* @brief Get captured value for input channel 2.
		2537	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2538	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2539	* whether or not a timer instance supports a 32 bits counter.
		2540	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2541	* input channel 2 is supported by a timer instance.
		2542	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2543	* @param TIMx Timer instance
		2544	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2545	*/
		2546	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2547	{
		2548	return (uint32_t)(READ_REG(TIMx->CCR2));
		2549	}
		2550
		2551	/**
		2552	* @brief Get captured value for input channel 3.
		2553	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2554	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2555	* whether or not a timer instance supports a 32 bits counter.
		2556	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2557	* input channel 3 is supported by a timer instance.
		2558	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2559	* @param TIMx Timer instance
		2560	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2561	*/
		2562	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2563	{
		2564	return (uint32_t)(READ_REG(TIMx->CCR3));
		2565	}
		2566
		2567	/**
		2568	* @brief Get captured value for input channel 4.
		2569	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2570	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2571	* whether or not a timer instance supports a 32 bits counter.
		2572	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2573	* input channel 4 is supported by a timer instance.
		2574	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2575	* @param TIMx Timer instance
		2576	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2577	*/
		2578	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2579	{
		2580	return (uint32_t)(READ_REG(TIMx->CCR4));
		2581	}
		2582
		2583	/**
		2584	* @}
		2585	*/
		2586
		2587	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2588	* @{
		2589	*/
		2590	/**
		2591	* @brief Enable external clock mode 2.
		2592	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
		2593	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2594	* whether or not a timer instance supports external clock mode2.
		2595	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2596	* @param TIMx Timer instance
		2597	* @retval None
		2598	*/
		2599	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2600	{
		2601	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2602	}
		2603
		2604	/**
		2605	* @brief Disable external clock mode 2.
		2606	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2607	* whether or not a timer instance supports external clock mode2.
		2608	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2609	* @param TIMx Timer instance
		2610	* @retval None
		2611	*/
		2612	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2613	{
		2614	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2615	}
		2616
		2617	/**
		2618	* @brief Indicate whether external clock mode 2 is enabled.
		2619	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2620	* whether or not a timer instance supports external clock mode2.
		2621	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2622	* @param TIMx Timer instance
		2623	* @retval State of bit (1 or 0).
		2624	*/
		2625	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2626	{
		2627	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
		2628	}
		2629
		2630	/**
		2631	* @brief Set the clock source of the counter clock.
		2632	* @note when selected clock source is external clock mode 1, the timer input
		2633	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2634	* function. This timer input must be configured by calling
		2635	* the @ref LL_TIM_IC_Config() function.
		2636	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
		2637	* whether or not a timer instance supports external clock mode1.
		2638	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2639	* whether or not a timer instance supports external clock mode2.
		2640	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2641	* SMCR ECE LL_TIM_SetClockSource
		2642	* @param TIMx Timer instance
		2643	* @param ClockSource This parameter can be one of the following values:
		2644	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2645	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2646	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2647	* @retval None
		2648	*/
		2649	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2650	{
		2651	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2652	}
		2653
		2654	/**
		2655	* @brief Set the encoder interface mode.
		2656	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
		2657	* whether or not a timer instance supports the encoder mode.
		2658	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2659	* @param TIMx Timer instance
		2660	* @param EncoderMode This parameter can be one of the following values:
		2661	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2662	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2663	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2664	* @retval None
		2665	*/
		2666	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2667	{
		2668	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2669	}
		2670
		2671	/**
		2672	* @}
		2673	*/
		2674
		2675	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2676	* @{
		2677	*/
		2678	/**
		2679	* @brief Set the trigger output (TRGO) used for timer synchronization .
		2680	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
		2681	* whether or not a timer instance can operate as a master timer.
		2682	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2683	* @param TIMx Timer instance
		2684	* @param TimerSynchronization This parameter can be one of the following values:
		2685	* @arg @ref LL_TIM_TRGO_RESET
		2686	* @arg @ref LL_TIM_TRGO_ENABLE
		2687	* @arg @ref LL_TIM_TRGO_UPDATE
		2688	* @arg @ref LL_TIM_TRGO_CC1IF
		2689	* @arg @ref LL_TIM_TRGO_OC1REF
		2690	* @arg @ref LL_TIM_TRGO_OC2REF
		2691	* @arg @ref LL_TIM_TRGO_OC3REF
		2692	* @arg @ref LL_TIM_TRGO_OC4REF
		2693	* @retval None
		2694	*/
		2695	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2696	{
		2697	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2698	}
		2699
		2700	/**
		2701	* @brief Set the synchronization mode of a slave timer.
		2702	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2703	* a timer instance can operate as a slave timer.
		2704	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2705	* @param TIMx Timer instance
		2706	* @param SlaveMode This parameter can be one of the following values:
		2707	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2708	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2709	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2710	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2711	* @retval None
		2712	*/
		2713	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2714	{
		2715	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2716	}
		2717
		2718	/**
		2719	* @brief Set the selects the trigger input to be used to synchronize the counter.
		2720	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2721	* a timer instance can operate as a slave timer.
		2722	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2723	* @param TIMx Timer instance
		2724	* @param TriggerInput This parameter can be one of the following values:
		2725	* @arg @ref LL_TIM_TS_ITR0
		2726	* @arg @ref LL_TIM_TS_ITR1
		2727	* @arg @ref LL_TIM_TS_ITR2
		2728	* @arg @ref LL_TIM_TS_ITR3
		2729	* @arg @ref LL_TIM_TS_TI1F_ED
		2730	* @arg @ref LL_TIM_TS_TI1FP1
		2731	* @arg @ref LL_TIM_TS_TI2FP2
		2732	* @arg @ref LL_TIM_TS_ETRF
		2733	* @retval None
		2734	*/
		2735	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2736	{
		2737	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2738	}
		2739
		2740	/**
		2741	* @brief Enable the Master/Slave mode.
		2742	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2743	* a timer instance can operate as a slave timer.
		2744	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2745	* @param TIMx Timer instance
		2746	* @retval None
		2747	*/
		2748	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2749	{
		2750	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2751	}
		2752
		2753	/**
		2754	* @brief Disable the Master/Slave mode.
		2755	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2756	* a timer instance can operate as a slave timer.
		2757	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2758	* @param TIMx Timer instance
		2759	* @retval None
		2760	*/
		2761	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2762	{
		2763	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2764	}
		2765
		2766	/**
		2767	* @brief Indicates whether the Master/Slave mode is enabled.
		2768	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2769	* a timer instance can operate as a slave timer.
		2770	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2771	* @param TIMx Timer instance
		2772	* @retval State of bit (1 or 0).
		2773	*/
		2774	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2775	{
		2776	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
		2777	}
		2778
		2779	/**
		2780	* @brief Configure the external trigger (ETR) input.
		2781	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
		2782	* a timer instance provides an external trigger input.
		2783	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2784	* SMCR ETPS LL_TIM_ConfigETR\n
		2785	* SMCR ETF LL_TIM_ConfigETR
		2786	* @param TIMx Timer instance
		2787	* @param ETRPolarity This parameter can be one of the following values:
		2788	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2789	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2790	* @param ETRPrescaler This parameter can be one of the following values:
		2791	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2792	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2793	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2794	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2795	* @param ETRFilter This parameter can be one of the following values:
		2796	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2797	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2798	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2799	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2800	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2801	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2802	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2803	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2804	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2805	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2806	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2807	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2808	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2809	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2810	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2811	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2812	* @retval None
		2813	*/
		2814	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2815	uint32_t ETRFilter)
		2816	{
		2817	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2818	}
		2819
		2820	/**
		2821	* @}
		2822	*/
		2823
		2824	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
		2825	* @{
		2826	*/
		2827	/**
		2828	* @brief Enable the break function.
		2829	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2830	* a timer instance provides a break input.
		2831	* @rmtoll BDTR BKE LL_TIM_EnableBRK
		2832	* @param TIMx Timer instance
		2833	* @retval None
		2834	*/
		2835	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
		2836	{
		2837	__IO uint32_t tmpreg;
		2838	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2839	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2840	tmpreg = READ_REG(TIMx->BDTR);
		2841	(void)(tmpreg);
		2842	}
		2843
		2844	/**
		2845	* @brief Disable the break function.
		2846	* @rmtoll BDTR BKE LL_TIM_DisableBRK
		2847	* @param TIMx Timer instance
		2848	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2849	* a timer instance provides a break input.
		2850	* @retval None
		2851	*/
		2852	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
		2853	{
		2854	__IO uint32_t tmpreg;
		2855	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2856	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2857	tmpreg = READ_REG(TIMx->BDTR);
		2858	(void)(tmpreg);
		2859	}
		2860
		2861	/**
		2862	* @brief Configure the break input.
		2863	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2864	* a timer instance provides a break input.
		2865	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
		2866	* @param TIMx Timer instance
		2867	* @param BreakPolarity This parameter can be one of the following values:
		2868	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
		2869	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
		2870	* @retval None
		2871	*/
		2872	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
		2873	{
		2874	__IO uint32_t tmpreg;
		2875	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
		2876	/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
		2877	tmpreg = READ_REG(TIMx->BDTR);
		2878	(void)(tmpreg);
		2879	}
		2880
		2881	/**
		2882	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
		2883	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2884	* a timer instance provides a break input.
		2885	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
		2886	* BDTR OSSR LL_TIM_SetOffStates
		2887	* @param TIMx Timer instance
		2888	* @param OffStateIdle This parameter can be one of the following values:
		2889	* @arg @ref LL_TIM_OSSI_DISABLE
		2890	* @arg @ref LL_TIM_OSSI_ENABLE
		2891	* @param OffStateRun This parameter can be one of the following values:
		2892	* @arg @ref LL_TIM_OSSR_DISABLE
		2893	* @arg @ref LL_TIM_OSSR_ENABLE
		2894	* @retval None
		2895	*/
		2896	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
		2897	{
		2898	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
		2899	}
		2900
		2901	/**
		2902	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
		2903	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2904	* a timer instance provides a break input.
		2905	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
		2906	* @param TIMx Timer instance
		2907	* @retval None
		2908	*/
		2909	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
		2910	{
		2911	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2912	}
		2913
		2914	/**
		2915	* @brief Disable automatic output (MOE can be set only by software).
		2916	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2917	* a timer instance provides a break input.
		2918	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
		2919	* @param TIMx Timer instance
		2920	* @retval None
		2921	*/
		2922	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
		2923	{
		2924	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2925	}
		2926
		2927	/**
		2928	* @brief Indicate whether automatic output is enabled.
		2929	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2930	* a timer instance provides a break input.
		2931	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
		2932	* @param TIMx Timer instance
		2933	* @retval State of bit (1 or 0).
		2934	*/
		2935	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
		2936	{
		2937	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
		2938	}
		2939
		2940	/**
		2941	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
		2942	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2943	* software and is reset in case of break or break2 event
		2944	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2945	* a timer instance provides a break input.
		2946	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
		2947	* @param TIMx Timer instance
		2948	* @retval None
		2949	*/
		2950	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
		2951	{
		2952	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2953	}
		2954
		2955	/**
		2956	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
		2957	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2958	* software and is reset in case of break or break2 event.
		2959	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2960	* a timer instance provides a break input.
		2961	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
		2962	* @param TIMx Timer instance
		2963	* @retval None
		2964	*/
		2965	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
		2966	{
		2967	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2968	}
		2969
		2970	/**
		2971	* @brief Indicates whether outputs are enabled.
		2972	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2973	* a timer instance provides a break input.
		2974	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
		2975	* @param TIMx Timer instance
		2976	* @retval State of bit (1 or 0).
		2977	*/
		2978	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
		2979	{
		2980	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
		2981	}
		2982
		2983	/**
		2984	* @}
		2985	*/
		2986
		2987	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2988	* @{
		2989	*/
		2990	/**
		2991	* @brief Configures the timer DMA burst feature.
		2992	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
		2993	* not a timer instance supports the DMA burst mode.
		2994	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2995	* DCR DBA LL_TIM_ConfigDMABurst
		2996	* @param TIMx Timer instance
		2997	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2998	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2999	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		3000	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		3001	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		3002	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		3003	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		3004	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		3005	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		3006	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		3007	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		3008	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		3009	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		3010	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
		3011	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		3012	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		3013	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		3014	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		3015	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
		3016	* @param DMABurstLength This parameter can be one of the following values:
		3017	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		3018	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		3019	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		3020	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		3021	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		3022	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		3023	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		3024	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		3025	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		3026	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		3027	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		3028	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		3029	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		3030	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		3031	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		3032	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		3033	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		3034	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		3035	* @retval None
		3036	*/
		3037	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		3038	{
		3039	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
		3040	}
		3041
		3042	/**
		3043	* @}
		3044	*/
		3045
		3046	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
		3047	* @{
		3048	*/
		3049	/**
		3050	* @brief Remap TIM inputs (input channel, internal/external triggers).
		3051	* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
		3052	* a some timer inputs can be remapped.
		3053	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
		3054	* @param TIMx Timer instance
		3055	* @param Remap This parameter can be one of the following values:
		3056	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
		3057	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
		3058	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
		3059	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
		3060	*
		3061	* @retval None
		3062	*/
		3063	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
		3064	{
		3065	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
		3066	}
		3067
		3068	/**
		3069	* @}
		3070	*/
		3071
		3072	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
		3073	* @{
		3074	*/
		3075	/**
		3076	* @brief Set the OCREF clear input source
		3077	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
		3078	* @note This function can only be used in Output compare and PWM modes.
		3079	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
		3080	* @param TIMx Timer instance
		3081	* @param OCRefClearInputSource This parameter can be one of the following values:
		3082	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
		3083	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
		3084	* @retval None
		3085	*/
		3086	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
		3087	{
		3088	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
		3089	}
		3090	/**
		3091	* @}
		3092	*/
		3093
		3094	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		3095	* @{
		3096	*/
		3097	/**
		3098	* @brief Clear the update interrupt flag (UIF).
		3099	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		3100	* @param TIMx Timer instance
		3101	* @retval None
		3102	*/
		3103	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		3104	{
		3105	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		3106	}
		3107
		3108	/**
		3109	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		3110	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		3111	* @param TIMx Timer instance
		3112	* @retval State of bit (1 or 0).
		3113	*/
		3114	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		3115	{
		3116	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
		3117	}
		3118
		3119	/**
		3120	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		3121	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		3122	* @param TIMx Timer instance
		3123	* @retval None
		3124	*/
		3125	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		3126	{
		3127	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		3128	}
		3129
		3130	/**
		3131	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		3132	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		3133	* @param TIMx Timer instance
		3134	* @retval State of bit (1 or 0).
		3135	*/
		3136	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		3137	{
		3138	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
		3139	}
		3140
		3141	/**
		3142	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		3143	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		3144	* @param TIMx Timer instance
		3145	* @retval None
		3146	*/
		3147	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		3148	{
		3149	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		3150	}
		3151
		3152	/**
		3153	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		3154	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		3155	* @param TIMx Timer instance
		3156	* @retval State of bit (1 or 0).
		3157	*/
		3158	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		3159	{
		3160	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
		3161	}
		3162
		3163	/**
		3164	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		3165	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		3166	* @param TIMx Timer instance
		3167	* @retval None
		3168	*/
		3169	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		3170	{
		3171	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		3172	}
		3173
		3174	/**
		3175	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		3176	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		3177	* @param TIMx Timer instance
		3178	* @retval State of bit (1 or 0).
		3179	*/
		3180	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		3181	{
		3182	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
		3183	}
		3184
		3185	/**
		3186	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		3187	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		3188	* @param TIMx Timer instance
		3189	* @retval None
		3190	*/
		3191	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		3192	{
		3193	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		3194	}
		3195
		3196	/**
		3197	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		3198	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		3199	* @param TIMx Timer instance
		3200	* @retval State of bit (1 or 0).
		3201	*/
		3202	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		3203	{
		3204	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
		3205	}
		3206
		3207	/**
		3208	* @brief Clear the commutation interrupt flag (COMIF).
		3209	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
		3210	* @param TIMx Timer instance
		3211	* @retval None
		3212	*/
		3213	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
		3214	{
		3215	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
		3216	}
		3217
		3218	/**
		3219	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
		3220	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
		3221	* @param TIMx Timer instance
		3222	* @retval State of bit (1 or 0).
		3223	*/
		3224	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
		3225	{
		3226	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
		3227	}
		3228
		3229	/**
		3230	* @brief Clear the trigger interrupt flag (TIF).
		3231	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		3232	* @param TIMx Timer instance
		3233	* @retval None
		3234	*/
		3235	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		3236	{
		3237	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		3238	}
		3239
		3240	/**
		3241	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		3242	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		3243	* @param TIMx Timer instance
		3244	* @retval State of bit (1 or 0).
		3245	*/
		3246	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		3247	{
		3248	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
		3249	}
		3250
		3251	/**
		3252	* @brief Clear the break interrupt flag (BIF).
		3253	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
		3254	* @param TIMx Timer instance
		3255	* @retval None
		3256	*/
		3257	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
		3258	{
		3259	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
		3260	}
		3261
		3262	/**
		3263	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
		3264	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
		3265	* @param TIMx Timer instance
		3266	* @retval State of bit (1 or 0).
		3267	*/
		3268	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
		3269	{
		3270	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
		3271	}
		3272
		3273	/**
		3274	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		3275	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		3276	* @param TIMx Timer instance
		3277	* @retval None
		3278	*/
		3279	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		3280	{
		3281	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		3282	}
		3283
		3284	/**
6	mjames	3285	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
		3286	* (Capture/Compare 1 interrupt is pending).
2	mjames	3287	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		3288	* @param TIMx Timer instance
		3289	* @retval State of bit (1 or 0).
		3290	*/
		3291	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		3292	{
		3293	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
		3294	}
		3295
		3296	/**
		3297	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		3298	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		3299	* @param TIMx Timer instance
		3300	* @retval None
		3301	*/
		3302	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		3303	{
		3304	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		3305	}
		3306
		3307	/**
6	mjames	3308	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
		3309	* (Capture/Compare 2 over-capture interrupt is pending).
2	mjames	3310	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		3311	* @param TIMx Timer instance
		3312	* @retval State of bit (1 or 0).
		3313	*/
		3314	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		3315	{
		3316	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
		3317	}
		3318
		3319	/**
		3320	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		3321	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		3322	* @param TIMx Timer instance
		3323	* @retval None
		3324	*/
		3325	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		3326	{
		3327	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		3328	}
		3329
		3330	/**
6	mjames	3331	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
		3332	* (Capture/Compare 3 over-capture interrupt is pending).
2	mjames	3333	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		3334	* @param TIMx Timer instance
		3335	* @retval State of bit (1 or 0).
		3336	*/
		3337	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		3338	{
		3339	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
		3340	}
		3341
		3342	/**
		3343	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		3344	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		3345	* @param TIMx Timer instance
		3346	* @retval None
		3347	*/
		3348	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		3349	{
		3350	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		3351	}
		3352
		3353	/**
6	mjames	3354	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
		3355	* (Capture/Compare 4 over-capture interrupt is pending).
2	mjames	3356	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		3357	* @param TIMx Timer instance
		3358	* @retval State of bit (1 or 0).
		3359	*/
		3360	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		3361	{
		3362	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
		3363	}
		3364
		3365	/**
		3366	* @}
		3367	*/
		3368
		3369	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		3370	* @{
		3371	*/
		3372	/**
		3373	* @brief Enable update interrupt (UIE).
		3374	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		3375	* @param TIMx Timer instance
		3376	* @retval None
		3377	*/
		3378	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		3379	{
		3380	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		3381	}
		3382
		3383	/**
		3384	* @brief Disable update interrupt (UIE).
		3385	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		3386	* @param TIMx Timer instance
		3387	* @retval None
		3388	*/
		3389	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		3390	{
		3391	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		3392	}
		3393
		3394	/**
		3395	* @brief Indicates whether the update interrupt (UIE) is enabled.
		3396	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		3397	* @param TIMx Timer instance
		3398	* @retval State of bit (1 or 0).
		3399	*/
		3400	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		3401	{
		3402	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
		3403	}
		3404
		3405	/**
		3406	* @brief Enable capture/compare 1 interrupt (CC1IE).
		3407	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		3408	* @param TIMx Timer instance
		3409	* @retval None
		3410	*/
		3411	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		3412	{
		3413	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3414	}
		3415
		3416	/**
		3417	* @brief Disable capture/compare 1 interrupt (CC1IE).
		3418	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		3419	* @param TIMx Timer instance
		3420	* @retval None
		3421	*/
		3422	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		3423	{
		3424	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3425	}
		3426
		3427	/**
		3428	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		3429	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		3430	* @param TIMx Timer instance
		3431	* @retval State of bit (1 or 0).
		3432	*/
		3433	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		3434	{
		3435	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
		3436	}
		3437
		3438	/**
		3439	* @brief Enable capture/compare 2 interrupt (CC2IE).
		3440	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		3441	* @param TIMx Timer instance
		3442	* @retval None
		3443	*/
		3444	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		3445	{
		3446	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3447	}
		3448
		3449	/**
		3450	* @brief Disable capture/compare 2 interrupt (CC2IE).
		3451	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		3452	* @param TIMx Timer instance
		3453	* @retval None
		3454	*/
		3455	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		3456	{
		3457	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3458	}
		3459
		3460	/**
		3461	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		3462	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		3463	* @param TIMx Timer instance
		3464	* @retval State of bit (1 or 0).
		3465	*/
		3466	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		3467	{
		3468	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
		3469	}
		3470
		3471	/**
		3472	* @brief Enable capture/compare 3 interrupt (CC3IE).
		3473	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		3474	* @param TIMx Timer instance
		3475	* @retval None
		3476	*/
		3477	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		3478	{
		3479	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3480	}
		3481
		3482	/**
		3483	* @brief Disable capture/compare 3 interrupt (CC3IE).
		3484	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		3485	* @param TIMx Timer instance
		3486	* @retval None
		3487	*/
		3488	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		3489	{
		3490	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3491	}
		3492
		3493	/**
		3494	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		3495	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		3496	* @param TIMx Timer instance
		3497	* @retval State of bit (1 or 0).
		3498	*/
		3499	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		3500	{
		3501	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
		3502	}
		3503
		3504	/**
		3505	* @brief Enable capture/compare 4 interrupt (CC4IE).
		3506	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		3507	* @param TIMx Timer instance
		3508	* @retval None
		3509	*/
		3510	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		3511	{
		3512	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3513	}
		3514
		3515	/**
		3516	* @brief Disable capture/compare 4 interrupt (CC4IE).
		3517	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		3518	* @param TIMx Timer instance
		3519	* @retval None
		3520	*/
		3521	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		3522	{
		3523	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3524	}
		3525
		3526	/**
		3527	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		3528	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		3529	* @param TIMx Timer instance
		3530	* @retval State of bit (1 or 0).
		3531	*/
		3532	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		3533	{
		3534	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
		3535	}
		3536
		3537	/**
		3538	* @brief Enable commutation interrupt (COMIE).
		3539	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
		3540	* @param TIMx Timer instance
		3541	* @retval None
		3542	*/
		3543	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
		3544	{
		3545	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3546	}
		3547
		3548	/**
		3549	* @brief Disable commutation interrupt (COMIE).
		3550	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
		3551	* @param TIMx Timer instance
		3552	* @retval None
		3553	*/
		3554	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
		3555	{
		3556	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3557	}
		3558
		3559	/**
		3560	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
		3561	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
		3562	* @param TIMx Timer instance
		3563	* @retval State of bit (1 or 0).
		3564	*/
		3565	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
		3566	{
		3567	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
		3568	}
		3569
		3570	/**
		3571	* @brief Enable trigger interrupt (TIE).
		3572	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		3573	* @param TIMx Timer instance
		3574	* @retval None
		3575	*/
		3576	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		3577	{
		3578	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		3579	}
		3580
		3581	/**
		3582	* @brief Disable trigger interrupt (TIE).
		3583	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		3584	* @param TIMx Timer instance
		3585	* @retval None
		3586	*/
		3587	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		3588	{
		3589	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		3590	}
		3591
		3592	/**
		3593	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		3594	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		3595	* @param TIMx Timer instance
		3596	* @retval State of bit (1 or 0).
		3597	*/
		3598	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		3599	{
		3600	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
		3601	}
		3602
		3603	/**
		3604	* @brief Enable break interrupt (BIE).
		3605	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
		3606	* @param TIMx Timer instance
		3607	* @retval None
		3608	*/
		3609	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
		3610	{
		3611	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
		3612	}
		3613
		3614	/**
		3615	* @brief Disable break interrupt (BIE).
		3616	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
		3617	* @param TIMx Timer instance
		3618	* @retval None
		3619	*/
		3620	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
		3621	{
		3622	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
		3623	}
		3624
		3625	/**
		3626	* @brief Indicates whether the break interrupt (BIE) is enabled.
		3627	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
		3628	* @param TIMx Timer instance
		3629	* @retval State of bit (1 or 0).
		3630	*/
		3631	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
		3632	{
		3633	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
		3634	}
		3635
		3636	/**
		3637	* @}
		3638	*/
		3639
6	mjames	3640	/** @defgroup TIM_LL_EF_DMA_Management DMA Management
2	mjames	3641	* @{
		3642	*/
		3643	/**
		3644	* @brief Enable update DMA request (UDE).
		3645	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3646	* @param TIMx Timer instance
		3647	* @retval None
		3648	*/
		3649	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3650	{
		3651	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3652	}
		3653
		3654	/**
		3655	* @brief Disable update DMA request (UDE).
		3656	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3657	* @param TIMx Timer instance
		3658	* @retval None
		3659	*/
		3660	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3661	{
		3662	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3663	}
		3664
		3665	/**
		3666	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3667	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3668	* @param TIMx Timer instance
		3669	* @retval State of bit (1 or 0).
		3670	*/
		3671	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3672	{
		3673	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
		3674	}
		3675
		3676	/**
		3677	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3678	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3679	* @param TIMx Timer instance
		3680	* @retval None
		3681	*/
		3682	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3683	{
		3684	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3685	}
		3686
		3687	/**
		3688	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3689	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3690	* @param TIMx Timer instance
		3691	* @retval None
		3692	*/
		3693	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3694	{
		3695	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3696	}
		3697
		3698	/**
		3699	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3700	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3701	* @param TIMx Timer instance
		3702	* @retval State of bit (1 or 0).
		3703	*/
		3704	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3705	{
		3706	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
		3707	}
		3708
		3709	/**
		3710	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3711	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3712	* @param TIMx Timer instance
		3713	* @retval None
		3714	*/
		3715	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3716	{
		3717	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3718	}
		3719
		3720	/**
		3721	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3722	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3723	* @param TIMx Timer instance
		3724	* @retval None
		3725	*/
		3726	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3727	{
		3728	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3729	}
		3730
		3731	/**
		3732	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3733	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3734	* @param TIMx Timer instance
		3735	* @retval State of bit (1 or 0).
		3736	*/
		3737	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3738	{
		3739	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
		3740	}
		3741
		3742	/**
		3743	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3744	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3745	* @param TIMx Timer instance
		3746	* @retval None
		3747	*/
		3748	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3749	{
		3750	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3751	}
		3752
		3753	/**
		3754	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3755	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3756	* @param TIMx Timer instance
		3757	* @retval None
		3758	*/
		3759	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3760	{
		3761	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3762	}
		3763
		3764	/**
		3765	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3766	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3767	* @param TIMx Timer instance
		3768	* @retval State of bit (1 or 0).
		3769	*/
		3770	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3771	{
		3772	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
		3773	}
		3774
		3775	/**
		3776	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3777	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3778	* @param TIMx Timer instance
		3779	* @retval None
		3780	*/
		3781	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3782	{
		3783	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3784	}
		3785
		3786	/**
		3787	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3788	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3789	* @param TIMx Timer instance
		3790	* @retval None
		3791	*/
		3792	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3793	{
		3794	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3795	}
		3796
		3797	/**
		3798	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3799	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3800	* @param TIMx Timer instance
		3801	* @retval State of bit (1 or 0).
		3802	*/
		3803	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3804	{
		3805	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
		3806	}
		3807
		3808	/**
		3809	* @brief Enable commutation DMA request (COMDE).
		3810	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
		3811	* @param TIMx Timer instance
		3812	* @retval None
		3813	*/
		3814	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
		3815	{
		3816	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3817	}
		3818
		3819	/**
		3820	* @brief Disable commutation DMA request (COMDE).
		3821	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
		3822	* @param TIMx Timer instance
		3823	* @retval None
		3824	*/
		3825	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
		3826	{
		3827	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3828	}
		3829
		3830	/**
		3831	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
		3832	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
		3833	* @param TIMx Timer instance
		3834	* @retval State of bit (1 or 0).
		3835	*/
		3836	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
		3837	{
		3838	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
		3839	}
		3840
		3841	/**
		3842	* @brief Enable trigger interrupt (TDE).
		3843	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3844	* @param TIMx Timer instance
		3845	* @retval None
		3846	*/
		3847	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3848	{
		3849	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3850	}
		3851
		3852	/**
		3853	* @brief Disable trigger interrupt (TDE).
		3854	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3855	* @param TIMx Timer instance
		3856	* @retval None
		3857	*/
		3858	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3859	{
		3860	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3861	}
		3862
		3863	/**
		3864	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3865	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3866	* @param TIMx Timer instance
		3867	* @retval State of bit (1 or 0).
		3868	*/
		3869	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3870	{
		3871	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
		3872	}
		3873
		3874	/**
		3875	* @}
		3876	*/
		3877
		3878	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3879	* @{
		3880	*/
		3881	/**
		3882	* @brief Generate an update event.
		3883	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3884	* @param TIMx Timer instance
		3885	* @retval None
		3886	*/
		3887	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3888	{
		3889	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3890	}
		3891
		3892	/**
		3893	* @brief Generate Capture/Compare 1 event.
		3894	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3895	* @param TIMx Timer instance
		3896	* @retval None
		3897	*/
		3898	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3899	{
		3900	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3901	}
		3902
		3903	/**
		3904	* @brief Generate Capture/Compare 2 event.
		3905	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3906	* @param TIMx Timer instance
		3907	* @retval None
		3908	*/
		3909	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3910	{
		3911	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3912	}
		3913
		3914	/**
		3915	* @brief Generate Capture/Compare 3 event.
		3916	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3917	* @param TIMx Timer instance
		3918	* @retval None
		3919	*/
		3920	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3921	{
		3922	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3923	}
		3924
		3925	/**
		3926	* @brief Generate Capture/Compare 4 event.
		3927	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3928	* @param TIMx Timer instance
		3929	* @retval None
		3930	*/
		3931	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3932	{
		3933	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3934	}
		3935
		3936	/**
		3937	* @brief Generate commutation event.
		3938	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
		3939	* @param TIMx Timer instance
		3940	* @retval None
		3941	*/
		3942	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
		3943	{
		3944	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
		3945	}
		3946
		3947	/**
		3948	* @brief Generate trigger event.
		3949	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3950	* @param TIMx Timer instance
		3951	* @retval None
		3952	*/
		3953	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3954	{
		3955	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3956	}
		3957
		3958	/**
		3959	* @brief Generate break event.
		3960	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
		3961	* @param TIMx Timer instance
		3962	* @retval None
		3963	*/
		3964	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
		3965	{
		3966	SET_BIT(TIMx->EGR, TIM_EGR_BG);
		3967	}
		3968
		3969	/**
		3970	* @}
		3971	*/
		3972
		3973	#if defined(USE_FULL_LL_DRIVER)
		3974	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3975	* @{
		3976	*/
		3977
		3978	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3979	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3980	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3981	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3982	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3983	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3984	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3985	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3986	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3987	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
		3988	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
		3989	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
		3990	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
		3991	/**
		3992	* @}
		3993	*/
		3994	#endif /* USE_FULL_LL_DRIVER */
		3995
		3996	/**
		3997	* @}
		3998	*/
		3999
		4000	/**
		4001	* @}
		4002	*/
		4003
		4004	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
		4005
		4006	/**
		4007	* @}
		4008	*/
		4009
		4010	#ifdef __cplusplus
		4011	}
		4012	#endif
		4013
		4014	#endif /* __STM32F0xx_LL_TIM_H */
		4015	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h – Rev 6