WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32F0xx_LL_TIM_H
		22	#define __STM32F0xx_LL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f0xx.h"
		30
		31	/** @addtogroup STM32F0xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
		36
		37	/** @defgroup TIM_LL TIM
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
		44	* @{
		45	*/
		46	static const uint8_t OFFSET_TAB_CCMRx[] =
		47	{
		48	0x00U, /* 0: TIMx_CH1 */
		49	0x00U, /* 1: TIMx_CH1N */
		50	0x00U, /* 2: TIMx_CH2 */
		51	0x00U, /* 3: TIMx_CH2N */
		52	0x04U, /* 4: TIMx_CH3 */
		53	0x04U, /* 5: TIMx_CH3N */
		54	0x04U /* 6: TIMx_CH4 */
		55	};
		56
		57	static const uint8_t SHIFT_TAB_OCxx[] =
		58	{
		59	0U, /* 0: OC1M, OC1FE, OC1PE */
		60	0U, /* 1: - NA */
		61	8U, /* 2: OC2M, OC2FE, OC2PE */
		62	0U, /* 3: - NA */
		63	0U, /* 4: OC3M, OC3FE, OC3PE */
		64	0U, /* 5: - NA */
		65	8U /* 6: OC4M, OC4FE, OC4PE */
		66	};
		67
		68	static const uint8_t SHIFT_TAB_ICxx[] =
		69	{
		70	0U, /* 0: CC1S, IC1PSC, IC1F */
		71	0U, /* 1: - NA */
		72	8U, /* 2: CC2S, IC2PSC, IC2F */
		73	0U, /* 3: - NA */
		74	0U, /* 4: CC3S, IC3PSC, IC3F */
		75	0U, /* 5: - NA */
		76	8U /* 6: CC4S, IC4PSC, IC4F */
		77	};
		78
		79	static const uint8_t SHIFT_TAB_CCxP[] =
		80	{
		81	0U, /* 0: CC1P */
		82	2U, /* 1: CC1NP */
		83	4U, /* 2: CC2P */
		84	6U, /* 3: CC2NP */
		85	8U, /* 4: CC3P */
		86	10U, /* 5: CC3NP */
		87	12U /* 6: CC4P */
		88	};
		89
		90	static const uint8_t SHIFT_TAB_OISx[] =
		91	{
		92	0U, /* 0: OIS1 */
		93	1U, /* 1: OIS1N */
		94	2U, /* 2: OIS2 */
		95	3U, /* 3: OIS2N */
		96	4U, /* 4: OIS3 */
		97	5U, /* 5: OIS3N */
		98	6U /* 6: OIS4 */
		99	};
		100	/**
		101	* @}
		102	*/
		103
		104	/* Private constants ---------------------------------------------------------*/
		105	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
		106	* @{
		107	*/
		108
		109
		110	#define TIMx_OR_RMP_SHIFT 16U
		111	#define TIMx_OR_RMP_MASK 0x0000FFFFU
		112	#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
		113
		114	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
		115	#define DT_DELAY_1 ((uint8_t)0x7F)
		116	#define DT_DELAY_2 ((uint8_t)0x3F)
		117	#define DT_DELAY_3 ((uint8_t)0x1F)
		118	#define DT_DELAY_4 ((uint8_t)0x1F)
		119
		120	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
		121	#define DT_RANGE_1 ((uint8_t)0x00)
		122	#define DT_RANGE_2 ((uint8_t)0x80)
		123	#define DT_RANGE_3 ((uint8_t)0xC0)
		124	#define DT_RANGE_4 ((uint8_t)0xE0)
		125
		126
		127	/**
		128	* @}
		129	*/
		130
		131	/* Private macros ------------------------------------------------------------*/
		132	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
		133	* @{
		134	*/
		135	/** @brief Convert channel id into channel index.
		136	* @param __CHANNEL__ This parameter can be one of the following values:
		137	* @arg @ref LL_TIM_CHANNEL_CH1
		138	* @arg @ref LL_TIM_CHANNEL_CH1N
		139	* @arg @ref LL_TIM_CHANNEL_CH2
		140	* @arg @ref LL_TIM_CHANNEL_CH2N
		141	* @arg @ref LL_TIM_CHANNEL_CH3
		142	* @arg @ref LL_TIM_CHANNEL_CH3N
		143	* @arg @ref LL_TIM_CHANNEL_CH4
		144	* @retval none
		145	*/
		146	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
		147	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
		148	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
		149	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
		150	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
		151	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
		152	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
		153
		154	/** @brief Calculate the deadtime sampling period(in ps).
		155	* @param __TIMCLK__ timer input clock frequency (in Hz).
		156	* @param __CKD__ This parameter can be one of the following values:
		157	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		158	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		159	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		160	* @retval none
		161	*/
		162	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
		163	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
		164	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
		165	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
		166	/**
		167	* @}
		168	*/
		169
		170
		171	/* Exported types ------------------------------------------------------------*/
		172	#if defined(USE_FULL_LL_DRIVER)
		173	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
		174	* @{
		175	*/
		176
		177	/**
		178	* @brief TIM Time Base configuration structure definition.
		179	*/
		180	typedef struct
		181	{
		182	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		183	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		184
		185	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
		186
		187	uint32_t CounterMode; /*!< Specifies the counter mode.
		188	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
		189
		190	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
		191
		192	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
		193	Auto-Reload Register at the next update event.
		194	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		195	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
		196
		197	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
		198
		199	uint32_t ClockDivision; /*!< Specifies the clock division.
		200	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
		201
		202	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
		203
		204	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		205	reaches zero, an update event is generated and counting restarts
		206	from the RCR value (N).
		207	This means in PWM mode that (N+1) corresponds to:
		208	- the number of PWM periods in edge-aligned mode
		209	- the number of half PWM period in center-aligned mode
		210	This parameter must be a number between 0x00 and 0xFF.
		211
		212	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
		213	} LL_TIM_InitTypeDef;
		214
		215	/**
		216	* @brief TIM Output Compare configuration structure definition.
		217	*/
		218	typedef struct
		219	{
		220	uint32_t OCMode; /*!< Specifies the output mode.
		221	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
		222
		223	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
		224
		225	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
		226	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		227
		228	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		229
		230	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
		231	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
		232
		233	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
		234
		235	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
		236	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
		237
		238	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
		239
		240	uint32_t OCPolarity; /*!< Specifies the output polarity.
		241	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		242
		243	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		244
		245	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		246	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
		247
		248	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
		249
		250
		251	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		252	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		253
		254	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
		255
		256	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		257	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
		258
		259	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
		260	} LL_TIM_OC_InitTypeDef;
		261
		262	/**
		263	* @brief TIM Input Capture configuration structure definition.
		264	*/
		265
		266	typedef struct
		267	{
		268
		269	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		270	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		271
		272	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		273
		274	uint32_t ICActiveInput; /*!< Specifies the input.
		275	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		276
		277	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		278
		279	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		280	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		281
		282	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		283
		284	uint32_t ICFilter; /*!< Specifies the input capture filter.
		285	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		286
		287	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		288	} LL_TIM_IC_InitTypeDef;
		289
		290
		291	/**
		292	* @brief TIM Encoder interface configuration structure definition.
		293	*/
		294	typedef struct
		295	{
		296	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
		297	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
		298
		299	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
		300
		301	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		302	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		303
		304	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		305
		306	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
		307	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		308
		309	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		310
		311	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		312	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		313
		314	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		315
		316	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		317	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		318
		319	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		320
		321	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
		322	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		323
		324	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		325
		326	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
		327	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
		328
		329	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
		330
		331	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
		332	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		333
		334	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		335
		336	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
		337	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		338
		339	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		340
		341	} LL_TIM_ENCODER_InitTypeDef;
		342
		343	/**
		344	* @brief TIM Hall sensor interface configuration structure definition.
		345	*/
		346	typedef struct
		347	{
		348
		349	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
		350	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
		351
		352	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
		353
		354	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
		355	Prescaler must be set to get a maximum counter period longer than the
		356	time interval between 2 consecutive changes on the Hall inputs.
		357	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
		358
		359	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
		360
		361	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
		362	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
		363
		364	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
		365
		366	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
		367	A positive pulse (TRGO event) is generated with a programmable delay every time
		368	a change occurs on the Hall inputs.
		369	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
		370
		371	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
		372	} LL_TIM_HALLSENSOR_InitTypeDef;
		373
		374	/**
		375	* @brief BDTR (Break and Dead Time) structure definition
		376	*/
		377	typedef struct
		378	{
		379	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
		380	This parameter can be a value of @ref TIM_LL_EC_OSSR
		381
		382	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
		383
		384	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
		385
		386	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
		387	This parameter can be a value of @ref TIM_LL_EC_OSSI
		388
		389	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
		390
		391	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
		392
		393	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
		394	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
		395
		396	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
		397	has been written, their content is frozen until the next reset.*/
		398
		399	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
		400	switching-on of the outputs.
		401	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		402
		403	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
		404
		405	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
		406
		407	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
		408	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
		409
		410	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
		411
		412	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		413
		414	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
		415	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
		416
		417	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
		418
		419	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		420
		421	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
		422	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
		423
		424	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
		425
		426	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
		427	} LL_TIM_BDTR_InitTypeDef;
		428
		429	/**
		430	* @}
		431	*/
		432	#endif /* USE_FULL_LL_DRIVER */
		433
		434	/* Exported constants --------------------------------------------------------*/
		435	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
		436	* @{
		437	*/
		438
		439	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
		440	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
		441	* @{
		442	*/
		443	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
		444	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
		445	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
		446	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
		447	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
		448	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
		449	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
		450	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
		451	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
		452	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
		453	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
		454	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
		455	/**
		456	* @}
		457	*/
		458
		459	#if defined(USE_FULL_LL_DRIVER)
		460	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
		461	* @{
		462	*/
		463	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
		464	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
		465	/**
		466	* @}
		467	*/
		468
		469	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
		470	* @{
		471	*/
		472	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		473	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
		474	/**
		475	* @}
		476	*/
		477	#endif /* USE_FULL_LL_DRIVER */
		478
		479	/** @defgroup TIM_LL_EC_IT IT Defines
		480	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
		481	* @{
		482	*/
		483	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
		484	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
		485	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
		486	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
		487	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
		488	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
		489	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
		490	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
		491	/**
		492	* @}
		493	*/
		494
		495	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
		496	* @{
		497	*/
		498	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
		499	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
		500	/**
		501	* @}
		502	*/
		503
		504	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
		505	* @{
		506	*/
		507	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
		508	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
		509	/**
		510	* @}
		511	*/
		512
		513	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
		514	* @{
		515	*/
		516	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
		517	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
		518	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
		519	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
		520	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
		521	/**
		522	* @}
		523	*/
		524
		525	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
		526	* @{
		527	*/
		528	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
		529	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
		530	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
		531	/**
		532	* @}
		533	*/
		534
		535	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
		536	* @{
		537	*/
		538	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
		539	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
		540	/**
		541	* @}
		542	*/
		543
		544	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
		545	* @{
		546	*/
		547	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
		548	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
		549	/**
		550	* @}
		551	*/
		552
		553	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
		554	* @{
		555	*/
		556	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
		557	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
		558	/**
		559	* @}
		560	*/
		561
		562	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
		563	* @{
		564	*/
		565	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
		566	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		567	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		568	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		569	/**
		570	* @}
		571	*/
		572
		573	/** @defgroup TIM_LL_EC_CHANNEL Channel
		574	* @{
		575	*/
		576	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
		577	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
		578	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
		579	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
		580	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
		581	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
		582	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
		583	/**
		584	* @}
		585	*/
		586
		587	#if defined(USE_FULL_LL_DRIVER)
		588	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
		589	* @{
		590	*/
		591	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
		592	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
		593	/**
		594	* @}
		595	*/
		596	#endif /* USE_FULL_LL_DRIVER */
		597
		598	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
		599	* @{
		600	*/
		601	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
		602	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
		603	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
		604	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
		605	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
		606	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
		607	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
		608	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
		609	/**
		610	* @}
		611	*/
		612
		613	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
		614	* @{
		615	*/
		616	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
		617	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
		618	/**
		619	* @}
		620	*/
		621
		622	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
		623	* @{
		624	*/
		625	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
		626	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
		627	/**
		628	* @}
		629	*/
		630
		631
		632	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
		633	* @{
		634	*/
		635	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
		636	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
		637	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
		638	/**
		639	* @}
		640	*/
		641
		642	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
		643	* @{
		644	*/
		645	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
		646	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
		647	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
		648	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
		649	/**
		650	* @}
		651	*/
		652
		653	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
		654	* @{
		655	*/
		656	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		657	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
		658	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
		659	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
		660	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
		661	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
		662	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
		663	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
		664	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
		665	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
		666	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
		667	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
		668	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
		669	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
		670	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
		671	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
		672	/**
		673	* @}
		674	*/
		675
		676	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
		677	* @{
		678	*/
		679	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
		680	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
		681	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
		682	/**
		683	* @}
		684	*/
		685
		686	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
		687	* @{
		688	*/
		689	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
		690	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
		691	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
		692	/**
		693	* @}
		694	*/
		695
		696	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
		697	* @{
		698	*/
		699	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
		700	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
		701	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
		702	/**
		703	* @}
		704	*/
		705
		706	/** @defgroup TIM_LL_EC_TRGO Trigger Output
		707	* @{
		708	*/
		709	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
		710	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
		711	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
		712	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
		713	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
		714	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
		715	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
		716	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
		717	/**
		718	* @}
		719	*/
		720
		721
		722	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
		723	* @{
		724	*/
		725	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
		726	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
		727	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
		728	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
		729	/**
		730	* @}
		731	*/
		732
		733	/** @defgroup TIM_LL_EC_TS Trigger Selection
		734	* @{
		735	*/
		736	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
		737	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
		738	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
		739	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
		740	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
		741	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
		742	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
		743	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
		744	/**
		745	* @}
		746	*/
		747
		748	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
		749	* @{
		750	*/
		751	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
		752	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
		753	/**
		754	* @}
		755	*/
		756
		757	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
		758	* @{
		759	*/
		760	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
		761	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
		762	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
		763	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
		764	/**
		765	* @}
		766	*/
		767
		768	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
		769	* @{
		770	*/
		771	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
		772	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
		773	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
		774	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
		775	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
		776	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
		777	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
		778	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
		779	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
		780	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
		781	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
		782	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
		783	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
		784	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
		785	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
		786	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
		787	/**
		788	* @}
		789	*/
		790
		791
		792	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
		793	* @{
		794	*/
		795	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		796	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		797	/**
		798	* @}
		799	*/
		800
		801
		802
		803
		804	/** @defgroup TIM_LL_EC_OSSI OSSI
		805	* @{
		806	*/
		807	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		808	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
		809	/**
		810	* @}
		811	*/
		812
		813	/** @defgroup TIM_LL_EC_OSSR OSSR
		814	* @{
		815	*/
		816	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
		817	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
		818	/**
		819	* @}
		820	*/
		821
		822
		823	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
		824	* @{
		825	*/
		826	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
		827	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
		828	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
		829	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
		830	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
		831	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
		832	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
		833	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
		834	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
		835	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
		836	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
		837	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
		838	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
		839	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
		840	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
		841	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
		842	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
		843	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
		844	/**
		845	* @}
		846	*/
		847
		848	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
		849	* @{
		850	*/
		851	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
		852	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
		853	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
		854	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
		855	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
		856	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
		857	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
		858	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
		859	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
		860	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
		861	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
		862	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
		863	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
		864	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
		865	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
		866	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
		867	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
		868	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
		869	/**
		870	* @}
		871	*/
		872
		873
		874	#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /!< TIM14_TI1 is connected to Ored GPIO /
		875	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC clock /
		876	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 clock /
		877	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
		878
		879
		880	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
		881	* @{
		882	*/
		883	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
		884	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
		885	/**
		886	* @}
		887	*/
		888
		889	/**
		890	* @}
		891	*/
		892
		893	/* Exported macro ------------------------------------------------------------*/
		894	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
		895	* @{
		896	*/
		897
		898	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
		899	* @{
		900	*/
		901	/**
		902	* @brief Write a value in TIM register.
		903	* @param __INSTANCE__ TIM Instance
		904	* @param __REG__ Register to be written
		905	* @param __VALUE__ Value to be written in the register
		906	* @retval None
		907	*/
		908	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
		909
		910	/**
		911	* @brief Read a value in TIM register.
		912	* @param __INSTANCE__ TIM Instance
		913	* @param __REG__ Register to be read
		914	* @retval Register value
		915	*/
		916	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
		917	/**
		918	* @}
		919	*/
		920
		921	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
		922	* @{
		923	*/
		924
		925	/**
		926	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
		927	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
		928	* @param __TIMCLK__ timer input clock frequency (in Hz)
		929	* @param __CKD__ This parameter can be one of the following values:
		930	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		931	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		932	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		933	* @param __DT__ deadtime duration (in ns)
		934	* @retval DTG[0:7]
		935	*/
		936	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
		937	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
		938	(((uint64_t)((__DT__)1000U)) < ((64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
		939	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
		940	(((uint64_t)((__DT__)1000U)) < ((32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
		941	0U)
		942
		943	/**
		944	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
		945	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
		946	* @param __TIMCLK__ timer input clock frequency (in Hz)
		947	* @param __CNTCLK__ counter clock frequency (in Hz)
		948	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
		949	*/
		950	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
		951	(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
		952
		953	/**
		954	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
		955	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
		956	* @param __TIMCLK__ timer input clock frequency (in Hz)
		957	* @param __PSC__ prescaler
		958	* @param __FREQ__ output signal frequency (in Hz)
		959	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		960	*/
		961	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
		962	((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
		963
		964	/**
		965	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
		966	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
		967	* @param __TIMCLK__ timer input clock frequency (in Hz)
		968	* @param __PSC__ prescaler
		969	* @param __DELAY__ timer output compare active/inactive delay (in us)
		970	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
		971	*/
		972	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
		973	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
		974	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
		975
		976	/**
		977	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
		978	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
		979	* @param __TIMCLK__ timer input clock frequency (in Hz)
		980	* @param __PSC__ prescaler
		981	* @param __DELAY__ timer output compare active/inactive delay (in us)
		982	* @param __PULSE__ pulse duration (in us)
		983	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
		984	*/
		985	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
		986	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
		987	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
		988
		989	/**
		990	* @brief HELPER macro retrieving the ratio of the input capture prescaler
		991	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
		992	* @param __ICPSC__ This parameter can be one of the following values:
		993	* @arg @ref LL_TIM_ICPSC_DIV1
		994	* @arg @ref LL_TIM_ICPSC_DIV2
		995	* @arg @ref LL_TIM_ICPSC_DIV4
		996	* @arg @ref LL_TIM_ICPSC_DIV8
		997	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
		998	*/
		999	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
		1000	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
		1001
		1002
		1003	/**
		1004	* @}
		1005	*/
		1006
		1007
		1008	/**
		1009	* @}
		1010	*/
		1011
		1012	/* Exported functions --------------------------------------------------------*/
		1013	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
		1014	* @{
		1015	*/
		1016
		1017	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
		1018	* @{
		1019	*/
		1020	/**
		1021	* @brief Enable timer counter.
		1022	* @rmtoll CR1 CEN LL_TIM_EnableCounter
		1023	* @param TIMx Timer instance
		1024	* @retval None
		1025	*/
		1026	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
		1027	{
		1028	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
		1029	}
		1030
		1031	/**
		1032	* @brief Disable timer counter.
		1033	* @rmtoll CR1 CEN LL_TIM_DisableCounter
		1034	* @param TIMx Timer instance
		1035	* @retval None
		1036	*/
		1037	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
		1038	{
		1039	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
		1040	}
		1041
		1042	/**
		1043	* @brief Indicates whether the timer counter is enabled.
		1044	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
		1045	* @param TIMx Timer instance
		1046	* @retval State of bit (1 or 0).
		1047	*/
		1048	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
		1049	{
		1050	return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
		1051	}
		1052
		1053	/**
		1054	* @brief Enable update event generation.
		1055	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
		1056	* @param TIMx Timer instance
		1057	* @retval None
		1058	*/
		1059	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
		1060	{
		1061	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1062	}
		1063
		1064	/**
		1065	* @brief Disable update event generation.
		1066	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
		1067	* @param TIMx Timer instance
		1068	* @retval None
		1069	*/
		1070	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
		1071	{
		1072	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
		1073	}
		1074
		1075	/**
		1076	* @brief Indicates whether update event generation is enabled.
		1077	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
		1078	* @param TIMx Timer instance
		1079	* @retval Inverted state of bit (0 or 1).
		1080	*/
		1081	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
		1082	{
		1083	return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
		1084	}
		1085
		1086	/**
		1087	* @brief Set update event source
		1088	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
		1089	* generate an update interrupt or DMA request if enabled:
		1090	* - Counter overflow/underflow
		1091	* - Setting the UG bit
		1092	* - Update generation through the slave mode controller
		1093	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
		1094	* overflow/underflow generates an update interrupt or DMA request if enabled.
		1095	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
		1096	* @param TIMx Timer instance
		1097	* @param UpdateSource This parameter can be one of the following values:
		1098	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1099	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1100	* @retval None
		1101	*/
		1102	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
		1103	{
		1104	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
		1105	}
		1106
		1107	/**
		1108	* @brief Get actual event update source
		1109	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
		1110	* @param TIMx Timer instance
		1111	* @retval Returned value can be one of the following values:
		1112	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
		1113	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
		1114	*/
		1115	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
		1116	{
		1117	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
		1118	}
		1119
		1120	/**
		1121	* @brief Set one pulse mode (one shot v.s. repetitive).
		1122	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
		1123	* @param TIMx Timer instance
		1124	* @param OnePulseMode This parameter can be one of the following values:
		1125	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1126	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1127	* @retval None
		1128	*/
		1129	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
		1130	{
		1131	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
		1132	}
		1133
		1134	/**
		1135	* @brief Get actual one pulse mode.
		1136	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
		1137	* @param TIMx Timer instance
		1138	* @retval Returned value can be one of the following values:
		1139	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
		1140	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
		1141	*/
		1142	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
		1143	{
		1144	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
		1145	}
		1146
		1147	/**
		1148	* @brief Set the timer counter counting mode.
		1149	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1150	* check whether or not the counter mode selection feature is supported
		1151	* by a timer instance.
		1152	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
		1153	* requires a timer reset to avoid unexpected direction
		1154	* due to DIR bit readonly in center aligned mode.
		1155	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
		1156	* CR1 CMS LL_TIM_SetCounterMode
		1157	* @param TIMx Timer instance
		1158	* @param CounterMode This parameter can be one of the following values:
		1159	* @arg @ref LL_TIM_COUNTERMODE_UP
		1160	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1161	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1162	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1163	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1164	* @retval None
		1165	*/
		1166	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
		1167	{
		1168	MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR \| TIM_CR1_CMS), CounterMode);
		1169	}
		1170
		1171	/**
		1172	* @brief Get actual counter mode.
		1173	* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
		1174	* check whether or not the counter mode selection feature is supported
		1175	* by a timer instance.
		1176	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
		1177	* CR1 CMS LL_TIM_GetCounterMode
		1178	* @param TIMx Timer instance
		1179	* @retval Returned value can be one of the following values:
		1180	* @arg @ref LL_TIM_COUNTERMODE_UP
		1181	* @arg @ref LL_TIM_COUNTERMODE_DOWN
		1182	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
		1183	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
		1184	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
		1185	*/
		1186	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
		1187	{
		1188	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
		1189	}
		1190
		1191	/**
		1192	* @brief Enable auto-reload (ARR) preload.
		1193	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
		1194	* @param TIMx Timer instance
		1195	* @retval None
		1196	*/
		1197	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
		1198	{
		1199	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1200	}
		1201
		1202	/**
		1203	* @brief Disable auto-reload (ARR) preload.
		1204	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
		1205	* @param TIMx Timer instance
		1206	* @retval None
		1207	*/
		1208	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
		1209	{
		1210	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
		1211	}
		1212
		1213	/**
		1214	* @brief Indicates whether auto-reload (ARR) preload is enabled.
		1215	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
		1216	* @param TIMx Timer instance
		1217	* @retval State of bit (1 or 0).
		1218	*/
		1219	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
		1220	{
		1221	return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
		1222	}
		1223
		1224	/**
		1225	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
		1226	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1227	* whether or not the clock division feature is supported by the timer
		1228	* instance.
		1229	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
		1230	* @param TIMx Timer instance
		1231	* @param ClockDivision This parameter can be one of the following values:
		1232	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1233	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1234	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1235	* @retval None
		1236	*/
		1237	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
		1238	{
		1239	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
		1240	}
		1241
		1242	/**
		1243	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
		1244	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
		1245	* whether or not the clock division feature is supported by the timer
		1246	* instance.
		1247	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
		1248	* @param TIMx Timer instance
		1249	* @retval Returned value can be one of the following values:
		1250	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
		1251	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
		1252	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
		1253	*/
		1254	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
		1255	{
		1256	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
		1257	}
		1258
		1259	/**
		1260	* @brief Set the counter value.
		1261	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1262	* whether or not a timer instance supports a 32 bits counter.
		1263	* @rmtoll CNT CNT LL_TIM_SetCounter
		1264	* @param TIMx Timer instance
		1265	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1266	* @retval None
		1267	*/
		1268	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
		1269	{
		1270	WRITE_REG(TIMx->CNT, Counter);
		1271	}
		1272
		1273	/**
		1274	* @brief Get the counter value.
		1275	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1276	* whether or not a timer instance supports a 32 bits counter.
		1277	* @rmtoll CNT CNT LL_TIM_GetCounter
		1278	* @param TIMx Timer instance
		1279	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
		1280	*/
		1281	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
		1282	{
		1283	return (uint32_t)(READ_REG(TIMx->CNT));
		1284	}
		1285
		1286	/**
		1287	* @brief Get the current direction of the counter
		1288	* @rmtoll CR1 DIR LL_TIM_GetDirection
		1289	* @param TIMx Timer instance
		1290	* @retval Returned value can be one of the following values:
		1291	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
		1292	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
		1293	*/
		1294	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
		1295	{
		1296	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
		1297	}
		1298
		1299	/**
		1300	* @brief Set the prescaler value.
		1301	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
		1302	* @note The prescaler can be changed on the fly as this control register is buffered. The new
		1303	* prescaler ratio is taken into account at the next update event.
		1304	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
		1305	* @rmtoll PSC PSC LL_TIM_SetPrescaler
		1306	* @param TIMx Timer instance
		1307	* @param Prescaler between Min_Data=0 and Max_Data=65535
		1308	* @retval None
		1309	*/
		1310	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
		1311	{
		1312	WRITE_REG(TIMx->PSC, Prescaler);
		1313	}
		1314
		1315	/**
		1316	* @brief Get the prescaler value.
		1317	* @rmtoll PSC PSC LL_TIM_GetPrescaler
		1318	* @param TIMx Timer instance
		1319	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
		1320	*/
		1321	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
		1322	{
		1323	return (uint32_t)(READ_REG(TIMx->PSC));
		1324	}
		1325
		1326	/**
		1327	* @brief Set the auto-reload value.
		1328	* @note The counter is blocked while the auto-reload value is null.
		1329	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1330	* whether or not a timer instance supports a 32 bits counter.
		1331	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
		1332	* @rmtoll ARR ARR LL_TIM_SetAutoReload
		1333	* @param TIMx Timer instance
		1334	* @param AutoReload between Min_Data=0 and Max_Data=65535
		1335	* @retval None
		1336	*/
		1337	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
		1338	{
		1339	WRITE_REG(TIMx->ARR, AutoReload);
		1340	}
		1341
		1342	/**
		1343	* @brief Get the auto-reload value.
		1344	* @rmtoll ARR ARR LL_TIM_GetAutoReload
		1345	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1346	* whether or not a timer instance supports a 32 bits counter.
		1347	* @param TIMx Timer instance
		1348	* @retval Auto-reload value
		1349	*/
		1350	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
		1351	{
		1352	return (uint32_t)(READ_REG(TIMx->ARR));
		1353	}
		1354
		1355	/**
		1356	* @brief Set the repetition counter value.
		1357	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1358	* whether or not a timer instance supports a repetition counter.
		1359	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
		1360	* @param TIMx Timer instance
		1361	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
		1362	* @retval None
		1363	*/
		1364	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
		1365	{
		1366	WRITE_REG(TIMx->RCR, RepetitionCounter);
		1367	}
		1368
		1369	/**
		1370	* @brief Get the repetition counter value.
		1371	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
		1372	* whether or not a timer instance supports a repetition counter.
		1373	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
		1374	* @param TIMx Timer instance
		1375	* @retval Repetition counter value
		1376	*/
		1377	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
		1378	{
		1379	return (uint32_t)(READ_REG(TIMx->RCR));
		1380	}
		1381
		1382	/**
		1383	* @}
		1384	*/
		1385
		1386	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
		1387	* @{
		1388	*/
		1389	/**
		1390	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1391	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
		1392	* they are updated only when a commutation event (COM) occurs.
		1393	* @note Only on channels that have a complementary output.
		1394	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1395	* whether or not a timer instance is able to generate a commutation event.
		1396	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
		1397	* @param TIMx Timer instance
		1398	* @retval None
		1399	*/
		1400	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
		1401	{
		1402	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1403	}
		1404
		1405	/**
		1406	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
		1407	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1408	* whether or not a timer instance is able to generate a commutation event.
		1409	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
		1410	* @param TIMx Timer instance
		1411	* @retval None
		1412	*/
		1413	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
		1414	{
		1415	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
		1416	}
		1417
		1418	/**
		1419	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
		1420	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
		1421	* whether or not a timer instance is able to generate a commutation event.
		1422	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
		1423	* @param TIMx Timer instance
		1424	* @param CCUpdateSource This parameter can be one of the following values:
		1425	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
		1426	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
		1427	* @retval None
		1428	*/
		1429	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
		1430	{
		1431	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
		1432	}
		1433
		1434	/**
		1435	* @brief Set the trigger of the capture/compare DMA request.
		1436	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
		1437	* @param TIMx Timer instance
		1438	* @param DMAReqTrigger This parameter can be one of the following values:
		1439	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1440	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1441	* @retval None
		1442	*/
		1443	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
		1444	{
		1445	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
		1446	}
		1447
		1448	/**
		1449	* @brief Get actual trigger of the capture/compare DMA request.
		1450	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
		1451	* @param TIMx Timer instance
		1452	* @retval Returned value can be one of the following values:
		1453	* @arg @ref LL_TIM_CCDMAREQUEST_CC
		1454	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
		1455	*/
		1456	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
		1457	{
		1458	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
		1459	}
		1460
		1461	/**
		1462	* @brief Set the lock level to freeze the
		1463	* configuration of several capture/compare parameters.
		1464	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		1465	* the lock mechanism is supported by a timer instance.
		1466	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
		1467	* @param TIMx Timer instance
		1468	* @param LockLevel This parameter can be one of the following values:
		1469	* @arg @ref LL_TIM_LOCKLEVEL_OFF
		1470	* @arg @ref LL_TIM_LOCKLEVEL_1
		1471	* @arg @ref LL_TIM_LOCKLEVEL_2
		1472	* @arg @ref LL_TIM_LOCKLEVEL_3
		1473	* @retval None
		1474	*/
		1475	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
		1476	{
		1477	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
		1478	}
		1479
		1480	/**
		1481	* @brief Enable capture/compare channels.
		1482	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
		1483	* CCER CC1NE LL_TIM_CC_EnableChannel\n
		1484	* CCER CC2E LL_TIM_CC_EnableChannel\n
		1485	* CCER CC2NE LL_TIM_CC_EnableChannel\n
		1486	* CCER CC3E LL_TIM_CC_EnableChannel\n
		1487	* CCER CC3NE LL_TIM_CC_EnableChannel\n
		1488	* CCER CC4E LL_TIM_CC_EnableChannel
		1489	* @param TIMx Timer instance
		1490	* @param Channels This parameter can be a combination of the following values:
		1491	* @arg @ref LL_TIM_CHANNEL_CH1
		1492	* @arg @ref LL_TIM_CHANNEL_CH1N
		1493	* @arg @ref LL_TIM_CHANNEL_CH2
		1494	* @arg @ref LL_TIM_CHANNEL_CH2N
		1495	* @arg @ref LL_TIM_CHANNEL_CH3
		1496	* @arg @ref LL_TIM_CHANNEL_CH3N
		1497	* @arg @ref LL_TIM_CHANNEL_CH4
		1498	* @retval None
		1499	*/
		1500	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1501	{
		1502	SET_BIT(TIMx->CCER, Channels);
		1503	}
		1504
		1505	/**
		1506	* @brief Disable capture/compare channels.
		1507	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
		1508	* CCER CC1NE LL_TIM_CC_DisableChannel\n
		1509	* CCER CC2E LL_TIM_CC_DisableChannel\n
		1510	* CCER CC2NE LL_TIM_CC_DisableChannel\n
		1511	* CCER CC3E LL_TIM_CC_DisableChannel\n
		1512	* CCER CC3NE LL_TIM_CC_DisableChannel\n
		1513	* CCER CC4E LL_TIM_CC_DisableChannel
		1514	* @param TIMx Timer instance
		1515	* @param Channels This parameter can be a combination of the following values:
		1516	* @arg @ref LL_TIM_CHANNEL_CH1
		1517	* @arg @ref LL_TIM_CHANNEL_CH1N
		1518	* @arg @ref LL_TIM_CHANNEL_CH2
		1519	* @arg @ref LL_TIM_CHANNEL_CH2N
		1520	* @arg @ref LL_TIM_CHANNEL_CH3
		1521	* @arg @ref LL_TIM_CHANNEL_CH3N
		1522	* @arg @ref LL_TIM_CHANNEL_CH4
		1523	* @retval None
		1524	*/
		1525	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1526	{
		1527	CLEAR_BIT(TIMx->CCER, Channels);
		1528	}
		1529
		1530	/**
		1531	* @brief Indicate whether channel(s) is(are) enabled.
		1532	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
		1533	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
		1534	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
		1535	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
		1536	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
		1537	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
		1538	* CCER CC4E LL_TIM_CC_IsEnabledChannel
		1539	* @param TIMx Timer instance
		1540	* @param Channels This parameter can be a combination of the following values:
		1541	* @arg @ref LL_TIM_CHANNEL_CH1
		1542	* @arg @ref LL_TIM_CHANNEL_CH1N
		1543	* @arg @ref LL_TIM_CHANNEL_CH2
		1544	* @arg @ref LL_TIM_CHANNEL_CH2N
		1545	* @arg @ref LL_TIM_CHANNEL_CH3
		1546	* @arg @ref LL_TIM_CHANNEL_CH3N
		1547	* @arg @ref LL_TIM_CHANNEL_CH4
		1548	* @retval State of bit (1 or 0).
		1549	*/
		1550	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
		1551	{
		1552	return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
		1553	}
		1554
		1555	/**
		1556	* @}
		1557	*/
		1558
		1559	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
		1560	* @{
		1561	*/
		1562	/**
		1563	* @brief Configure an output channel.
		1564	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
		1565	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
		1566	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
		1567	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
		1568	* CCER CC1P LL_TIM_OC_ConfigOutput\n
		1569	* CCER CC2P LL_TIM_OC_ConfigOutput\n
		1570	* CCER CC3P LL_TIM_OC_ConfigOutput\n
		1571	* CCER CC4P LL_TIM_OC_ConfigOutput\n
		1572	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
		1573	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
		1574	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
		1575	* CR2 OIS4 LL_TIM_OC_ConfigOutput
		1576	* @param TIMx Timer instance
		1577	* @param Channel This parameter can be one of the following values:
		1578	* @arg @ref LL_TIM_CHANNEL_CH1
		1579	* @arg @ref LL_TIM_CHANNEL_CH2
		1580	* @arg @ref LL_TIM_CHANNEL_CH3
		1581	* @arg @ref LL_TIM_CHANNEL_CH4
		1582	* @param Configuration This parameter must be a combination of all the following values:
		1583	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
		1584	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
		1585	* @retval None
		1586	*/
		1587	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		1588	{
		1589	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1590	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1591	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
		1592	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
		1593	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
		1594	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
		1595	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
		1596	}
		1597
		1598	/**
		1599	* @brief Define the behavior of the output reference signal OCxREF from which
		1600	* OCx and OCxN (when relevant) are derived.
		1601	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
		1602	* CCMR1 OC2M LL_TIM_OC_SetMode\n
		1603	* CCMR2 OC3M LL_TIM_OC_SetMode\n
		1604	* CCMR2 OC4M LL_TIM_OC_SetMode
		1605	* @param TIMx Timer instance
		1606	* @param Channel This parameter can be one of the following values:
		1607	* @arg @ref LL_TIM_CHANNEL_CH1
		1608	* @arg @ref LL_TIM_CHANNEL_CH2
		1609	* @arg @ref LL_TIM_CHANNEL_CH3
		1610	* @arg @ref LL_TIM_CHANNEL_CH4
		1611	* @param Mode This parameter can be one of the following values:
		1612	* @arg @ref LL_TIM_OCMODE_FROZEN
		1613	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1614	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1615	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1616	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1617	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1618	* @arg @ref LL_TIM_OCMODE_PWM1
		1619	* @arg @ref LL_TIM_OCMODE_PWM2
		1620	* @retval None
		1621	*/
		1622	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
		1623	{
		1624	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1625	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1626	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
		1627	}
		1628
		1629	/**
		1630	* @brief Get the output compare mode of an output channel.
		1631	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
		1632	* CCMR1 OC2M LL_TIM_OC_GetMode\n
		1633	* CCMR2 OC3M LL_TIM_OC_GetMode\n
		1634	* CCMR2 OC4M LL_TIM_OC_GetMode
		1635	* @param TIMx Timer instance
		1636	* @param Channel This parameter can be one of the following values:
		1637	* @arg @ref LL_TIM_CHANNEL_CH1
		1638	* @arg @ref LL_TIM_CHANNEL_CH2
		1639	* @arg @ref LL_TIM_CHANNEL_CH3
		1640	* @arg @ref LL_TIM_CHANNEL_CH4
		1641	* @retval Returned value can be one of the following values:
		1642	* @arg @ref LL_TIM_OCMODE_FROZEN
		1643	* @arg @ref LL_TIM_OCMODE_ACTIVE
		1644	* @arg @ref LL_TIM_OCMODE_INACTIVE
		1645	* @arg @ref LL_TIM_OCMODE_TOGGLE
		1646	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
		1647	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
		1648	* @arg @ref LL_TIM_OCMODE_PWM1
		1649	* @arg @ref LL_TIM_OCMODE_PWM2
		1650	*/
		1651	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
		1652	{
		1653	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1654	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1655	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
		1656	}
		1657
		1658	/**
		1659	* @brief Set the polarity of an output channel.
		1660	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
		1661	* CCER CC1NP LL_TIM_OC_SetPolarity\n
		1662	* CCER CC2P LL_TIM_OC_SetPolarity\n
		1663	* CCER CC2NP LL_TIM_OC_SetPolarity\n
		1664	* CCER CC3P LL_TIM_OC_SetPolarity\n
		1665	* CCER CC3NP LL_TIM_OC_SetPolarity\n
		1666	* CCER CC4P LL_TIM_OC_SetPolarity
		1667	* @param TIMx Timer instance
		1668	* @param Channel This parameter can be one of the following values:
		1669	* @arg @ref LL_TIM_CHANNEL_CH1
		1670	* @arg @ref LL_TIM_CHANNEL_CH1N
		1671	* @arg @ref LL_TIM_CHANNEL_CH2
		1672	* @arg @ref LL_TIM_CHANNEL_CH2N
		1673	* @arg @ref LL_TIM_CHANNEL_CH3
		1674	* @arg @ref LL_TIM_CHANNEL_CH3N
		1675	* @arg @ref LL_TIM_CHANNEL_CH4
		1676	* @param Polarity This parameter can be one of the following values:
		1677	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1678	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1679	* @retval None
		1680	*/
		1681	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
		1682	{
		1683	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1684	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
		1685	}
		1686
		1687	/**
		1688	* @brief Get the polarity of an output channel.
		1689	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
		1690	* CCER CC1NP LL_TIM_OC_GetPolarity\n
		1691	* CCER CC2P LL_TIM_OC_GetPolarity\n
		1692	* CCER CC2NP LL_TIM_OC_GetPolarity\n
		1693	* CCER CC3P LL_TIM_OC_GetPolarity\n
		1694	* CCER CC3NP LL_TIM_OC_GetPolarity\n
		1695	* CCER CC4P LL_TIM_OC_GetPolarity
		1696	* @param TIMx Timer instance
		1697	* @param Channel This parameter can be one of the following values:
		1698	* @arg @ref LL_TIM_CHANNEL_CH1
		1699	* @arg @ref LL_TIM_CHANNEL_CH1N
		1700	* @arg @ref LL_TIM_CHANNEL_CH2
		1701	* @arg @ref LL_TIM_CHANNEL_CH2N
		1702	* @arg @ref LL_TIM_CHANNEL_CH3
		1703	* @arg @ref LL_TIM_CHANNEL_CH3N
		1704	* @arg @ref LL_TIM_CHANNEL_CH4
		1705	* @retval Returned value can be one of the following values:
		1706	* @arg @ref LL_TIM_OCPOLARITY_HIGH
		1707	* @arg @ref LL_TIM_OCPOLARITY_LOW
		1708	*/
		1709	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		1710	{
		1711	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1712	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
		1713	}
		1714
		1715	/**
		1716	* @brief Set the IDLE state of an output channel
		1717	* @note This function is significant only for the timer instances
		1718	* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
		1719	* can be used to check whether or not a timer instance provides
		1720	* a break input.
		1721	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
		1722	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
		1723	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
		1724	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
		1725	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
		1726	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
		1727	* CR2 OIS4 LL_TIM_OC_SetIdleState
		1728	* @param TIMx Timer instance
		1729	* @param Channel This parameter can be one of the following values:
		1730	* @arg @ref LL_TIM_CHANNEL_CH1
		1731	* @arg @ref LL_TIM_CHANNEL_CH1N
		1732	* @arg @ref LL_TIM_CHANNEL_CH2
		1733	* @arg @ref LL_TIM_CHANNEL_CH2N
		1734	* @arg @ref LL_TIM_CHANNEL_CH3
		1735	* @arg @ref LL_TIM_CHANNEL_CH3N
		1736	* @arg @ref LL_TIM_CHANNEL_CH4
		1737	* @param IdleState This parameter can be one of the following values:
		1738	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1739	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1740	* @retval None
		1741	*/
		1742	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
		1743	{
		1744	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1745	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
		1746	}
		1747
		1748	/**
		1749	* @brief Get the IDLE state of an output channel
		1750	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
		1751	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
		1752	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
		1753	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
		1754	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
		1755	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
		1756	* CR2 OIS4 LL_TIM_OC_GetIdleState
		1757	* @param TIMx Timer instance
		1758	* @param Channel This parameter can be one of the following values:
		1759	* @arg @ref LL_TIM_CHANNEL_CH1
		1760	* @arg @ref LL_TIM_CHANNEL_CH1N
		1761	* @arg @ref LL_TIM_CHANNEL_CH2
		1762	* @arg @ref LL_TIM_CHANNEL_CH2N
		1763	* @arg @ref LL_TIM_CHANNEL_CH3
		1764	* @arg @ref LL_TIM_CHANNEL_CH3N
		1765	* @arg @ref LL_TIM_CHANNEL_CH4
		1766	* @retval Returned value can be one of the following values:
		1767	* @arg @ref LL_TIM_OCIDLESTATE_LOW
		1768	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
		1769	*/
		1770	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
		1771	{
		1772	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1773	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
		1774	}
		1775
		1776	/**
		1777	* @brief Enable fast mode for the output channel.
		1778	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
		1779	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
		1780	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
		1781	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
		1782	* CCMR2 OC4FE LL_TIM_OC_EnableFast
		1783	* @param TIMx Timer instance
		1784	* @param Channel This parameter can be one of the following values:
		1785	* @arg @ref LL_TIM_CHANNEL_CH1
		1786	* @arg @ref LL_TIM_CHANNEL_CH2
		1787	* @arg @ref LL_TIM_CHANNEL_CH3
		1788	* @arg @ref LL_TIM_CHANNEL_CH4
		1789	* @retval None
		1790	*/
		1791	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1792	{
		1793	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1794	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1795	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1796
		1797	}
		1798
		1799	/**
		1800	* @brief Disable fast mode for the output channel.
		1801	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
		1802	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
		1803	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
		1804	* CCMR2 OC4FE LL_TIM_OC_DisableFast
		1805	* @param TIMx Timer instance
		1806	* @param Channel This parameter can be one of the following values:
		1807	* @arg @ref LL_TIM_CHANNEL_CH1
		1808	* @arg @ref LL_TIM_CHANNEL_CH2
		1809	* @arg @ref LL_TIM_CHANNEL_CH3
		1810	* @arg @ref LL_TIM_CHANNEL_CH4
		1811	* @retval None
		1812	*/
		1813	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1814	{
		1815	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1816	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1817	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
		1818
		1819	}
		1820
		1821	/**
		1822	* @brief Indicates whether fast mode is enabled for the output channel.
		1823	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
		1824	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
		1825	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
		1826	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
		1827	* @param TIMx Timer instance
		1828	* @param Channel This parameter can be one of the following values:
		1829	* @arg @ref LL_TIM_CHANNEL_CH1
		1830	* @arg @ref LL_TIM_CHANNEL_CH2
		1831	* @arg @ref LL_TIM_CHANNEL_CH3
		1832	* @arg @ref LL_TIM_CHANNEL_CH4
		1833	* @retval State of bit (1 or 0).
		1834	*/
		1835	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
		1836	{
		1837	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1838	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1839	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
		1840	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1841	}
		1842
		1843	/**
		1844	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
		1845	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
		1846	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
		1847	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
		1848	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
		1849	* @param TIMx Timer instance
		1850	* @param Channel This parameter can be one of the following values:
		1851	* @arg @ref LL_TIM_CHANNEL_CH1
		1852	* @arg @ref LL_TIM_CHANNEL_CH2
		1853	* @arg @ref LL_TIM_CHANNEL_CH3
		1854	* @arg @ref LL_TIM_CHANNEL_CH4
		1855	* @retval None
		1856	*/
		1857	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1858	{
		1859	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1860	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1861	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1862	}
		1863
		1864	/**
		1865	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
		1866	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
		1867	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
		1868	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
		1869	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
		1870	* @param TIMx Timer instance
		1871	* @param Channel This parameter can be one of the following values:
		1872	* @arg @ref LL_TIM_CHANNEL_CH1
		1873	* @arg @ref LL_TIM_CHANNEL_CH2
		1874	* @arg @ref LL_TIM_CHANNEL_CH3
		1875	* @arg @ref LL_TIM_CHANNEL_CH4
		1876	* @retval None
		1877	*/
		1878	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1879	{
		1880	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1881	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1882	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
		1883	}
		1884
		1885	/**
		1886	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
		1887	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
		1888	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
		1889	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
		1890	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
		1891	* @param TIMx Timer instance
		1892	* @param Channel This parameter can be one of the following values:
		1893	* @arg @ref LL_TIM_CHANNEL_CH1
		1894	* @arg @ref LL_TIM_CHANNEL_CH2
		1895	* @arg @ref LL_TIM_CHANNEL_CH3
		1896	* @arg @ref LL_TIM_CHANNEL_CH4
		1897	* @retval State of bit (1 or 0).
		1898	*/
		1899	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
		1900	{
		1901	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1902	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1903	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
		1904	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1905	}
		1906
		1907	/**
		1908	* @brief Enable clearing the output channel on an external event.
		1909	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1910	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1911	* or not a timer instance can clear the OCxREF signal on an external event.
		1912	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
		1913	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
		1914	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
		1915	* CCMR2 OC4CE LL_TIM_OC_EnableClear
		1916	* @param TIMx Timer instance
		1917	* @param Channel This parameter can be one of the following values:
		1918	* @arg @ref LL_TIM_CHANNEL_CH1
		1919	* @arg @ref LL_TIM_CHANNEL_CH2
		1920	* @arg @ref LL_TIM_CHANNEL_CH3
		1921	* @arg @ref LL_TIM_CHANNEL_CH4
		1922	* @retval None
		1923	*/
		1924	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1925	{
		1926	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1927	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1928	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1929	}
		1930
		1931	/**
		1932	* @brief Disable clearing the output channel on an external event.
		1933	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1934	* or not a timer instance can clear the OCxREF signal on an external event.
		1935	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
		1936	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
		1937	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
		1938	* CCMR2 OC4CE LL_TIM_OC_DisableClear
		1939	* @param TIMx Timer instance
		1940	* @param Channel This parameter can be one of the following values:
		1941	* @arg @ref LL_TIM_CHANNEL_CH1
		1942	* @arg @ref LL_TIM_CHANNEL_CH2
		1943	* @arg @ref LL_TIM_CHANNEL_CH3
		1944	* @arg @ref LL_TIM_CHANNEL_CH4
		1945	* @retval None
		1946	*/
		1947	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1948	{
		1949	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1950	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1951	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
		1952	}
		1953
		1954	/**
		1955	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
		1956	* @note This function enables clearing the output channel on an external event.
		1957	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
		1958	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
		1959	* or not a timer instance can clear the OCxREF signal on an external event.
		1960	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
		1961	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
		1962	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
		1963	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
		1964	* @param TIMx Timer instance
		1965	* @param Channel This parameter can be one of the following values:
		1966	* @arg @ref LL_TIM_CHANNEL_CH1
		1967	* @arg @ref LL_TIM_CHANNEL_CH2
		1968	* @arg @ref LL_TIM_CHANNEL_CH3
		1969	* @arg @ref LL_TIM_CHANNEL_CH4
		1970	* @retval State of bit (1 or 0).
		1971	*/
		1972	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
		1973	{
		1974	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		1975	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		1976	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
		1977	return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
		1978	}
		1979
		1980	/**
		1981	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
		1982	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		1983	* dead-time insertion feature is supported by a timer instance.
		1984	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
		1985	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
		1986	* @param TIMx Timer instance
		1987	* @param DeadTime between Min_Data=0 and Max_Data=255
		1988	* @retval None
		1989	*/
		1990	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
		1991	{
		1992	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
		1993	}
		1994
		1995	/**
		1996	* @brief Set compare value for output channel 1 (TIMx_CCR1).
		1997	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		1998	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		1999	* whether or not a timer instance supports a 32 bits counter.
		2000	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2001	* output channel 1 is supported by a timer instance.
		2002	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
		2003	* @param TIMx Timer instance
		2004	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2005	* @retval None
		2006	*/
		2007	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2008	{
		2009	WRITE_REG(TIMx->CCR1, CompareValue);
		2010	}
		2011
		2012	/**
		2013	* @brief Set compare value for output channel 2 (TIMx_CCR2).
		2014	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2015	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2016	* whether or not a timer instance supports a 32 bits counter.
		2017	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2018	* output channel 2 is supported by a timer instance.
		2019	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
		2020	* @param TIMx Timer instance
		2021	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2022	* @retval None
		2023	*/
		2024	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2025	{
		2026	WRITE_REG(TIMx->CCR2, CompareValue);
		2027	}
		2028
		2029	/**
		2030	* @brief Set compare value for output channel 3 (TIMx_CCR3).
		2031	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2032	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2033	* whether or not a timer instance supports a 32 bits counter.
		2034	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2035	* output channel is supported by a timer instance.
		2036	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
		2037	* @param TIMx Timer instance
		2038	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2039	* @retval None
		2040	*/
		2041	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2042	{
		2043	WRITE_REG(TIMx->CCR3, CompareValue);
		2044	}
		2045
		2046	/**
		2047	* @brief Set compare value for output channel 4 (TIMx_CCR4).
		2048	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
		2049	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2050	* whether or not a timer instance supports a 32 bits counter.
		2051	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2052	* output channel 4 is supported by a timer instance.
		2053	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
		2054	* @param TIMx Timer instance
		2055	* @param CompareValue between Min_Data=0 and Max_Data=65535
		2056	* @retval None
		2057	*/
		2058	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
		2059	{
		2060	WRITE_REG(TIMx->CCR4, CompareValue);
		2061	}
		2062
		2063	/**
		2064	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
		2065	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2066	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2067	* whether or not a timer instance supports a 32 bits counter.
		2068	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2069	* output channel 1 is supported by a timer instance.
		2070	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
		2071	* @param TIMx Timer instance
		2072	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2073	*/
		2074	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
		2075	{
		2076	return (uint32_t)(READ_REG(TIMx->CCR1));
		2077	}
		2078
		2079	/**
		2080	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
		2081	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2082	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2083	* whether or not a timer instance supports a 32 bits counter.
		2084	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2085	* output channel 2 is supported by a timer instance.
		2086	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
		2087	* @param TIMx Timer instance
		2088	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2089	*/
		2090	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
		2091	{
		2092	return (uint32_t)(READ_REG(TIMx->CCR2));
		2093	}
		2094
		2095	/**
		2096	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
		2097	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2098	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2099	* whether or not a timer instance supports a 32 bits counter.
		2100	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2101	* output channel 3 is supported by a timer instance.
		2102	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
		2103	* @param TIMx Timer instance
		2104	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2105	*/
		2106	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
		2107	{
		2108	return (uint32_t)(READ_REG(TIMx->CCR3));
		2109	}
		2110
		2111	/**
		2112	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
		2113	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
		2114	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2115	* whether or not a timer instance supports a 32 bits counter.
		2116	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2117	* output channel 4 is supported by a timer instance.
		2118	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
		2119	* @param TIMx Timer instance
		2120	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
		2121	*/
		2122	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
		2123	{
		2124	return (uint32_t)(READ_REG(TIMx->CCR4));
		2125	}
		2126
		2127	/**
		2128	* @}
		2129	*/
		2130
		2131	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
		2132	* @{
		2133	*/
		2134	/**
		2135	* @brief Configure input channel.
		2136	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
		2137	* CCMR1 IC1PSC LL_TIM_IC_Config\n
		2138	* CCMR1 IC1F LL_TIM_IC_Config\n
		2139	* CCMR1 CC2S LL_TIM_IC_Config\n
		2140	* CCMR1 IC2PSC LL_TIM_IC_Config\n
		2141	* CCMR1 IC2F LL_TIM_IC_Config\n
		2142	* CCMR2 CC3S LL_TIM_IC_Config\n
		2143	* CCMR2 IC3PSC LL_TIM_IC_Config\n
		2144	* CCMR2 IC3F LL_TIM_IC_Config\n
		2145	* CCMR2 CC4S LL_TIM_IC_Config\n
		2146	* CCMR2 IC4PSC LL_TIM_IC_Config\n
		2147	* CCMR2 IC4F LL_TIM_IC_Config\n
		2148	* CCER CC1P LL_TIM_IC_Config\n
		2149	* CCER CC1NP LL_TIM_IC_Config\n
		2150	* CCER CC2P LL_TIM_IC_Config\n
		2151	* CCER CC2NP LL_TIM_IC_Config\n
		2152	* CCER CC3P LL_TIM_IC_Config\n
		2153	* CCER CC3NP LL_TIM_IC_Config\n
		2154	* CCER CC4P LL_TIM_IC_Config\n
		2155	* CCER CC4NP LL_TIM_IC_Config
		2156	* @param TIMx Timer instance
		2157	* @param Channel This parameter can be one of the following values:
		2158	* @arg @ref LL_TIM_CHANNEL_CH1
		2159	* @arg @ref LL_TIM_CHANNEL_CH2
		2160	* @arg @ref LL_TIM_CHANNEL_CH3
		2161	* @arg @ref LL_TIM_CHANNEL_CH4
		2162	* @param Configuration This parameter must be a combination of all the following values:
		2163	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
		2164	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
		2165	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
		2166	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2167	* @retval None
		2168	*/
		2169	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
		2170	{
		2171	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2172	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2173	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
		2174	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
		2175	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2176	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
		2177	}
		2178
		2179	/**
		2180	* @brief Set the active input.
		2181	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
		2182	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
		2183	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
		2184	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
		2185	* @param TIMx Timer instance
		2186	* @param Channel This parameter can be one of the following values:
		2187	* @arg @ref LL_TIM_CHANNEL_CH1
		2188	* @arg @ref LL_TIM_CHANNEL_CH2
		2189	* @arg @ref LL_TIM_CHANNEL_CH3
		2190	* @arg @ref LL_TIM_CHANNEL_CH4
		2191	* @param ICActiveInput This parameter can be one of the following values:
		2192	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2193	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2194	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2195	* @retval None
		2196	*/
		2197	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
		2198	{
		2199	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2200	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2201	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2202	}
		2203
		2204	/**
		2205	* @brief Get the current active input.
		2206	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
		2207	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
		2208	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
		2209	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
		2210	* @param TIMx Timer instance
		2211	* @param Channel This parameter can be one of the following values:
		2212	* @arg @ref LL_TIM_CHANNEL_CH1
		2213	* @arg @ref LL_TIM_CHANNEL_CH2
		2214	* @arg @ref LL_TIM_CHANNEL_CH3
		2215	* @arg @ref LL_TIM_CHANNEL_CH4
		2216	* @retval Returned value can be one of the following values:
		2217	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
		2218	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
		2219	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
		2220	*/
		2221	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
		2222	{
		2223	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2224	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2225	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2226	}
		2227
		2228	/**
		2229	* @brief Set the prescaler of input channel.
		2230	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
		2231	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
		2232	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
		2233	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
		2234	* @param TIMx Timer instance
		2235	* @param Channel This parameter can be one of the following values:
		2236	* @arg @ref LL_TIM_CHANNEL_CH1
		2237	* @arg @ref LL_TIM_CHANNEL_CH2
		2238	* @arg @ref LL_TIM_CHANNEL_CH3
		2239	* @arg @ref LL_TIM_CHANNEL_CH4
		2240	* @param ICPrescaler This parameter can be one of the following values:
		2241	* @arg @ref LL_TIM_ICPSC_DIV1
		2242	* @arg @ref LL_TIM_ICPSC_DIV2
		2243	* @arg @ref LL_TIM_ICPSC_DIV4
		2244	* @arg @ref LL_TIM_ICPSC_DIV8
		2245	* @retval None
		2246	*/
		2247	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
		2248	{
		2249	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2250	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2251	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2252	}
		2253
		2254	/**
		2255	* @brief Get the current prescaler value acting on an input channel.
		2256	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
		2257	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
		2258	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
		2259	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
		2260	* @param TIMx Timer instance
		2261	* @param Channel This parameter can be one of the following values:
		2262	* @arg @ref LL_TIM_CHANNEL_CH1
		2263	* @arg @ref LL_TIM_CHANNEL_CH2
		2264	* @arg @ref LL_TIM_CHANNEL_CH3
		2265	* @arg @ref LL_TIM_CHANNEL_CH4
		2266	* @retval Returned value can be one of the following values:
		2267	* @arg @ref LL_TIM_ICPSC_DIV1
		2268	* @arg @ref LL_TIM_ICPSC_DIV2
		2269	* @arg @ref LL_TIM_ICPSC_DIV4
		2270	* @arg @ref LL_TIM_ICPSC_DIV8
		2271	*/
		2272	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
		2273	{
		2274	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2275	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2276	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2277	}
		2278
		2279	/**
		2280	* @brief Set the input filter duration.
		2281	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
		2282	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
		2283	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
		2284	* CCMR2 IC4F LL_TIM_IC_SetFilter
		2285	* @param TIMx Timer instance
		2286	* @param Channel This parameter can be one of the following values:
		2287	* @arg @ref LL_TIM_CHANNEL_CH1
		2288	* @arg @ref LL_TIM_CHANNEL_CH2
		2289	* @arg @ref LL_TIM_CHANNEL_CH3
		2290	* @arg @ref LL_TIM_CHANNEL_CH4
		2291	* @param ICFilter This parameter can be one of the following values:
		2292	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2293	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2294	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2295	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2296	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2297	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2298	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2299	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2300	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2301	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2302	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2303	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2304	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2305	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2306	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2307	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2308	* @retval None
		2309	*/
		2310	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
		2311	{
		2312	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2313	register __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2314	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
		2315	}
		2316
		2317	/**
		2318	* @brief Get the input filter duration.
		2319	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
		2320	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
		2321	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
		2322	* CCMR2 IC4F LL_TIM_IC_GetFilter
		2323	* @param TIMx Timer instance
		2324	* @param Channel This parameter can be one of the following values:
		2325	* @arg @ref LL_TIM_CHANNEL_CH1
		2326	* @arg @ref LL_TIM_CHANNEL_CH2
		2327	* @arg @ref LL_TIM_CHANNEL_CH3
		2328	* @arg @ref LL_TIM_CHANNEL_CH4
		2329	* @retval Returned value can be one of the following values:
		2330	* @arg @ref LL_TIM_IC_FILTER_FDIV1
		2331	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
		2332	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
		2333	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
		2334	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
		2335	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
		2336	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
		2337	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
		2338	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
		2339	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
		2340	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
		2341	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
		2342	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
		2343	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
		2344	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
		2345	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
		2346	*/
		2347	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
		2348	{
		2349	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2350	register const __IO uint32_t pReg = (__IO uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
		2351	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
		2352	}
		2353
		2354	/**
		2355	* @brief Set the input channel polarity.
		2356	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
		2357	* CCER CC1NP LL_TIM_IC_SetPolarity\n
		2358	* CCER CC2P LL_TIM_IC_SetPolarity\n
		2359	* CCER CC2NP LL_TIM_IC_SetPolarity\n
		2360	* CCER CC3P LL_TIM_IC_SetPolarity\n
		2361	* CCER CC3NP LL_TIM_IC_SetPolarity\n
		2362	* CCER CC4P LL_TIM_IC_SetPolarity\n
		2363	* CCER CC4NP LL_TIM_IC_SetPolarity
		2364	* @param TIMx Timer instance
		2365	* @param Channel This parameter can be one of the following values:
		2366	* @arg @ref LL_TIM_CHANNEL_CH1
		2367	* @arg @ref LL_TIM_CHANNEL_CH2
		2368	* @arg @ref LL_TIM_CHANNEL_CH3
		2369	* @arg @ref LL_TIM_CHANNEL_CH4
		2370	* @param ICPolarity This parameter can be one of the following values:
		2371	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2372	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2373	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2374	* @retval None
		2375	*/
		2376	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
		2377	{
		2378	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2379	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
		2380	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
		2381	}
		2382
		2383	/**
		2384	* @brief Get the current input channel polarity.
		2385	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
		2386	* CCER CC1NP LL_TIM_IC_GetPolarity\n
		2387	* CCER CC2P LL_TIM_IC_GetPolarity\n
		2388	* CCER CC2NP LL_TIM_IC_GetPolarity\n
		2389	* CCER CC3P LL_TIM_IC_GetPolarity\n
		2390	* CCER CC3NP LL_TIM_IC_GetPolarity\n
		2391	* CCER CC4P LL_TIM_IC_GetPolarity\n
		2392	* CCER CC4NP LL_TIM_IC_GetPolarity
		2393	* @param TIMx Timer instance
		2394	* @param Channel This parameter can be one of the following values:
		2395	* @arg @ref LL_TIM_CHANNEL_CH1
		2396	* @arg @ref LL_TIM_CHANNEL_CH2
		2397	* @arg @ref LL_TIM_CHANNEL_CH3
		2398	* @arg @ref LL_TIM_CHANNEL_CH4
		2399	* @retval Returned value can be one of the following values:
		2400	* @arg @ref LL_TIM_IC_POLARITY_RISING
		2401	* @arg @ref LL_TIM_IC_POLARITY_FALLING
		2402	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
		2403	*/
		2404	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
		2405	{
		2406	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
		2407	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
		2408	SHIFT_TAB_CCxP[iChannel]);
		2409	}
		2410
		2411	/**
		2412	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
		2413	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2414	* a timer instance provides an XOR input.
		2415	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
		2416	* @param TIMx Timer instance
		2417	* @retval None
		2418	*/
		2419	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
		2420	{
		2421	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2422	}
		2423
		2424	/**
		2425	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
		2426	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2427	* a timer instance provides an XOR input.
		2428	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
		2429	* @param TIMx Timer instance
		2430	* @retval None
		2431	*/
		2432	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
		2433	{
		2434	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
		2435	}
		2436
		2437	/**
		2438	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
		2439	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
		2440	* a timer instance provides an XOR input.
		2441	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
		2442	* @param TIMx Timer instance
		2443	* @retval State of bit (1 or 0).
		2444	*/
		2445	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
		2446	{
		2447	return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
		2448	}
		2449
		2450	/**
		2451	* @brief Get captured value for input channel 1.
		2452	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2453	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2454	* whether or not a timer instance supports a 32 bits counter.
		2455	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
		2456	* input channel 1 is supported by a timer instance.
		2457	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
		2458	* @param TIMx Timer instance
		2459	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2460	*/
		2461	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
		2462	{
		2463	return (uint32_t)(READ_REG(TIMx->CCR1));
		2464	}
		2465
		2466	/**
		2467	* @brief Get captured value for input channel 2.
		2468	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2469	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2470	* whether or not a timer instance supports a 32 bits counter.
		2471	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
		2472	* input channel 2 is supported by a timer instance.
		2473	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
		2474	* @param TIMx Timer instance
		2475	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2476	*/
		2477	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
		2478	{
		2479	return (uint32_t)(READ_REG(TIMx->CCR2));
		2480	}
		2481
		2482	/**
		2483	* @brief Get captured value for input channel 3.
		2484	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2485	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2486	* whether or not a timer instance supports a 32 bits counter.
		2487	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
		2488	* input channel 3 is supported by a timer instance.
		2489	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
		2490	* @param TIMx Timer instance
		2491	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2492	*/
		2493	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
		2494	{
		2495	return (uint32_t)(READ_REG(TIMx->CCR3));
		2496	}
		2497
		2498	/**
		2499	* @brief Get captured value for input channel 4.
		2500	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
		2501	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
		2502	* whether or not a timer instance supports a 32 bits counter.
		2503	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
		2504	* input channel 4 is supported by a timer instance.
		2505	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
		2506	* @param TIMx Timer instance
		2507	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
		2508	*/
		2509	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
		2510	{
		2511	return (uint32_t)(READ_REG(TIMx->CCR4));
		2512	}
		2513
		2514	/**
		2515	* @}
		2516	*/
		2517
		2518	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
		2519	* @{
		2520	*/
		2521	/**
		2522	* @brief Enable external clock mode 2.
		2523	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
		2524	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2525	* whether or not a timer instance supports external clock mode2.
		2526	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
		2527	* @param TIMx Timer instance
		2528	* @retval None
		2529	*/
		2530	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
		2531	{
		2532	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2533	}
		2534
		2535	/**
		2536	* @brief Disable external clock mode 2.
		2537	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2538	* whether or not a timer instance supports external clock mode2.
		2539	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
		2540	* @param TIMx Timer instance
		2541	* @retval None
		2542	*/
		2543	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
		2544	{
		2545	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
		2546	}
		2547
		2548	/**
		2549	* @brief Indicate whether external clock mode 2 is enabled.
		2550	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2551	* whether or not a timer instance supports external clock mode2.
		2552	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
		2553	* @param TIMx Timer instance
		2554	* @retval State of bit (1 or 0).
		2555	*/
		2556	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
		2557	{
		2558	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
		2559	}
		2560
		2561	/**
		2562	* @brief Set the clock source of the counter clock.
		2563	* @note when selected clock source is external clock mode 1, the timer input
		2564	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
		2565	* function. This timer input must be configured by calling
		2566	* the @ref LL_TIM_IC_Config() function.
		2567	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
		2568	* whether or not a timer instance supports external clock mode1.
		2569	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
		2570	* whether or not a timer instance supports external clock mode2.
		2571	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
		2572	* SMCR ECE LL_TIM_SetClockSource
		2573	* @param TIMx Timer instance
		2574	* @param ClockSource This parameter can be one of the following values:
		2575	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
		2576	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
		2577	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
		2578	* @retval None
		2579	*/
		2580	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
		2581	{
		2582	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
		2583	}
		2584
		2585	/**
		2586	* @brief Set the encoder interface mode.
		2587	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
		2588	* whether or not a timer instance supports the encoder mode.
		2589	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
		2590	* @param TIMx Timer instance
		2591	* @param EncoderMode This parameter can be one of the following values:
		2592	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
		2593	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
		2594	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
		2595	* @retval None
		2596	*/
		2597	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
		2598	{
		2599	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
		2600	}
		2601
		2602	/**
		2603	* @}
		2604	*/
		2605
		2606	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
		2607	* @{
		2608	*/
		2609	/**
		2610	* @brief Set the trigger output (TRGO) used for timer synchronization .
		2611	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
		2612	* whether or not a timer instance can operate as a master timer.
		2613	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
		2614	* @param TIMx Timer instance
		2615	* @param TimerSynchronization This parameter can be one of the following values:
		2616	* @arg @ref LL_TIM_TRGO_RESET
		2617	* @arg @ref LL_TIM_TRGO_ENABLE
		2618	* @arg @ref LL_TIM_TRGO_UPDATE
		2619	* @arg @ref LL_TIM_TRGO_CC1IF
		2620	* @arg @ref LL_TIM_TRGO_OC1REF
		2621	* @arg @ref LL_TIM_TRGO_OC2REF
		2622	* @arg @ref LL_TIM_TRGO_OC3REF
		2623	* @arg @ref LL_TIM_TRGO_OC4REF
		2624	* @retval None
		2625	*/
		2626	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
		2627	{
		2628	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
		2629	}
		2630
		2631	/**
		2632	* @brief Set the synchronization mode of a slave timer.
		2633	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2634	* a timer instance can operate as a slave timer.
		2635	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
		2636	* @param TIMx Timer instance
		2637	* @param SlaveMode This parameter can be one of the following values:
		2638	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
		2639	* @arg @ref LL_TIM_SLAVEMODE_RESET
		2640	* @arg @ref LL_TIM_SLAVEMODE_GATED
		2641	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
		2642	* @retval None
		2643	*/
		2644	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
		2645	{
		2646	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
		2647	}
		2648
		2649	/**
		2650	* @brief Set the selects the trigger input to be used to synchronize the counter.
		2651	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2652	* a timer instance can operate as a slave timer.
		2653	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
		2654	* @param TIMx Timer instance
		2655	* @param TriggerInput This parameter can be one of the following values:
		2656	* @arg @ref LL_TIM_TS_ITR0
		2657	* @arg @ref LL_TIM_TS_ITR1
		2658	* @arg @ref LL_TIM_TS_ITR2
		2659	* @arg @ref LL_TIM_TS_ITR3
		2660	* @arg @ref LL_TIM_TS_TI1F_ED
		2661	* @arg @ref LL_TIM_TS_TI1FP1
		2662	* @arg @ref LL_TIM_TS_TI2FP2
		2663	* @arg @ref LL_TIM_TS_ETRF
		2664	* @retval None
		2665	*/
		2666	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
		2667	{
		2668	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
		2669	}
		2670
		2671	/**
		2672	* @brief Enable the Master/Slave mode.
		2673	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2674	* a timer instance can operate as a slave timer.
		2675	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
		2676	* @param TIMx Timer instance
		2677	* @retval None
		2678	*/
		2679	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
		2680	{
		2681	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2682	}
		2683
		2684	/**
		2685	* @brief Disable the Master/Slave mode.
		2686	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2687	* a timer instance can operate as a slave timer.
		2688	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
		2689	* @param TIMx Timer instance
		2690	* @retval None
		2691	*/
		2692	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
		2693	{
		2694	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
		2695	}
		2696
		2697	/**
		2698	* @brief Indicates whether the Master/Slave mode is enabled.
		2699	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
		2700	* a timer instance can operate as a slave timer.
		2701	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
		2702	* @param TIMx Timer instance
		2703	* @retval State of bit (1 or 0).
		2704	*/
		2705	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
		2706	{
		2707	return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
		2708	}
		2709
		2710	/**
		2711	* @brief Configure the external trigger (ETR) input.
		2712	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
		2713	* a timer instance provides an external trigger input.
		2714	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
		2715	* SMCR ETPS LL_TIM_ConfigETR\n
		2716	* SMCR ETF LL_TIM_ConfigETR
		2717	* @param TIMx Timer instance
		2718	* @param ETRPolarity This parameter can be one of the following values:
		2719	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
		2720	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
		2721	* @param ETRPrescaler This parameter can be one of the following values:
		2722	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
		2723	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
		2724	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
		2725	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
		2726	* @param ETRFilter This parameter can be one of the following values:
		2727	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
		2728	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
		2729	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
		2730	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
		2731	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
		2732	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
		2733	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
		2734	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
		2735	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
		2736	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
		2737	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
		2738	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
		2739	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
		2740	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
		2741	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
		2742	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
		2743	* @retval None
		2744	*/
		2745	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
		2746	uint32_t ETRFilter)
		2747	{
		2748	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
		2749	}
		2750
		2751	/**
		2752	* @}
		2753	*/
		2754
		2755	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
		2756	* @{
		2757	*/
		2758	/**
		2759	* @brief Enable the break function.
		2760	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2761	* a timer instance provides a break input.
		2762	* @rmtoll BDTR BKE LL_TIM_EnableBRK
		2763	* @param TIMx Timer instance
		2764	* @retval None
		2765	*/
		2766	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
		2767	{
		2768	__IO uint32_t tmpreg;
		2769	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2770	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2771	tmpreg = READ_REG(TIMx->BDTR);
		2772	(void)(tmpreg);
		2773	}
		2774
		2775	/**
		2776	* @brief Disable the break function.
		2777	* @rmtoll BDTR BKE LL_TIM_DisableBRK
		2778	* @param TIMx Timer instance
		2779	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2780	* a timer instance provides a break input.
		2781	* @retval None
		2782	*/
		2783	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
		2784	{
		2785	__IO uint32_t tmpreg;
		2786	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
		2787	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
		2788	tmpreg = READ_REG(TIMx->BDTR);
		2789	(void)(tmpreg);
		2790	}
		2791
		2792	/**
		2793	* @brief Configure the break input.
		2794	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2795	* a timer instance provides a break input.
		2796	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
		2797	* @param TIMx Timer instance
		2798	* @param BreakPolarity This parameter can be one of the following values:
		2799	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
		2800	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
		2801	* @retval None
		2802	*/
		2803	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
		2804	{
		2805	__IO uint32_t tmpreg;
		2806	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
		2807	/* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
		2808	tmpreg = READ_REG(TIMx->BDTR);
		2809	(void)(tmpreg);
		2810	}
		2811
		2812	/**
		2813	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
		2814	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2815	* a timer instance provides a break input.
		2816	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
		2817	* BDTR OSSR LL_TIM_SetOffStates
		2818	* @param TIMx Timer instance
		2819	* @param OffStateIdle This parameter can be one of the following values:
		2820	* @arg @ref LL_TIM_OSSI_DISABLE
		2821	* @arg @ref LL_TIM_OSSI_ENABLE
		2822	* @param OffStateRun This parameter can be one of the following values:
		2823	* @arg @ref LL_TIM_OSSR_DISABLE
		2824	* @arg @ref LL_TIM_OSSR_ENABLE
		2825	* @retval None
		2826	*/
		2827	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
		2828	{
		2829	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
		2830	}
		2831
		2832	/**
		2833	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
		2834	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2835	* a timer instance provides a break input.
		2836	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
		2837	* @param TIMx Timer instance
		2838	* @retval None
		2839	*/
		2840	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
		2841	{
		2842	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2843	}
		2844
		2845	/**
		2846	* @brief Disable automatic output (MOE can be set only by software).
		2847	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2848	* a timer instance provides a break input.
		2849	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
		2850	* @param TIMx Timer instance
		2851	* @retval None
		2852	*/
		2853	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
		2854	{
		2855	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
		2856	}
		2857
		2858	/**
		2859	* @brief Indicate whether automatic output is enabled.
		2860	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2861	* a timer instance provides a break input.
		2862	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
		2863	* @param TIMx Timer instance
		2864	* @retval State of bit (1 or 0).
		2865	*/
		2866	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
		2867	{
		2868	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
		2869	}
		2870
		2871	/**
		2872	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
		2873	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2874	* software and is reset in case of break or break2 event
		2875	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2876	* a timer instance provides a break input.
		2877	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
		2878	* @param TIMx Timer instance
		2879	* @retval None
		2880	*/
		2881	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
		2882	{
		2883	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2884	}
		2885
		2886	/**
		2887	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
		2888	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
		2889	* software and is reset in case of break or break2 event.
		2890	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2891	* a timer instance provides a break input.
		2892	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
		2893	* @param TIMx Timer instance
		2894	* @retval None
		2895	*/
		2896	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
		2897	{
		2898	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
		2899	}
		2900
		2901	/**
		2902	* @brief Indicates whether outputs are enabled.
		2903	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
		2904	* a timer instance provides a break input.
		2905	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
		2906	* @param TIMx Timer instance
		2907	* @retval State of bit (1 or 0).
		2908	*/
		2909	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
		2910	{
		2911	return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
		2912	}
		2913
		2914	/**
		2915	* @}
		2916	*/
		2917
		2918	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
		2919	* @{
		2920	*/
		2921	/**
		2922	* @brief Configures the timer DMA burst feature.
		2923	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
		2924	* not a timer instance supports the DMA burst mode.
		2925	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
		2926	* DCR DBA LL_TIM_ConfigDMABurst
		2927	* @param TIMx Timer instance
		2928	* @param DMABurstBaseAddress This parameter can be one of the following values:
		2929	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
		2930	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
		2931	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
		2932	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
		2933	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
		2934	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
		2935	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
		2936	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
		2937	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
		2938	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
		2939	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
		2940	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
		2941	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
		2942	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
		2943	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
		2944	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
		2945	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
		2946	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
		2947	* @param DMABurstLength This parameter can be one of the following values:
		2948	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
		2949	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
		2950	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
		2951	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
		2952	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
		2953	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
		2954	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
		2955	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
		2956	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
		2957	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
		2958	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
		2959	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
		2960	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
		2961	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
		2962	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
		2963	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
		2964	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
		2965	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
		2966	* @retval None
		2967	*/
		2968	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
		2969	{
		2970	MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL \| TIM_DCR_DBA), (DMABurstBaseAddress \| DMABurstLength));
		2971	}
		2972
		2973	/**
		2974	* @}
		2975	*/
		2976
		2977	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
		2978	* @{
		2979	*/
		2980	/**
		2981	* @brief Remap TIM inputs (input channel, internal/external triggers).
		2982	* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
		2983	* a some timer inputs can be remapped.
		2984	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
		2985	* @param TIMx Timer instance
		2986	* @param Remap This parameter can be one of the following values:
		2987	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
		2988	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
		2989	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
		2990	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
		2991	*
		2992	* @retval None
		2993	*/
		2994	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
		2995	{
		2996	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
		2997	}
		2998
		2999	/**
		3000	* @}
		3001	*/
		3002
		3003	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
		3004	* @{
		3005	*/
		3006	/**
		3007	* @brief Set the OCREF clear input source
		3008	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
		3009	* @note This function can only be used in Output compare and PWM modes.
		3010	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
		3011	* @param TIMx Timer instance
		3012	* @param OCRefClearInputSource This parameter can be one of the following values:
		3013	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
		3014	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
		3015	* @retval None
		3016	*/
		3017	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
		3018	{
		3019	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
		3020	}
		3021	/**
		3022	* @}
		3023	*/
		3024
		3025	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
		3026	* @{
		3027	*/
		3028	/**
		3029	* @brief Clear the update interrupt flag (UIF).
		3030	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
		3031	* @param TIMx Timer instance
		3032	* @retval None
		3033	*/
		3034	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
		3035	{
		3036	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
		3037	}
		3038
		3039	/**
		3040	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
		3041	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
		3042	* @param TIMx Timer instance
		3043	* @retval State of bit (1 or 0).
		3044	*/
		3045	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
		3046	{
		3047	return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
		3048	}
		3049
		3050	/**
		3051	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
		3052	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
		3053	* @param TIMx Timer instance
		3054	* @retval None
		3055	*/
		3056	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
		3057	{
		3058	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
		3059	}
		3060
		3061	/**
		3062	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
		3063	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
		3064	* @param TIMx Timer instance
		3065	* @retval State of bit (1 or 0).
		3066	*/
		3067	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
		3068	{
		3069	return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
		3070	}
		3071
		3072	/**
		3073	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
		3074	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
		3075	* @param TIMx Timer instance
		3076	* @retval None
		3077	*/
		3078	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
		3079	{
		3080	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
		3081	}
		3082
		3083	/**
		3084	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
		3085	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
		3086	* @param TIMx Timer instance
		3087	* @retval State of bit (1 or 0).
		3088	*/
		3089	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
		3090	{
		3091	return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
		3092	}
		3093
		3094	/**
		3095	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
		3096	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
		3097	* @param TIMx Timer instance
		3098	* @retval None
		3099	*/
		3100	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
		3101	{
		3102	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
		3103	}
		3104
		3105	/**
		3106	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
		3107	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
		3108	* @param TIMx Timer instance
		3109	* @retval State of bit (1 or 0).
		3110	*/
		3111	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
		3112	{
		3113	return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
		3114	}
		3115
		3116	/**
		3117	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
		3118	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
		3119	* @param TIMx Timer instance
		3120	* @retval None
		3121	*/
		3122	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
		3123	{
		3124	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
		3125	}
		3126
		3127	/**
		3128	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
		3129	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
		3130	* @param TIMx Timer instance
		3131	* @retval State of bit (1 or 0).
		3132	*/
		3133	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
		3134	{
		3135	return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
		3136	}
		3137
		3138	/**
		3139	* @brief Clear the commutation interrupt flag (COMIF).
		3140	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
		3141	* @param TIMx Timer instance
		3142	* @retval None
		3143	*/
		3144	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
		3145	{
		3146	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
		3147	}
		3148
		3149	/**
		3150	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
		3151	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
		3152	* @param TIMx Timer instance
		3153	* @retval State of bit (1 or 0).
		3154	*/
		3155	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
		3156	{
		3157	return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
		3158	}
		3159
		3160	/**
		3161	* @brief Clear the trigger interrupt flag (TIF).
		3162	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
		3163	* @param TIMx Timer instance
		3164	* @retval None
		3165	*/
		3166	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
		3167	{
		3168	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
		3169	}
		3170
		3171	/**
		3172	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
		3173	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
		3174	* @param TIMx Timer instance
		3175	* @retval State of bit (1 or 0).
		3176	*/
		3177	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
		3178	{
		3179	return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
		3180	}
		3181
		3182	/**
		3183	* @brief Clear the break interrupt flag (BIF).
		3184	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
		3185	* @param TIMx Timer instance
		3186	* @retval None
		3187	*/
		3188	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
		3189	{
		3190	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
		3191	}
		3192
		3193	/**
		3194	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
		3195	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
		3196	* @param TIMx Timer instance
		3197	* @retval State of bit (1 or 0).
		3198	*/
		3199	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
		3200	{
		3201	return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
		3202	}
		3203
		3204	/**
		3205	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
		3206	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
		3207	* @param TIMx Timer instance
		3208	* @retval None
		3209	*/
		3210	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
		3211	{
		3212	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
		3213	}
		3214
		3215	/**
		3216	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
		3217	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
		3218	* @param TIMx Timer instance
		3219	* @retval State of bit (1 or 0).
		3220	*/
		3221	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
		3222	{
		3223	return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
		3224	}
		3225
		3226	/**
		3227	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
		3228	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
		3229	* @param TIMx Timer instance
		3230	* @retval None
		3231	*/
		3232	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
		3233	{
		3234	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
		3235	}
		3236
		3237	/**
		3238	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
		3239	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
		3240	* @param TIMx Timer instance
		3241	* @retval State of bit (1 or 0).
		3242	*/
		3243	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
		3244	{
		3245	return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
		3246	}
		3247
		3248	/**
		3249	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
		3250	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
		3251	* @param TIMx Timer instance
		3252	* @retval None
		3253	*/
		3254	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
		3255	{
		3256	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
		3257	}
		3258
		3259	/**
		3260	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
		3261	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
		3262	* @param TIMx Timer instance
		3263	* @retval State of bit (1 or 0).
		3264	*/
		3265	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
		3266	{
		3267	return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
		3268	}
		3269
		3270	/**
		3271	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
		3272	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
		3273	* @param TIMx Timer instance
		3274	* @retval None
		3275	*/
		3276	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
		3277	{
		3278	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
		3279	}
		3280
		3281	/**
		3282	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
		3283	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
		3284	* @param TIMx Timer instance
		3285	* @retval State of bit (1 or 0).
		3286	*/
		3287	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
		3288	{
		3289	return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
		3290	}
		3291
		3292	/**
		3293	* @}
		3294	*/
		3295
		3296	/** @defgroup TIM_LL_EF_IT_Management IT-Management
		3297	* @{
		3298	*/
		3299	/**
		3300	* @brief Enable update interrupt (UIE).
		3301	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
		3302	* @param TIMx Timer instance
		3303	* @retval None
		3304	*/
		3305	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
		3306	{
		3307	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
		3308	}
		3309
		3310	/**
		3311	* @brief Disable update interrupt (UIE).
		3312	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
		3313	* @param TIMx Timer instance
		3314	* @retval None
		3315	*/
		3316	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
		3317	{
		3318	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
		3319	}
		3320
		3321	/**
		3322	* @brief Indicates whether the update interrupt (UIE) is enabled.
		3323	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
		3324	* @param TIMx Timer instance
		3325	* @retval State of bit (1 or 0).
		3326	*/
		3327	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
		3328	{
		3329	return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
		3330	}
		3331
		3332	/**
		3333	* @brief Enable capture/compare 1 interrupt (CC1IE).
		3334	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
		3335	* @param TIMx Timer instance
		3336	* @retval None
		3337	*/
		3338	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
		3339	{
		3340	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3341	}
		3342
		3343	/**
		3344	* @brief Disable capture/compare 1 interrupt (CC1IE).
		3345	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
		3346	* @param TIMx Timer instance
		3347	* @retval None
		3348	*/
		3349	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
		3350	{
		3351	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
		3352	}
		3353
		3354	/**
		3355	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
		3356	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
		3357	* @param TIMx Timer instance
		3358	* @retval State of bit (1 or 0).
		3359	*/
		3360	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
		3361	{
		3362	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
		3363	}
		3364
		3365	/**
		3366	* @brief Enable capture/compare 2 interrupt (CC2IE).
		3367	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
		3368	* @param TIMx Timer instance
		3369	* @retval None
		3370	*/
		3371	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
		3372	{
		3373	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3374	}
		3375
		3376	/**
		3377	* @brief Disable capture/compare 2 interrupt (CC2IE).
		3378	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
		3379	* @param TIMx Timer instance
		3380	* @retval None
		3381	*/
		3382	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
		3383	{
		3384	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
		3385	}
		3386
		3387	/**
		3388	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
		3389	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
		3390	* @param TIMx Timer instance
		3391	* @retval State of bit (1 or 0).
		3392	*/
		3393	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
		3394	{
		3395	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
		3396	}
		3397
		3398	/**
		3399	* @brief Enable capture/compare 3 interrupt (CC3IE).
		3400	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
		3401	* @param TIMx Timer instance
		3402	* @retval None
		3403	*/
		3404	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
		3405	{
		3406	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3407	}
		3408
		3409	/**
		3410	* @brief Disable capture/compare 3 interrupt (CC3IE).
		3411	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
		3412	* @param TIMx Timer instance
		3413	* @retval None
		3414	*/
		3415	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
		3416	{
		3417	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
		3418	}
		3419
		3420	/**
		3421	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
		3422	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
		3423	* @param TIMx Timer instance
		3424	* @retval State of bit (1 or 0).
		3425	*/
		3426	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
		3427	{
		3428	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
		3429	}
		3430
		3431	/**
		3432	* @brief Enable capture/compare 4 interrupt (CC4IE).
		3433	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
		3434	* @param TIMx Timer instance
		3435	* @retval None
		3436	*/
		3437	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
		3438	{
		3439	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3440	}
		3441
		3442	/**
		3443	* @brief Disable capture/compare 4 interrupt (CC4IE).
		3444	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
		3445	* @param TIMx Timer instance
		3446	* @retval None
		3447	*/
		3448	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
		3449	{
		3450	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
		3451	}
		3452
		3453	/**
		3454	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
		3455	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
		3456	* @param TIMx Timer instance
		3457	* @retval State of bit (1 or 0).
		3458	*/
		3459	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
		3460	{
		3461	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
		3462	}
		3463
		3464	/**
		3465	* @brief Enable commutation interrupt (COMIE).
		3466	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
		3467	* @param TIMx Timer instance
		3468	* @retval None
		3469	*/
		3470	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
		3471	{
		3472	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3473	}
		3474
		3475	/**
		3476	* @brief Disable commutation interrupt (COMIE).
		3477	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
		3478	* @param TIMx Timer instance
		3479	* @retval None
		3480	*/
		3481	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
		3482	{
		3483	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
		3484	}
		3485
		3486	/**
		3487	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
		3488	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
		3489	* @param TIMx Timer instance
		3490	* @retval State of bit (1 or 0).
		3491	*/
		3492	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
		3493	{
		3494	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
		3495	}
		3496
		3497	/**
		3498	* @brief Enable trigger interrupt (TIE).
		3499	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
		3500	* @param TIMx Timer instance
		3501	* @retval None
		3502	*/
		3503	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
		3504	{
		3505	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
		3506	}
		3507
		3508	/**
		3509	* @brief Disable trigger interrupt (TIE).
		3510	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
		3511	* @param TIMx Timer instance
		3512	* @retval None
		3513	*/
		3514	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
		3515	{
		3516	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
		3517	}
		3518
		3519	/**
		3520	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
		3521	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
		3522	* @param TIMx Timer instance
		3523	* @retval State of bit (1 or 0).
		3524	*/
		3525	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
		3526	{
		3527	return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
		3528	}
		3529
		3530	/**
		3531	* @brief Enable break interrupt (BIE).
		3532	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
		3533	* @param TIMx Timer instance
		3534	* @retval None
		3535	*/
		3536	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
		3537	{
		3538	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
		3539	}
		3540
		3541	/**
		3542	* @brief Disable break interrupt (BIE).
		3543	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
		3544	* @param TIMx Timer instance
		3545	* @retval None
		3546	*/
		3547	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
		3548	{
		3549	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
		3550	}
		3551
		3552	/**
		3553	* @brief Indicates whether the break interrupt (BIE) is enabled.
		3554	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
		3555	* @param TIMx Timer instance
		3556	* @retval State of bit (1 or 0).
		3557	*/
		3558	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
		3559	{
		3560	return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
		3561	}
		3562
		3563	/**
		3564	* @}
		3565	*/
		3566
		3567	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
		3568	* @{
		3569	*/
		3570	/**
		3571	* @brief Enable update DMA request (UDE).
		3572	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
		3573	* @param TIMx Timer instance
		3574	* @retval None
		3575	*/
		3576	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3577	{
		3578	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
		3579	}
		3580
		3581	/**
		3582	* @brief Disable update DMA request (UDE).
		3583	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
		3584	* @param TIMx Timer instance
		3585	* @retval None
		3586	*/
		3587	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3588	{
		3589	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
		3590	}
		3591
		3592	/**
		3593	* @brief Indicates whether the update DMA request (UDE) is enabled.
		3594	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
		3595	* @param TIMx Timer instance
		3596	* @retval State of bit (1 or 0).
		3597	*/
		3598	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
		3599	{
		3600	return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
		3601	}
		3602
		3603	/**
		3604	* @brief Enable capture/compare 1 DMA request (CC1DE).
		3605	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
		3606	* @param TIMx Timer instance
		3607	* @retval None
		3608	*/
		3609	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
		3610	{
		3611	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3612	}
		3613
		3614	/**
		3615	* @brief Disable capture/compare 1 DMA request (CC1DE).
		3616	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
		3617	* @param TIMx Timer instance
		3618	* @retval None
		3619	*/
		3620	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
		3621	{
		3622	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
		3623	}
		3624
		3625	/**
		3626	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
		3627	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
		3628	* @param TIMx Timer instance
		3629	* @retval State of bit (1 or 0).
		3630	*/
		3631	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
		3632	{
		3633	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
		3634	}
		3635
		3636	/**
		3637	* @brief Enable capture/compare 2 DMA request (CC2DE).
		3638	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
		3639	* @param TIMx Timer instance
		3640	* @retval None
		3641	*/
		3642	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
		3643	{
		3644	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3645	}
		3646
		3647	/**
		3648	* @brief Disable capture/compare 2 DMA request (CC2DE).
		3649	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
		3650	* @param TIMx Timer instance
		3651	* @retval None
		3652	*/
		3653	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
		3654	{
		3655	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
		3656	}
		3657
		3658	/**
		3659	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
		3660	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
		3661	* @param TIMx Timer instance
		3662	* @retval State of bit (1 or 0).
		3663	*/
		3664	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
		3665	{
		3666	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
		3667	}
		3668
		3669	/**
		3670	* @brief Enable capture/compare 3 DMA request (CC3DE).
		3671	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
		3672	* @param TIMx Timer instance
		3673	* @retval None
		3674	*/
		3675	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
		3676	{
		3677	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3678	}
		3679
		3680	/**
		3681	* @brief Disable capture/compare 3 DMA request (CC3DE).
		3682	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
		3683	* @param TIMx Timer instance
		3684	* @retval None
		3685	*/
		3686	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
		3687	{
		3688	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
		3689	}
		3690
		3691	/**
		3692	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
		3693	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
		3694	* @param TIMx Timer instance
		3695	* @retval State of bit (1 or 0).
		3696	*/
		3697	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
		3698	{
		3699	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
		3700	}
		3701
		3702	/**
		3703	* @brief Enable capture/compare 4 DMA request (CC4DE).
		3704	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
		3705	* @param TIMx Timer instance
		3706	* @retval None
		3707	*/
		3708	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
		3709	{
		3710	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3711	}
		3712
		3713	/**
		3714	* @brief Disable capture/compare 4 DMA request (CC4DE).
		3715	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
		3716	* @param TIMx Timer instance
		3717	* @retval None
		3718	*/
		3719	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
		3720	{
		3721	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
		3722	}
		3723
		3724	/**
		3725	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
		3726	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
		3727	* @param TIMx Timer instance
		3728	* @retval State of bit (1 or 0).
		3729	*/
		3730	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
		3731	{
		3732	return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
		3733	}
		3734
		3735	/**
		3736	* @brief Enable commutation DMA request (COMDE).
		3737	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
		3738	* @param TIMx Timer instance
		3739	* @retval None
		3740	*/
		3741	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
		3742	{
		3743	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3744	}
		3745
		3746	/**
		3747	* @brief Disable commutation DMA request (COMDE).
		3748	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
		3749	* @param TIMx Timer instance
		3750	* @retval None
		3751	*/
		3752	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
		3753	{
		3754	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
		3755	}
		3756
		3757	/**
		3758	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
		3759	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
		3760	* @param TIMx Timer instance
		3761	* @retval State of bit (1 or 0).
		3762	*/
		3763	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
		3764	{
		3765	return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
		3766	}
		3767
		3768	/**
		3769	* @brief Enable trigger interrupt (TDE).
		3770	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
		3771	* @param TIMx Timer instance
		3772	* @retval None
		3773	*/
		3774	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3775	{
		3776	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
		3777	}
		3778
		3779	/**
		3780	* @brief Disable trigger interrupt (TDE).
		3781	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
		3782	* @param TIMx Timer instance
		3783	* @retval None
		3784	*/
		3785	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
		3786	{
		3787	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
		3788	}
		3789
		3790	/**
		3791	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
		3792	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
		3793	* @param TIMx Timer instance
		3794	* @retval State of bit (1 or 0).
		3795	*/
		3796	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
		3797	{
		3798	return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
		3799	}
		3800
		3801	/**
		3802	* @}
		3803	*/
		3804
		3805	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
		3806	* @{
		3807	*/
		3808	/**
		3809	* @brief Generate an update event.
		3810	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
		3811	* @param TIMx Timer instance
		3812	* @retval None
		3813	*/
		3814	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
		3815	{
		3816	SET_BIT(TIMx->EGR, TIM_EGR_UG);
		3817	}
		3818
		3819	/**
		3820	* @brief Generate Capture/Compare 1 event.
		3821	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
		3822	* @param TIMx Timer instance
		3823	* @retval None
		3824	*/
		3825	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
		3826	{
		3827	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
		3828	}
		3829
		3830	/**
		3831	* @brief Generate Capture/Compare 2 event.
		3832	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
		3833	* @param TIMx Timer instance
		3834	* @retval None
		3835	*/
		3836	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
		3837	{
		3838	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
		3839	}
		3840
		3841	/**
		3842	* @brief Generate Capture/Compare 3 event.
		3843	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
		3844	* @param TIMx Timer instance
		3845	* @retval None
		3846	*/
		3847	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
		3848	{
		3849	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
		3850	}
		3851
		3852	/**
		3853	* @brief Generate Capture/Compare 4 event.
		3854	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
		3855	* @param TIMx Timer instance
		3856	* @retval None
		3857	*/
		3858	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
		3859	{
		3860	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
		3861	}
		3862
		3863	/**
		3864	* @brief Generate commutation event.
		3865	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
		3866	* @param TIMx Timer instance
		3867	* @retval None
		3868	*/
		3869	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
		3870	{
		3871	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
		3872	}
		3873
		3874	/**
		3875	* @brief Generate trigger event.
		3876	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
		3877	* @param TIMx Timer instance
		3878	* @retval None
		3879	*/
		3880	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
		3881	{
		3882	SET_BIT(TIMx->EGR, TIM_EGR_TG);
		3883	}
		3884
		3885	/**
		3886	* @brief Generate break event.
		3887	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
		3888	* @param TIMx Timer instance
		3889	* @retval None
		3890	*/
		3891	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
		3892	{
		3893	SET_BIT(TIMx->EGR, TIM_EGR_BG);
		3894	}
		3895
		3896	/**
		3897	* @}
		3898	*/
		3899
		3900	#if defined(USE_FULL_LL_DRIVER)
		3901	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
		3902	* @{
		3903	*/
		3904
		3905	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
		3906	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
		3907	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
		3908	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
		3909	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
		3910	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
		3911	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
		3912	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
		3913	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
		3914	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
		3915	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
		3916	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
		3917	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
		3918	/**
		3919	* @}
		3920	*/
		3921	#endif /* USE_FULL_LL_DRIVER */
		3922
		3923	/**
		3924	* @}
		3925	*/
		3926
		3927	/**
		3928	* @}
		3929	*/
		3930
		3931	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
		3932
		3933	/**
		3934	* @}
		3935	*/
		3936
		3937	#ifdef __cplusplus
		3938	}
		3939	#endif
		3940
		3941	#endif /* __STM32F0xx_LL_TIM_H */
		3942	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_tim.h – Rev 2