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Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_system.h
		4	* @author MCD Application Team
		5	* @brief Header file of SYSTEM LL module.
		6	@verbatim
		7	==============================================================================
		8	##### How to use this driver #####
		9	==============================================================================
		10	[..]
		11	The LL SYSTEM driver contains a set of generic APIs that can be
		12	used by user:
		13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
		14	(+) Access to DBGCMU registers
		15	(+) Access to SYSCFG registers
		16
		17	@endverbatim
		18	******************************************************************************
		19	* @attention
		20	*
		21	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		22	* All rights reserved.</center></h2>
		23	*
		24	* This software component is licensed by ST under BSD 3-Clause license,
		25	* the "License"; You may not use this file except in compliance with the
		26	* License. You may obtain a copy of the License at:
		27	* opensource.org/licenses/BSD-3-Clause
		28	*
		29	******************************************************************************
		30	*/
		31
		32	/* Define to prevent recursive inclusion -------------------------------------*/
		33	#ifndef __STM32F0xx_LL_SYSTEM_H
		34	#define __STM32F0xx_LL_SYSTEM_H
		35
		36	#ifdef __cplusplus
		37	extern "C" {
		38	#endif
		39
		40	/* Includes ------------------------------------------------------------------*/
		41	#include "stm32f0xx.h"
		42
		43	/** @addtogroup STM32F0xx_LL_Driver
		44	* @{
		45	*/
		46
		47	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
		48
		49	/** @defgroup SYSTEM_LL SYSTEM
		50	* @{
		51	*/
		52
		53	/* Private types -------------------------------------------------------------*/
		54	/* Private variables ---------------------------------------------------------*/
		55
		56	/* Private constants ---------------------------------------------------------*/
		57	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
		58	* @{
		59	*/
		60
		61	/**
		62	* @}
		63	*/
		64
		65	/* Private macros ------------------------------------------------------------*/
		66
		67	/* Exported types ------------------------------------------------------------*/
		68	/* Exported constants --------------------------------------------------------*/
		69	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
		70	* @{
		71	*/
		72
		73	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap
		74	* @{
		75	*/
		76	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /!< Main Flash memory mapped at 0x00000000 /
		77	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
		78	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /!< Embedded SRAM mapped at 0x00000000 /
		79	/**
		80	* @}
		81	*/
		82
		83	#if defined(SYSCFG_CFGR1_IR_MOD)
		84	/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
		85	* @{
		86	*/
		87	#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /!< Timer16 is selected as IR Modulation enveloppe source /
		88	#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /!< USART1 is selected as IR Modulation enveloppe source /
		89	#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /!< USART4 is selected as IR Modulation enveloppe source /
		90	/**
		91	* @}
		92	*/
		93
		94	#endif /* SYSCFG_CFGR1_IR_MOD */
		95
		96	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
		97	/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap
		98	* @{
		99	*/
		100	#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP)
		101	#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_TX DMA request mapped on DMA channel 2U /
		102	#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1TX_DMA_RMP) /!< USART1_TX DMA request mapped on DMA channel 4U /
		103	#endif /SYSCFG_CFGR1_USART1TX_DMA_RMP/
		104	#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP)
		105	#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_RX DMA request mapped on DMA channel 3U /
		106	#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1RX_DMA_RMP) /!< USART1_RX DMA request mapped on DMA channel 5 /
		107	#endif /SYSCFG_CFGR1_USART1RX_DMA_RMP/
		108	#if defined (SYSCFG_CFGR1_USART2_DMA_RMP)
		109	#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively /
		110	#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART2_DMA_RMP) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
		111	#endif /SYSCFG_CFGR1_USART2_DMA_RMP/
		112	#if defined (SYSCFG_CFGR1_USART3_DMA_RMP)
		113	#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively /
		114	#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART3_DMA_RMP) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively /
		115	#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */
		116	/**
		117	* @}
		118	*/
		119	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
		120
		121	#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP)
		122	/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap
		123	* @{
		124	*/
		125	#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively /
		126	#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
		127	/**
		128	* @}
		129	*/
		130
		131	#endif /SYSCFG_CFGR1_SPI2_DMA_RMP/
		132
		133	#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP)
		134	/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap
		135	* @{
		136	*/
		137	#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively /
		138	#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively /
		139	/**
		140	* @}
		141	*/
		142
		143	#endif /SYSCFG_CFGR1_I2C1_DMA_RMP/
		144
		145	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
		146	/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap
		147	* @{
		148	*/
		149	#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /!< ADC DMA request mapped on DMA channel 1U /
		150	#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /!< ADC DMA request mapped on DMA channel 2U /
		151	/**
		152	* @}
		153	*/
		154
		155	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
		156
		157	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
		158	/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap
		159	* @{
		160	*/
		161	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP)
		162	#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2)
		163	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
		164	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
		165	#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP2) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 /
		166	#else
		167	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
		168	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
		169	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */
		170	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */
		171	#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP)
		172	#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2)
		173	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
		174	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
		175	#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP2) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 /
		176	#else
		177	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
		178	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
		179	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */
		180	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */
		181	#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP)
		182	#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively /
		183	#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM1_DMA_RMP) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 /
		184	#endif /SYSCFG_CFGR1_TIM1_DMA_RMP/
		185	#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP)
		186	#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively /
		187	#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM2_DMA_RMP) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 /
		188	#endif /SYSCFG_CFGR1_TIM2_DMA_RMP/
		189	#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP)
		190	#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 /
		191	#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM3_DMA_RMP) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 /
		192	#endif /SYSCFG_CFGR1_TIM3_DMA_RMP/
		193	/**
		194	* @}
		195	*/
		196
		197	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
		198
		199	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
		200	* @{
		201	*/
		202	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /!< I2C PB6 Fast mode plus /
		203	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /!< I2C PB7 Fast mode plus /
		204	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /!< I2C PB8 Fast mode plus /
		205	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /!< I2C PB9 Fast mode plus /
		206	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
		207	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
		208	#endif /SYSCFG_CFGR1_I2C_FMP_I2C1/
		209	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
		210	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /!< Enable I2C2 Fast mode plus /
		211	#endif /SYSCFG_CFGR1_I2C_FMP_I2C2/
		212	#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
		213	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /!< Enable Fast Mode Plus on PA9 /
		214	#endif /SYSCFG_CFGR1_I2C_FMP_PA9/
		215	#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
		216	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /!< Enable Fast Mode Plus on PA10 /
		217	#endif /SYSCFG_CFGR1_I2C_FMP_PA10/
		218	/**
		219	* @}
		220	*/
		221
		222	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
		223	* @{
		224	*/
		225	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /!< EXTI PORT A /
		226	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /!< EXTI PORT B /
		227	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /!< EXTI PORT C /
		228	#if defined(GPIOD_BASE)
		229	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /!< EXTI PORT D /
		230	#endif /GPIOD_BASE/
		231	#if defined(GPIOE_BASE)
		232	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /!< EXTI PORT E /
		233	#endif /GPIOE_BASE/
		234	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /!< EXTI PORT F /
		235	/**
		236	* @}
		237	*/
		238
		239	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
		240	* @{
		241	*/
		242	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
		243	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
		244	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
		245	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
		246	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
		247	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
		248	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
		249	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
		250	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
		251	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
		252	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
		253	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
		254	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
		255	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
		256	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
		257	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
		258	/**
		259	* @}
		260	*/
		261
		262	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
		263	* @{
		264	*/
		265	#if defined(SYSCFG_CFGR2_PVD_LOCK)
		266	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection
		267	with TIM1/15/16U/17 Break Input and also
		268	the PVDE and PLS bits of the Power Control Interface */
		269	#endif /SYSCFG_CFGR2_PVD_LOCK/
		270	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal
		271	with Break Input of TIM1/15/16/17 */
		272	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of
		273	CortexM0 with Break Input of TIM1/15/16/17 */
		274	/**
		275	* @}
		276	*/
		277
		278	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
		279	* @{
		280	*/
		281	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
		282	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
		283	#endif /DBGMCU_APB1_FZ_DBG_TIM2_STOP/
		284	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
		285	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
		286	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
		287	#endif /DBGMCU_APB1_FZ_DBG_TIM6_STOP/
		288	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
		289	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
		290	#endif /DBGMCU_APB1_FZ_DBG_TIM7_STOP/
		291	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
		292	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC Calendar frozen when core is halted /
		293	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
		294	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
		295	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
		296	#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
		297	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /!< CAN debug stopped when Core is halted /
		298	#endif /DBGMCU_APB1_FZ_DBG_CAN_STOP/
		299	/**
		300	* @}
		301	*/
		302
		303	/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
		304	* @{
		305	*/
		306	#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
		307	#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
		308	#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
		309	#endif /DBGMCU_APB2_FZ_DBG_TIM15_STOP/
		310	#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
		311	#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
		312	/**
		313	* @}
		314	*/
		315
		316	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
		317	* @{
		318	*/
		319	#define LL_FLASH_LATENCY_0 0x00000000U /!< FLASH Zero Latency cycle /
		320	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /!< FLASH One Latency cycle /
		321	/**
		322	* @}
		323	*/
		324
		325	/**
		326	* @}
		327	*/
		328
		329	/* Exported macro ------------------------------------------------------------*/
		330
		331	/* Exported functions --------------------------------------------------------*/
		332	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
		333	* @{
		334	*/
		335
		336	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
		337	* @{
		338	*/
		339
		340	/**
		341	* @brief Set memory mapping at address 0x00000000
		342	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
		343	* @param Memory This parameter can be one of the following values:
		344	* @arg @ref LL_SYSCFG_REMAP_FLASH
		345	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
		346	* @arg @ref LL_SYSCFG_REMAP_SRAM
		347	* @retval None
		348	*/
		349	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
		350	{
		351	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
		352	}
		353
		354	/**
		355	* @brief Get memory mapping at address 0x00000000
		356	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
		357	* @retval Returned value can be one of the following values:
		358	* @arg @ref LL_SYSCFG_REMAP_FLASH
		359	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
		360	* @arg @ref LL_SYSCFG_REMAP_SRAM
		361	*/
		362	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
		363	{
		364	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
		365	}
		366
		367	#if defined(SYSCFG_CFGR1_IR_MOD)
		368	/**
		369	* @brief Set IR Modulation Envelope signal source.
		370	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
		371	* @param Source This parameter can be one of the following values:
		372	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
		373	* @arg @ref LL_SYSCFG_IR_MOD_USART1
		374	* @arg @ref LL_SYSCFG_IR_MOD_USART4
		375	* @retval None
		376	*/
		377	__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
		378	{
		379	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
		380	}
		381
		382	/**
		383	* @brief Get IR Modulation Envelope signal source.
		384	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
		385	* @retval Returned value can be one of the following values:
		386	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
		387	* @arg @ref LL_SYSCFG_IR_MOD_USART1
		388	* @arg @ref LL_SYSCFG_IR_MOD_USART4
		389	*/
		390	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
		391	{
		392	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
		393	}
		394	#endif /* SYSCFG_CFGR1_IR_MOD */
		395
		396	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
		397	/**
		398	* @brief Set DMA request remapping bits for USART
		399	* @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
		400	* SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
		401	* SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
		402	* SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART
		403	* @param Remap This parameter can be one of the following values:
		404	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*)
		405	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*)
		406	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*)
		407	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*)
		408	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*)
		409	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*)
		410	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*)
		411	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*)
		412	*
		413	* (*) value not defined in all devices.
		414	* @retval None
		415	*/
		416	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)
		417	{
		418	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
		419	}
		420	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
		421
		422	#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP)
		423	/**
		424	* @brief Set DMA request remapping bits for SPI
		425	* @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
		426	* @param Remap This parameter can be one of the following values:
		427	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45
		428	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67
		429	* @retval None
		430	*/
		431	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
		432	{
		433	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap);
		434	}
		435	#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */
		436
		437	#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP)
		438	/**
		439	* @brief Set DMA request remapping bits for I2C
		440	* @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
		441	* @param Remap This parameter can be one of the following values:
		442	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32
		443	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76
		444	* @retval None
		445	*/
		446	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
		447	{
		448	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap);
		449	}
		450	#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */
		451
		452	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
		453	/**
		454	* @brief Set DMA request remapping bits for ADC
		455	* @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
		456	* @param Remap This parameter can be one of the following values:
		457	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1
		458	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2
		459	* @retval None
		460	*/
		461	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
		462	{
		463	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap);
		464	}
		465	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
		466
		467	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
		468	/**
		469	* @brief Set DMA request remapping bits for TIM
		470	* @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
		471	* SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
		472	* SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
		473	* SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
		474	* SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
		475	* SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
		476	* SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
		477	* @param Remap This parameter can be one of the following values:
		478	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*)
		479	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*)
		480	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*)
		481	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*)
		482	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*)
		483	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*)
		484	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*)
		485	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*)
		486	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*)
		487	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*)
		488	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*)
		489	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*)
		490	*
		491	* (*) value not defined in all devices.
		492	* @retval None
		493	*/
		494	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
		495	{
		496	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
		497	}
		498	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
		499
		500	#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
		501	/**
		502	* @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
		503	* PA9/10 or PA11/12 pin pair on small pin-count packages)
		504	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap
		505	* @retval None
		506	*/
		507	__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void)
		508	{
		509	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
		510	}
		511
		512	/**
		513	* @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
		514	* PA9/10 or PA11/12 pin pair on small pin-count packages)
		515	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap
		516	* @retval None
		517	*/
		518	__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void)
		519	{
		520	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
		521	}
		522	#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
		523
		524	/**
		525	* @brief Enable the I2C fast mode plus driving capability.
		526	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
		527	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
		528	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
		529	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
		530	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
		531	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
		532	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
		533	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
		534	* @param ConfigFastModePlus This parameter can be a combination of the following values:
		535	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
		536	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
		537	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
		538	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
		539	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
		540	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
		541	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
		542	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
		543	*
		544	* (*) value not defined in all devices
		545	* @retval None
		546	*/
		547	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
		548	{
		549	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
		550	}
		551
		552	/**
		553	* @brief Disable the I2C fast mode plus driving capability.
		554	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
		555	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
		556	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
		557	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
		558	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
		559	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
		560	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
		561	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
		562	* @param ConfigFastModePlus This parameter can be a combination of the following values:
		563	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
		564	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
		565	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
		566	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
		567	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
		568	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
		569	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
		570	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
		571	*
		572	* (*) value not defined in all devices
		573	* @retval None
		574	*/
		575	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
		576	{
		577	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
		578	}
		579
		580	/**
		581	* @brief Configure source input for the EXTI external interrupt.
		582	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
		583	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
		584	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
		585	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
		586	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
		587	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
		588	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
		589	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
		590	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
		591	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
		592	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
		593	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
		594	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
		595	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
		596	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
		597	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
		598	* @param Port This parameter can be one of the following values:
		599	* @arg @ref LL_SYSCFG_EXTI_PORTA
		600	* @arg @ref LL_SYSCFG_EXTI_PORTB
		601	* @arg @ref LL_SYSCFG_EXTI_PORTC
		602	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
		603	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
		604	* @arg @ref LL_SYSCFG_EXTI_PORTF
		605	*
		606	* (*) value not defined in all devices
		607	* @param Line This parameter can be one of the following values:
		608	* @arg @ref LL_SYSCFG_EXTI_LINE0
		609	* @arg @ref LL_SYSCFG_EXTI_LINE1
		610	* @arg @ref LL_SYSCFG_EXTI_LINE2
		611	* @arg @ref LL_SYSCFG_EXTI_LINE3
		612	* @arg @ref LL_SYSCFG_EXTI_LINE4
		613	* @arg @ref LL_SYSCFG_EXTI_LINE5
		614	* @arg @ref LL_SYSCFG_EXTI_LINE6
		615	* @arg @ref LL_SYSCFG_EXTI_LINE7
		616	* @arg @ref LL_SYSCFG_EXTI_LINE8
		617	* @arg @ref LL_SYSCFG_EXTI_LINE9
		618	* @arg @ref LL_SYSCFG_EXTI_LINE10
		619	* @arg @ref LL_SYSCFG_EXTI_LINE11
		620	* @arg @ref LL_SYSCFG_EXTI_LINE12
		621	* @arg @ref LL_SYSCFG_EXTI_LINE13
		622	* @arg @ref LL_SYSCFG_EXTI_LINE14
		623	* @arg @ref LL_SYSCFG_EXTI_LINE15
		624	* @retval None
		625	*/
		626	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
		627	{
		628	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16));
		629	}
		630
		631	/**
		632	* @brief Get the configured defined for specific EXTI Line
		633	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
		634	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
		635	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
		636	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
		637	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
		638	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
		639	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
		640	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
		641	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
		642	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
		643	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
		644	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
		645	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
		646	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
		647	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
		648	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
		649	* @param Line This parameter can be one of the following values:
		650	* @arg @ref LL_SYSCFG_EXTI_LINE0
		651	* @arg @ref LL_SYSCFG_EXTI_LINE1
		652	* @arg @ref LL_SYSCFG_EXTI_LINE2
		653	* @arg @ref LL_SYSCFG_EXTI_LINE3
		654	* @arg @ref LL_SYSCFG_EXTI_LINE4
		655	* @arg @ref LL_SYSCFG_EXTI_LINE5
		656	* @arg @ref LL_SYSCFG_EXTI_LINE6
		657	* @arg @ref LL_SYSCFG_EXTI_LINE7
		658	* @arg @ref LL_SYSCFG_EXTI_LINE8
		659	* @arg @ref LL_SYSCFG_EXTI_LINE9
		660	* @arg @ref LL_SYSCFG_EXTI_LINE10
		661	* @arg @ref LL_SYSCFG_EXTI_LINE11
		662	* @arg @ref LL_SYSCFG_EXTI_LINE12
		663	* @arg @ref LL_SYSCFG_EXTI_LINE13
		664	* @arg @ref LL_SYSCFG_EXTI_LINE14
		665	* @arg @ref LL_SYSCFG_EXTI_LINE15
		666	* @retval Returned value can be one of the following values:
		667	* @arg @ref LL_SYSCFG_EXTI_PORTA
		668	* @arg @ref LL_SYSCFG_EXTI_PORTB
		669	* @arg @ref LL_SYSCFG_EXTI_PORTC
		670	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
		671	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
		672	* @arg @ref LL_SYSCFG_EXTI_PORTF
		673	*
		674	* (*) value not defined in all devices
		675	*/
		676	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
		677	{
		678	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16));
		679	}
		680
		681	#if defined(SYSCFG_ITLINE0_SR_EWDG)
		682	/**
		683	* @brief Check if Window watchdog interrupt occurred or not.
		684	* @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
		685	* @retval State of bit (1 or 0).
		686	*/
		687	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
		688	{
		689	return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG));
		690	}
		691	#endif /* SYSCFG_ITLINE0_SR_EWDG */
		692
		693	#if defined(SYSCFG_ITLINE1_SR_PVDOUT)
		694	/**
		695	* @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
		696	* @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
		697	* @retval State of bit (1 or 0).
		698	*/
		699	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
		700	{
		701	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT));
		702	}
		703	#endif /* SYSCFG_ITLINE1_SR_PVDOUT */
		704
		705	#if defined(SYSCFG_ITLINE1_SR_VDDIO2)
		706	/**
		707	* @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31).
		708	* @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2
		709	* @retval State of bit (1 or 0).
		710	*/
		711	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void)
		712	{
		713	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2));
		714	}
		715	#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */
		716
		717	#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP)
		718	/**
		719	* @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20).
		720	* @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
		721	* @retval State of bit (1 or 0).
		722	*/
		723	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
		724	{
		725	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP));
		726	}
		727	#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */
		728
		729	#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP)
		730	/**
		731	* @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19).
		732	* @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP
		733	* @retval State of bit (1 or 0).
		734	*/
		735	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)
		736	{
		737	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP));
		738	}
		739	#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */
		740
		741	#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA)
		742	/**
		743	* @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17).
		744	* @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA
		745	* @retval State of bit (1 or 0).
		746	*/
		747	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)
		748	{
		749	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA));
		750	}
		751	#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */
		752
		753	#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
		754	/**
		755	* @brief Check if Flash interface interrupt occurred or not.
		756	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
		757	* @retval State of bit (1 or 0).
		758	*/
		759	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
		760	{
		761	return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF));
		762	}
		763	#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
		764
		765	#if defined(SYSCFG_ITLINE4_SR_CRS)
		766	/**
		767	* @brief Check if Clock recovery system interrupt occurred or not.
		768	* @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
		769	* @retval State of bit (1 or 0).
		770	*/
		771	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
		772	{
		773	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS));
		774	}
		775	#endif /* SYSCFG_ITLINE4_SR_CRS */
		776
		777	#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
		778	/**
		779	* @brief Check if Reset and clock control interrupt occurred or not.
		780	* @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
		781	* @retval State of bit (1 or 0).
		782	*/
		783	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
		784	{
		785	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL));
		786	}
		787	#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
		788
		789	#if defined(SYSCFG_ITLINE5_SR_EXTI0)
		790	/**
		791	* @brief Check if EXTI line 0 interrupt occurred or not.
		792	* @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
		793	* @retval State of bit (1 or 0).
		794	*/
		795	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
		796	{
		797	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0));
		798	}
		799	#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
		800
		801	#if defined(SYSCFG_ITLINE5_SR_EXTI1)
		802	/**
		803	* @brief Check if EXTI line 1 interrupt occurred or not.
		804	* @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
		805	* @retval State of bit (1 or 0).
		806	*/
		807	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
		808	{
		809	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1));
		810	}
		811	#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
		812
		813	#if defined(SYSCFG_ITLINE6_SR_EXTI2)
		814	/**
		815	* @brief Check if EXTI line 2 interrupt occurred or not.
		816	* @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
		817	* @retval State of bit (1 or 0).
		818	*/
		819	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
		820	{
		821	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2));
		822	}
		823	#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
		824
		825	#if defined(SYSCFG_ITLINE6_SR_EXTI3)
		826	/**
		827	* @brief Check if EXTI line 3 interrupt occurred or not.
		828	* @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
		829	* @retval State of bit (1 or 0).
		830	*/
		831	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
		832	{
		833	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3));
		834	}
		835	#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
		836
		837	#if defined(SYSCFG_ITLINE7_SR_EXTI4)
		838	/**
		839	* @brief Check if EXTI line 4 interrupt occurred or not.
		840	* @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
		841	* @retval State of bit (1 or 0).
		842	*/
		843	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
		844	{
		845	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4));
		846	}
		847	#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
		848
		849	#if defined(SYSCFG_ITLINE7_SR_EXTI5)
		850	/**
		851	* @brief Check if EXTI line 5 interrupt occurred or not.
		852	* @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
		853	* @retval State of bit (1 or 0).
		854	*/
		855	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
		856	{
		857	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5));
		858	}
		859	#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
		860
		861	#if defined(SYSCFG_ITLINE7_SR_EXTI6)
		862	/**
		863	* @brief Check if EXTI line 6 interrupt occurred or not.
		864	* @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
		865	* @retval State of bit (1 or 0).
		866	*/
		867	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
		868	{
		869	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6));
		870	}
		871	#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
		872
		873	#if defined(SYSCFG_ITLINE7_SR_EXTI7)
		874	/**
		875	* @brief Check if EXTI line 7 interrupt occurred or not.
		876	* @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
		877	* @retval State of bit (1 or 0).
		878	*/
		879	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
		880	{
		881	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7));
		882	}
		883	#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
		884
		885	#if defined(SYSCFG_ITLINE7_SR_EXTI8)
		886	/**
		887	* @brief Check if EXTI line 8 interrupt occurred or not.
		888	* @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
		889	* @retval State of bit (1 or 0).
		890	*/
		891	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
		892	{
		893	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8));
		894	}
		895	#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
		896
		897	#if defined(SYSCFG_ITLINE7_SR_EXTI9)
		898	/**
		899	* @brief Check if EXTI line 9 interrupt occurred or not.
		900	* @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
		901	* @retval State of bit (1 or 0).
		902	*/
		903	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
		904	{
		905	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9));
		906	}
		907	#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
		908
		909	#if defined(SYSCFG_ITLINE7_SR_EXTI10)
		910	/**
		911	* @brief Check if EXTI line 10 interrupt occurred or not.
		912	* @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
		913	* @retval State of bit (1 or 0).
		914	*/
		915	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
		916	{
		917	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10));
		918	}
		919	#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
		920
		921	#if defined(SYSCFG_ITLINE7_SR_EXTI11)
		922	/**
		923	* @brief Check if EXTI line 11 interrupt occurred or not.
		924	* @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
		925	* @retval State of bit (1 or 0).
		926	*/
		927	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
		928	{
		929	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11));
		930	}
		931	#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
		932
		933	#if defined(SYSCFG_ITLINE7_SR_EXTI12)
		934	/**
		935	* @brief Check if EXTI line 12 interrupt occurred or not.
		936	* @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
		937	* @retval State of bit (1 or 0).
		938	*/
		939	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
		940	{
		941	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12));
		942	}
		943	#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
		944
		945	#if defined(SYSCFG_ITLINE7_SR_EXTI13)
		946	/**
		947	* @brief Check if EXTI line 13 interrupt occurred or not.
		948	* @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
		949	* @retval State of bit (1 or 0).
		950	*/
		951	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
		952	{
		953	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13));
		954	}
		955	#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
		956
		957	#if defined(SYSCFG_ITLINE7_SR_EXTI14)
		958	/**
		959	* @brief Check if EXTI line 14 interrupt occurred or not.
		960	* @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
		961	* @retval State of bit (1 or 0).
		962	*/
		963	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
		964	{
		965	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14));
		966	}
		967	#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
		968
		969	#if defined(SYSCFG_ITLINE7_SR_EXTI15)
		970	/**
		971	* @brief Check if EXTI line 15 interrupt occurred or not.
		972	* @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
		973	* @retval State of bit (1 or 0).
		974	*/
		975	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
		976	{
		977	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15));
		978	}
		979	#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
		980
		981	#if defined(SYSCFG_ITLINE8_SR_TSC_EOA)
		982	/**
		983	* @brief Check if Touch sensing controller end of acquisition interrupt occurred or not.
		984	* @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
		985	* @retval State of bit (1 or 0).
		986	*/
		987	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
		988	{
		989	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA));
		990	}
		991	#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */
		992
		993	#if defined(SYSCFG_ITLINE8_SR_TSC_MCE)
		994	/**
		995	* @brief Check if Touch sensing controller max counterror interrupt occurred or not.
		996	* @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
		997	* @retval State of bit (1 or 0).
		998	*/
		999	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
		1000	{
		1001	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE));
		1002	}
		1003	#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */
		1004
		1005	#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
		1006	/**
		1007	* @brief Check if DMA1 channel 1 interrupt occurred or not.
		1008	* @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
		1009	* @retval State of bit (1 or 0).
		1010	*/
		1011	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
		1012	{
		1013	return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1));
		1014	}
		1015	#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
		1016
		1017	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
		1018	/**
		1019	* @brief Check if DMA1 channel 2 interrupt occurred or not.
		1020	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
		1021	* @retval State of bit (1 or 0).
		1022	*/
		1023	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
		1024	{
		1025	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2));
		1026	}
		1027	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
		1028
		1029	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
		1030	/**
		1031	* @brief Check if DMA1 channel 3 interrupt occurred or not.
		1032	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
		1033	* @retval State of bit (1 or 0).
		1034	*/
		1035	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
		1036	{
		1037	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3));
		1038	}
		1039	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
		1040
		1041	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1)
		1042	/**
		1043	* @brief Check if DMA2 channel 1 interrupt occurred or not.
		1044	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
		1045	* @retval State of bit (1 or 0).
		1046	*/
		1047	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
		1048	{
		1049	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1));
		1050	}
		1051	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */
		1052
		1053	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2)
		1054	/**
		1055	* @brief Check if DMA2 channel 2 interrupt occurred or not.
		1056	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
		1057	* @retval State of bit (1 or 0).
		1058	*/
		1059	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
		1060	{
		1061	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2));
		1062	}
		1063	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */
		1064
		1065	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
		1066	/**
		1067	* @brief Check if DMA1 channel 4 interrupt occurred or not.
		1068	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
		1069	* @retval State of bit (1 or 0).
		1070	*/
		1071	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
		1072	{
		1073	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4));
		1074	}
		1075	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
		1076
		1077	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
		1078	/**
		1079	* @brief Check if DMA1 channel 5 interrupt occurred or not.
		1080	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
		1081	* @retval State of bit (1 or 0).
		1082	*/
		1083	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
		1084	{
		1085	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5));
		1086	}
		1087	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
		1088
		1089	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
		1090	/**
		1091	* @brief Check if DMA1 channel 6 interrupt occurred or not.
		1092	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
		1093	* @retval State of bit (1 or 0).
		1094	*/
		1095	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
		1096	{
		1097	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6));
		1098	}
		1099	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
		1100
		1101	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
		1102	/**
		1103	* @brief Check if DMA1 channel 7 interrupt occurred or not.
		1104	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
		1105	* @retval State of bit (1 or 0).
		1106	*/
		1107	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
		1108	{
		1109	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7));
		1110	}
		1111	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
		1112
		1113	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
		1114	/**
		1115	* @brief Check if DMA2 channel 3 interrupt occurred or not.
		1116	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
		1117	* @retval State of bit (1 or 0).
		1118	*/
		1119	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
		1120	{
		1121	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3));
		1122	}
		1123	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
		1124
		1125	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
		1126	/**
		1127	* @brief Check if DMA2 channel 4 interrupt occurred or not.
		1128	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
		1129	* @retval State of bit (1 or 0).
		1130	*/
		1131	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
		1132	{
		1133	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4));
		1134	}
		1135	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
		1136
		1137	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
		1138	/**
		1139	* @brief Check if DMA2 channel 5 interrupt occurred or not.
		1140	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
		1141	* @retval State of bit (1 or 0).
		1142	*/
		1143	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
		1144	{
		1145	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5));
		1146	}
		1147	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
		1148
		1149	#if defined(SYSCFG_ITLINE12_SR_ADC)
		1150	/**
		1151	* @brief Check if ADC interrupt occurred or not.
		1152	* @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
		1153	* @retval State of bit (1 or 0).
		1154	*/
		1155	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
		1156	{
		1157	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC));
		1158	}
		1159	#endif /* SYSCFG_ITLINE12_SR_ADC */
		1160
		1161	#if defined(SYSCFG_ITLINE12_SR_COMP1)
		1162	/**
		1163	* @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21).
		1164	* @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
		1165	* @retval State of bit (1 or 0).
		1166	*/
		1167	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
		1168	{
		1169	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1));
		1170	}
		1171	#endif /* SYSCFG_ITLINE12_SR_COMP1 */
		1172
		1173	#if defined(SYSCFG_ITLINE12_SR_COMP2)
		1174	/**
		1175	* @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22).
		1176	* @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
		1177	* @retval State of bit (1 or 0).
		1178	*/
		1179	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
		1180	{
		1181	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2));
		1182	}
		1183	#endif /* SYSCFG_ITLINE12_SR_COMP2 */
		1184
		1185	#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
		1186	/**
		1187	* @brief Check if Timer 1 break interrupt occurred or not.
		1188	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
		1189	* @retval State of bit (1 or 0).
		1190	*/
		1191	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
		1192	{
		1193	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK));
		1194	}
		1195	#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
		1196
		1197	#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
		1198	/**
		1199	* @brief Check if Timer 1 update interrupt occurred or not.
		1200	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
		1201	* @retval State of bit (1 or 0).
		1202	*/
		1203	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
		1204	{
		1205	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD));
		1206	}
		1207	#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
		1208
		1209	#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
		1210	/**
		1211	* @brief Check if Timer 1 trigger interrupt occurred or not.
		1212	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
		1213	* @retval State of bit (1 or 0).
		1214	*/
		1215	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
		1216	{
		1217	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG));
		1218	}
		1219	#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
		1220
		1221	#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
		1222	/**
		1223	* @brief Check if Timer 1 commutation interrupt occurred or not.
		1224	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
		1225	* @retval State of bit (1 or 0).
		1226	*/
		1227	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
		1228	{
		1229	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU));
		1230	}
		1231	#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
		1232
		1233	#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
		1234	/**
		1235	* @brief Check if Timer 1 capture compare interrupt occurred or not.
		1236	* @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
		1237	* @retval State of bit (1 or 0).
		1238	*/
		1239	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
		1240	{
		1241	return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC));
		1242	}
		1243	#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
		1244
		1245	#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
		1246	/**
		1247	* @brief Check if Timer 2 interrupt occurred or not.
		1248	* @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
		1249	* @retval State of bit (1 or 0).
		1250	*/
		1251	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
		1252	{
		1253	return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB));
		1254	}
		1255	#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
		1256
		1257	#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
		1258	/**
		1259	* @brief Check if Timer 3 interrupt occurred or not.
		1260	* @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
		1261	* @retval State of bit (1 or 0).
		1262	*/
		1263	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
		1264	{
		1265	return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB));
		1266	}
		1267	#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
		1268
		1269	#if defined(SYSCFG_ITLINE17_SR_DAC)
		1270	/**
		1271	* @brief Check if DAC underrun interrupt occurred or not.
		1272	* @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
		1273	* @retval State of bit (1 or 0).
		1274	*/
		1275	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
		1276	{
		1277	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC));
		1278	}
		1279	#endif /* SYSCFG_ITLINE17_SR_DAC */
		1280
		1281	#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
		1282	/**
		1283	* @brief Check if Timer 6 interrupt occurred or not.
		1284	* @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
		1285	* @retval State of bit (1 or 0).
		1286	*/
		1287	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
		1288	{
		1289	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB));
		1290	}
		1291	#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
		1292
		1293	#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
		1294	/**
		1295	* @brief Check if Timer 7 interrupt occurred or not.
		1296	* @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
		1297	* @retval State of bit (1 or 0).
		1298	*/
		1299	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
		1300	{
		1301	return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB));
		1302	}
		1303	#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
		1304
		1305	#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
		1306	/**
		1307	* @brief Check if Timer 14 interrupt occurred or not.
		1308	* @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
		1309	* @retval State of bit (1 or 0).
		1310	*/
		1311	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
		1312	{
		1313	return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB));
		1314	}
		1315	#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
		1316
		1317	#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
		1318	/**
		1319	* @brief Check if Timer 15 interrupt occurred or not.
		1320	* @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
		1321	* @retval State of bit (1 or 0).
		1322	*/
		1323	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
		1324	{
		1325	return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB));
		1326	}
		1327	#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
		1328
		1329	#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
		1330	/**
		1331	* @brief Check if Timer 16 interrupt occurred or not.
		1332	* @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
		1333	* @retval State of bit (1 or 0).
		1334	*/
		1335	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
		1336	{
		1337	return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB));
		1338	}
		1339	#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
		1340
		1341	#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
		1342	/**
		1343	* @brief Check if Timer 17 interrupt occurred or not.
		1344	* @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
		1345	* @retval State of bit (1 or 0).
		1346	*/
		1347	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
		1348	{
		1349	return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB));
		1350	}
		1351	#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
		1352
		1353	#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
		1354	/**
		1355	* @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
		1356	* @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
		1357	* @retval State of bit (1 or 0).
		1358	*/
		1359	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
		1360	{
		1361	return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB));
		1362	}
		1363	#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
		1364
		1365	#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
		1366	/**
		1367	* @brief Check if I2C2 interrupt occurred or not.
		1368	* @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
		1369	* @retval State of bit (1 or 0).
		1370	*/
		1371	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
		1372	{
		1373	return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB));
		1374	}
		1375	#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
		1376
		1377	#if defined(SYSCFG_ITLINE25_SR_SPI1)
		1378	/**
		1379	* @brief Check if SPI1 interrupt occurred or not.
		1380	* @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
		1381	* @retval State of bit (1 or 0).
		1382	*/
		1383	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
		1384	{
		1385	return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1));
		1386	}
		1387	#endif /* SYSCFG_ITLINE25_SR_SPI1 */
		1388
		1389	#if defined(SYSCFG_ITLINE26_SR_SPI2)
		1390	/**
		1391	* @brief Check if SPI2 interrupt occurred or not.
		1392	* @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
		1393	* @retval State of bit (1 or 0).
		1394	*/
		1395	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
		1396	{
		1397	return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2));
		1398	}
		1399	#endif /* SYSCFG_ITLINE26_SR_SPI2 */
		1400
		1401	#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
		1402	/**
		1403	* @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
		1404	* @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
		1405	* @retval State of bit (1 or 0).
		1406	*/
		1407	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
		1408	{
		1409	return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB));
		1410	}
		1411	#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
		1412
		1413	#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
		1414	/**
		1415	* @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
		1416	* @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
		1417	* @retval State of bit (1 or 0).
		1418	*/
		1419	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
		1420	{
		1421	return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB));
		1422	}
		1423	#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
		1424
		1425	#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
		1426	/**
		1427	* @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
		1428	* @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
		1429	* @retval State of bit (1 or 0).
		1430	*/
		1431	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
		1432	{
		1433	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB));
		1434	}
		1435	#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
		1436
		1437	#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
		1438	/**
		1439	* @brief Check if USART4 interrupt occurred or not.
		1440	* @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
		1441	* @retval State of bit (1 or 0).
		1442	*/
		1443	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
		1444	{
		1445	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB));
		1446	}
		1447	#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
		1448
		1449	#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
		1450	/**
		1451	* @brief Check if USART5 interrupt occurred or not.
		1452	* @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
		1453	* @retval State of bit (1 or 0).
		1454	*/
		1455	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
		1456	{
		1457	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB));
		1458	}
		1459	#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
		1460
		1461	#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
		1462	/**
		1463	* @brief Check if USART6 interrupt occurred or not.
		1464	* @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
		1465	* @retval State of bit (1 or 0).
		1466	*/
		1467	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
		1468	{
		1469	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB));
		1470	}
		1471	#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
		1472
		1473	#if defined(SYSCFG_ITLINE29_SR_USART7_GLB)
		1474	/**
		1475	* @brief Check if USART7 interrupt occurred or not.
		1476	* @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7
		1477	* @retval State of bit (1 or 0).
		1478	*/
		1479	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void)
		1480	{
		1481	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB));
		1482	}
		1483	#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */
		1484
		1485	#if defined(SYSCFG_ITLINE29_SR_USART8_GLB)
		1486	/**
		1487	* @brief Check if USART8 interrupt occurred or not.
		1488	* @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8
		1489	* @retval State of bit (1 or 0).
		1490	*/
		1491	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void)
		1492	{
		1493	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB));
		1494	}
		1495	#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */
		1496
		1497	#if defined(SYSCFG_ITLINE30_SR_CAN)
		1498	/**
		1499	* @brief Check if CAN interrupt occurred or not.
		1500	* @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN
		1501	* @retval State of bit (1 or 0).
		1502	*/
		1503	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void)
		1504	{
		1505	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN));
		1506	}
		1507	#endif /* SYSCFG_ITLINE30_SR_CAN */
		1508
		1509	#if defined(SYSCFG_ITLINE30_SR_CEC)
		1510	/**
		1511	* @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
		1512	* @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
		1513	* @retval State of bit (1 or 0).
		1514	*/
		1515	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
		1516	{
		1517	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC));
		1518	}
		1519	#endif /* SYSCFG_ITLINE30_SR_CEC */
		1520
		1521	/**
		1522	* @brief Set connections to TIMx Break inputs
		1523	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
		1524	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
		1525	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
		1526	* @param Break This parameter can be a combination of the following values:
		1527	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
		1528	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
		1529	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
		1530	*
		1531	* (*) value not defined in all devices
		1532	* @retval None
		1533	*/
		1534	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
		1535	{
		1536	#if defined(SYSCFG_CFGR2_PVD_LOCK)
		1537	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
		1538	#else
		1539	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break);
		1540	#endif /SYSCFG_CFGR2_PVD_LOCK/
		1541	}
		1542
		1543	/**
		1544	* @brief Get connections to TIMx Break inputs
		1545	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
		1546	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
		1547	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
		1548	* @retval Returned value can be can be a combination of the following values:
		1549	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
		1550	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
		1551	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
		1552	*
		1553	* (*) value not defined in all devices
		1554	*/
		1555	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
		1556	{
		1557	#if defined(SYSCFG_CFGR2_PVD_LOCK)
		1558	return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
		1559	SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
		1560	#else
		1561	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK));
		1562	#endif /SYSCFG_CFGR2_PVD_LOCK/
		1563	}
		1564
		1565	/**
		1566	* @brief Check if SRAM parity error detected
		1567	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP
		1568	* @retval State of bit (1 or 0).
		1569	*/
		1570	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
		1571	{
		1572	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF));
		1573	}
		1574
		1575	/**
		1576	* @brief Clear SRAM parity error flag
		1577	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP
		1578	* @retval None
		1579	*/
		1580	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
		1581	{
		1582	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF);
		1583	}
		1584
		1585	/**
		1586	* @}
		1587	*/
		1588
		1589	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
		1590	* @{
		1591	*/
		1592
		1593	/**
		1594	* @brief Return the device identifier
		1595	* @note For STM32F03x devices, the device ID is 0x444
		1596	* @note For STM32F04x devices, the device ID is 0x445.
		1597	* @note For STM32F05x devices, the device ID is 0x440
		1598	* @note For STM32F07x devices, the device ID is 0x448
		1599	* @note For STM32F09x devices, the device ID is 0x442
		1600	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
		1601	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
		1602	*/
		1603	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
		1604	{
		1605	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
		1606	}
		1607
		1608	/**
		1609	* @brief Return the device revision identifier
		1610	* @note This field indicates the revision of the device.
		1611	For example, it is read as 0x1000 for Revision 1.0.
		1612	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
		1613	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
		1614	*/
		1615	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
		1616	{
		1617	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
		1618	}
		1619
		1620	/**
		1621	* @brief Enable the Debug Module during STOP mode
		1622	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
		1623	* @retval None
		1624	*/
		1625	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
		1626	{
		1627	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
		1628	}
		1629
		1630	/**
		1631	* @brief Disable the Debug Module during STOP mode
		1632	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
		1633	* @retval None
		1634	*/
		1635	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
		1636	{
		1637	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
		1638	}
		1639
		1640	/**
		1641	* @brief Enable the Debug Module during STANDBY mode
		1642	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
		1643	* @retval None
		1644	*/
		1645	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
		1646	{
		1647	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
		1648	}
		1649
		1650	/**
		1651	* @brief Disable the Debug Module during STANDBY mode
		1652	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
		1653	* @retval None
		1654	*/
		1655	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
		1656	{
		1657	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
		1658	}
		1659
		1660	/**
		1661	* @brief Freeze APB1 peripherals (group1 peripherals)
		1662	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1663	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1664	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1665	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1666	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1667	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1668	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1669	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1670	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
		1671	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
		1672	* @param Periphs This parameter can be a combination of the following values:
		1673	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
		1674	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
		1675	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
		1676	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
		1677	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
		1678	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
		1679	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
		1680	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
		1681	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
		1682	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
		1683	*
		1684	* (*) value not defined in all devices
		1685	* @retval None
		1686	*/
		1687	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
		1688	{
		1689	SET_BIT(DBGMCU->APB1FZ, Periphs);
		1690	}
		1691
		1692	/**
		1693	* @brief Unfreeze APB1 peripherals (group1 peripherals)
		1694	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1695	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1696	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1697	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1698	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1699	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1700	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1701	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1702	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
		1703	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
		1704	* @param Periphs This parameter can be a combination of the following values:
		1705	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
		1706	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
		1707	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
		1708	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
		1709	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
		1710	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
		1711	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
		1712	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
		1713	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
		1714	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
		1715	*
		1716	* (*) value not defined in all devices
		1717	* @retval None
		1718	*/
		1719	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
		1720	{
		1721	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
		1722	}
		1723
		1724	/**
		1725	* @brief Freeze APB1 peripherals (group2 peripherals)
		1726	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
		1727	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
		1728	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
		1729	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
		1730	* @param Periphs This parameter can be a combination of the following values:
		1731	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
		1732	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
		1733	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
		1734	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
		1735	*
		1736	* (*) value not defined in all devices
		1737	* @retval None
		1738	*/
		1739	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
		1740	{
		1741	SET_BIT(DBGMCU->APB2FZ, Periphs);
		1742	}
		1743
		1744	/**
		1745	* @brief Unfreeze APB1 peripherals (group2 peripherals)
		1746	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
		1747	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
		1748	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
		1749	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
		1750	* @param Periphs This parameter can be a combination of the following values:
		1751	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
		1752	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
		1753	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
		1754	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
		1755	*
		1756	* (*) value not defined in all devices
		1757	* @retval None
		1758	*/
		1759	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
		1760	{
		1761	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
		1762	}
		1763	/**
		1764	* @}
		1765	*/
		1766
		1767	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
		1768	* @{
		1769	*/
		1770
		1771	/**
		1772	* @brief Set FLASH Latency
		1773	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
		1774	* @param Latency This parameter can be one of the following values:
		1775	* @arg @ref LL_FLASH_LATENCY_0
		1776	* @arg @ref LL_FLASH_LATENCY_1
		1777	* @retval None
		1778	*/
		1779	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
		1780	{
		1781	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
		1782	}
		1783
		1784	/**
		1785	* @brief Get FLASH Latency
		1786	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
		1787	* @retval Returned value can be one of the following values:
		1788	* @arg @ref LL_FLASH_LATENCY_0
		1789	* @arg @ref LL_FLASH_LATENCY_1
		1790	*/
		1791	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
		1792	{
		1793	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
		1794	}
		1795
		1796	/**
		1797	* @brief Enable Prefetch
		1798	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
		1799	* @retval None
		1800	*/
		1801	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
		1802	{
		1803	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
		1804	}
		1805
		1806	/**
		1807	* @brief Disable Prefetch
		1808	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
		1809	* @retval None
		1810	*/
		1811	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
		1812	{
		1813	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
		1814	}
		1815
		1816	/**
		1817	* @brief Check if Prefetch buffer is enabled
		1818	* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
		1819	* @retval State of bit (1 or 0).
		1820	*/
		1821	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
		1822	{
		1823	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
		1824	}
		1825
		1826
		1827
		1828	/**
		1829	* @}
		1830	*/
		1831
		1832	/**
		1833	* @}
		1834	*/
		1835
		1836	/**
		1837	* @}
		1838	*/
		1839
		1840	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
		1841
		1842	/**
		1843	* @}
		1844	*/
		1845
		1846	#ifdef __cplusplus
		1847	}
		1848	#endif
		1849
		1850	#endif /* __STM32F0xx_LL_SYSTEM_H */
		1851
		1852	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_system.h – Rev 2