WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_spi.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_spi.h
		4	* @author MCD Application Team
		5	* @brief Header file of SPI LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef STM32F0xx_LL_SPI_H
		22	#define STM32F0xx_LL_SPI_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f0xx.h"
		30
		31	/** @addtogroup STM32F0xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (SPI1) \|\| defined (SPI2)
		36
		37	/** @defgroup SPI_LL SPI
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43	/* Private macros ------------------------------------------------------------*/
		44
		45	/* Exported types ------------------------------------------------------------*/
		46	#if defined(USE_FULL_LL_DRIVER)
		47	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
		48	* @{
		49	*/
		50
		51	/**
		52	* @brief SPI Init structures definition
		53	*/
		54	typedef struct
		55	{
		56	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
		57	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
		58
		59	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
		60
		61	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
		62	This parameter can be a value of @ref SPI_LL_EC_MODE.
		63
		64	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
		65
		66	uint32_t DataWidth; /*!< Specifies the SPI data width.
		67	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
		68
		69	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
		70
		71	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
		72	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
		73
		74	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
		75
		76	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
		77	This parameter can be a value of @ref SPI_LL_EC_PHASE.
		78
		79	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
		80
		81	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
		82	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
		83
		84	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
		85
		86	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
		87	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
		88	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
		89
		90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
		91
		92	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
		93	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
		94
		95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
		96
		97	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
		98	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
		99
		100	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
		101
		102	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
		103	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
		104
		105	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
		106
		107	} LL_SPI_InitTypeDef;
		108
		109	/**
		110	* @}
		111	*/
		112	#endif /* USE_FULL_LL_DRIVER */
		113
		114	/* Exported constants --------------------------------------------------------*/
		115	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
		116	* @{
		117	*/
		118
		119	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
		120	* @brief Flags defines which can be used with LL_SPI_ReadReg function
		121	* @{
		122	*/
		123	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
		124	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
		125	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
		126	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
		127	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
		128	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
		129	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
		130	/**
		131	* @}
		132	*/
		133
		134	/** @defgroup SPI_LL_EC_IT IT Defines
		135	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
		136	* @{
		137	*/
		138	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
		139	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
		140	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
		141	/**
		142	* @}
		143	*/
		144
		145	/** @defgroup SPI_LL_EC_MODE Operation Mode
		146	* @{
		147	*/
		148	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
		149	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
		150	/**
		151	* @}
		152	*/
		153
		154	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
		155	* @{
		156	*/
		157	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
		158	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
		159	/**
		160	* @}
		161	*/
		162
		163	/** @defgroup SPI_LL_EC_PHASE Clock Phase
		164	* @{
		165	*/
		166	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
		167	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
		168	/**
		169	* @}
		170	*/
		171
		172	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
		173	* @{
		174	*/
		175	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
		176	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
		177	/**
		178	* @}
		179	*/
		180
		181	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
		182	* @{
		183	*/
		184	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
		185	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
		186	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
		187	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
		188	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
		189	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
		190	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
		191	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
		192	/**
		193	* @}
		194	*/
		195
		196	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
		197	* @{
		198	*/
		199	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
		200	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
		201	/**
		202	* @}
		203	*/
		204
		205	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
		206	* @{
		207	*/
		208	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
		209	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
		210	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
		211	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
		212	/**
		213	* @}
		214	*/
		215
		216	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
		217	* @{
		218	*/
		219	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
		220	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
		221	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
		222	/**
		223	* @}
		224	*/
		225
		226	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
		227	* @{
		228	*/
		229	#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 4 bits /
		230	#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /!< Data length for SPI transfer: 5 bits /
		231	#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 6 bits /
		232	#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 7 bits /
		233	#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 8 bits /
		234	#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /!< Data length for SPI transfer: 9 bits /
		235	#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 10 bits /
		236	#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 11 bits /
		237	#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 12 bits /
		238	#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2) /!< Data length for SPI transfer: 13 bits /
		239	#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 14 bits /
		240	#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1) /!< Data length for SPI transfer: 15 bits /
		241	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 \| SPI_CR2_DS_2 \| SPI_CR2_DS_1 \| SPI_CR2_DS_0) /!< Data length for SPI transfer: 16 bits /
		242	/**
		243	* @}
		244	*/
		245	#if defined(USE_FULL_LL_DRIVER)
		246
		247	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
		248	* @{
		249	*/
		250	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
		251	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
		252	/**
		253	* @}
		254	*/
		255	#endif /* USE_FULL_LL_DRIVER */
		256
		257	/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
		258	* @{
		259	*/
		260	#define LL_SPI_CRC_8BIT 0x00000000U /!< 8-bit CRC length /
		261	#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /!< 16-bit CRC length /
		262	/**
		263	* @}
		264	*/
		265
		266	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
		267	* @{
		268	*/
		269	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /
		270	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /
		271	/**
		272	* @}
		273	*/
		274
		275	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
		276	* @{
		277	*/
		278	#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /!< FIFO reception empty /
		279	#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /!< FIFO reception 1/4 /
		280	#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /!< FIFO reception 1/2 /
		281	#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 \| SPI_SR_FRLVL_0) /!< FIFO reception full /
		282	/**
		283	* @}
		284	*/
		285
		286	/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
		287	* @{
		288	*/
		289	#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /!< FIFO transmission empty /
		290	#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /!< FIFO transmission 1/4 /
		291	#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /!< FIFO transmission 1/2 /
		292	#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 \| SPI_SR_FTLVL_0) /!< FIFO transmission full /
		293	/**
		294	* @}
		295	*/
		296
		297	/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
		298	* @{
		299	*/
		300	#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /!< Select DMA parity Even /
		301	#define LL_SPI_DMA_PARITY_ODD 0x00000001U /!< Select DMA parity Odd /
		302
		303	/**
		304	* @}
		305	*/
		306
		307	/**
		308	* @}
		309	*/
		310
		311	/* Exported macro ------------------------------------------------------------*/
		312	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
		313	* @{
		314	*/
		315
		316	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
		317	* @{
		318	*/
		319
		320	/**
		321	* @brief Write a value in SPI register
		322	* @param __INSTANCE__ SPI Instance
		323	* @param __REG__ Register to be written
		324	* @param __VALUE__ Value to be written in the register
		325	* @retval None
		326	*/
		327	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		328
		329	/**
		330	* @brief Read a value in SPI register
		331	* @param __INSTANCE__ SPI Instance
		332	* @param __REG__ Register to be read
		333	* @retval Register value
		334	*/
		335	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		336	/**
		337	* @}
		338	*/
		339
		340	/**
		341	* @}
		342	*/
		343
		344	/* Exported functions --------------------------------------------------------*/
		345	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
		346	* @{
		347	*/
		348
		349	/** @defgroup SPI_LL_EF_Configuration Configuration
		350	* @{
		351	*/
		352
		353	/**
		354	* @brief Enable SPI peripheral
		355	* @rmtoll CR1 SPE LL_SPI_Enable
		356	* @param SPIx SPI Instance
		357	* @retval None
		358	*/
		359	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
		360	{
		361	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
		362	}
		363
		364	/**
		365	* @brief Disable SPI peripheral
		366	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
		367	* @rmtoll CR1 SPE LL_SPI_Disable
		368	* @param SPIx SPI Instance
		369	* @retval None
		370	*/
		371	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
		372	{
		373	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
		374	}
		375
		376	/**
		377	* @brief Check if SPI peripheral is enabled
		378	* @rmtoll CR1 SPE LL_SPI_IsEnabled
		379	* @param SPIx SPI Instance
		380	* @retval State of bit (1 or 0).
		381	*/
		382	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
		383	{
		384	return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
		385	}
		386
		387	/**
		388	* @brief Set SPI operation mode to Master or Slave
		389	* @note This bit should not be changed when communication is ongoing.
		390	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
		391	* CR1 SSI LL_SPI_SetMode
		392	* @param SPIx SPI Instance
		393	* @param Mode This parameter can be one of the following values:
		394	* @arg @ref LL_SPI_MODE_MASTER
		395	* @arg @ref LL_SPI_MODE_SLAVE
		396	* @retval None
		397	*/
		398	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
		399	{
		400	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
		401	}
		402
		403	/**
		404	* @brief Get SPI operation mode (Master or Slave)
		405	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
		406	* CR1 SSI LL_SPI_GetMode
		407	* @param SPIx SPI Instance
		408	* @retval Returned value can be one of the following values:
		409	* @arg @ref LL_SPI_MODE_MASTER
		410	* @arg @ref LL_SPI_MODE_SLAVE
		411	*/
		412	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
		413	{
		414	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
		415	}
		416
		417	/**
		418	* @brief Set serial protocol used
		419	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		420	* @rmtoll CR2 FRF LL_SPI_SetStandard
		421	* @param SPIx SPI Instance
		422	* @param Standard This parameter can be one of the following values:
		423	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
		424	* @arg @ref LL_SPI_PROTOCOL_TI
		425	* @retval None
		426	*/
		427	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
		428	{
		429	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
		430	}
		431
		432	/**
		433	* @brief Get serial protocol used
		434	* @rmtoll CR2 FRF LL_SPI_GetStandard
		435	* @param SPIx SPI Instance
		436	* @retval Returned value can be one of the following values:
		437	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
		438	* @arg @ref LL_SPI_PROTOCOL_TI
		439	*/
		440	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
		441	{
		442	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
		443	}
		444
		445	/**
		446	* @brief Set clock phase
		447	* @note This bit should not be changed when communication is ongoing.
		448	* This bit is not used in SPI TI mode.
		449	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
		450	* @param SPIx SPI Instance
		451	* @param ClockPhase This parameter can be one of the following values:
		452	* @arg @ref LL_SPI_PHASE_1EDGE
		453	* @arg @ref LL_SPI_PHASE_2EDGE
		454	* @retval None
		455	*/
		456	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
		457	{
		458	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
		459	}
		460
		461	/**
		462	* @brief Get clock phase
		463	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
		464	* @param SPIx SPI Instance
		465	* @retval Returned value can be one of the following values:
		466	* @arg @ref LL_SPI_PHASE_1EDGE
		467	* @arg @ref LL_SPI_PHASE_2EDGE
		468	*/
		469	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
		470	{
		471	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
		472	}
		473
		474	/**
		475	* @brief Set clock polarity
		476	* @note This bit should not be changed when communication is ongoing.
		477	* This bit is not used in SPI TI mode.
		478	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
		479	* @param SPIx SPI Instance
		480	* @param ClockPolarity This parameter can be one of the following values:
		481	* @arg @ref LL_SPI_POLARITY_LOW
		482	* @arg @ref LL_SPI_POLARITY_HIGH
		483	* @retval None
		484	*/
		485	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
		486	{
		487	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
		488	}
		489
		490	/**
		491	* @brief Get clock polarity
		492	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
		493	* @param SPIx SPI Instance
		494	* @retval Returned value can be one of the following values:
		495	* @arg @ref LL_SPI_POLARITY_LOW
		496	* @arg @ref LL_SPI_POLARITY_HIGH
		497	*/
		498	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
		499	{
		500	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
		501	}
		502
		503	/**
		504	* @brief Set baud rate prescaler
		505	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
		506	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
		507	* @param SPIx SPI Instance
		508	* @param BaudRate This parameter can be one of the following values:
		509	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
		510	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
		511	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
		512	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
		513	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
		514	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
		515	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
		516	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
		517	* @retval None
		518	*/
		519	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
		520	{
		521	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
		522	}
		523
		524	/**
		525	* @brief Get baud rate prescaler
		526	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
		527	* @param SPIx SPI Instance
		528	* @retval Returned value can be one of the following values:
		529	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
		530	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
		531	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
		532	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
		533	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
		534	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
		535	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
		536	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
		537	*/
		538	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
		539	{
		540	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
		541	}
		542
		543	/**
		544	* @brief Set transfer bit order
		545	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
		546	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
		547	* @param SPIx SPI Instance
		548	* @param BitOrder This parameter can be one of the following values:
		549	* @arg @ref LL_SPI_LSB_FIRST
		550	* @arg @ref LL_SPI_MSB_FIRST
		551	* @retval None
		552	*/
		553	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
		554	{
		555	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
		556	}
		557
		558	/**
		559	* @brief Get transfer bit order
		560	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
		561	* @param SPIx SPI Instance
		562	* @retval Returned value can be one of the following values:
		563	* @arg @ref LL_SPI_LSB_FIRST
		564	* @arg @ref LL_SPI_MSB_FIRST
		565	*/
		566	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
		567	{
		568	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
		569	}
		570
		571	/**
		572	* @brief Set transfer direction mode
		573	* @note For Half-Duplex mode, Rx Direction is set by default.
		574	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
		575	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
		576	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
		577	* CR1 BIDIOE LL_SPI_SetTransferDirection
		578	* @param SPIx SPI Instance
		579	* @param TransferDirection This parameter can be one of the following values:
		580	* @arg @ref LL_SPI_FULL_DUPLEX
		581	* @arg @ref LL_SPI_SIMPLEX_RX
		582	* @arg @ref LL_SPI_HALF_DUPLEX_RX
		583	* @arg @ref LL_SPI_HALF_DUPLEX_TX
		584	* @retval None
		585	*/
		586	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
		587	{
		588	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
		589	}
		590
		591	/**
		592	* @brief Get transfer direction mode
		593	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
		594	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
		595	* CR1 BIDIOE LL_SPI_GetTransferDirection
		596	* @param SPIx SPI Instance
		597	* @retval Returned value can be one of the following values:
		598	* @arg @ref LL_SPI_FULL_DUPLEX
		599	* @arg @ref LL_SPI_SIMPLEX_RX
		600	* @arg @ref LL_SPI_HALF_DUPLEX_RX
		601	* @arg @ref LL_SPI_HALF_DUPLEX_TX
		602	*/
		603	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
		604	{
		605	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
		606	}
		607
		608	/**
		609	* @brief Set frame data width
		610	* @rmtoll CR2 DS LL_SPI_SetDataWidth
		611	* @param SPIx SPI Instance
		612	* @param DataWidth This parameter can be one of the following values:
		613	* @arg @ref LL_SPI_DATAWIDTH_4BIT
		614	* @arg @ref LL_SPI_DATAWIDTH_5BIT
		615	* @arg @ref LL_SPI_DATAWIDTH_6BIT
		616	* @arg @ref LL_SPI_DATAWIDTH_7BIT
		617	* @arg @ref LL_SPI_DATAWIDTH_8BIT
		618	* @arg @ref LL_SPI_DATAWIDTH_9BIT
		619	* @arg @ref LL_SPI_DATAWIDTH_10BIT
		620	* @arg @ref LL_SPI_DATAWIDTH_11BIT
		621	* @arg @ref LL_SPI_DATAWIDTH_12BIT
		622	* @arg @ref LL_SPI_DATAWIDTH_13BIT
		623	* @arg @ref LL_SPI_DATAWIDTH_14BIT
		624	* @arg @ref LL_SPI_DATAWIDTH_15BIT
		625	* @arg @ref LL_SPI_DATAWIDTH_16BIT
		626	* @retval None
		627	*/
		628	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
		629	{
		630	MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
		631	}
		632
		633	/**
		634	* @brief Get frame data width
		635	* @rmtoll CR2 DS LL_SPI_GetDataWidth
		636	* @param SPIx SPI Instance
		637	* @retval Returned value can be one of the following values:
		638	* @arg @ref LL_SPI_DATAWIDTH_4BIT
		639	* @arg @ref LL_SPI_DATAWIDTH_5BIT
		640	* @arg @ref LL_SPI_DATAWIDTH_6BIT
		641	* @arg @ref LL_SPI_DATAWIDTH_7BIT
		642	* @arg @ref LL_SPI_DATAWIDTH_8BIT
		643	* @arg @ref LL_SPI_DATAWIDTH_9BIT
		644	* @arg @ref LL_SPI_DATAWIDTH_10BIT
		645	* @arg @ref LL_SPI_DATAWIDTH_11BIT
		646	* @arg @ref LL_SPI_DATAWIDTH_12BIT
		647	* @arg @ref LL_SPI_DATAWIDTH_13BIT
		648	* @arg @ref LL_SPI_DATAWIDTH_14BIT
		649	* @arg @ref LL_SPI_DATAWIDTH_15BIT
		650	* @arg @ref LL_SPI_DATAWIDTH_16BIT
		651	*/
		652	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
		653	{
		654	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
		655	}
		656
		657	/**
		658	* @brief Set threshold of RXFIFO that triggers an RXNE event
		659	* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
		660	* @param SPIx SPI Instance
		661	* @param Threshold This parameter can be one of the following values:
		662	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
		663	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
		664	* @retval None
		665	*/
		666	__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
		667	{
		668	MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
		669	}
		670
		671	/**
		672	* @brief Get threshold of RXFIFO that triggers an RXNE event
		673	* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
		674	* @param SPIx SPI Instance
		675	* @retval Returned value can be one of the following values:
		676	* @arg @ref LL_SPI_RX_FIFO_TH_HALF
		677	* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
		678	*/
		679	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
		680	{
		681	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
		682	}
		683
		684	/**
		685	* @}
		686	*/
		687
		688	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
		689	* @{
		690	*/
		691
		692	/**
		693	* @brief Enable CRC
		694	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		695	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
		696	* @param SPIx SPI Instance
		697	* @retval None
		698	*/
		699	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
		700	{
		701	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
		702	}
		703
		704	/**
		705	* @brief Disable CRC
		706	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		707	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
		708	* @param SPIx SPI Instance
		709	* @retval None
		710	*/
		711	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
		712	{
		713	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
		714	}
		715
		716	/**
		717	* @brief Check if CRC is enabled
		718	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		719	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
		720	* @param SPIx SPI Instance
		721	* @retval State of bit (1 or 0).
		722	*/
		723	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
		724	{
		725	return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
		726	}
		727
		728	/**
		729	* @brief Set CRC Length
		730	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
		731	* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
		732	* @param SPIx SPI Instance
		733	* @param CRCLength This parameter can be one of the following values:
		734	* @arg @ref LL_SPI_CRC_8BIT
		735	* @arg @ref LL_SPI_CRC_16BIT
		736	* @retval None
		737	*/
		738	__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
		739	{
		740	MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
		741	}
		742
		743	/**
		744	* @brief Get CRC Length
		745	* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
		746	* @param SPIx SPI Instance
		747	* @retval Returned value can be one of the following values:
		748	* @arg @ref LL_SPI_CRC_8BIT
		749	* @arg @ref LL_SPI_CRC_16BIT
		750	*/
		751	__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
		752	{
		753	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
		754	}
		755
		756	/**
		757	* @brief Set CRCNext to transfer CRC on the line
		758	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
		759	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
		760	* @param SPIx SPI Instance
		761	* @retval None
		762	*/
		763	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
		764	{
		765	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
		766	}
		767
		768	/**
		769	* @brief Set polynomial for CRC calculation
		770	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
		771	* @param SPIx SPI Instance
		772	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		773	* @retval None
		774	*/
		775	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
		776	{
		777	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
		778	}
		779
		780	/**
		781	* @brief Get polynomial for CRC calculation
		782	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
		783	* @param SPIx SPI Instance
		784	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		785	*/
		786	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
		787	{
		788	return (uint32_t)(READ_REG(SPIx->CRCPR));
		789	}
		790
		791	/**
		792	* @brief Get Rx CRC
		793	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
		794	* @param SPIx SPI Instance
		795	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		796	*/
		797	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
		798	{
		799	return (uint32_t)(READ_REG(SPIx->RXCRCR));
		800	}
		801
		802	/**
		803	* @brief Get Tx CRC
		804	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
		805	* @param SPIx SPI Instance
		806	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
		807	*/
		808	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
		809	{
		810	return (uint32_t)(READ_REG(SPIx->TXCRCR));
		811	}
		812
		813	/**
		814	* @}
		815	*/
		816
		817	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
		818	* @{
		819	*/
		820
		821	/**
		822	* @brief Set NSS mode
		823	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
		824	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
		825	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
		826	* @param SPIx SPI Instance
		827	* @param NSS This parameter can be one of the following values:
		828	* @arg @ref LL_SPI_NSS_SOFT
		829	* @arg @ref LL_SPI_NSS_HARD_INPUT
		830	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
		831	* @retval None
		832	*/
		833	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
		834	{
		835	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
		836	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
		837	}
		838
		839	/**
		840	* @brief Get NSS mode
		841	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
		842	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
		843	* @param SPIx SPI Instance
		844	* @retval Returned value can be one of the following values:
		845	* @arg @ref LL_SPI_NSS_SOFT
		846	* @arg @ref LL_SPI_NSS_HARD_INPUT
		847	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
		848	*/
		849	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
		850	{
		851	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
		852	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
		853	return (Ssm \| Ssoe);
		854	}
		855
		856	/**
		857	* @brief Enable NSS pulse management
		858	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
		859	* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
		860	* @param SPIx SPI Instance
		861	* @retval None
		862	*/
		863	__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
		864	{
		865	SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
		866	}
		867
		868	/**
		869	* @brief Disable NSS pulse management
		870	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
		871	* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
		872	* @param SPIx SPI Instance
		873	* @retval None
		874	*/
		875	__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
		876	{
		877	CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
		878	}
		879
		880	/**
		881	* @brief Check if NSS pulse is enabled
		882	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
		883	* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
		884	* @param SPIx SPI Instance
		885	* @retval State of bit (1 or 0).
		886	*/
		887	__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
		888	{
		889	return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
		890	}
		891
		892	/**
		893	* @}
		894	*/
		895
		896	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
		897	* @{
		898	*/
		899
		900	/**
		901	* @brief Check if Rx buffer is not empty
		902	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
		903	* @param SPIx SPI Instance
		904	* @retval State of bit (1 or 0).
		905	*/
		906	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
		907	{
		908	return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
		909	}
		910
		911	/**
		912	* @brief Check if Tx buffer is empty
		913	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
		914	* @param SPIx SPI Instance
		915	* @retval State of bit (1 or 0).
		916	*/
		917	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
		918	{
		919	return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
		920	}
		921
		922	/**
		923	* @brief Get CRC error flag
		924	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
		925	* @param SPIx SPI Instance
		926	* @retval State of bit (1 or 0).
		927	*/
		928	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
		929	{
		930	return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
		931	}
		932
		933	/**
		934	* @brief Get mode fault error flag
		935	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
		936	* @param SPIx SPI Instance
		937	* @retval State of bit (1 or 0).
		938	*/
		939	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
		940	{
		941	return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
		942	}
		943
		944	/**
		945	* @brief Get overrun error flag
		946	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
		947	* @param SPIx SPI Instance
		948	* @retval State of bit (1 or 0).
		949	*/
		950	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
		951	{
		952	return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
		953	}
		954
		955	/**
		956	* @brief Get busy flag
		957	* @note The BSY flag is cleared under any one of the following conditions:
		958	* -When the SPI is correctly disabled
		959	* -When a fault is detected in Master mode (MODF bit set to 1)
		960	* -In Master mode, when it finishes a data transmission and no new data is ready to be
		961	* sent
		962	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
		963	* each data transfer.
		964	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
		965	* @param SPIx SPI Instance
		966	* @retval State of bit (1 or 0).
		967	*/
		968	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
		969	{
		970	return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
		971	}
		972
		973	/**
		974	* @brief Get frame format error flag
		975	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
		976	* @param SPIx SPI Instance
		977	* @retval State of bit (1 or 0).
		978	*/
		979	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
		980	{
		981	return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
		982	}
		983
		984	/**
		985	* @brief Get FIFO reception Level
		986	* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
		987	* @param SPIx SPI Instance
		988	* @retval Returned value can be one of the following values:
		989	* @arg @ref LL_SPI_RX_FIFO_EMPTY
		990	* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
		991	* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
		992	* @arg @ref LL_SPI_RX_FIFO_FULL
		993	*/
		994	__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
		995	{
		996	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
		997	}
		998
		999	/**
		1000	* @brief Get FIFO Transmission Level
		1001	* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
		1002	* @param SPIx SPI Instance
		1003	* @retval Returned value can be one of the following values:
		1004	* @arg @ref LL_SPI_TX_FIFO_EMPTY
		1005	* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
		1006	* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
		1007	* @arg @ref LL_SPI_TX_FIFO_FULL
		1008	*/
		1009	__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
		1010	{
		1011	return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
		1012	}
		1013
		1014	/**
		1015	* @brief Clear CRC error flag
		1016	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
		1017	* @param SPIx SPI Instance
		1018	* @retval None
		1019	*/
		1020	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
		1021	{
		1022	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
		1023	}
		1024
		1025	/**
		1026	* @brief Clear mode fault error flag
		1027	* @note Clearing this flag is done by a read access to the SPIx_SR
		1028	* register followed by a write access to the SPIx_CR1 register
		1029	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
		1030	* @param SPIx SPI Instance
		1031	* @retval None
		1032	*/
		1033	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
		1034	{
		1035	__IO uint32_t tmpreg_sr;
		1036	tmpreg_sr = SPIx->SR;
		1037	(void) tmpreg_sr;
		1038	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
		1039	}
		1040
		1041	/**
		1042	* @brief Clear overrun error flag
		1043	* @note Clearing this flag is done by a read access to the SPIx_DR
		1044	* register followed by a read access to the SPIx_SR register
		1045	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
		1046	* @param SPIx SPI Instance
		1047	* @retval None
		1048	*/
		1049	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
		1050	{
		1051	__IO uint32_t tmpreg;
		1052	tmpreg = SPIx->DR;
		1053	(void) tmpreg;
		1054	tmpreg = SPIx->SR;
		1055	(void) tmpreg;
		1056	}
		1057
		1058	/**
		1059	* @brief Clear frame format error flag
		1060	* @note Clearing this flag is done by reading SPIx_SR register
		1061	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
		1062	* @param SPIx SPI Instance
		1063	* @retval None
		1064	*/
		1065	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
		1066	{
		1067	__IO uint32_t tmpreg;
		1068	tmpreg = SPIx->SR;
		1069	(void) tmpreg;
		1070	}
		1071
		1072	/**
		1073	* @}
		1074	*/
		1075
		1076	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
		1077	* @{
		1078	*/
		1079
		1080	/**
		1081	* @brief Enable error interrupt
		1082	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
		1083	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
		1084	* @param SPIx SPI Instance
		1085	* @retval None
		1086	*/
		1087	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
		1088	{
		1089	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
		1090	}
		1091
		1092	/**
		1093	* @brief Enable Rx buffer not empty interrupt
		1094	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
		1095	* @param SPIx SPI Instance
		1096	* @retval None
		1097	*/
		1098	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
		1099	{
		1100	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
		1101	}
		1102
		1103	/**
		1104	* @brief Enable Tx buffer empty interrupt
		1105	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
		1106	* @param SPIx SPI Instance
		1107	* @retval None
		1108	*/
		1109	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
		1110	{
		1111	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
		1112	}
		1113
		1114	/**
		1115	* @brief Disable error interrupt
		1116	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
		1117	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
		1118	* @param SPIx SPI Instance
		1119	* @retval None
		1120	*/
		1121	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
		1122	{
		1123	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
		1124	}
		1125
		1126	/**
		1127	* @brief Disable Rx buffer not empty interrupt
		1128	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
		1129	* @param SPIx SPI Instance
		1130	* @retval None
		1131	*/
		1132	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
		1133	{
		1134	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
		1135	}
		1136
		1137	/**
		1138	* @brief Disable Tx buffer empty interrupt
		1139	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
		1140	* @param SPIx SPI Instance
		1141	* @retval None
		1142	*/
		1143	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
		1144	{
		1145	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
		1146	}
		1147
		1148	/**
		1149	* @brief Check if error interrupt is enabled
		1150	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
		1151	* @param SPIx SPI Instance
		1152	* @retval State of bit (1 or 0).
		1153	*/
		1154	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
		1155	{
		1156	return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
		1157	}
		1158
		1159	/**
		1160	* @brief Check if Rx buffer not empty interrupt is enabled
		1161	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
		1162	* @param SPIx SPI Instance
		1163	* @retval State of bit (1 or 0).
		1164	*/
		1165	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
		1166	{
		1167	return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
		1168	}
		1169
		1170	/**
		1171	* @brief Check if Tx buffer empty interrupt
		1172	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
		1173	* @param SPIx SPI Instance
		1174	* @retval State of bit (1 or 0).
		1175	*/
		1176	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
		1177	{
		1178	return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
		1179	}
		1180
		1181	/**
		1182	* @}
		1183	*/
		1184
		1185	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
		1186	* @{
		1187	*/
		1188
		1189	/**
		1190	* @brief Enable DMA Rx
		1191	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
		1192	* @param SPIx SPI Instance
		1193	* @retval None
		1194	*/
		1195	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
		1196	{
		1197	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
		1198	}
		1199
		1200	/**
		1201	* @brief Disable DMA Rx
		1202	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
		1203	* @param SPIx SPI Instance
		1204	* @retval None
		1205	*/
		1206	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
		1207	{
		1208	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
		1209	}
		1210
		1211	/**
		1212	* @brief Check if DMA Rx is enabled
		1213	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
		1214	* @param SPIx SPI Instance
		1215	* @retval State of bit (1 or 0).
		1216	*/
		1217	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
		1218	{
		1219	return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
		1220	}
		1221
		1222	/**
		1223	* @brief Enable DMA Tx
		1224	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
		1225	* @param SPIx SPI Instance
		1226	* @retval None
		1227	*/
		1228	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
		1229	{
		1230	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
		1231	}
		1232
		1233	/**
		1234	* @brief Disable DMA Tx
		1235	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
		1236	* @param SPIx SPI Instance
		1237	* @retval None
		1238	*/
		1239	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
		1240	{
		1241	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
		1242	}
		1243
		1244	/**
		1245	* @brief Check if DMA Tx is enabled
		1246	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
		1247	* @param SPIx SPI Instance
		1248	* @retval State of bit (1 or 0).
		1249	*/
		1250	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
		1251	{
		1252	return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
		1253	}
		1254
		1255	/**
		1256	* @brief Set parity of Last DMA reception
		1257	* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
		1258	* @param SPIx SPI Instance
		1259	* @param Parity This parameter can be one of the following values:
		1260	* @arg @ref LL_SPI_DMA_PARITY_ODD
		1261	* @arg @ref LL_SPI_DMA_PARITY_EVEN
		1262	* @retval None
		1263	*/
		1264	__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
		1265	{
		1266	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
		1267	}
		1268
		1269	/**
		1270	* @brief Get parity configuration for Last DMA reception
		1271	* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
		1272	* @param SPIx SPI Instance
		1273	* @retval Returned value can be one of the following values:
		1274	* @arg @ref LL_SPI_DMA_PARITY_ODD
		1275	* @arg @ref LL_SPI_DMA_PARITY_EVEN
		1276	*/
		1277	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
		1278	{
		1279	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
		1280	}
		1281
		1282	/**
		1283	* @brief Set parity of Last DMA transmission
		1284	* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
		1285	* @param SPIx SPI Instance
		1286	* @param Parity This parameter can be one of the following values:
		1287	* @arg @ref LL_SPI_DMA_PARITY_ODD
		1288	* @arg @ref LL_SPI_DMA_PARITY_EVEN
		1289	* @retval None
		1290	*/
		1291	__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
		1292	{
		1293	MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
		1294	}
		1295
		1296	/**
		1297	* @brief Get parity configuration for Last DMA transmission
		1298	* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
		1299	* @param SPIx SPI Instance
		1300	* @retval Returned value can be one of the following values:
		1301	* @arg @ref LL_SPI_DMA_PARITY_ODD
		1302	* @arg @ref LL_SPI_DMA_PARITY_EVEN
		1303	*/
		1304	__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
		1305	{
		1306	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
		1307	}
		1308
		1309	/**
		1310	* @brief Get the data register address used for DMA transfer
		1311	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
		1312	* @param SPIx SPI Instance
		1313	* @retval Address of data register
		1314	*/
		1315	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
		1316	{
		1317	return (uint32_t) &(SPIx->DR);
		1318	}
		1319
		1320	/**
		1321	* @}
		1322	*/
		1323
		1324	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
		1325	* @{
		1326	*/
		1327
		1328	/**
		1329	* @brief Read 8-Bits in the data register
		1330	* @rmtoll DR DR LL_SPI_ReceiveData8
		1331	* @param SPIx SPI Instance
		1332	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
		1333	*/
		1334	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
		1335	{
		1336	return (uint8_t)(READ_REG(SPIx->DR));
		1337	}
		1338
		1339	/**
		1340	* @brief Read 16-Bits in the data register
		1341	* @rmtoll DR DR LL_SPI_ReceiveData16
		1342	* @param SPIx SPI Instance
		1343	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
		1344	*/
		1345	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
		1346	{
		1347	return (uint16_t)(READ_REG(SPIx->DR));
		1348	}
		1349
		1350	/**
		1351	* @brief Write 8-Bits in the data register
		1352	* @rmtoll DR DR LL_SPI_TransmitData8
		1353	* @param SPIx SPI Instance
		1354	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
		1355	* @retval None
		1356	*/
		1357	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
		1358	{
		1359	#if defined (__GNUC__)
		1360	__IO uint8_t spidr = ((__IO uint8_t )&SPIx->DR);
		1361	*spidr = TxData;
		1362	#else
		1363	((__IO uint8_t )&SPIx->DR) = TxData;
		1364	#endif /* __GNUC__ */
		1365	}
		1366
		1367	/**
		1368	* @brief Write 16-Bits in the data register
		1369	* @rmtoll DR DR LL_SPI_TransmitData16
		1370	* @param SPIx SPI Instance
		1371	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
		1372	* @retval None
		1373	*/
		1374	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
		1375	{
		1376	#if defined (__GNUC__)
		1377	__IO uint16_t spidr = ((__IO uint16_t )&SPIx->DR);
		1378	*spidr = TxData;
		1379	#else
		1380	SPIx->DR = TxData;
		1381	#endif /* __GNUC__ */
		1382	}
		1383
		1384	/**
		1385	* @}
		1386	*/
		1387	#if defined(USE_FULL_LL_DRIVER)
		1388	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
		1389	* @{
		1390	*/
		1391
		1392	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
		1393	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
		1394	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
		1395
		1396	/**
		1397	* @}
		1398	*/
		1399	#endif /* USE_FULL_LL_DRIVER */
		1400	/**
		1401	* @}
		1402	*/
		1403
		1404	/**
		1405	* @}
		1406	*/
		1407
		1408	#if defined(SPI_I2S_SUPPORT)
		1409	/** @defgroup I2S_LL I2S
		1410	* @{
		1411	*/
		1412
		1413	/* Private variables ---------------------------------------------------------*/
		1414	/* Private constants ---------------------------------------------------------*/
		1415	/* Private macros ------------------------------------------------------------*/
		1416
		1417	/* Exported types ------------------------------------------------------------*/
		1418	#if defined(USE_FULL_LL_DRIVER)
		1419	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
		1420	* @{
		1421	*/
		1422
		1423	/**
		1424	* @brief I2S Init structure definition
		1425	*/
		1426
		1427	typedef struct
		1428	{
		1429	uint32_t Mode; /*!< Specifies the I2S operating mode.
		1430	This parameter can be a value of @ref I2S_LL_EC_MODE
		1431
		1432	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
		1433
		1434	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
		1435	This parameter can be a value of @ref I2S_LL_EC_STANDARD
		1436
		1437	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
		1438
		1439
		1440	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
		1441	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
		1442
		1443	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
		1444
		1445
		1446	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
		1447	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
		1448
		1449	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
		1450
		1451
		1452	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
		1453	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
		1454
		1455	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
		1456	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
		1457
		1458
		1459	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
		1460	This parameter can be a value of @ref I2S_LL_EC_POLARITY
		1461
		1462	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
		1463
		1464	} LL_I2S_InitTypeDef;
		1465
		1466	/**
		1467	* @}
		1468	*/
		1469	#endif /USE_FULL_LL_DRIVER/
		1470
		1471	/* Exported constants --------------------------------------------------------*/
		1472	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
		1473	* @{
		1474	*/
		1475
		1476	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
		1477	* @brief Flags defines which can be used with LL_I2S_ReadReg function
		1478	* @{
		1479	*/
		1480	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
		1481	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
		1482	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
		1483	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
		1484	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
		1485	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
		1486	/**
		1487	* @}
		1488	*/
		1489
		1490	/** @defgroup SPI_LL_EC_IT IT Defines
		1491	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
		1492	* @{
		1493	*/
		1494	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
		1495	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
		1496	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
		1497	/**
		1498	* @}
		1499	*/
		1500
		1501	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
		1502	* @{
		1503	*/
		1504	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
		1505	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
		1506	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
		1507	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
		1508	/**
		1509	* @}
		1510	*/
		1511
		1512	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
		1513	* @{
		1514	*/
		1515	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
		1516	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
		1517	/**
		1518	* @}
		1519	*/
		1520
		1521	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
		1522	* @{
		1523	*/
		1524	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
		1525	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
		1526	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
		1527	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
		1528	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
		1529	/**
		1530	* @}
		1531	*/
		1532
		1533	/** @defgroup I2S_LL_EC_MODE Operation Mode
		1534	* @{
		1535	*/
		1536	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
		1537	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
		1538	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
		1539	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
		1540	/**
		1541	* @}
		1542	*/
		1543
		1544	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
		1545	* @{
		1546	*/
		1547	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
		1548	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
		1549	/**
		1550	* @}
		1551	*/
		1552
		1553	#if defined(USE_FULL_LL_DRIVER)
		1554
		1555	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
		1556	* @{
		1557	*/
		1558	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
		1559	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
		1560	/**
		1561	* @}
		1562	*/
		1563
		1564	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
		1565	* @{
		1566	*/
		1567
		1568	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
		1569	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
		1570	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
		1571	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
		1572	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
		1573	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
		1574	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
		1575	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
		1576	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
		1577	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
		1578	/**
		1579	* @}
		1580	*/
		1581	#endif /* USE_FULL_LL_DRIVER */
		1582
		1583	/**
		1584	* @}
		1585	*/
		1586
		1587	/* Exported macro ------------------------------------------------------------*/
		1588	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
		1589	* @{
		1590	*/
		1591
		1592	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
		1593	* @{
		1594	*/
		1595
		1596	/**
		1597	* @brief Write a value in I2S register
		1598	* @param __INSTANCE__ I2S Instance
		1599	* @param __REG__ Register to be written
		1600	* @param __VALUE__ Value to be written in the register
		1601	* @retval None
		1602	*/
		1603	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		1604
		1605	/**
		1606	* @brief Read a value in I2S register
		1607	* @param __INSTANCE__ I2S Instance
		1608	* @param __REG__ Register to be read
		1609	* @retval Register value
		1610	*/
		1611	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		1612	/**
		1613	* @}
		1614	*/
		1615
		1616	/**
		1617	* @}
		1618	*/
		1619
		1620
		1621	/* Exported functions --------------------------------------------------------*/
		1622
		1623	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
		1624	* @{
		1625	*/
		1626
		1627	/** @defgroup I2S_LL_EF_Configuration Configuration
		1628	* @{
		1629	*/
		1630
		1631	/**
		1632	* @brief Select I2S mode and Enable I2S peripheral
		1633	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
		1634	* I2SCFGR I2SE LL_I2S_Enable
		1635	* @param SPIx SPI Instance
		1636	* @retval None
		1637	*/
		1638	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
		1639	{
		1640	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
		1641	}
		1642
		1643	/**
		1644	* @brief Disable I2S peripheral
		1645	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
		1646	* @param SPIx SPI Instance
		1647	* @retval None
		1648	*/
		1649	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
		1650	{
		1651	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
		1652	}
		1653
		1654	/**
		1655	* @brief Check if I2S peripheral is enabled
		1656	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
		1657	* @param SPIx SPI Instance
		1658	* @retval State of bit (1 or 0).
		1659	*/
		1660	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
		1661	{
		1662	return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
		1663	}
		1664
		1665	/**
		1666	* @brief Set I2S data frame length
		1667	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
		1668	* I2SCFGR CHLEN LL_I2S_SetDataFormat
		1669	* @param SPIx SPI Instance
		1670	* @param DataFormat This parameter can be one of the following values:
		1671	* @arg @ref LL_I2S_DATAFORMAT_16B
		1672	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
		1673	* @arg @ref LL_I2S_DATAFORMAT_24B
		1674	* @arg @ref LL_I2S_DATAFORMAT_32B
		1675	* @retval None
		1676	*/
		1677	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
		1678	{
		1679	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
		1680	}
		1681
		1682	/**
		1683	* @brief Get I2S data frame length
		1684	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
		1685	* I2SCFGR CHLEN LL_I2S_GetDataFormat
		1686	* @param SPIx SPI Instance
		1687	* @retval Returned value can be one of the following values:
		1688	* @arg @ref LL_I2S_DATAFORMAT_16B
		1689	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
		1690	* @arg @ref LL_I2S_DATAFORMAT_24B
		1691	* @arg @ref LL_I2S_DATAFORMAT_32B
		1692	*/
		1693	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
		1694	{
		1695	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
		1696	}
		1697
		1698	/**
		1699	* @brief Set I2S clock polarity
		1700	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
		1701	* @param SPIx SPI Instance
		1702	* @param ClockPolarity This parameter can be one of the following values:
		1703	* @arg @ref LL_I2S_POLARITY_LOW
		1704	* @arg @ref LL_I2S_POLARITY_HIGH
		1705	* @retval None
		1706	*/
		1707	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
		1708	{
		1709	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
		1710	}
		1711
		1712	/**
		1713	* @brief Get I2S clock polarity
		1714	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
		1715	* @param SPIx SPI Instance
		1716	* @retval Returned value can be one of the following values:
		1717	* @arg @ref LL_I2S_POLARITY_LOW
		1718	* @arg @ref LL_I2S_POLARITY_HIGH
		1719	*/
		1720	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
		1721	{
		1722	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
		1723	}
		1724
		1725	/**
		1726	* @brief Set I2S standard protocol
		1727	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
		1728	* I2SCFGR PCMSYNC LL_I2S_SetStandard
		1729	* @param SPIx SPI Instance
		1730	* @param Standard This parameter can be one of the following values:
		1731	* @arg @ref LL_I2S_STANDARD_PHILIPS
		1732	* @arg @ref LL_I2S_STANDARD_MSB
		1733	* @arg @ref LL_I2S_STANDARD_LSB
		1734	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
		1735	* @arg @ref LL_I2S_STANDARD_PCM_LONG
		1736	* @retval None
		1737	*/
		1738	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
		1739	{
		1740	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
		1741	}
		1742
		1743	/**
		1744	* @brief Get I2S standard protocol
		1745	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
		1746	* I2SCFGR PCMSYNC LL_I2S_GetStandard
		1747	* @param SPIx SPI Instance
		1748	* @retval Returned value can be one of the following values:
		1749	* @arg @ref LL_I2S_STANDARD_PHILIPS
		1750	* @arg @ref LL_I2S_STANDARD_MSB
		1751	* @arg @ref LL_I2S_STANDARD_LSB
		1752	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
		1753	* @arg @ref LL_I2S_STANDARD_PCM_LONG
		1754	*/
		1755	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
		1756	{
		1757	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
		1758	}
		1759
		1760	/**
		1761	* @brief Set I2S transfer mode
		1762	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
		1763	* @param SPIx SPI Instance
		1764	* @param Mode This parameter can be one of the following values:
		1765	* @arg @ref LL_I2S_MODE_SLAVE_TX
		1766	* @arg @ref LL_I2S_MODE_SLAVE_RX
		1767	* @arg @ref LL_I2S_MODE_MASTER_TX
		1768	* @arg @ref LL_I2S_MODE_MASTER_RX
		1769	* @retval None
		1770	*/
		1771	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
		1772	{
		1773	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
		1774	}
		1775
		1776	/**
		1777	* @brief Get I2S transfer mode
		1778	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
		1779	* @param SPIx SPI Instance
		1780	* @retval Returned value can be one of the following values:
		1781	* @arg @ref LL_I2S_MODE_SLAVE_TX
		1782	* @arg @ref LL_I2S_MODE_SLAVE_RX
		1783	* @arg @ref LL_I2S_MODE_MASTER_TX
		1784	* @arg @ref LL_I2S_MODE_MASTER_RX
		1785	*/
		1786	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
		1787	{
		1788	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
		1789	}
		1790
		1791	/**
		1792	* @brief Set I2S linear prescaler
		1793	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
		1794	* @param SPIx SPI Instance
		1795	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
		1796	* @retval None
		1797	*/
		1798	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
		1799	{
		1800	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
		1801	}
		1802
		1803	/**
		1804	* @brief Get I2S linear prescaler
		1805	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
		1806	* @param SPIx SPI Instance
		1807	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
		1808	*/
		1809	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
		1810	{
		1811	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
		1812	}
		1813
		1814	/**
		1815	* @brief Set I2S parity prescaler
		1816	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
		1817	* @param SPIx SPI Instance
		1818	* @param PrescalerParity This parameter can be one of the following values:
		1819	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
		1820	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
		1821	* @retval None
		1822	*/
		1823	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
		1824	{
		1825	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
		1826	}
		1827
		1828	/**
		1829	* @brief Get I2S parity prescaler
		1830	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
		1831	* @param SPIx SPI Instance
		1832	* @retval Returned value can be one of the following values:
		1833	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
		1834	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
		1835	*/
		1836	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
		1837	{
		1838	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
		1839	}
		1840
		1841	/**
		1842	* @brief Enable the master clock ouput (Pin MCK)
		1843	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
		1844	* @param SPIx SPI Instance
		1845	* @retval None
		1846	*/
		1847	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
		1848	{
		1849	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
		1850	}
		1851
		1852	/**
		1853	* @brief Disable the master clock ouput (Pin MCK)
		1854	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
		1855	* @param SPIx SPI Instance
		1856	* @retval None
		1857	*/
		1858	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
		1859	{
		1860	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
		1861	}
		1862
		1863	/**
		1864	* @brief Check if the master clock ouput (Pin MCK) is enabled
		1865	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
		1866	* @param SPIx SPI Instance
		1867	* @retval State of bit (1 or 0).
		1868	*/
		1869	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
		1870	{
		1871	return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
		1872	}
		1873
		1874	#if defined(SPI_I2SCFGR_ASTRTEN)
		1875	/**
		1876	* @brief Enable asynchronous start
		1877	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
		1878	* @param SPIx SPI Instance
		1879	* @retval None
		1880	*/
		1881	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
		1882	{
		1883	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
		1884	}
		1885
		1886	/**
		1887	* @brief Disable asynchronous start
		1888	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
		1889	* @param SPIx SPI Instance
		1890	* @retval None
		1891	*/
		1892	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
		1893	{
		1894	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
		1895	}
		1896
		1897	/**
		1898	* @brief Check if asynchronous start is enabled
		1899	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
		1900	* @param SPIx SPI Instance
		1901	* @retval State of bit (1 or 0).
		1902	*/
		1903	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
		1904	{
		1905	return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
		1906	}
		1907	#endif /* SPI_I2SCFGR_ASTRTEN */
		1908
		1909	/**
		1910	* @}
		1911	*/
		1912
		1913	/** @defgroup I2S_LL_EF_FLAG FLAG Management
		1914	* @{
		1915	*/
		1916
		1917	/**
		1918	* @brief Check if Rx buffer is not empty
		1919	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
		1920	* @param SPIx SPI Instance
		1921	* @retval State of bit (1 or 0).
		1922	*/
		1923	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
		1924	{
		1925	return LL_SPI_IsActiveFlag_RXNE(SPIx);
		1926	}
		1927
		1928	/**
		1929	* @brief Check if Tx buffer is empty
		1930	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
		1931	* @param SPIx SPI Instance
		1932	* @retval State of bit (1 or 0).
		1933	*/
		1934	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
		1935	{
		1936	return LL_SPI_IsActiveFlag_TXE(SPIx);
		1937	}
		1938
		1939	/**
		1940	* @brief Get busy flag
		1941	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
		1942	* @param SPIx SPI Instance
		1943	* @retval State of bit (1 or 0).
		1944	*/
		1945	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
		1946	{
		1947	return LL_SPI_IsActiveFlag_BSY(SPIx);
		1948	}
		1949
		1950	/**
		1951	* @brief Get overrun error flag
		1952	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
		1953	* @param SPIx SPI Instance
		1954	* @retval State of bit (1 or 0).
		1955	*/
		1956	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
		1957	{
		1958	return LL_SPI_IsActiveFlag_OVR(SPIx);
		1959	}
		1960
		1961	/**
		1962	* @brief Get underrun error flag
		1963	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
		1964	* @param SPIx SPI Instance
		1965	* @retval State of bit (1 or 0).
		1966	*/
		1967	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
		1968	{
		1969	return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
		1970	}
		1971
		1972	/**
		1973	* @brief Get frame format error flag
		1974	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
		1975	* @param SPIx SPI Instance
		1976	* @retval State of bit (1 or 0).
		1977	*/
		1978	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
		1979	{
		1980	return LL_SPI_IsActiveFlag_FRE(SPIx);
		1981	}
		1982
		1983	/**
		1984	* @brief Get channel side flag.
		1985	* @note 0: Channel Left has to be transmitted or has been received\n
		1986	* 1: Channel Right has to be transmitted or has been received\n
		1987	* It has no significance in PCM mode.
		1988	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
		1989	* @param SPIx SPI Instance
		1990	* @retval State of bit (1 or 0).
		1991	*/
		1992	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
		1993	{
		1994	return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
		1995	}
		1996
		1997	/**
		1998	* @brief Clear overrun error flag
		1999	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
		2000	* @param SPIx SPI Instance
		2001	* @retval None
		2002	*/
		2003	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
		2004	{
		2005	LL_SPI_ClearFlag_OVR(SPIx);
		2006	}
		2007
		2008	/**
		2009	* @brief Clear underrun error flag
		2010	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
		2011	* @param SPIx SPI Instance
		2012	* @retval None
		2013	*/
		2014	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
		2015	{
		2016	__IO uint32_t tmpreg;
		2017	tmpreg = SPIx->SR;
		2018	(void)tmpreg;
		2019	}
		2020
		2021	/**
		2022	* @brief Clear frame format error flag
		2023	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
		2024	* @param SPIx SPI Instance
		2025	* @retval None
		2026	*/
		2027	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
		2028	{
		2029	LL_SPI_ClearFlag_FRE(SPIx);
		2030	}
		2031
		2032	/**
		2033	* @}
		2034	*/
		2035
		2036	/** @defgroup I2S_LL_EF_IT Interrupt Management
		2037	* @{
		2038	*/
		2039
		2040	/**
		2041	* @brief Enable error IT
		2042	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
		2043	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
		2044	* @param SPIx SPI Instance
		2045	* @retval None
		2046	*/
		2047	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
		2048	{
		2049	LL_SPI_EnableIT_ERR(SPIx);
		2050	}
		2051
		2052	/**
		2053	* @brief Enable Rx buffer not empty IT
		2054	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
		2055	* @param SPIx SPI Instance
		2056	* @retval None
		2057	*/
		2058	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
		2059	{
		2060	LL_SPI_EnableIT_RXNE(SPIx);
		2061	}
		2062
		2063	/**
		2064	* @brief Enable Tx buffer empty IT
		2065	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
		2066	* @param SPIx SPI Instance
		2067	* @retval None
		2068	*/
		2069	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
		2070	{
		2071	LL_SPI_EnableIT_TXE(SPIx);
		2072	}
		2073
		2074	/**
		2075	* @brief Disable error IT
		2076	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
		2077	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
		2078	* @param SPIx SPI Instance
		2079	* @retval None
		2080	*/
		2081	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
		2082	{
		2083	LL_SPI_DisableIT_ERR(SPIx);
		2084	}
		2085
		2086	/**
		2087	* @brief Disable Rx buffer not empty IT
		2088	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
		2089	* @param SPIx SPI Instance
		2090	* @retval None
		2091	*/
		2092	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
		2093	{
		2094	LL_SPI_DisableIT_RXNE(SPIx);
		2095	}
		2096
		2097	/**
		2098	* @brief Disable Tx buffer empty IT
		2099	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
		2100	* @param SPIx SPI Instance
		2101	* @retval None
		2102	*/
		2103	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
		2104	{
		2105	LL_SPI_DisableIT_TXE(SPIx);
		2106	}
		2107
		2108	/**
		2109	* @brief Check if ERR IT is enabled
		2110	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
		2111	* @param SPIx SPI Instance
		2112	* @retval State of bit (1 or 0).
		2113	*/
		2114	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
		2115	{
		2116	return LL_SPI_IsEnabledIT_ERR(SPIx);
		2117	}
		2118
		2119	/**
		2120	* @brief Check if RXNE IT is enabled
		2121	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
		2122	* @param SPIx SPI Instance
		2123	* @retval State of bit (1 or 0).
		2124	*/
		2125	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
		2126	{
		2127	return LL_SPI_IsEnabledIT_RXNE(SPIx);
		2128	}
		2129
		2130	/**
		2131	* @brief Check if TXE IT is enabled
		2132	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
		2133	* @param SPIx SPI Instance
		2134	* @retval State of bit (1 or 0).
		2135	*/
		2136	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
		2137	{
		2138	return LL_SPI_IsEnabledIT_TXE(SPIx);
		2139	}
		2140
		2141	/**
		2142	* @}
		2143	*/
		2144
		2145	/** @defgroup I2S_LL_EF_DMA DMA Management
		2146	* @{
		2147	*/
		2148
		2149	/**
		2150	* @brief Enable DMA Rx
		2151	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
		2152	* @param SPIx SPI Instance
		2153	* @retval None
		2154	*/
		2155	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
		2156	{
		2157	LL_SPI_EnableDMAReq_RX(SPIx);
		2158	}
		2159
		2160	/**
		2161	* @brief Disable DMA Rx
		2162	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
		2163	* @param SPIx SPI Instance
		2164	* @retval None
		2165	*/
		2166	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
		2167	{
		2168	LL_SPI_DisableDMAReq_RX(SPIx);
		2169	}
		2170
		2171	/**
		2172	* @brief Check if DMA Rx is enabled
		2173	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
		2174	* @param SPIx SPI Instance
		2175	* @retval State of bit (1 or 0).
		2176	*/
		2177	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
		2178	{
		2179	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
		2180	}
		2181
		2182	/**
		2183	* @brief Enable DMA Tx
		2184	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
		2185	* @param SPIx SPI Instance
		2186	* @retval None
		2187	*/
		2188	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
		2189	{
		2190	LL_SPI_EnableDMAReq_TX(SPIx);
		2191	}
		2192
		2193	/**
		2194	* @brief Disable DMA Tx
		2195	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
		2196	* @param SPIx SPI Instance
		2197	* @retval None
		2198	*/
		2199	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
		2200	{
		2201	LL_SPI_DisableDMAReq_TX(SPIx);
		2202	}
		2203
		2204	/**
		2205	* @brief Check if DMA Tx is enabled
		2206	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
		2207	* @param SPIx SPI Instance
		2208	* @retval State of bit (1 or 0).
		2209	*/
		2210	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
		2211	{
		2212	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
		2213	}
		2214
		2215	/**
		2216	* @}
		2217	*/
		2218
		2219	/** @defgroup I2S_LL_EF_DATA DATA Management
		2220	* @{
		2221	*/
		2222
		2223	/**
		2224	* @brief Read 16-Bits in data register
		2225	* @rmtoll DR DR LL_I2S_ReceiveData16
		2226	* @param SPIx SPI Instance
		2227	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
		2228	*/
		2229	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
		2230	{
		2231	return LL_SPI_ReceiveData16(SPIx);
		2232	}
		2233
		2234	/**
		2235	* @brief Write 16-Bits in data register
		2236	* @rmtoll DR DR LL_I2S_TransmitData16
		2237	* @param SPIx SPI Instance
		2238	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
		2239	* @retval None
		2240	*/
		2241	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
		2242	{
		2243	LL_SPI_TransmitData16(SPIx, TxData);
		2244	}
		2245
		2246	/**
		2247	* @}
		2248	*/
		2249
		2250	#if defined(USE_FULL_LL_DRIVER)
		2251	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
		2252	* @{
		2253	*/
		2254
		2255	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
		2256	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
		2257	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
		2258	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
		2259
		2260	/**
		2261	* @}
		2262	*/
		2263	#endif /* USE_FULL_LL_DRIVER */
		2264
		2265	/**
		2266	* @}
		2267	*/
		2268
		2269	/**
		2270	* @}
		2271	*/
		2272	#endif /* SPI_I2S_SUPPORT */
		2273
		2274	#endif /* defined (SPI1) \|\| defined (SPI2) */
		2275
		2276	/**
		2277	* @}
		2278	*/
		2279
		2280	#ifdef __cplusplus
		2281	}
		2282	#endif
		2283
		2284	#endif /* STM32F0xx_LL_SPI_H */
		2285
		2286	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_spi.h – Rev 2