WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_i2c.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_i2c.h
		4	* @author MCD Application Team
		5	* @brief Header file of I2C LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef STM32F0xx_LL_I2C_H
		22	#define STM32F0xx_LL_I2C_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f0xx.h"
		30
		31	/** @addtogroup STM32F0xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (I2C1) \|\| defined (I2C2)
		36
		37	/** @defgroup I2C_LL I2C
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43
		44	/* Private constants ---------------------------------------------------------*/
		45	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
		46	* @{
		47	*/
		48	/**
		49	* @}
		50	*/
		51
		52	/* Private macros ------------------------------------------------------------*/
		53	#if defined(USE_FULL_LL_DRIVER)
		54	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
		55	* @{
		56	*/
		57	/**
		58	* @}
		59	*/
		60	#endif /USE_FULL_LL_DRIVER/
		61
		62	/* Exported types ------------------------------------------------------------*/
		63	#if defined(USE_FULL_LL_DRIVER)
		64	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
		65	* @{
		66	*/
		67	typedef struct
		68	{
		69	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
		70	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
		71
		72	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
		73
		74	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
		75	This parameter must be set by referring to the STM32CubeMX Tool and
		76	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
		77
		78	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
		79
		80	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
		81	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
		82
		83	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
		84
		85	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
		86	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
		87
		88	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
		89
		90	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
		91	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
		92
		93	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
		94
		95	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
		96	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
		97
		98	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
		99
		100	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
		101	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
		102
		103	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
		104	} LL_I2C_InitTypeDef;
		105	/**
		106	* @}
		107	*/
		108	#endif /USE_FULL_LL_DRIVER/
		109
		110	/* Exported constants --------------------------------------------------------*/
		111	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
		112	* @{
		113	*/
		114
		115	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
		116	* @brief Flags defines which can be used with LL_I2C_WriteReg function
		117	* @{
		118	*/
		119	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
		120	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
		121	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
		122	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
		123	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
		124	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
		125	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
		126	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
		127	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
		128	/**
		129	* @}
		130	*/
		131
		132	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
		133	* @brief Flags defines which can be used with LL_I2C_ReadReg function
		134	* @{
		135	*/
		136	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
		137	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
		138	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
		139	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
		140	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
		141	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
		142	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
		143	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
		144	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
		145	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
		146	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
		147	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
		148	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
		149	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
		150	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
		151	/**
		152	* @}
		153	*/
		154
		155	/** @defgroup I2C_LL_EC_IT IT Defines
		156	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
		157	* @{
		158	*/
		159	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
		160	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
		161	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
		162	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
		163	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
		164	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
		165	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
		166	/**
		167	* @}
		168	*/
		169
		170	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
		171	* @{
		172	*/
		173	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
		174	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
		175	#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /!< SMBus Device default mode (Default address not acknowledge) /
		176	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
		177	/**
		178	* @}
		179	*/
		180
		181	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
		182	* @{
		183	*/
		184	#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /!< Analog filter is enabled. /
		185	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
		186	/**
		187	* @}
		188	*/
		189
		190	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
		191	* @{
		192	*/
		193	#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /!< Master operates in 7-bit addressing mode. /
		194	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
		195	/**
		196	* @}
		197	*/
		198
		199	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
		200	* @{
		201	*/
		202	#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /!< Own address 1 is a 7-bit address. /
		203	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
		204	/**
		205	* @}
		206	*/
		207
		208	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
		209	* @{
		210	*/
		211	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
		212	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
		213	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
		214	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
		215	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
		216	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
		217	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
		218	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
		219	/**
		220	* @}
		221	*/
		222
		223	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
		224	* @{
		225	*/
		226	#define LL_I2C_ACK 0x00000000U /!< ACK is sent after current received byte. /
		227	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
		228	/**
		229	* @}
		230	*/
		231
		232	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
		233	* @{
		234	*/
		235	#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /!< Slave Address in 7-bit. /
		236	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
		237	/**
		238	* @}
		239	*/
		240
		241	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
		242	* @{
		243	*/
		244	#define LL_I2C_REQUEST_WRITE 0x00000000U /!< Master request a write transfer. /
		245	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
		246	/**
		247	* @}
		248	*/
		249
		250	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
		251	* @{
		252	*/
		253	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
		254	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
		255	#define LL_I2C_MODE_SOFTEND 0x00000000U /!< Enable I2C Software end mode with no HW PEC comparison. /
		256	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
		257	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
		258	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
		259	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
		260	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
		261	/**
		262	* @}
		263	*/
		264
		265	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
		266	* @{
		267	*/
		268	#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /!< Don't Generate Stop and Start condition. /
		269	#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U \| I2C_CR2_STOP) /!< Generate Stop condition (Size should be set to 0). /
		270	#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U \| I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
		271	#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U \| I2C_CR2_START) /!< Generate Start for write request. /
		272	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U \| I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
		273	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U \| I2C_CR2_START) /!< Generate Restart for write request, slave 7Bit address. /
		274	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U \| I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
		275	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U \| I2C_CR2_START) /!< Generate Restart for write request, slave 10Bit address./
		276	/**
		277	* @}
		278	*/
		279
		280	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
		281	* @{
		282	*/
		283	#define LL_I2C_DIRECTION_WRITE 0x00000000U /!< Write transfer request by master, slave enters receiver mode. /
		284	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
		285	/**
		286	* @}
		287	*/
		288
		289	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
		290	* @{
		291	*/
		292	#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /!< Get address of data register used for transmission /
		293	#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /!< Get address of data register used for reception /
		294	/**
		295	* @}
		296	*/
		297
		298	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
		299	* @{
		300	*/
		301	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /!< TimeoutA is used to detect SCL low level timeout. /
		302	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
		303	/**
		304	* @}
		305	*/
		306
		307	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
		308	* @{
		309	*/
		310	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
		311	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
		312	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
		313	/**
		314	* @}
		315	*/
		316
		317	/**
		318	* @}
		319	*/
		320
		321	/* Exported macro ------------------------------------------------------------*/
		322	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
		323	* @{
		324	*/
		325
		326	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
		327	* @{
		328	*/
		329
		330	/**
		331	* @brief Write a value in I2C register
		332	* @param __INSTANCE__ I2C Instance
		333	* @param __REG__ Register to be written
		334	* @param __VALUE__ Value to be written in the register
		335	* @retval None
		336	*/
		337	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		338
		339	/**
		340	* @brief Read a value in I2C register
		341	* @param __INSTANCE__ I2C Instance
		342	* @param __REG__ Register to be read
		343	* @retval Register value
		344	*/
		345	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		346	/**
		347	* @}
		348	*/
		349
		350	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
		351	* @{
		352	*/
		353	/**
		354	* @brief Configure the SDA setup, hold time and the SCL high, low period.
		355	* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
		356	* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
		357	* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
		358	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
		359	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
		360	* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
		361	*/
		362	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
		363	((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) \| \
		364	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) \| \
		365	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) \| \
		366	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) \| \
		367	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
		368	/**
		369	* @}
		370	*/
		371
		372	/**
		373	* @}
		374	*/
		375
		376	/* Exported functions --------------------------------------------------------*/
		377	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
		378	* @{
		379	*/
		380
		381	/** @defgroup I2C_LL_EF_Configuration Configuration
		382	* @{
		383	*/
		384
		385	/**
		386	* @brief Enable I2C peripheral (PE = 1).
		387	* @rmtoll CR1 PE LL_I2C_Enable
		388	* @param I2Cx I2C Instance.
		389	* @retval None
		390	*/
		391	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
		392	{
		393	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
		394	}
		395
		396	/**
		397	* @brief Disable I2C peripheral (PE = 0).
		398	* @note When PE = 0, the I2C SCL and SDA lines are released.
		399	* Internal state machines and status bits are put back to their reset value.
		400	* When cleared, PE must be kept low for at least 3 APB clock cycles.
		401	* @rmtoll CR1 PE LL_I2C_Disable
		402	* @param I2Cx I2C Instance.
		403	* @retval None
		404	*/
		405	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
		406	{
		407	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
		408	}
		409
		410	/**
		411	* @brief Check if the I2C peripheral is enabled or disabled.
		412	* @rmtoll CR1 PE LL_I2C_IsEnabled
		413	* @param I2Cx I2C Instance.
		414	* @retval State of bit (1 or 0).
		415	*/
		416	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
		417	{
		418	return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
		419	}
		420
		421	/**
		422	* @brief Configure Noise Filters (Analog and Digital).
		423	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
		424	* The filters can only be programmed when the I2C is disabled (PE = 0).
		425	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
		426	* CR1 DNF LL_I2C_ConfigFilters
		427	* @param I2Cx I2C Instance.
		428	* @param AnalogFilter This parameter can be one of the following values:
		429	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
		430	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
		431	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
		432	* This parameter is used to configure the digital noise filter on SDA and SCL input.
		433	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
		434	* @retval None
		435	*/
		436	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
		437	{
		438	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_CR1_DNF_Pos));
		439	}
		440
		441	/**
		442	* @brief Configure Digital Noise Filter.
		443	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
		444	* This filter can only be programmed when the I2C is disabled (PE = 0).
		445	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
		446	* @param I2Cx I2C Instance.
		447	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
		448	* This parameter is used to configure the digital noise filter on SDA and SCL input.
		449	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
		450	* @retval None
		451	*/
		452	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
		453	{
		454	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
		455	}
		456
		457	/**
		458	* @brief Get the current Digital Noise Filter configuration.
		459	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
		460	* @param I2Cx I2C Instance.
		461	* @retval Value between Min_Data=0x0 and Max_Data=0xF
		462	*/
		463	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
		464	{
		465	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
		466	}
		467
		468	/**
		469	* @brief Enable Analog Noise Filter.
		470	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
		471	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
		472	* @param I2Cx I2C Instance.
		473	* @retval None
		474	*/
		475	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
		476	{
		477	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
		478	}
		479
		480	/**
		481	* @brief Disable Analog Noise Filter.
		482	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
		483	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
		484	* @param I2Cx I2C Instance.
		485	* @retval None
		486	*/
		487	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
		488	{
		489	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
		490	}
		491
		492	/**
		493	* @brief Check if Analog Noise Filter is enabled or disabled.
		494	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
		495	* @param I2Cx I2C Instance.
		496	* @retval State of bit (1 or 0).
		497	*/
		498	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
		499	{
		500	return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
		501	}
		502
		503	/**
		504	* @brief Enable DMA transmission requests.
		505	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
		506	* @param I2Cx I2C Instance.
		507	* @retval None
		508	*/
		509	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
		510	{
		511	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
		512	}
		513
		514	/**
		515	* @brief Disable DMA transmission requests.
		516	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
		517	* @param I2Cx I2C Instance.
		518	* @retval None
		519	*/
		520	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
		521	{
		522	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
		523	}
		524
		525	/**
		526	* @brief Check if DMA transmission requests are enabled or disabled.
		527	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
		528	* @param I2Cx I2C Instance.
		529	* @retval State of bit (1 or 0).
		530	*/
		531	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
		532	{
		533	return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
		534	}
		535
		536	/**
		537	* @brief Enable DMA reception requests.
		538	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
		539	* @param I2Cx I2C Instance.
		540	* @retval None
		541	*/
		542	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
		543	{
		544	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
		545	}
		546
		547	/**
		548	* @brief Disable DMA reception requests.
		549	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
		550	* @param I2Cx I2C Instance.
		551	* @retval None
		552	*/
		553	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
		554	{
		555	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
		556	}
		557
		558	/**
		559	* @brief Check if DMA reception requests are enabled or disabled.
		560	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
		561	* @param I2Cx I2C Instance.
		562	* @retval State of bit (1 or 0).
		563	*/
		564	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
		565	{
		566	return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
		567	}
		568
		569	/**
		570	* @brief Get the data register address used for DMA transfer
		571	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
		572	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
		573	* @param I2Cx I2C Instance
		574	* @param Direction This parameter can be one of the following values:
		575	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
		576	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
		577	* @retval Address of data register
		578	*/
		579	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
		580	{
		581	register uint32_t data_reg_addr;
		582
		583	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
		584	{
		585	/* return address of TXDR register */
		586	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
		587	}
		588	else
		589	{
		590	/* return address of RXDR register */
		591	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
		592	}
		593
		594	return data_reg_addr;
		595	}
		596
		597	/**
		598	* @brief Enable Clock stretching.
		599	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		600	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
		601	* @param I2Cx I2C Instance.
		602	* @retval None
		603	*/
		604	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
		605	{
		606	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
		607	}
		608
		609	/**
		610	* @brief Disable Clock stretching.
		611	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		612	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
		613	* @param I2Cx I2C Instance.
		614	* @retval None
		615	*/
		616	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
		617	{
		618	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
		619	}
		620
		621	/**
		622	* @brief Check if Clock stretching is enabled or disabled.
		623	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
		624	* @param I2Cx I2C Instance.
		625	* @retval State of bit (1 or 0).
		626	*/
		627	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
		628	{
		629	return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
		630	}
		631
		632	/**
		633	* @brief Enable hardware byte control in slave mode.
		634	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
		635	* @param I2Cx I2C Instance.
		636	* @retval None
		637	*/
		638	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
		639	{
		640	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
		641	}
		642
		643	/**
		644	* @brief Disable hardware byte control in slave mode.
		645	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
		646	* @param I2Cx I2C Instance.
		647	* @retval None
		648	*/
		649	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
		650	{
		651	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
		652	}
		653
		654	/**
		655	* @brief Check if hardware byte control in slave mode is enabled or disabled.
		656	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
		657	* @param I2Cx I2C Instance.
		658	* @retval State of bit (1 or 0).
		659	*/
		660	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
		661	{
		662	return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
		663	}
		664
		665	#if defined(I2C_CR1_WUPEN)
		666	/**
		667	* @brief Enable Wakeup from STOP.
		668	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
		669	* WakeUpFromStop feature is supported by the I2Cx Instance.
		670	* @note This bit can only be programmed when Digital Filter is disabled.
		671	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
		672	* @param I2Cx I2C Instance.
		673	* @retval None
		674	*/
		675	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
		676	{
		677	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
		678	}
		679
		680	/**
		681	* @brief Disable Wakeup from STOP.
		682	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
		683	* WakeUpFromStop feature is supported by the I2Cx Instance.
		684	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
		685	* @param I2Cx I2C Instance.
		686	* @retval None
		687	*/
		688	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
		689	{
		690	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
		691	}
		692
		693	/**
		694	* @brief Check if Wakeup from STOP is enabled or disabled.
		695	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
		696	* WakeUpFromStop feature is supported by the I2Cx Instance.
		697	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
		698	* @param I2Cx I2C Instance.
		699	* @retval State of bit (1 or 0).
		700	*/
		701	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
		702	{
		703	return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
		704	}
		705	#endif
		706
		707	/**
		708	* @brief Enable General Call.
		709	* @note When enabled the Address 0x00 is ACKed.
		710	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
		711	* @param I2Cx I2C Instance.
		712	* @retval None
		713	*/
		714	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
		715	{
		716	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
		717	}
		718
		719	/**
		720	* @brief Disable General Call.
		721	* @note When disabled the Address 0x00 is NACKed.
		722	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
		723	* @param I2Cx I2C Instance.
		724	* @retval None
		725	*/
		726	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
		727	{
		728	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
		729	}
		730
		731	/**
		732	* @brief Check if General Call is enabled or disabled.
		733	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
		734	* @param I2Cx I2C Instance.
		735	* @retval State of bit (1 or 0).
		736	*/
		737	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
		738	{
		739	return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
		740	}
		741
		742	/**
		743	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
		744	* @note Changing this bit is not allowed, when the START bit is set.
		745	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
		746	* @param I2Cx I2C Instance.
		747	* @param AddressingMode This parameter can be one of the following values:
		748	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
		749	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
		750	* @retval None
		751	*/
		752	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
		753	{
		754	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
		755	}
		756
		757	/**
		758	* @brief Get the Master addressing mode.
		759	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
		760	* @param I2Cx I2C Instance.
		761	* @retval Returned value can be one of the following values:
		762	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
		763	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
		764	*/
		765	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
		766	{
		767	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
		768	}
		769
		770	/**
		771	* @brief Set the Own Address1.
		772	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
		773	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
		774	* @param I2Cx I2C Instance.
		775	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
		776	* @param OwnAddrSize This parameter can be one of the following values:
		777	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
		778	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
		779	* @retval None
		780	*/
		781	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
		782	{
		783	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
		784	}
		785
		786	/**
		787	* @brief Enable acknowledge on Own Address1 match address.
		788	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
		789	* @param I2Cx I2C Instance.
		790	* @retval None
		791	*/
		792	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
		793	{
		794	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
		795	}
		796
		797	/**
		798	* @brief Disable acknowledge on Own Address1 match address.
		799	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
		800	* @param I2Cx I2C Instance.
		801	* @retval None
		802	*/
		803	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
		804	{
		805	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
		806	}
		807
		808	/**
		809	* @brief Check if Own Address1 acknowledge is enabled or disabled.
		810	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
		811	* @param I2Cx I2C Instance.
		812	* @retval State of bit (1 or 0).
		813	*/
		814	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
		815	{
		816	return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
		817	}
		818
		819	/**
		820	* @brief Set the 7bits Own Address2.
		821	* @note This action has no effect if own address2 is enabled.
		822	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
		823	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
		824	* @param I2Cx I2C Instance.
		825	* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
		826	* @param OwnAddrMask This parameter can be one of the following values:
		827	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
		828	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
		829	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
		830	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
		831	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
		832	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
		833	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
		834	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
		835	* @retval None
		836	*/
		837	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
		838	{
		839	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
		840	}
		841
		842	/**
		843	* @brief Enable acknowledge on Own Address2 match address.
		844	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
		845	* @param I2Cx I2C Instance.
		846	* @retval None
		847	*/
		848	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
		849	{
		850	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
		851	}
		852
		853	/**
		854	* @brief Disable acknowledge on Own Address2 match address.
		855	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
		856	* @param I2Cx I2C Instance.
		857	* @retval None
		858	*/
		859	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
		860	{
		861	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
		862	}
		863
		864	/**
		865	* @brief Check if Own Address1 acknowledge is enabled or disabled.
		866	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
		867	* @param I2Cx I2C Instance.
		868	* @retval State of bit (1 or 0).
		869	*/
		870	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
		871	{
		872	return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
		873	}
		874
		875	/**
		876	* @brief Configure the SDA setup, hold time and the SCL high, low period.
		877	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
		878	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
		879	* @param I2Cx I2C Instance.
		880	* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
		881	* @note This parameter is computed with the STM32CubeMX Tool.
		882	* @retval None
		883	*/
		884	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
		885	{
		886	WRITE_REG(I2Cx->TIMINGR, Timing);
		887	}
		888
		889	/**
		890	* @brief Get the Timing Prescaler setting.
		891	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
		892	* @param I2Cx I2C Instance.
		893	* @retval Value between Min_Data=0x0 and Max_Data=0xF
		894	*/
		895	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
		896	{
		897	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
		898	}
		899
		900	/**
		901	* @brief Get the SCL low period setting.
		902	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
		903	* @param I2Cx I2C Instance.
		904	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		905	*/
		906	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
		907	{
		908	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
		909	}
		910
		911	/**
		912	* @brief Get the SCL high period setting.
		913	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
		914	* @param I2Cx I2C Instance.
		915	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		916	*/
		917	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
		918	{
		919	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
		920	}
		921
		922	/**
		923	* @brief Get the SDA hold time.
		924	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
		925	* @param I2Cx I2C Instance.
		926	* @retval Value between Min_Data=0x0 and Max_Data=0xF
		927	*/
		928	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
		929	{
		930	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
		931	}
		932
		933	/**
		934	* @brief Get the SDA setup time.
		935	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
		936	* @param I2Cx I2C Instance.
		937	* @retval Value between Min_Data=0x0 and Max_Data=0xF
		938	*/
		939	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
		940	{
		941	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
		942	}
		943
		944	/**
		945	* @brief Configure peripheral mode.
		946	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		947	* SMBus feature is supported by the I2Cx Instance.
		948	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
		949	* CR1 SMBDEN LL_I2C_SetMode
		950	* @param I2Cx I2C Instance.
		951	* @param PeripheralMode This parameter can be one of the following values:
		952	* @arg @ref LL_I2C_MODE_I2C
		953	* @arg @ref LL_I2C_MODE_SMBUS_HOST
		954	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
		955	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
		956	* @retval None
		957	*/
		958	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
		959	{
		960	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
		961	}
		962
		963	/**
		964	* @brief Get peripheral mode.
		965	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		966	* SMBus feature is supported by the I2Cx Instance.
		967	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
		968	* CR1 SMBDEN LL_I2C_GetMode
		969	* @param I2Cx I2C Instance.
		970	* @retval Returned value can be one of the following values:
		971	* @arg @ref LL_I2C_MODE_I2C
		972	* @arg @ref LL_I2C_MODE_SMBUS_HOST
		973	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
		974	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
		975	*/
		976	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
		977	{
		978	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
		979	}
		980
		981	/**
		982	* @brief Enable SMBus alert (Host or Device mode)
		983	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		984	* SMBus feature is supported by the I2Cx Instance.
		985	* @note SMBus Device mode:
		986	* - SMBus Alert pin is drived low and
		987	* Alert Response Address Header acknowledge is enabled.
		988	* SMBus Host mode:
		989	* - SMBus Alert pin management is supported.
		990	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
		991	* @param I2Cx I2C Instance.
		992	* @retval None
		993	*/
		994	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
		995	{
		996	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
		997	}
		998
		999	/**
		1000	* @brief Disable SMBus alert (Host or Device mode)
		1001	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1002	* SMBus feature is supported by the I2Cx Instance.
		1003	* @note SMBus Device mode:
		1004	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
		1005	* Alert Response Address Header acknowledge is disabled.
		1006	* SMBus Host mode:
		1007	* - SMBus Alert pin management is not supported.
		1008	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
		1009	* @param I2Cx I2C Instance.
		1010	* @retval None
		1011	*/
		1012	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
		1013	{
		1014	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
		1015	}
		1016
		1017	/**
		1018	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
		1019	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1020	* SMBus feature is supported by the I2Cx Instance.
		1021	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
		1022	* @param I2Cx I2C Instance.
		1023	* @retval State of bit (1 or 0).
		1024	*/
		1025	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
		1026	{
		1027	return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
		1028	}
		1029
		1030	/**
		1031	* @brief Enable SMBus Packet Error Calculation (PEC).
		1032	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1033	* SMBus feature is supported by the I2Cx Instance.
		1034	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
		1035	* @param I2Cx I2C Instance.
		1036	* @retval None
		1037	*/
		1038	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
		1039	{
		1040	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
		1041	}
		1042
		1043	/**
		1044	* @brief Disable SMBus Packet Error Calculation (PEC).
		1045	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1046	* SMBus feature is supported by the I2Cx Instance.
		1047	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
		1048	* @param I2Cx I2C Instance.
		1049	* @retval None
		1050	*/
		1051	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
		1052	{
		1053	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
		1054	}
		1055
		1056	/**
		1057	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
		1058	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1059	* SMBus feature is supported by the I2Cx Instance.
		1060	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
		1061	* @param I2Cx I2C Instance.
		1062	* @retval State of bit (1 or 0).
		1063	*/
		1064	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
		1065	{
		1066	return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
		1067	}
		1068
		1069	/**
		1070	* @brief Configure the SMBus Clock Timeout.
		1071	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1072	* SMBus feature is supported by the I2Cx Instance.
		1073	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
		1074	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
		1075	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
		1076	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
		1077	* @param I2Cx I2C Instance.
		1078	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
		1079	* @param TimeoutAMode This parameter can be one of the following values:
		1080	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
		1081	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
		1082	* @param TimeoutB
		1083	* @retval None
		1084	*/
		1085	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
		1086	uint32_t TimeoutB)
		1087	{
		1088	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
		1089	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
		1090	}
		1091
		1092	/**
		1093	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
		1094	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1095	* SMBus feature is supported by the I2Cx Instance.
		1096	* @note These bits can only be programmed when TimeoutA is disabled.
		1097	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
		1098	* @param I2Cx I2C Instance.
		1099	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
		1100	* @retval None
		1101	*/
		1102	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
		1103	{
		1104	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
		1105	}
		1106
		1107	/**
		1108	* @brief Get the SMBus Clock TimeoutA setting.
		1109	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1110	* SMBus feature is supported by the I2Cx Instance.
		1111	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
		1112	* @param I2Cx I2C Instance.
		1113	* @retval Value between Min_Data=0 and Max_Data=0xFFF
		1114	*/
		1115	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
		1116	{
		1117	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
		1118	}
		1119
		1120	/**
		1121	* @brief Set the SMBus Clock TimeoutA mode.
		1122	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1123	* SMBus feature is supported by the I2Cx Instance.
		1124	* @note This bit can only be programmed when TimeoutA is disabled.
		1125	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
		1126	* @param I2Cx I2C Instance.
		1127	* @param TimeoutAMode This parameter can be one of the following values:
		1128	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
		1129	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
		1130	* @retval None
		1131	*/
		1132	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
		1133	{
		1134	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
		1135	}
		1136
		1137	/**
		1138	* @brief Get the SMBus Clock TimeoutA mode.
		1139	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1140	* SMBus feature is supported by the I2Cx Instance.
		1141	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
		1142	* @param I2Cx I2C Instance.
		1143	* @retval Returned value can be one of the following values:
		1144	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
		1145	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
		1146	*/
		1147	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
		1148	{
		1149	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
		1150	}
		1151
		1152	/**
		1153	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
		1154	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1155	* SMBus feature is supported by the I2Cx Instance.
		1156	* @note These bits can only be programmed when TimeoutB is disabled.
		1157	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
		1158	* @param I2Cx I2C Instance.
		1159	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
		1160	* @retval None
		1161	*/
		1162	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
		1163	{
		1164	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
		1165	}
		1166
		1167	/**
		1168	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
		1169	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1170	* SMBus feature is supported by the I2Cx Instance.
		1171	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
		1172	* @param I2Cx I2C Instance.
		1173	* @retval Value between Min_Data=0 and Max_Data=0xFFF
		1174	*/
		1175	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
		1176	{
		1177	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
		1178	}
		1179
		1180	/**
		1181	* @brief Enable the SMBus Clock Timeout.
		1182	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1183	* SMBus feature is supported by the I2Cx Instance.
		1184	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
		1185	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
		1186	* @param I2Cx I2C Instance.
		1187	* @param ClockTimeout This parameter can be one of the following values:
		1188	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
		1189	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
		1190	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
		1191	* @retval None
		1192	*/
		1193	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
		1194	{
		1195	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
		1196	}
		1197
		1198	/**
		1199	* @brief Disable the SMBus Clock Timeout.
		1200	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1201	* SMBus feature is supported by the I2Cx Instance.
		1202	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
		1203	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
		1204	* @param I2Cx I2C Instance.
		1205	* @param ClockTimeout This parameter can be one of the following values:
		1206	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
		1207	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
		1208	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
		1209	* @retval None
		1210	*/
		1211	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
		1212	{
		1213	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
		1214	}
		1215
		1216	/**
		1217	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
		1218	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1219	* SMBus feature is supported by the I2Cx Instance.
		1220	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
		1221	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
		1222	* @param I2Cx I2C Instance.
		1223	* @param ClockTimeout This parameter can be one of the following values:
		1224	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
		1225	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
		1226	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
		1227	* @retval State of bit (1 or 0).
		1228	*/
		1229	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
		1230	{
		1231	return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
		1232	}
		1233
		1234	/**
		1235	* @}
		1236	*/
		1237
		1238	/** @defgroup I2C_LL_EF_IT_Management IT_Management
		1239	* @{
		1240	*/
		1241
		1242	/**
		1243	* @brief Enable TXIS interrupt.
		1244	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
		1245	* @param I2Cx I2C Instance.
		1246	* @retval None
		1247	*/
		1248	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
		1249	{
		1250	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
		1251	}
		1252
		1253	/**
		1254	* @brief Disable TXIS interrupt.
		1255	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
		1256	* @param I2Cx I2C Instance.
		1257	* @retval None
		1258	*/
		1259	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
		1260	{
		1261	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
		1262	}
		1263
		1264	/**
		1265	* @brief Check if the TXIS Interrupt is enabled or disabled.
		1266	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
		1267	* @param I2Cx I2C Instance.
		1268	* @retval State of bit (1 or 0).
		1269	*/
		1270	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
		1271	{
		1272	return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
		1273	}
		1274
		1275	/**
		1276	* @brief Enable RXNE interrupt.
		1277	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
		1278	* @param I2Cx I2C Instance.
		1279	* @retval None
		1280	*/
		1281	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
		1282	{
		1283	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
		1284	}
		1285
		1286	/**
		1287	* @brief Disable RXNE interrupt.
		1288	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
		1289	* @param I2Cx I2C Instance.
		1290	* @retval None
		1291	*/
		1292	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
		1293	{
		1294	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
		1295	}
		1296
		1297	/**
		1298	* @brief Check if the RXNE Interrupt is enabled or disabled.
		1299	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
		1300	* @param I2Cx I2C Instance.
		1301	* @retval State of bit (1 or 0).
		1302	*/
		1303	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
		1304	{
		1305	return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
		1306	}
		1307
		1308	/**
		1309	* @brief Enable Address match interrupt (slave mode only).
		1310	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
		1311	* @param I2Cx I2C Instance.
		1312	* @retval None
		1313	*/
		1314	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
		1315	{
		1316	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
		1317	}
		1318
		1319	/**
		1320	* @brief Disable Address match interrupt (slave mode only).
		1321	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
		1322	* @param I2Cx I2C Instance.
		1323	* @retval None
		1324	*/
		1325	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
		1326	{
		1327	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
		1328	}
		1329
		1330	/**
		1331	* @brief Check if Address match interrupt is enabled or disabled.
		1332	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
		1333	* @param I2Cx I2C Instance.
		1334	* @retval State of bit (1 or 0).
		1335	*/
		1336	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
		1337	{
		1338	return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
		1339	}
		1340
		1341	/**
		1342	* @brief Enable Not acknowledge received interrupt.
		1343	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
		1344	* @param I2Cx I2C Instance.
		1345	* @retval None
		1346	*/
		1347	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
		1348	{
		1349	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
		1350	}
		1351
		1352	/**
		1353	* @brief Disable Not acknowledge received interrupt.
		1354	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
		1355	* @param I2Cx I2C Instance.
		1356	* @retval None
		1357	*/
		1358	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
		1359	{
		1360	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
		1361	}
		1362
		1363	/**
		1364	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
		1365	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
		1366	* @param I2Cx I2C Instance.
		1367	* @retval State of bit (1 or 0).
		1368	*/
		1369	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
		1370	{
		1371	return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
		1372	}
		1373
		1374	/**
		1375	* @brief Enable STOP detection interrupt.
		1376	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
		1377	* @param I2Cx I2C Instance.
		1378	* @retval None
		1379	*/
		1380	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
		1381	{
		1382	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
		1383	}
		1384
		1385	/**
		1386	* @brief Disable STOP detection interrupt.
		1387	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
		1388	* @param I2Cx I2C Instance.
		1389	* @retval None
		1390	*/
		1391	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
		1392	{
		1393	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
		1394	}
		1395
		1396	/**
		1397	* @brief Check if STOP detection interrupt is enabled or disabled.
		1398	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
		1399	* @param I2Cx I2C Instance.
		1400	* @retval State of bit (1 or 0).
		1401	*/
		1402	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
		1403	{
		1404	return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
		1405	}
		1406
		1407	/**
		1408	* @brief Enable Transfer Complete interrupt.
		1409	* @note Any of these events will generate interrupt :
		1410	* Transfer Complete (TC)
		1411	* Transfer Complete Reload (TCR)
		1412	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
		1413	* @param I2Cx I2C Instance.
		1414	* @retval None
		1415	*/
		1416	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
		1417	{
		1418	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
		1419	}
		1420
		1421	/**
		1422	* @brief Disable Transfer Complete interrupt.
		1423	* @note Any of these events will generate interrupt :
		1424	* Transfer Complete (TC)
		1425	* Transfer Complete Reload (TCR)
		1426	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
		1427	* @param I2Cx I2C Instance.
		1428	* @retval None
		1429	*/
		1430	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
		1431	{
		1432	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
		1433	}
		1434
		1435	/**
		1436	* @brief Check if Transfer Complete interrupt is enabled or disabled.
		1437	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
		1438	* @param I2Cx I2C Instance.
		1439	* @retval State of bit (1 or 0).
		1440	*/
		1441	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
		1442	{
		1443	return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
		1444	}
		1445
		1446	/**
		1447	* @brief Enable Error interrupts.
		1448	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1449	* SMBus feature is supported by the I2Cx Instance.
		1450	* @note Any of these errors will generate interrupt :
		1451	* Arbitration Loss (ARLO)
		1452	* Bus Error detection (BERR)
		1453	* Overrun/Underrun (OVR)
		1454	* SMBus Timeout detection (TIMEOUT)
		1455	* SMBus PEC error detection (PECERR)
		1456	* SMBus Alert pin event detection (ALERT)
		1457	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
		1458	* @param I2Cx I2C Instance.
		1459	* @retval None
		1460	*/
		1461	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
		1462	{
		1463	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
		1464	}
		1465
		1466	/**
		1467	* @brief Disable Error interrupts.
		1468	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1469	* SMBus feature is supported by the I2Cx Instance.
		1470	* @note Any of these errors will generate interrupt :
		1471	* Arbitration Loss (ARLO)
		1472	* Bus Error detection (BERR)
		1473	* Overrun/Underrun (OVR)
		1474	* SMBus Timeout detection (TIMEOUT)
		1475	* SMBus PEC error detection (PECERR)
		1476	* SMBus Alert pin event detection (ALERT)
		1477	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
		1478	* @param I2Cx I2C Instance.
		1479	* @retval None
		1480	*/
		1481	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
		1482	{
		1483	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
		1484	}
		1485
		1486	/**
		1487	* @brief Check if Error interrupts are enabled or disabled.
		1488	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
		1489	* @param I2Cx I2C Instance.
		1490	* @retval State of bit (1 or 0).
		1491	*/
		1492	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
		1493	{
		1494	return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
		1495	}
		1496
		1497	/**
		1498	* @}
		1499	*/
		1500
		1501	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
		1502	* @{
		1503	*/
		1504
		1505	/**
		1506	* @brief Indicate the status of Transmit data register empty flag.
		1507	* @note RESET: When next data is written in Transmit data register.
		1508	* SET: When Transmit data register is empty.
		1509	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
		1510	* @param I2Cx I2C Instance.
		1511	* @retval State of bit (1 or 0).
		1512	*/
		1513	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
		1514	{
		1515	return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
		1516	}
		1517
		1518	/**
		1519	* @brief Indicate the status of Transmit interrupt flag.
		1520	* @note RESET: When next data is written in Transmit data register.
		1521	* SET: When Transmit data register is empty.
		1522	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
		1523	* @param I2Cx I2C Instance.
		1524	* @retval State of bit (1 or 0).
		1525	*/
		1526	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
		1527	{
		1528	return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
		1529	}
		1530
		1531	/**
		1532	* @brief Indicate the status of Receive data register not empty flag.
		1533	* @note RESET: When Receive data register is read.
		1534	* SET: When the received data is copied in Receive data register.
		1535	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
		1536	* @param I2Cx I2C Instance.
		1537	* @retval State of bit (1 or 0).
		1538	*/
		1539	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
		1540	{
		1541	return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
		1542	}
		1543
		1544	/**
		1545	* @brief Indicate the status of Address matched flag (slave mode).
		1546	* @note RESET: Clear default value.
		1547	* SET: When the received slave address matched with one of the enabled slave address.
		1548	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
		1549	* @param I2Cx I2C Instance.
		1550	* @retval State of bit (1 or 0).
		1551	*/
		1552	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
		1553	{
		1554	return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
		1555	}
		1556
		1557	/**
		1558	* @brief Indicate the status of Not Acknowledge received flag.
		1559	* @note RESET: Clear default value.
		1560	* SET: When a NACK is received after a byte transmission.
		1561	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
		1562	* @param I2Cx I2C Instance.
		1563	* @retval State of bit (1 or 0).
		1564	*/
		1565	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
		1566	{
		1567	return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
		1568	}
		1569
		1570	/**
		1571	* @brief Indicate the status of Stop detection flag.
		1572	* @note RESET: Clear default value.
		1573	* SET: When a Stop condition is detected.
		1574	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
		1575	* @param I2Cx I2C Instance.
		1576	* @retval State of bit (1 or 0).
		1577	*/
		1578	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
		1579	{
		1580	return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
		1581	}
		1582
		1583	/**
		1584	* @brief Indicate the status of Transfer complete flag (master mode).
		1585	* @note RESET: Clear default value.
		1586	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
		1587	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
		1588	* @param I2Cx I2C Instance.
		1589	* @retval State of bit (1 or 0).
		1590	*/
		1591	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
		1592	{
		1593	return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
		1594	}
		1595
		1596	/**
		1597	* @brief Indicate the status of Transfer complete flag (master mode).
		1598	* @note RESET: Clear default value.
		1599	* SET: When RELOAD=1 and NBYTES date have been transferred.
		1600	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
		1601	* @param I2Cx I2C Instance.
		1602	* @retval State of bit (1 or 0).
		1603	*/
		1604	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
		1605	{
		1606	return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
		1607	}
		1608
		1609	/**
		1610	* @brief Indicate the status of Bus error flag.
		1611	* @note RESET: Clear default value.
		1612	* SET: When a misplaced Start or Stop condition is detected.
		1613	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
		1614	* @param I2Cx I2C Instance.
		1615	* @retval State of bit (1 or 0).
		1616	*/
		1617	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
		1618	{
		1619	return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
		1620	}
		1621
		1622	/**
		1623	* @brief Indicate the status of Arbitration lost flag.
		1624	* @note RESET: Clear default value.
		1625	* SET: When arbitration lost.
		1626	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
		1627	* @param I2Cx I2C Instance.
		1628	* @retval State of bit (1 or 0).
		1629	*/
		1630	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
		1631	{
		1632	return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
		1633	}
		1634
		1635	/**
		1636	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
		1637	* @note RESET: Clear default value.
		1638	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
		1639	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
		1640	* @param I2Cx I2C Instance.
		1641	* @retval State of bit (1 or 0).
		1642	*/
		1643	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
		1644	{
		1645	return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
		1646	}
		1647
		1648	/**
		1649	* @brief Indicate the status of SMBus PEC error flag in reception.
		1650	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1651	* SMBus feature is supported by the I2Cx Instance.
		1652	* @note RESET: Clear default value.
		1653	* SET: When the received PEC does not match with the PEC register content.
		1654	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
		1655	* @param I2Cx I2C Instance.
		1656	* @retval State of bit (1 or 0).
		1657	*/
		1658	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
		1659	{
		1660	return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
		1661	}
		1662
		1663	/**
		1664	* @brief Indicate the status of SMBus Timeout detection flag.
		1665	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1666	* SMBus feature is supported by the I2Cx Instance.
		1667	* @note RESET: Clear default value.
		1668	* SET: When a timeout or extended clock timeout occurs.
		1669	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
		1670	* @param I2Cx I2C Instance.
		1671	* @retval State of bit (1 or 0).
		1672	*/
		1673	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
		1674	{
		1675	return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
		1676	}
		1677
		1678	/**
		1679	* @brief Indicate the status of SMBus alert flag.
		1680	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1681	* SMBus feature is supported by the I2Cx Instance.
		1682	* @note RESET: Clear default value.
		1683	* SET: When SMBus host configuration, SMBus alert enabled and
		1684	* a falling edge event occurs on SMBA pin.
		1685	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
		1686	* @param I2Cx I2C Instance.
		1687	* @retval State of bit (1 or 0).
		1688	*/
		1689	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
		1690	{
		1691	return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
		1692	}
		1693
		1694	/**
		1695	* @brief Indicate the status of Bus Busy flag.
		1696	* @note RESET: Clear default value.
		1697	* SET: When a Start condition is detected.
		1698	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
		1699	* @param I2Cx I2C Instance.
		1700	* @retval State of bit (1 or 0).
		1701	*/
		1702	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
		1703	{
		1704	return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
		1705	}
		1706
		1707	/**
		1708	* @brief Clear Address Matched flag.
		1709	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
		1710	* @param I2Cx I2C Instance.
		1711	* @retval None
		1712	*/
		1713	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
		1714	{
		1715	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
		1716	}
		1717
		1718	/**
		1719	* @brief Clear Not Acknowledge flag.
		1720	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
		1721	* @param I2Cx I2C Instance.
		1722	* @retval None
		1723	*/
		1724	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
		1725	{
		1726	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
		1727	}
		1728
		1729	/**
		1730	* @brief Clear Stop detection flag.
		1731	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
		1732	* @param I2Cx I2C Instance.
		1733	* @retval None
		1734	*/
		1735	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
		1736	{
		1737	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
		1738	}
		1739
		1740	/**
		1741	* @brief Clear Transmit data register empty flag (TXE).
		1742	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
		1743	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
		1744	* @param I2Cx I2C Instance.
		1745	* @retval None
		1746	*/
		1747	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
		1748	{
		1749	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
		1750	}
		1751
		1752	/**
		1753	* @brief Clear Bus error flag.
		1754	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
		1755	* @param I2Cx I2C Instance.
		1756	* @retval None
		1757	*/
		1758	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
		1759	{
		1760	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
		1761	}
		1762
		1763	/**
		1764	* @brief Clear Arbitration lost flag.
		1765	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
		1766	* @param I2Cx I2C Instance.
		1767	* @retval None
		1768	*/
		1769	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
		1770	{
		1771	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
		1772	}
		1773
		1774	/**
		1775	* @brief Clear Overrun/Underrun flag.
		1776	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
		1777	* @param I2Cx I2C Instance.
		1778	* @retval None
		1779	*/
		1780	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
		1781	{
		1782	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
		1783	}
		1784
		1785	/**
		1786	* @brief Clear SMBus PEC error flag.
		1787	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1788	* SMBus feature is supported by the I2Cx Instance.
		1789	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
		1790	* @param I2Cx I2C Instance.
		1791	* @retval None
		1792	*/
		1793	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
		1794	{
		1795	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
		1796	}
		1797
		1798	/**
		1799	* @brief Clear SMBus Timeout detection flag.
		1800	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1801	* SMBus feature is supported by the I2Cx Instance.
		1802	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
		1803	* @param I2Cx I2C Instance.
		1804	* @retval None
		1805	*/
		1806	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
		1807	{
		1808	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
		1809	}
		1810
		1811	/**
		1812	* @brief Clear SMBus Alert flag.
		1813	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		1814	* SMBus feature is supported by the I2Cx Instance.
		1815	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
		1816	* @param I2Cx I2C Instance.
		1817	* @retval None
		1818	*/
		1819	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
		1820	{
		1821	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
		1822	}
		1823
		1824	/**
		1825	* @}
		1826	*/
		1827
		1828	/** @defgroup I2C_LL_EF_Data_Management Data_Management
		1829	* @{
		1830	*/
		1831
		1832	/**
		1833	* @brief Enable automatic STOP condition generation (master mode).
		1834	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
		1835	* This bit has no effect in slave mode or when RELOAD bit is set.
		1836	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
		1837	* @param I2Cx I2C Instance.
		1838	* @retval None
		1839	*/
		1840	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
		1841	{
		1842	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
		1843	}
		1844
		1845	/**
		1846	* @brief Disable automatic STOP condition generation (master mode).
		1847	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
		1848	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
		1849	* @param I2Cx I2C Instance.
		1850	* @retval None
		1851	*/
		1852	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
		1853	{
		1854	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
		1855	}
		1856
		1857	/**
		1858	* @brief Check if automatic STOP condition is enabled or disabled.
		1859	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
		1860	* @param I2Cx I2C Instance.
		1861	* @retval State of bit (1 or 0).
		1862	*/
		1863	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
		1864	{
		1865	return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
		1866	}
		1867
		1868	/**
		1869	* @brief Enable reload mode (master mode).
		1870	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
		1871	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
		1872	* @param I2Cx I2C Instance.
		1873	* @retval None
		1874	*/
		1875	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
		1876	{
		1877	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
		1878	}
		1879
		1880	/**
		1881	* @brief Disable reload mode (master mode).
		1882	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
		1883	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
		1884	* @param I2Cx I2C Instance.
		1885	* @retval None
		1886	*/
		1887	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
		1888	{
		1889	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
		1890	}
		1891
		1892	/**
		1893	* @brief Check if reload mode is enabled or disabled.
		1894	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
		1895	* @param I2Cx I2C Instance.
		1896	* @retval State of bit (1 or 0).
		1897	*/
		1898	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
		1899	{
		1900	return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
		1901	}
		1902
		1903	/**
		1904	* @brief Configure the number of bytes for transfer.
		1905	* @note Changing these bits when START bit is set is not allowed.
		1906	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
		1907	* @param I2Cx I2C Instance.
		1908	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
		1909	* @retval None
		1910	*/
		1911	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
		1912	{
		1913	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
		1914	}
		1915
		1916	/**
		1917	* @brief Get the number of bytes configured for transfer.
		1918	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
		1919	* @param I2Cx I2C Instance.
		1920	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
		1921	*/
		1922	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
		1923	{
		1924	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
		1925	}
		1926
		1927	/**
		1928	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
		1929	* @note Usage in Slave mode only.
		1930	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
		1931	* @param I2Cx I2C Instance.
		1932	* @param TypeAcknowledge This parameter can be one of the following values:
		1933	* @arg @ref LL_I2C_ACK
		1934	* @arg @ref LL_I2C_NACK
		1935	* @retval None
		1936	*/
		1937	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
		1938	{
		1939	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
		1940	}
		1941
		1942	/**
		1943	* @brief Generate a START or RESTART condition
		1944	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
		1945	* This action has no effect when RELOAD is set.
		1946	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
		1947	* @param I2Cx I2C Instance.
		1948	* @retval None
		1949	*/
		1950	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
		1951	{
		1952	SET_BIT(I2Cx->CR2, I2C_CR2_START);
		1953	}
		1954
		1955	/**
		1956	* @brief Generate a STOP condition after the current byte transfer (master mode).
		1957	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
		1958	* @param I2Cx I2C Instance.
		1959	* @retval None
		1960	*/
		1961	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
		1962	{
		1963	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
		1964	}
		1965
		1966	/**
		1967	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
		1968	* @note The master sends the complete 10bit slave address read sequence :
		1969	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
		1970	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
		1971	* @param I2Cx I2C Instance.
		1972	* @retval None
		1973	*/
		1974	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
		1975	{
		1976	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
		1977	}
		1978
		1979	/**
		1980	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
		1981	* @note The master only sends the first 7 bits of 10bit address in Read direction.
		1982	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
		1983	* @param I2Cx I2C Instance.
		1984	* @retval None
		1985	*/
		1986	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
		1987	{
		1988	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
		1989	}
		1990
		1991	/**
		1992	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
		1993	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
		1994	* @param I2Cx I2C Instance.
		1995	* @retval State of bit (1 or 0).
		1996	*/
		1997	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
		1998	{
		1999	return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
		2000	}
		2001
		2002	/**
		2003	* @brief Configure the transfer direction (master mode).
		2004	* @note Changing these bits when START bit is set is not allowed.
		2005	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
		2006	* @param I2Cx I2C Instance.
		2007	* @param TransferRequest This parameter can be one of the following values:
		2008	* @arg @ref LL_I2C_REQUEST_WRITE
		2009	* @arg @ref LL_I2C_REQUEST_READ
		2010	* @retval None
		2011	*/
		2012	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
		2013	{
		2014	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
		2015	}
		2016
		2017	/**
		2018	* @brief Get the transfer direction requested (master mode).
		2019	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
		2020	* @param I2Cx I2C Instance.
		2021	* @retval Returned value can be one of the following values:
		2022	* @arg @ref LL_I2C_REQUEST_WRITE
		2023	* @arg @ref LL_I2C_REQUEST_READ
		2024	*/
		2025	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
		2026	{
		2027	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
		2028	}
		2029
		2030	/**
		2031	* @brief Configure the slave address for transfer (master mode).
		2032	* @note Changing these bits when START bit is set is not allowed.
		2033	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
		2034	* @param I2Cx I2C Instance.
		2035	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
		2036	* @retval None
		2037	*/
		2038	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
		2039	{
		2040	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
		2041	}
		2042
		2043	/**
		2044	* @brief Get the slave address programmed for transfer.
		2045	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
		2046	* @param I2Cx I2C Instance.
		2047	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
		2048	*/
		2049	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
		2050	{
		2051	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
		2052	}
		2053
		2054	/**
		2055	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
		2056	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
		2057	* CR2 ADD10 LL_I2C_HandleTransfer\n
		2058	* CR2 RD_WRN LL_I2C_HandleTransfer\n
		2059	* CR2 START LL_I2C_HandleTransfer\n
		2060	* CR2 STOP LL_I2C_HandleTransfer\n
		2061	* CR2 RELOAD LL_I2C_HandleTransfer\n
		2062	* CR2 NBYTES LL_I2C_HandleTransfer\n
		2063	* CR2 AUTOEND LL_I2C_HandleTransfer\n
		2064	* CR2 HEAD10R LL_I2C_HandleTransfer
		2065	* @param I2Cx I2C Instance.
		2066	* @param SlaveAddr Specifies the slave address to be programmed.
		2067	* @param SlaveAddrSize This parameter can be one of the following values:
		2068	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
		2069	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
		2070	* @param TransferSize Specifies the number of bytes to be programmed.
		2071	* This parameter must be a value between Min_Data=0 and Max_Data=255.
		2072	* @param EndMode This parameter can be one of the following values:
		2073	* @arg @ref LL_I2C_MODE_RELOAD
		2074	* @arg @ref LL_I2C_MODE_AUTOEND
		2075	* @arg @ref LL_I2C_MODE_SOFTEND
		2076	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
		2077	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
		2078	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
		2079	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
		2080	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
		2081	* @param Request This parameter can be one of the following values:
		2082	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
		2083	* @arg @ref LL_I2C_GENERATE_STOP
		2084	* @arg @ref LL_I2C_GENERATE_START_READ
		2085	* @arg @ref LL_I2C_GENERATE_START_WRITE
		2086	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
		2087	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
		2088	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
		2089	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
		2090	* @retval None
		2091	*/
		2092	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
		2093	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
		2094	{
		2095	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
		2096	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
		2097	SlaveAddr \| SlaveAddrSize \| (TransferSize << I2C_CR2_NBYTES_Pos) \| EndMode \| Request);
		2098	}
		2099
		2100	/**
		2101	* @brief Indicate the value of transfer direction (slave mode).
		2102	* @note RESET: Write transfer, Slave enters in receiver mode.
		2103	* SET: Read transfer, Slave enters in transmitter mode.
		2104	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
		2105	* @param I2Cx I2C Instance.
		2106	* @retval Returned value can be one of the following values:
		2107	* @arg @ref LL_I2C_DIRECTION_WRITE
		2108	* @arg @ref LL_I2C_DIRECTION_READ
		2109	*/
		2110	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
		2111	{
		2112	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
		2113	}
		2114
		2115	/**
		2116	* @brief Return the slave matched address.
		2117	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
		2118	* @param I2Cx I2C Instance.
		2119	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
		2120	*/
		2121	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
		2122	{
		2123	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
		2124	}
		2125
		2126	/**
		2127	* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
		2128	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		2129	* SMBus feature is supported by the I2Cx Instance.
		2130	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
		2131	* This bit has no effect when RELOAD bit is set.
		2132	* This bit has no effect in device mode when SBC bit is not set.
		2133	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
		2134	* @param I2Cx I2C Instance.
		2135	* @retval None
		2136	*/
		2137	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
		2138	{
		2139	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
		2140	}
		2141
		2142	/**
		2143	* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
		2144	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		2145	* SMBus feature is supported by the I2Cx Instance.
		2146	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
		2147	* @param I2Cx I2C Instance.
		2148	* @retval State of bit (1 or 0).
		2149	*/
		2150	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
		2151	{
		2152	return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
		2153	}
		2154
		2155	/**
		2156	* @brief Get the SMBus Packet Error byte calculated.
		2157	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
		2158	* SMBus feature is supported by the I2Cx Instance.
		2159	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
		2160	* @param I2Cx I2C Instance.
		2161	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		2162	*/
		2163	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
		2164	{
		2165	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
		2166	}
		2167
		2168	/**
		2169	* @brief Read Receive Data register.
		2170	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
		2171	* @param I2Cx I2C Instance.
		2172	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		2173	*/
		2174	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
		2175	{
		2176	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
		2177	}
		2178
		2179	/**
		2180	* @brief Write in Transmit Data Register .
		2181	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
		2182	* @param I2Cx I2C Instance.
		2183	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
		2184	* @retval None
		2185	*/
		2186	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
		2187	{
		2188	WRITE_REG(I2Cx->TXDR, Data);
		2189	}
		2190
		2191	/**
		2192	* @}
		2193	*/
		2194
		2195	#if defined(USE_FULL_LL_DRIVER)
		2196	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
		2197	* @{
		2198	*/
		2199
		2200	ErrorStatus LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
		2201	ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
		2202	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
		2203
		2204
		2205	/**
		2206	* @}
		2207	*/
		2208	#endif /* USE_FULL_LL_DRIVER */
		2209
		2210	/**
		2211	* @}
		2212	*/
		2213
		2214	/**
		2215	* @}
		2216	*/
		2217
		2218	#endif /* I2C1 \|\| I2C2 */
		2219
		2220	/**
		2221	* @}
		2222	*/
		2223
		2224	#ifdef __cplusplus
		2225	}
		2226	#endif
		2227
		2228	#endif /* STM32F0xx_LL_I2C_H */
		2229
		2230	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_i2c.h – Rev 2