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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_ll_dma.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of DMA LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F0xx_LL_DMA_H |
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| 22 | #define __STM32F0xx_LL_DMA_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined (DMA1) || defined (DMA2) |
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| 36 | |||
| 37 | /** @defgroup DMA_LL DMA |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | /** @defgroup DMA_LL_Private_Variables DMA Private Variables |
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| 44 | * @{ |
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| 45 | */ |
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| 46 | /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ |
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| 47 | static const uint8_t CHANNEL_OFFSET_TAB[] = |
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| 48 | { |
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| 49 | (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), |
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| 50 | (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), |
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| 51 | (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), |
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| 52 | (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), |
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| 53 | (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), |
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| 54 | #if defined(DMA1_Channel6) |
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| 55 | (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), |
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| 56 | #endif /*DMA1_Channel6*/ |
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| 57 | #if defined(DMA1_Channel7) |
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| 58 | (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) |
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| 59 | #endif /*DMA1_Channel7*/ |
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| 60 | }; |
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| 61 | /** |
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| 62 | * @} |
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| 63 | */ |
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| 64 | |||
| 65 | /* Private constants ---------------------------------------------------------*/ |
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| 66 | /** @defgroup DMA_LL_Private_Constants DMA Private Constants |
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| 67 | * @{ |
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| 68 | */ |
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| 69 | /* Define used to get CSELR register offset */ |
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| 70 | #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) |
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| 71 | |||
| 72 | /* Defines used for the bit position in the register and perform offsets */ |
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| 73 | #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) |
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| 74 | /** |
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| 75 | * @} |
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| 76 | */ |
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| 77 | |||
| 78 | /* Private macros ------------------------------------------------------------*/ |
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| 79 | #if defined(USE_FULL_LL_DRIVER) |
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| 80 | /** @defgroup DMA_LL_Private_Macros DMA Private Macros |
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| 81 | * @{ |
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| 82 | */ |
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| 83 | /** |
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| 84 | * @} |
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| 85 | */ |
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| 86 | #endif /*USE_FULL_LL_DRIVER*/ |
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| 87 | |||
| 88 | /* Exported types ------------------------------------------------------------*/ |
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| 89 | #if defined(USE_FULL_LL_DRIVER) |
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| 90 | /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure |
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| 91 | * @{ |
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| 92 | */ |
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| 93 | typedef struct |
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| 94 | { |
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| 95 | uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer |
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| 96 | or as Source base address in case of memory to memory transfer direction. |
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| 97 | |||
| 98 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
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| 99 | |||
| 100 | uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer |
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| 101 | or as Destination base address in case of memory to memory transfer direction. |
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| 102 | |||
| 103 | This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ |
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| 104 | |||
| 105 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
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| 106 | from memory to memory or from peripheral to memory. |
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| 107 | This parameter can be a value of @ref DMA_LL_EC_DIRECTION |
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| 108 | |||
| 109 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ |
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| 110 | |||
| 111 | uint32_t Mode; /*!< Specifies the normal or circular operation mode. |
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| 112 | This parameter can be a value of @ref DMA_LL_EC_MODE |
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| 113 | @note: The circular buffer mode cannot be used if the memory to memory |
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| 114 | data transfer direction is configured on the selected Channel |
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| 115 | |||
| 116 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ |
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| 117 | |||
| 118 | uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction |
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| 119 | is incremented or not. |
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| 120 | This parameter can be a value of @ref DMA_LL_EC_PERIPH |
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| 121 | |||
| 122 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ |
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| 123 | |||
| 124 | uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction |
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| 125 | is incremented or not. |
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| 126 | This parameter can be a value of @ref DMA_LL_EC_MEMORY |
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| 127 | |||
| 128 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ |
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| 129 | |||
| 130 | uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) |
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| 131 | in case of memory to memory transfer direction. |
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| 132 | This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN |
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| 133 | |||
| 134 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ |
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| 135 | |||
| 136 | uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) |
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| 137 | in case of memory to memory transfer direction. |
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| 138 | This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN |
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| 139 | |||
| 140 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ |
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| 141 | |||
| 142 | uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. |
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| 143 | The data unit is equal to the source buffer configuration set in PeripheralSize |
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| 144 | or MemorySize parameters depending in the transfer direction. |
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| 145 | This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF |
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| 146 | |||
| 147 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ |
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| 148 | #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) |
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| 149 | |||
| 150 | uint32_t PeriphRequest; /*!< Specifies the peripheral request. |
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| 151 | This parameter can be a value of @ref DMA_LL_EC_REQUEST |
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| 152 | |||
| 153 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ |
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| 154 | #endif |
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| 155 | |||
| 156 | uint32_t Priority; /*!< Specifies the channel priority level. |
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| 157 | This parameter can be a value of @ref DMA_LL_EC_PRIORITY |
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| 158 | |||
| 159 | This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ |
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| 160 | |||
| 161 | } LL_DMA_InitTypeDef; |
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| 162 | /** |
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| 163 | * @} |
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| 164 | */ |
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| 165 | #endif /*USE_FULL_LL_DRIVER*/ |
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| 166 | |||
| 167 | /* Exported constants --------------------------------------------------------*/ |
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| 168 | /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants |
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| 169 | * @{ |
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| 170 | */ |
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| 171 | /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines |
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| 172 | * @brief Flags defines which can be used with LL_DMA_WriteReg function |
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| 173 | * @{ |
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| 174 | */ |
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| 175 | #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ |
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| 176 | #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ |
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| 177 | #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ |
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| 178 | #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ |
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| 179 | #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ |
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| 180 | #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ |
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| 181 | #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ |
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| 182 | #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ |
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| 183 | #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ |
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| 184 | #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ |
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| 185 | #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ |
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| 186 | #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ |
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| 187 | #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ |
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| 188 | #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ |
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| 189 | #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ |
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| 190 | #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ |
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| 191 | #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ |
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| 192 | #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ |
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| 193 | #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ |
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| 194 | #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ |
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| 195 | #if defined(DMA1_Channel6) |
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| 196 | #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ |
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| 197 | #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ |
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| 198 | #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ |
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| 199 | #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ |
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| 200 | #endif |
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| 201 | #if defined(DMA1_Channel7) |
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| 202 | #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ |
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| 203 | #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ |
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| 204 | #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ |
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| 205 | #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ |
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| 206 | #endif |
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| 207 | /** |
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| 208 | * @} |
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| 209 | */ |
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| 210 | |||
| 211 | /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines |
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| 212 | * @brief Flags defines which can be used with LL_DMA_ReadReg function |
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| 213 | * @{ |
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| 214 | */ |
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| 215 | #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ |
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| 216 | #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ |
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| 217 | #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ |
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| 218 | #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ |
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| 219 | #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ |
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| 220 | #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ |
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| 221 | #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ |
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| 222 | #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ |
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| 223 | #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ |
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| 224 | #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ |
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| 225 | #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ |
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| 226 | #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ |
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| 227 | #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ |
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| 228 | #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ |
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| 229 | #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ |
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| 230 | #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ |
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| 231 | #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ |
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| 232 | #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ |
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| 233 | #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ |
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| 234 | #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ |
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| 235 | #if defined(DMA1_Channel6) |
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| 236 | #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ |
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| 237 | #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ |
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| 238 | #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ |
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| 239 | #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ |
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| 240 | #endif |
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| 241 | #if defined(DMA1_Channel7) |
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| 242 | #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ |
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| 243 | #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ |
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| 244 | #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ |
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| 245 | #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ |
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| 246 | #endif |
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| 247 | /** |
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| 248 | * @} |
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| 249 | */ |
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| 250 | |||
| 251 | /** @defgroup DMA_LL_EC_IT IT Defines |
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| 252 | * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions |
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| 253 | * @{ |
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| 254 | */ |
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| 255 | #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ |
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| 256 | #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ |
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| 257 | #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ |
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| 258 | /** |
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| 259 | * @} |
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| 260 | */ |
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| 261 | |||
| 262 | /** @defgroup DMA_LL_EC_CHANNEL CHANNEL |
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| 263 | * @{ |
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| 264 | */ |
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| 265 | #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ |
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| 266 | #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ |
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| 267 | #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ |
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| 268 | #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ |
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| 269 | #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ |
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| 270 | #if defined(DMA1_Channel6) |
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| 271 | #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ |
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| 272 | #endif |
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| 273 | #if defined(DMA1_Channel7) |
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| 274 | #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ |
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| 275 | #endif |
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| 276 | #if defined(USE_FULL_LL_DRIVER) |
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| 277 | #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ |
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| 278 | #endif /*USE_FULL_LL_DRIVER*/ |
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| 279 | /** |
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| 280 | * @} |
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| 281 | */ |
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| 282 | |||
| 283 | /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction |
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| 284 | * @{ |
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| 285 | */ |
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| 286 | #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ |
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| 287 | #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ |
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| 288 | #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ |
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| 289 | /** |
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| 290 | * @} |
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| 291 | */ |
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| 292 | |||
| 293 | /** @defgroup DMA_LL_EC_MODE Transfer mode |
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| 294 | * @{ |
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| 295 | */ |
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| 296 | #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ |
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| 297 | #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ |
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| 298 | /** |
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| 299 | * @} |
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| 300 | */ |
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| 301 | |||
| 302 | /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode |
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| 303 | * @{ |
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| 304 | */ |
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| 305 | #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ |
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| 306 | #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ |
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| 307 | /** |
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| 308 | * @} |
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| 309 | */ |
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| 310 | |||
| 311 | /** @defgroup DMA_LL_EC_MEMORY Memory increment mode |
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| 312 | * @{ |
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| 313 | */ |
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| 314 | #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ |
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| 315 | #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ |
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| 316 | /** |
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| 317 | * @} |
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| 318 | */ |
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| 319 | |||
| 320 | /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment |
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| 321 | * @{ |
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| 322 | */ |
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| 323 | #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ |
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| 324 | #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ |
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| 325 | #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ |
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| 326 | /** |
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| 327 | * @} |
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| 328 | */ |
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| 329 | |||
| 330 | /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment |
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| 331 | * @{ |
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| 332 | */ |
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| 333 | #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ |
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| 334 | #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ |
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| 335 | #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ |
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| 336 | /** |
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| 337 | * @} |
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| 338 | */ |
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| 339 | |||
| 340 | /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level |
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| 341 | * @{ |
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| 342 | */ |
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| 343 | #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ |
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| 344 | #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ |
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| 345 | #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ |
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| 346 | #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ |
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| 347 | /** |
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| 348 | * @} |
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| 349 | */ |
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| 350 | |||
| 351 | #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) |
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| 352 | /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request |
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| 353 | * @{ |
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| 354 | */ |
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| 355 | #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ |
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| 356 | #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ |
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| 357 | #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ |
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| 358 | #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ |
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| 359 | #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ |
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| 360 | #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ |
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| 361 | #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ |
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| 362 | #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ |
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| 363 | #define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ |
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| 364 | #define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ |
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| 365 | #define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ |
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| 366 | #define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ |
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| 367 | #define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ |
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| 368 | #define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ |
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| 369 | #define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ |
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| 370 | #define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ |
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| 371 | /** |
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| 372 | * @} |
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| 373 | */ |
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| 374 | #endif |
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| 375 | |||
| 376 | /** |
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| 377 | * @} |
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| 378 | */ |
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| 379 | |||
| 380 | /* Exported macro ------------------------------------------------------------*/ |
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| 381 | /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros |
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| 382 | * @{ |
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| 383 | */ |
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| 384 | |||
| 385 | /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros |
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| 386 | * @{ |
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| 387 | */ |
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| 388 | /** |
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| 389 | * @brief Write a value in DMA register |
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| 390 | * @param __INSTANCE__ DMA Instance |
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| 391 | * @param __REG__ Register to be written |
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| 392 | * @param __VALUE__ Value to be written in the register |
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| 393 | * @retval None |
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| 394 | */ |
||
| 395 | #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
||
| 396 | |||
| 397 | /** |
||
| 398 | * @brief Read a value in DMA register |
||
| 399 | * @param __INSTANCE__ DMA Instance |
||
| 400 | * @param __REG__ Register to be read |
||
| 401 | * @retval Register value |
||
| 402 | */ |
||
| 403 | #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
||
| 404 | /** |
||
| 405 | * @} |
||
| 406 | */ |
||
| 407 | |||
| 408 | /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely |
||
| 409 | * @{ |
||
| 410 | */ |
||
| 411 | /** |
||
| 412 | * @brief Convert DMAx_Channely into DMAx |
||
| 413 | * @param __CHANNEL_INSTANCE__ DMAx_Channely |
||
| 414 | * @retval DMAx |
||
| 415 | */ |
||
| 416 | #if defined(DMA2) |
||
| 417 | #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ |
||
| 418 | (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) |
||
| 419 | #else |
||
| 420 | #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) |
||
| 421 | #endif |
||
| 422 | |||
| 423 | /** |
||
| 424 | * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y |
||
| 425 | * @param __CHANNEL_INSTANCE__ DMAx_Channely |
||
| 426 | * @retval LL_DMA_CHANNEL_y |
||
| 427 | */ |
||
| 428 | #if defined (DMA2) |
||
| 429 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
||
| 430 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
||
| 431 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 432 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 433 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 434 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 435 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 436 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 437 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 438 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 439 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
||
| 440 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
||
| 441 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
||
| 442 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
||
| 443 | LL_DMA_CHANNEL_7) |
||
| 444 | #else |
||
| 445 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
||
| 446 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 447 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 448 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 449 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 450 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 451 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 452 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 453 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 454 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
||
| 455 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
||
| 456 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
||
| 457 | LL_DMA_CHANNEL_7) |
||
| 458 | #endif |
||
| 459 | #else |
||
| 460 | #if defined (DMA1_Channel6) && defined (DMA1_Channel7) |
||
| 461 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
||
| 462 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 463 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 464 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 465 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 466 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
||
| 467 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ |
||
| 468 | LL_DMA_CHANNEL_7) |
||
| 469 | #elif defined (DMA1_Channel6) |
||
| 470 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
||
| 471 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 472 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 473 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 474 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 475 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ |
||
| 476 | LL_DMA_CHANNEL_6) |
||
| 477 | #else |
||
| 478 | #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ |
||
| 479 | (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ |
||
| 480 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ |
||
| 481 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ |
||
| 482 | ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ |
||
| 483 | LL_DMA_CHANNEL_5) |
||
| 484 | #endif /* DMA1_Channel6 && DMA1_Channel7 */ |
||
| 485 | #endif |
||
| 486 | |||
| 487 | /** |
||
| 488 | * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely |
||
| 489 | * @param __DMA_INSTANCE__ DMAx |
||
| 490 | * @param __CHANNEL__ LL_DMA_CHANNEL_y |
||
| 491 | * @retval DMAx_Channely |
||
| 492 | */ |
||
| 493 | #if defined (DMA2) |
||
| 494 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
||
| 495 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
||
| 496 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
||
| 497 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ |
||
| 498 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
||
| 499 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ |
||
| 500 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
||
| 501 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ |
||
| 502 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
||
| 503 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ |
||
| 504 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
||
| 505 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ |
||
| 506 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
||
| 507 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ |
||
| 508 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ |
||
| 509 | DMA2_Channel7) |
||
| 510 | #else |
||
| 511 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
||
| 512 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
||
| 513 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ |
||
| 514 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
||
| 515 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ |
||
| 516 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
||
| 517 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ |
||
| 518 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
||
| 519 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ |
||
| 520 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
||
| 521 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ |
||
| 522 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
||
| 523 | DMA1_Channel7) |
||
| 524 | #endif |
||
| 525 | #else |
||
| 526 | #if defined (DMA1_Channel6) && defined (DMA1_Channel7) |
||
| 527 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
||
| 528 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
||
| 529 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
||
| 530 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
||
| 531 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
||
| 532 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
||
| 533 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ |
||
| 534 | DMA1_Channel7) |
||
| 535 | #elif defined (DMA1_Channel6) |
||
| 536 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
||
| 537 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
||
| 538 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
||
| 539 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
||
| 540 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
||
| 541 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ |
||
| 542 | DMA1_Channel6) |
||
| 543 | #else |
||
| 544 | #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ |
||
| 545 | ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ |
||
| 546 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ |
||
| 547 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ |
||
| 548 | (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ |
||
| 549 | DMA1_Channel5) |
||
| 550 | #endif /* DMA1_Channel6 && DMA1_Channel7 */ |
||
| 551 | #endif |
||
| 552 | |||
| 553 | /** |
||
| 554 | * @} |
||
| 555 | */ |
||
| 556 | |||
| 557 | /** |
||
| 558 | * @} |
||
| 559 | */ |
||
| 560 | |||
| 561 | /* Exported functions --------------------------------------------------------*/ |
||
| 562 | /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions |
||
| 563 | * @{ |
||
| 564 | */ |
||
| 565 | |||
| 566 | /** @defgroup DMA_LL_EF_Configuration Configuration |
||
| 567 | * @{ |
||
| 568 | */ |
||
| 569 | /** |
||
| 570 | * @brief Enable DMA channel. |
||
| 571 | * @rmtoll CCR EN LL_DMA_EnableChannel |
||
| 572 | * @param DMAx DMAx Instance |
||
| 573 | * @param Channel This parameter can be one of the following values: |
||
| 574 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 575 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 576 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 577 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 578 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 579 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 580 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 581 | * @retval None |
||
| 582 | */ |
||
| 583 | __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 584 | { |
||
| 585 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); |
||
| 586 | } |
||
| 587 | |||
| 588 | /** |
||
| 589 | * @brief Disable DMA channel. |
||
| 590 | * @rmtoll CCR EN LL_DMA_DisableChannel |
||
| 591 | * @param DMAx DMAx Instance |
||
| 592 | * @param Channel This parameter can be one of the following values: |
||
| 593 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 594 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 595 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 596 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 597 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 598 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 599 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 600 | * @retval None |
||
| 601 | */ |
||
| 602 | __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 603 | { |
||
| 604 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); |
||
| 605 | } |
||
| 606 | |||
| 607 | /** |
||
| 608 | * @brief Check if DMA channel is enabled or disabled. |
||
| 609 | * @rmtoll CCR EN LL_DMA_IsEnabledChannel |
||
| 610 | * @param DMAx DMAx Instance |
||
| 611 | * @param Channel This parameter can be one of the following values: |
||
| 612 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 613 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 614 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 615 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 616 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 617 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 618 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 619 | * @retval State of bit (1 or 0). |
||
| 620 | */ |
||
| 621 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 622 | { |
||
| 623 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 624 | DMA_CCR_EN) == (DMA_CCR_EN)); |
||
| 625 | } |
||
| 626 | |||
| 627 | /** |
||
| 628 | * @brief Configure all parameters link to DMA transfer. |
||
| 629 | * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n |
||
| 630 | * CCR MEM2MEM LL_DMA_ConfigTransfer\n |
||
| 631 | * CCR CIRC LL_DMA_ConfigTransfer\n |
||
| 632 | * CCR PINC LL_DMA_ConfigTransfer\n |
||
| 633 | * CCR MINC LL_DMA_ConfigTransfer\n |
||
| 634 | * CCR PSIZE LL_DMA_ConfigTransfer\n |
||
| 635 | * CCR MSIZE LL_DMA_ConfigTransfer\n |
||
| 636 | * CCR PL LL_DMA_ConfigTransfer |
||
| 637 | * @param DMAx DMAx Instance |
||
| 638 | * @param Channel This parameter can be one of the following values: |
||
| 639 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 640 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 641 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 642 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 643 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 644 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 645 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 646 | * @param Configuration This parameter must be a combination of all the following values: |
||
| 647 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
||
| 648 | * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR |
||
| 649 | * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT |
||
| 650 | * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT |
||
| 651 | * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD |
||
| 652 | * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD |
||
| 653 | * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH |
||
| 654 | * @retval None |
||
| 655 | */ |
||
| 656 | __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) |
||
| 657 | { |
||
| 658 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 659 | DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, |
||
| 660 | Configuration); |
||
| 661 | } |
||
| 662 | |||
| 663 | /** |
||
| 664 | * @brief Set Data transfer direction (read from peripheral or from memory). |
||
| 665 | * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n |
||
| 666 | * CCR MEM2MEM LL_DMA_SetDataTransferDirection |
||
| 667 | * @param DMAx DMAx Instance |
||
| 668 | * @param Channel This parameter can be one of the following values: |
||
| 669 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 670 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 671 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 672 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 673 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 674 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 675 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 676 | * @param Direction This parameter can be one of the following values: |
||
| 677 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
||
| 678 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
||
| 679 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
||
| 680 | * @retval None |
||
| 681 | */ |
||
| 682 | __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) |
||
| 683 | { |
||
| 684 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 685 | DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); |
||
| 686 | } |
||
| 687 | |||
| 688 | /** |
||
| 689 | * @brief Get Data transfer direction (read from peripheral or from memory). |
||
| 690 | * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n |
||
| 691 | * CCR MEM2MEM LL_DMA_GetDataTransferDirection |
||
| 692 | * @param DMAx DMAx Instance |
||
| 693 | * @param Channel This parameter can be one of the following values: |
||
| 694 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 695 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 696 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 697 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 698 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 699 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 700 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 701 | * @retval Returned value can be one of the following values: |
||
| 702 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
||
| 703 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
||
| 704 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
||
| 705 | */ |
||
| 706 | __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 707 | { |
||
| 708 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 709 | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); |
||
| 710 | } |
||
| 711 | |||
| 712 | /** |
||
| 713 | * @brief Set DMA mode circular or normal. |
||
| 714 | * @note The circular buffer mode cannot be used if the memory-to-memory |
||
| 715 | * data transfer is configured on the selected Channel. |
||
| 716 | * @rmtoll CCR CIRC LL_DMA_SetMode |
||
| 717 | * @param DMAx DMAx Instance |
||
| 718 | * @param Channel This parameter can be one of the following values: |
||
| 719 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 720 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 721 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 722 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 723 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 724 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 725 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 726 | * @param Mode This parameter can be one of the following values: |
||
| 727 | * @arg @ref LL_DMA_MODE_NORMAL |
||
| 728 | * @arg @ref LL_DMA_MODE_CIRCULAR |
||
| 729 | * @retval None |
||
| 730 | */ |
||
| 731 | __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) |
||
| 732 | { |
||
| 733 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, |
||
| 734 | Mode); |
||
| 735 | } |
||
| 736 | |||
| 737 | /** |
||
| 738 | * @brief Get DMA mode circular or normal. |
||
| 739 | * @rmtoll CCR CIRC LL_DMA_GetMode |
||
| 740 | * @param DMAx DMAx Instance |
||
| 741 | * @param Channel This parameter can be one of the following values: |
||
| 742 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 743 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 744 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 745 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 746 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 747 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 748 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 749 | * @retval Returned value can be one of the following values: |
||
| 750 | * @arg @ref LL_DMA_MODE_NORMAL |
||
| 751 | * @arg @ref LL_DMA_MODE_CIRCULAR |
||
| 752 | */ |
||
| 753 | __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 754 | { |
||
| 755 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 756 | DMA_CCR_CIRC)); |
||
| 757 | } |
||
| 758 | |||
| 759 | /** |
||
| 760 | * @brief Set Peripheral increment mode. |
||
| 761 | * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode |
||
| 762 | * @param DMAx DMAx Instance |
||
| 763 | * @param Channel This parameter can be one of the following values: |
||
| 764 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 765 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 766 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 767 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 768 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 769 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 770 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 771 | * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: |
||
| 772 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
||
| 773 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
||
| 774 | * @retval None |
||
| 775 | */ |
||
| 776 | __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) |
||
| 777 | { |
||
| 778 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, |
||
| 779 | PeriphOrM2MSrcIncMode); |
||
| 780 | } |
||
| 781 | |||
| 782 | /** |
||
| 783 | * @brief Get Peripheral increment mode. |
||
| 784 | * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode |
||
| 785 | * @param DMAx DMAx Instance |
||
| 786 | * @param Channel This parameter can be one of the following values: |
||
| 787 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 788 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 789 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 790 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 791 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 792 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 793 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 794 | * @retval Returned value can be one of the following values: |
||
| 795 | * @arg @ref LL_DMA_PERIPH_INCREMENT |
||
| 796 | * @arg @ref LL_DMA_PERIPH_NOINCREMENT |
||
| 797 | */ |
||
| 798 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 799 | { |
||
| 800 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 801 | DMA_CCR_PINC)); |
||
| 802 | } |
||
| 803 | |||
| 804 | /** |
||
| 805 | * @brief Set Memory increment mode. |
||
| 806 | * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode |
||
| 807 | * @param DMAx DMAx Instance |
||
| 808 | * @param Channel This parameter can be one of the following values: |
||
| 809 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 810 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 811 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 812 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 813 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 814 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 815 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 816 | * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: |
||
| 817 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
||
| 818 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
||
| 819 | * @retval None |
||
| 820 | */ |
||
| 821 | __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) |
||
| 822 | { |
||
| 823 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, |
||
| 824 | MemoryOrM2MDstIncMode); |
||
| 825 | } |
||
| 826 | |||
| 827 | /** |
||
| 828 | * @brief Get Memory increment mode. |
||
| 829 | * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode |
||
| 830 | * @param DMAx DMAx Instance |
||
| 831 | * @param Channel This parameter can be one of the following values: |
||
| 832 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 833 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 834 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 835 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 836 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 837 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 838 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 839 | * @retval Returned value can be one of the following values: |
||
| 840 | * @arg @ref LL_DMA_MEMORY_INCREMENT |
||
| 841 | * @arg @ref LL_DMA_MEMORY_NOINCREMENT |
||
| 842 | */ |
||
| 843 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 844 | { |
||
| 845 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 846 | DMA_CCR_MINC)); |
||
| 847 | } |
||
| 848 | |||
| 849 | /** |
||
| 850 | * @brief Set Peripheral size. |
||
| 851 | * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize |
||
| 852 | * @param DMAx DMAx Instance |
||
| 853 | * @param Channel This parameter can be one of the following values: |
||
| 854 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 855 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 856 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 857 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 858 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 859 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 860 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 861 | * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: |
||
| 862 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
||
| 863 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
||
| 864 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
||
| 865 | * @retval None |
||
| 866 | */ |
||
| 867 | __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) |
||
| 868 | { |
||
| 869 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, |
||
| 870 | PeriphOrM2MSrcDataSize); |
||
| 871 | } |
||
| 872 | |||
| 873 | /** |
||
| 874 | * @brief Get Peripheral size. |
||
| 875 | * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize |
||
| 876 | * @param DMAx DMAx Instance |
||
| 877 | * @param Channel This parameter can be one of the following values: |
||
| 878 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 879 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 880 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 881 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 882 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 883 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 884 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 885 | * @retval Returned value can be one of the following values: |
||
| 886 | * @arg @ref LL_DMA_PDATAALIGN_BYTE |
||
| 887 | * @arg @ref LL_DMA_PDATAALIGN_HALFWORD |
||
| 888 | * @arg @ref LL_DMA_PDATAALIGN_WORD |
||
| 889 | */ |
||
| 890 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 891 | { |
||
| 892 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 893 | DMA_CCR_PSIZE)); |
||
| 894 | } |
||
| 895 | |||
| 896 | /** |
||
| 897 | * @brief Set Memory size. |
||
| 898 | * @rmtoll CCR MSIZE LL_DMA_SetMemorySize |
||
| 899 | * @param DMAx DMAx Instance |
||
| 900 | * @param Channel This parameter can be one of the following values: |
||
| 901 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 902 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 903 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 904 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 905 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 906 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 907 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 908 | * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: |
||
| 909 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
||
| 910 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
||
| 911 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
||
| 912 | * @retval None |
||
| 913 | */ |
||
| 914 | __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) |
||
| 915 | { |
||
| 916 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, |
||
| 917 | MemoryOrM2MDstDataSize); |
||
| 918 | } |
||
| 919 | |||
| 920 | /** |
||
| 921 | * @brief Get Memory size. |
||
| 922 | * @rmtoll CCR MSIZE LL_DMA_GetMemorySize |
||
| 923 | * @param DMAx DMAx Instance |
||
| 924 | * @param Channel This parameter can be one of the following values: |
||
| 925 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 926 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 927 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 928 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 929 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 930 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 931 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 932 | * @retval Returned value can be one of the following values: |
||
| 933 | * @arg @ref LL_DMA_MDATAALIGN_BYTE |
||
| 934 | * @arg @ref LL_DMA_MDATAALIGN_HALFWORD |
||
| 935 | * @arg @ref LL_DMA_MDATAALIGN_WORD |
||
| 936 | */ |
||
| 937 | __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 938 | { |
||
| 939 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 940 | DMA_CCR_MSIZE)); |
||
| 941 | } |
||
| 942 | |||
| 943 | /** |
||
| 944 | * @brief Set Channel priority level. |
||
| 945 | * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel |
||
| 946 | * @param DMAx DMAx Instance |
||
| 947 | * @param Channel This parameter can be one of the following values: |
||
| 948 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 949 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 950 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 951 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 952 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 953 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 954 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 955 | * @param Priority This parameter can be one of the following values: |
||
| 956 | * @arg @ref LL_DMA_PRIORITY_LOW |
||
| 957 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
||
| 958 | * @arg @ref LL_DMA_PRIORITY_HIGH |
||
| 959 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
||
| 960 | * @retval None |
||
| 961 | */ |
||
| 962 | __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) |
||
| 963 | { |
||
| 964 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, |
||
| 965 | Priority); |
||
| 966 | } |
||
| 967 | |||
| 968 | /** |
||
| 969 | * @brief Get Channel priority level. |
||
| 970 | * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel |
||
| 971 | * @param DMAx DMAx Instance |
||
| 972 | * @param Channel This parameter can be one of the following values: |
||
| 973 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 974 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 975 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 976 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 977 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 978 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 979 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 980 | * @retval Returned value can be one of the following values: |
||
| 981 | * @arg @ref LL_DMA_PRIORITY_LOW |
||
| 982 | * @arg @ref LL_DMA_PRIORITY_MEDIUM |
||
| 983 | * @arg @ref LL_DMA_PRIORITY_HIGH |
||
| 984 | * @arg @ref LL_DMA_PRIORITY_VERYHIGH |
||
| 985 | */ |
||
| 986 | __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 987 | { |
||
| 988 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 989 | DMA_CCR_PL)); |
||
| 990 | } |
||
| 991 | |||
| 992 | /** |
||
| 993 | * @brief Set Number of data to transfer. |
||
| 994 | * @note This action has no effect if |
||
| 995 | * channel is enabled. |
||
| 996 | * @rmtoll CNDTR NDT LL_DMA_SetDataLength |
||
| 997 | * @param DMAx DMAx Instance |
||
| 998 | * @param Channel This parameter can be one of the following values: |
||
| 999 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1000 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1001 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1002 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1003 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1004 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1005 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1006 | * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF |
||
| 1007 | * @retval None |
||
| 1008 | */ |
||
| 1009 | __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) |
||
| 1010 | { |
||
| 1011 | MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, |
||
| 1012 | DMA_CNDTR_NDT, NbData); |
||
| 1013 | } |
||
| 1014 | |||
| 1015 | /** |
||
| 1016 | * @brief Get Number of data to transfer. |
||
| 1017 | * @note Once the channel is enabled, the return value indicate the |
||
| 1018 | * remaining bytes to be transmitted. |
||
| 1019 | * @rmtoll CNDTR NDT LL_DMA_GetDataLength |
||
| 1020 | * @param DMAx DMAx Instance |
||
| 1021 | * @param Channel This parameter can be one of the following values: |
||
| 1022 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1023 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1024 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1025 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1026 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1027 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1028 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1029 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1030 | */ |
||
| 1031 | __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 1032 | { |
||
| 1033 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, |
||
| 1034 | DMA_CNDTR_NDT)); |
||
| 1035 | } |
||
| 1036 | |||
| 1037 | /** |
||
| 1038 | * @brief Configure the Source and Destination addresses. |
||
| 1039 | * @note This API must not be called when the DMA channel is enabled. |
||
| 1040 | * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). |
||
| 1041 | * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n |
||
| 1042 | * CMAR MA LL_DMA_ConfigAddresses |
||
| 1043 | * @param DMAx DMAx Instance |
||
| 1044 | * @param Channel This parameter can be one of the following values: |
||
| 1045 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1046 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1047 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1048 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1049 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1050 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1051 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1052 | * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1053 | * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1054 | * @param Direction This parameter can be one of the following values: |
||
| 1055 | * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY |
||
| 1056 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH |
||
| 1057 | * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY |
||
| 1058 | * @retval None |
||
| 1059 | */ |
||
| 1060 | __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, |
||
| 1061 | uint32_t DstAddress, uint32_t Direction) |
||
| 1062 | { |
||
| 1063 | /* Direction Memory to Periph */ |
||
| 1064 | if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) |
||
| 1065 | { |
||
| 1066 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); |
||
| 1067 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); |
||
| 1068 | } |
||
| 1069 | /* Direction Periph to Memory and Memory to Memory */ |
||
| 1070 | else |
||
| 1071 | { |
||
| 1072 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); |
||
| 1073 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); |
||
| 1074 | } |
||
| 1075 | } |
||
| 1076 | |||
| 1077 | /** |
||
| 1078 | * @brief Set the Memory address. |
||
| 1079 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
||
| 1080 | * @note This API must not be called when the DMA channel is enabled. |
||
| 1081 | * @rmtoll CMAR MA LL_DMA_SetMemoryAddress |
||
| 1082 | * @param DMAx DMAx Instance |
||
| 1083 | * @param Channel This parameter can be one of the following values: |
||
| 1084 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1085 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1086 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1087 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1088 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1089 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1090 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1091 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1092 | * @retval None |
||
| 1093 | */ |
||
| 1094 | __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
||
| 1095 | { |
||
| 1096 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); |
||
| 1097 | } |
||
| 1098 | |||
| 1099 | /** |
||
| 1100 | * @brief Set the Peripheral address. |
||
| 1101 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
||
| 1102 | * @note This API must not be called when the DMA channel is enabled. |
||
| 1103 | * @rmtoll CPAR PA LL_DMA_SetPeriphAddress |
||
| 1104 | * @param DMAx DMAx Instance |
||
| 1105 | * @param Channel This parameter can be one of the following values: |
||
| 1106 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1107 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1108 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1109 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1110 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1111 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1112 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1113 | * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1114 | * @retval None |
||
| 1115 | */ |
||
| 1116 | __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) |
||
| 1117 | { |
||
| 1118 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); |
||
| 1119 | } |
||
| 1120 | |||
| 1121 | /** |
||
| 1122 | * @brief Get Memory address. |
||
| 1123 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
||
| 1124 | * @rmtoll CMAR MA LL_DMA_GetMemoryAddress |
||
| 1125 | * @param DMAx DMAx Instance |
||
| 1126 | * @param Channel This parameter can be one of the following values: |
||
| 1127 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1128 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1129 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1130 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1131 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1132 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1133 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1134 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1135 | */ |
||
| 1136 | __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 1137 | { |
||
| 1138 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); |
||
| 1139 | } |
||
| 1140 | |||
| 1141 | /** |
||
| 1142 | * @brief Get Peripheral address. |
||
| 1143 | * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. |
||
| 1144 | * @rmtoll CPAR PA LL_DMA_GetPeriphAddress |
||
| 1145 | * @param DMAx DMAx Instance |
||
| 1146 | * @param Channel This parameter can be one of the following values: |
||
| 1147 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1148 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1149 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1150 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1151 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1152 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1153 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1154 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1155 | */ |
||
| 1156 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 1157 | { |
||
| 1158 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); |
||
| 1159 | } |
||
| 1160 | |||
| 1161 | /** |
||
| 1162 | * @brief Set the Memory to Memory Source address. |
||
| 1163 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
||
| 1164 | * @note This API must not be called when the DMA channel is enabled. |
||
| 1165 | * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress |
||
| 1166 | * @param DMAx DMAx Instance |
||
| 1167 | * @param Channel This parameter can be one of the following values: |
||
| 1168 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1169 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1170 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1171 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1172 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1173 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1174 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1175 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1176 | * @retval None |
||
| 1177 | */ |
||
| 1178 | __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
||
| 1179 | { |
||
| 1180 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); |
||
| 1181 | } |
||
| 1182 | |||
| 1183 | /** |
||
| 1184 | * @brief Set the Memory to Memory Destination address. |
||
| 1185 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
||
| 1186 | * @note This API must not be called when the DMA channel is enabled. |
||
| 1187 | * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress |
||
| 1188 | * @param DMAx DMAx Instance |
||
| 1189 | * @param Channel This parameter can be one of the following values: |
||
| 1190 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1191 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1192 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1193 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1194 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1195 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1196 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1197 | * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1198 | * @retval None |
||
| 1199 | */ |
||
| 1200 | __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) |
||
| 1201 | { |
||
| 1202 | WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); |
||
| 1203 | } |
||
| 1204 | |||
| 1205 | /** |
||
| 1206 | * @brief Get the Memory to Memory Source address. |
||
| 1207 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
||
| 1208 | * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress |
||
| 1209 | * @param DMAx DMAx Instance |
||
| 1210 | * @param Channel This parameter can be one of the following values: |
||
| 1211 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1212 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1213 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1214 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1215 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1216 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1217 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1218 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1219 | */ |
||
| 1220 | __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 1221 | { |
||
| 1222 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); |
||
| 1223 | } |
||
| 1224 | |||
| 1225 | /** |
||
| 1226 | * @brief Get the Memory to Memory Destination address. |
||
| 1227 | * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. |
||
| 1228 | * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress |
||
| 1229 | * @param DMAx DMAx Instance |
||
| 1230 | * @param Channel This parameter can be one of the following values: |
||
| 1231 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1232 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1233 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1234 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1235 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1236 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1237 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1238 | * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF |
||
| 1239 | */ |
||
| 1240 | __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 1241 | { |
||
| 1242 | return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); |
||
| 1243 | } |
||
| 1244 | |||
| 1245 | #if (defined(DMA1_CSELR_DEFAULT)||defined(DMA2_CSELR_DEFAULT)) |
||
| 1246 | /** |
||
| 1247 | * @brief Set DMA request for DMA instance on Channel x. |
||
| 1248 | * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. |
||
| 1249 | * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n |
||
| 1250 | * CSELR C2S LL_DMA_SetPeriphRequest\n |
||
| 1251 | * CSELR C3S LL_DMA_SetPeriphRequest\n |
||
| 1252 | * CSELR C4S LL_DMA_SetPeriphRequest\n |
||
| 1253 | * CSELR C5S LL_DMA_SetPeriphRequest\n |
||
| 1254 | * CSELR C6S LL_DMA_SetPeriphRequest\n |
||
| 1255 | * CSELR C7S LL_DMA_SetPeriphRequest |
||
| 1256 | * @param DMAx DMAx Instance |
||
| 1257 | * @param Channel This parameter can be one of the following values: |
||
| 1258 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1259 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1260 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1261 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1262 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1263 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1264 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1265 | * @param PeriphRequest This parameter can be one of the following values: |
||
| 1266 | * @arg @ref LL_DMA_REQUEST_0 |
||
| 1267 | * @arg @ref LL_DMA_REQUEST_1 |
||
| 1268 | * @arg @ref LL_DMA_REQUEST_2 |
||
| 1269 | * @arg @ref LL_DMA_REQUEST_3 |
||
| 1270 | * @arg @ref LL_DMA_REQUEST_4 |
||
| 1271 | * @arg @ref LL_DMA_REQUEST_5 |
||
| 1272 | * @arg @ref LL_DMA_REQUEST_6 |
||
| 1273 | * @arg @ref LL_DMA_REQUEST_7 |
||
| 1274 | * @arg @ref LL_DMA_REQUEST_8 |
||
| 1275 | * @arg @ref LL_DMA_REQUEST_9 |
||
| 1276 | * @arg @ref LL_DMA_REQUEST_10 |
||
| 1277 | * @arg @ref LL_DMA_REQUEST_11 |
||
| 1278 | * @arg @ref LL_DMA_REQUEST_12 |
||
| 1279 | * @arg @ref LL_DMA_REQUEST_13 |
||
| 1280 | * @arg @ref LL_DMA_REQUEST_14 |
||
| 1281 | * @arg @ref LL_DMA_REQUEST_15 |
||
| 1282 | * @retval None |
||
| 1283 | */ |
||
| 1284 | __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) |
||
| 1285 | { |
||
| 1286 | MODIFY_REG(DMAx->CSELR, |
||
| 1287 | DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); |
||
| 1288 | } |
||
| 1289 | |||
| 1290 | /** |
||
| 1291 | * @brief Get DMA request for DMA instance on Channel x. |
||
| 1292 | * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n |
||
| 1293 | * CSELR C2S LL_DMA_GetPeriphRequest\n |
||
| 1294 | * CSELR C3S LL_DMA_GetPeriphRequest\n |
||
| 1295 | * CSELR C4S LL_DMA_GetPeriphRequest\n |
||
| 1296 | * CSELR C5S LL_DMA_GetPeriphRequest\n |
||
| 1297 | * CSELR C6S LL_DMA_GetPeriphRequest\n |
||
| 1298 | * CSELR C7S LL_DMA_GetPeriphRequest |
||
| 1299 | * @param DMAx DMAx Instance |
||
| 1300 | * @param Channel This parameter can be one of the following values: |
||
| 1301 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 1302 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 1303 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 1304 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 1305 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 1306 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 1307 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 1308 | * @retval Returned value can be one of the following values: |
||
| 1309 | * @arg @ref LL_DMA_REQUEST_0 |
||
| 1310 | * @arg @ref LL_DMA_REQUEST_1 |
||
| 1311 | * @arg @ref LL_DMA_REQUEST_2 |
||
| 1312 | * @arg @ref LL_DMA_REQUEST_3 |
||
| 1313 | * @arg @ref LL_DMA_REQUEST_4 |
||
| 1314 | * @arg @ref LL_DMA_REQUEST_5 |
||
| 1315 | * @arg @ref LL_DMA_REQUEST_6 |
||
| 1316 | * @arg @ref LL_DMA_REQUEST_7 |
||
| 1317 | * @arg @ref LL_DMA_REQUEST_8 |
||
| 1318 | * @arg @ref LL_DMA_REQUEST_9 |
||
| 1319 | * @arg @ref LL_DMA_REQUEST_10 |
||
| 1320 | * @arg @ref LL_DMA_REQUEST_11 |
||
| 1321 | * @arg @ref LL_DMA_REQUEST_12 |
||
| 1322 | * @arg @ref LL_DMA_REQUEST_13 |
||
| 1323 | * @arg @ref LL_DMA_REQUEST_14 |
||
| 1324 | * @arg @ref LL_DMA_REQUEST_15 |
||
| 1325 | */ |
||
| 1326 | __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 1327 | { |
||
| 1328 | return (READ_BIT(DMAx->CSELR, |
||
| 1329 | DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); |
||
| 1330 | } |
||
| 1331 | #endif |
||
| 1332 | |||
| 1333 | /** |
||
| 1334 | * @} |
||
| 1335 | */ |
||
| 1336 | |||
| 1337 | /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management |
||
| 1338 | * @{ |
||
| 1339 | */ |
||
| 1340 | |||
| 1341 | /** |
||
| 1342 | * @brief Get Channel 1 global interrupt flag. |
||
| 1343 | * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 |
||
| 1344 | * @param DMAx DMAx Instance |
||
| 1345 | * @retval State of bit (1 or 0). |
||
| 1346 | */ |
||
| 1347 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) |
||
| 1348 | { |
||
| 1349 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); |
||
| 1350 | } |
||
| 1351 | |||
| 1352 | /** |
||
| 1353 | * @brief Get Channel 2 global interrupt flag. |
||
| 1354 | * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 |
||
| 1355 | * @param DMAx DMAx Instance |
||
| 1356 | * @retval State of bit (1 or 0). |
||
| 1357 | */ |
||
| 1358 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) |
||
| 1359 | { |
||
| 1360 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); |
||
| 1361 | } |
||
| 1362 | |||
| 1363 | /** |
||
| 1364 | * @brief Get Channel 3 global interrupt flag. |
||
| 1365 | * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 |
||
| 1366 | * @param DMAx DMAx Instance |
||
| 1367 | * @retval State of bit (1 or 0). |
||
| 1368 | */ |
||
| 1369 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) |
||
| 1370 | { |
||
| 1371 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); |
||
| 1372 | } |
||
| 1373 | |||
| 1374 | /** |
||
| 1375 | * @brief Get Channel 4 global interrupt flag. |
||
| 1376 | * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 |
||
| 1377 | * @param DMAx DMAx Instance |
||
| 1378 | * @retval State of bit (1 or 0). |
||
| 1379 | */ |
||
| 1380 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) |
||
| 1381 | { |
||
| 1382 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); |
||
| 1383 | } |
||
| 1384 | |||
| 1385 | /** |
||
| 1386 | * @brief Get Channel 5 global interrupt flag. |
||
| 1387 | * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 |
||
| 1388 | * @param DMAx DMAx Instance |
||
| 1389 | * @retval State of bit (1 or 0). |
||
| 1390 | */ |
||
| 1391 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) |
||
| 1392 | { |
||
| 1393 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); |
||
| 1394 | } |
||
| 1395 | |||
| 1396 | #if defined(DMA1_Channel6) |
||
| 1397 | /** |
||
| 1398 | * @brief Get Channel 6 global interrupt flag. |
||
| 1399 | * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 |
||
| 1400 | * @param DMAx DMAx Instance |
||
| 1401 | * @retval State of bit (1 or 0). |
||
| 1402 | */ |
||
| 1403 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) |
||
| 1404 | { |
||
| 1405 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); |
||
| 1406 | } |
||
| 1407 | #endif |
||
| 1408 | |||
| 1409 | #if defined(DMA1_Channel7) |
||
| 1410 | /** |
||
| 1411 | * @brief Get Channel 7 global interrupt flag. |
||
| 1412 | * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 |
||
| 1413 | * @param DMAx DMAx Instance |
||
| 1414 | * @retval State of bit (1 or 0). |
||
| 1415 | */ |
||
| 1416 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) |
||
| 1417 | { |
||
| 1418 | return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); |
||
| 1419 | } |
||
| 1420 | #endif |
||
| 1421 | |||
| 1422 | /** |
||
| 1423 | * @brief Get Channel 1 transfer complete flag. |
||
| 1424 | * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 |
||
| 1425 | * @param DMAx DMAx Instance |
||
| 1426 | * @retval State of bit (1 or 0). |
||
| 1427 | */ |
||
| 1428 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) |
||
| 1429 | { |
||
| 1430 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); |
||
| 1431 | } |
||
| 1432 | |||
| 1433 | /** |
||
| 1434 | * @brief Get Channel 2 transfer complete flag. |
||
| 1435 | * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 |
||
| 1436 | * @param DMAx DMAx Instance |
||
| 1437 | * @retval State of bit (1 or 0). |
||
| 1438 | */ |
||
| 1439 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) |
||
| 1440 | { |
||
| 1441 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); |
||
| 1442 | } |
||
| 1443 | |||
| 1444 | /** |
||
| 1445 | * @brief Get Channel 3 transfer complete flag. |
||
| 1446 | * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 |
||
| 1447 | * @param DMAx DMAx Instance |
||
| 1448 | * @retval State of bit (1 or 0). |
||
| 1449 | */ |
||
| 1450 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) |
||
| 1451 | { |
||
| 1452 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); |
||
| 1453 | } |
||
| 1454 | |||
| 1455 | /** |
||
| 1456 | * @brief Get Channel 4 transfer complete flag. |
||
| 1457 | * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 |
||
| 1458 | * @param DMAx DMAx Instance |
||
| 1459 | * @retval State of bit (1 or 0). |
||
| 1460 | */ |
||
| 1461 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) |
||
| 1462 | { |
||
| 1463 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); |
||
| 1464 | } |
||
| 1465 | |||
| 1466 | /** |
||
| 1467 | * @brief Get Channel 5 transfer complete flag. |
||
| 1468 | * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 |
||
| 1469 | * @param DMAx DMAx Instance |
||
| 1470 | * @retval State of bit (1 or 0). |
||
| 1471 | */ |
||
| 1472 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) |
||
| 1473 | { |
||
| 1474 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); |
||
| 1475 | } |
||
| 1476 | |||
| 1477 | #if defined(DMA1_Channel6) |
||
| 1478 | /** |
||
| 1479 | * @brief Get Channel 6 transfer complete flag. |
||
| 1480 | * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 |
||
| 1481 | * @param DMAx DMAx Instance |
||
| 1482 | * @retval State of bit (1 or 0). |
||
| 1483 | */ |
||
| 1484 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) |
||
| 1485 | { |
||
| 1486 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); |
||
| 1487 | } |
||
| 1488 | #endif |
||
| 1489 | |||
| 1490 | #if defined(DMA1_Channel7) |
||
| 1491 | /** |
||
| 1492 | * @brief Get Channel 7 transfer complete flag. |
||
| 1493 | * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 |
||
| 1494 | * @param DMAx DMAx Instance |
||
| 1495 | * @retval State of bit (1 or 0). |
||
| 1496 | */ |
||
| 1497 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) |
||
| 1498 | { |
||
| 1499 | return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); |
||
| 1500 | } |
||
| 1501 | #endif |
||
| 1502 | |||
| 1503 | /** |
||
| 1504 | * @brief Get Channel 1 half transfer flag. |
||
| 1505 | * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 |
||
| 1506 | * @param DMAx DMAx Instance |
||
| 1507 | * @retval State of bit (1 or 0). |
||
| 1508 | */ |
||
| 1509 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) |
||
| 1510 | { |
||
| 1511 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); |
||
| 1512 | } |
||
| 1513 | |||
| 1514 | /** |
||
| 1515 | * @brief Get Channel 2 half transfer flag. |
||
| 1516 | * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 |
||
| 1517 | * @param DMAx DMAx Instance |
||
| 1518 | * @retval State of bit (1 or 0). |
||
| 1519 | */ |
||
| 1520 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) |
||
| 1521 | { |
||
| 1522 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); |
||
| 1523 | } |
||
| 1524 | |||
| 1525 | /** |
||
| 1526 | * @brief Get Channel 3 half transfer flag. |
||
| 1527 | * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 |
||
| 1528 | * @param DMAx DMAx Instance |
||
| 1529 | * @retval State of bit (1 or 0). |
||
| 1530 | */ |
||
| 1531 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) |
||
| 1532 | { |
||
| 1533 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); |
||
| 1534 | } |
||
| 1535 | |||
| 1536 | /** |
||
| 1537 | * @brief Get Channel 4 half transfer flag. |
||
| 1538 | * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 |
||
| 1539 | * @param DMAx DMAx Instance |
||
| 1540 | * @retval State of bit (1 or 0). |
||
| 1541 | */ |
||
| 1542 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) |
||
| 1543 | { |
||
| 1544 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); |
||
| 1545 | } |
||
| 1546 | |||
| 1547 | /** |
||
| 1548 | * @brief Get Channel 5 half transfer flag. |
||
| 1549 | * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 |
||
| 1550 | * @param DMAx DMAx Instance |
||
| 1551 | * @retval State of bit (1 or 0). |
||
| 1552 | */ |
||
| 1553 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) |
||
| 1554 | { |
||
| 1555 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); |
||
| 1556 | } |
||
| 1557 | |||
| 1558 | #if defined(DMA1_Channel6) |
||
| 1559 | /** |
||
| 1560 | * @brief Get Channel 6 half transfer flag. |
||
| 1561 | * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 |
||
| 1562 | * @param DMAx DMAx Instance |
||
| 1563 | * @retval State of bit (1 or 0). |
||
| 1564 | */ |
||
| 1565 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) |
||
| 1566 | { |
||
| 1567 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); |
||
| 1568 | } |
||
| 1569 | #endif |
||
| 1570 | |||
| 1571 | #if defined(DMA1_Channel7) |
||
| 1572 | /** |
||
| 1573 | * @brief Get Channel 7 half transfer flag. |
||
| 1574 | * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 |
||
| 1575 | * @param DMAx DMAx Instance |
||
| 1576 | * @retval State of bit (1 or 0). |
||
| 1577 | */ |
||
| 1578 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) |
||
| 1579 | { |
||
| 1580 | return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); |
||
| 1581 | } |
||
| 1582 | #endif |
||
| 1583 | |||
| 1584 | /** |
||
| 1585 | * @brief Get Channel 1 transfer error flag. |
||
| 1586 | * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 |
||
| 1587 | * @param DMAx DMAx Instance |
||
| 1588 | * @retval State of bit (1 or 0). |
||
| 1589 | */ |
||
| 1590 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) |
||
| 1591 | { |
||
| 1592 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); |
||
| 1593 | } |
||
| 1594 | |||
| 1595 | /** |
||
| 1596 | * @brief Get Channel 2 transfer error flag. |
||
| 1597 | * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 |
||
| 1598 | * @param DMAx DMAx Instance |
||
| 1599 | * @retval State of bit (1 or 0). |
||
| 1600 | */ |
||
| 1601 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) |
||
| 1602 | { |
||
| 1603 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); |
||
| 1604 | } |
||
| 1605 | |||
| 1606 | /** |
||
| 1607 | * @brief Get Channel 3 transfer error flag. |
||
| 1608 | * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 |
||
| 1609 | * @param DMAx DMAx Instance |
||
| 1610 | * @retval State of bit (1 or 0). |
||
| 1611 | */ |
||
| 1612 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) |
||
| 1613 | { |
||
| 1614 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); |
||
| 1615 | } |
||
| 1616 | |||
| 1617 | /** |
||
| 1618 | * @brief Get Channel 4 transfer error flag. |
||
| 1619 | * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 |
||
| 1620 | * @param DMAx DMAx Instance |
||
| 1621 | * @retval State of bit (1 or 0). |
||
| 1622 | */ |
||
| 1623 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) |
||
| 1624 | { |
||
| 1625 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); |
||
| 1626 | } |
||
| 1627 | |||
| 1628 | /** |
||
| 1629 | * @brief Get Channel 5 transfer error flag. |
||
| 1630 | * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 |
||
| 1631 | * @param DMAx DMAx Instance |
||
| 1632 | * @retval State of bit (1 or 0). |
||
| 1633 | */ |
||
| 1634 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) |
||
| 1635 | { |
||
| 1636 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); |
||
| 1637 | } |
||
| 1638 | |||
| 1639 | #if defined(DMA1_Channel6) |
||
| 1640 | /** |
||
| 1641 | * @brief Get Channel 6 transfer error flag. |
||
| 1642 | * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 |
||
| 1643 | * @param DMAx DMAx Instance |
||
| 1644 | * @retval State of bit (1 or 0). |
||
| 1645 | */ |
||
| 1646 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) |
||
| 1647 | { |
||
| 1648 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); |
||
| 1649 | } |
||
| 1650 | #endif |
||
| 1651 | |||
| 1652 | #if defined(DMA1_Channel7) |
||
| 1653 | /** |
||
| 1654 | * @brief Get Channel 7 transfer error flag. |
||
| 1655 | * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 |
||
| 1656 | * @param DMAx DMAx Instance |
||
| 1657 | * @retval State of bit (1 or 0). |
||
| 1658 | */ |
||
| 1659 | __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) |
||
| 1660 | { |
||
| 1661 | return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); |
||
| 1662 | } |
||
| 1663 | #endif |
||
| 1664 | |||
| 1665 | /** |
||
| 1666 | * @brief Clear Channel 1 global interrupt flag. |
||
| 6 | mjames | 1667 | * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. |
| 1668 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1669 | error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, |
||
| 1670 | LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1671 | * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 |
| 1672 | * @param DMAx DMAx Instance |
||
| 1673 | * @retval None |
||
| 1674 | */ |
||
| 1675 | __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) |
||
| 1676 | { |
||
| 1677 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); |
||
| 1678 | } |
||
| 1679 | |||
| 1680 | /** |
||
| 1681 | * @brief Clear Channel 2 global interrupt flag. |
||
| 6 | mjames | 1682 | * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. |
| 1683 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1684 | error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, |
||
| 1685 | LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1686 | * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 |
| 1687 | * @param DMAx DMAx Instance |
||
| 1688 | * @retval None |
||
| 1689 | */ |
||
| 1690 | __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) |
||
| 1691 | { |
||
| 1692 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); |
||
| 1693 | } |
||
| 1694 | |||
| 1695 | /** |
||
| 1696 | * @brief Clear Channel 3 global interrupt flag. |
||
| 6 | mjames | 1697 | * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. |
| 1698 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1699 | error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, |
||
| 1700 | LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1701 | * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 |
| 1702 | * @param DMAx DMAx Instance |
||
| 1703 | * @retval None |
||
| 1704 | */ |
||
| 1705 | __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) |
||
| 1706 | { |
||
| 1707 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); |
||
| 1708 | } |
||
| 1709 | |||
| 1710 | /** |
||
| 1711 | * @brief Clear Channel 4 global interrupt flag. |
||
| 6 | mjames | 1712 | * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. |
| 1713 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1714 | error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, |
||
| 1715 | LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1716 | * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 |
| 1717 | * @param DMAx DMAx Instance |
||
| 1718 | * @retval None |
||
| 1719 | */ |
||
| 1720 | __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) |
||
| 1721 | { |
||
| 1722 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); |
||
| 1723 | } |
||
| 1724 | |||
| 1725 | /** |
||
| 1726 | * @brief Clear Channel 5 global interrupt flag. |
||
| 6 | mjames | 1727 | * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. |
| 1728 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1729 | error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, |
||
| 1730 | LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1731 | * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 |
| 1732 | * @param DMAx DMAx Instance |
||
| 1733 | * @retval None |
||
| 1734 | */ |
||
| 1735 | __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) |
||
| 1736 | { |
||
| 1737 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); |
||
| 1738 | } |
||
| 1739 | |||
| 1740 | #if defined(DMA1_Channel6) |
||
| 1741 | /** |
||
| 1742 | * @brief Clear Channel 6 global interrupt flag. |
||
| 6 | mjames | 1743 | * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. |
| 1744 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1745 | error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, |
||
| 1746 | LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1747 | * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 |
| 1748 | * @param DMAx DMAx Instance |
||
| 1749 | * @retval None |
||
| 1750 | */ |
||
| 1751 | __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) |
||
| 1752 | { |
||
| 1753 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); |
||
| 1754 | } |
||
| 1755 | #endif |
||
| 1756 | |||
| 1757 | #if defined(DMA1_Channel7) |
||
| 1758 | /** |
||
| 1759 | * @brief Clear Channel 7 global interrupt flag. |
||
| 6 | mjames | 1760 | * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. |
| 1761 | Instead clear specific flags transfer complete, half transfer & transfer |
||
| 1762 | error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, |
||
| 1763 | LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet. |
||
| 2 | mjames | 1764 | * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 |
| 1765 | * @param DMAx DMAx Instance |
||
| 1766 | * @retval None |
||
| 1767 | */ |
||
| 1768 | __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) |
||
| 1769 | { |
||
| 1770 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); |
||
| 1771 | } |
||
| 1772 | #endif |
||
| 1773 | |||
| 1774 | /** |
||
| 1775 | * @brief Clear Channel 1 transfer complete flag. |
||
| 1776 | * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 |
||
| 1777 | * @param DMAx DMAx Instance |
||
| 1778 | * @retval None |
||
| 1779 | */ |
||
| 1780 | __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) |
||
| 1781 | { |
||
| 1782 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); |
||
| 1783 | } |
||
| 1784 | |||
| 1785 | /** |
||
| 1786 | * @brief Clear Channel 2 transfer complete flag. |
||
| 1787 | * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 |
||
| 1788 | * @param DMAx DMAx Instance |
||
| 1789 | * @retval None |
||
| 1790 | */ |
||
| 1791 | __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) |
||
| 1792 | { |
||
| 1793 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); |
||
| 1794 | } |
||
| 1795 | |||
| 1796 | /** |
||
| 1797 | * @brief Clear Channel 3 transfer complete flag. |
||
| 1798 | * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 |
||
| 1799 | * @param DMAx DMAx Instance |
||
| 1800 | * @retval None |
||
| 1801 | */ |
||
| 1802 | __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) |
||
| 1803 | { |
||
| 1804 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); |
||
| 1805 | } |
||
| 1806 | |||
| 1807 | /** |
||
| 1808 | * @brief Clear Channel 4 transfer complete flag. |
||
| 1809 | * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 |
||
| 1810 | * @param DMAx DMAx Instance |
||
| 1811 | * @retval None |
||
| 1812 | */ |
||
| 1813 | __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) |
||
| 1814 | { |
||
| 1815 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); |
||
| 1816 | } |
||
| 1817 | |||
| 1818 | /** |
||
| 1819 | * @brief Clear Channel 5 transfer complete flag. |
||
| 1820 | * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 |
||
| 1821 | * @param DMAx DMAx Instance |
||
| 1822 | * @retval None |
||
| 1823 | */ |
||
| 1824 | __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) |
||
| 1825 | { |
||
| 1826 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); |
||
| 1827 | } |
||
| 1828 | |||
| 1829 | #if defined(DMA1_Channel6) |
||
| 1830 | /** |
||
| 1831 | * @brief Clear Channel 6 transfer complete flag. |
||
| 1832 | * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 |
||
| 1833 | * @param DMAx DMAx Instance |
||
| 1834 | * @retval None |
||
| 1835 | */ |
||
| 1836 | __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) |
||
| 1837 | { |
||
| 1838 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); |
||
| 1839 | } |
||
| 1840 | #endif |
||
| 1841 | |||
| 1842 | #if defined(DMA1_Channel7) |
||
| 1843 | /** |
||
| 1844 | * @brief Clear Channel 7 transfer complete flag. |
||
| 1845 | * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 |
||
| 1846 | * @param DMAx DMAx Instance |
||
| 1847 | * @retval None |
||
| 1848 | */ |
||
| 1849 | __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) |
||
| 1850 | { |
||
| 1851 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); |
||
| 1852 | } |
||
| 1853 | #endif |
||
| 1854 | |||
| 1855 | /** |
||
| 1856 | * @brief Clear Channel 1 half transfer flag. |
||
| 1857 | * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 |
||
| 1858 | * @param DMAx DMAx Instance |
||
| 1859 | * @retval None |
||
| 1860 | */ |
||
| 1861 | __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) |
||
| 1862 | { |
||
| 1863 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); |
||
| 1864 | } |
||
| 1865 | |||
| 1866 | /** |
||
| 1867 | * @brief Clear Channel 2 half transfer flag. |
||
| 1868 | * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 |
||
| 1869 | * @param DMAx DMAx Instance |
||
| 1870 | * @retval None |
||
| 1871 | */ |
||
| 1872 | __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) |
||
| 1873 | { |
||
| 1874 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); |
||
| 1875 | } |
||
| 1876 | |||
| 1877 | /** |
||
| 1878 | * @brief Clear Channel 3 half transfer flag. |
||
| 1879 | * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 |
||
| 1880 | * @param DMAx DMAx Instance |
||
| 1881 | * @retval None |
||
| 1882 | */ |
||
| 1883 | __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) |
||
| 1884 | { |
||
| 1885 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); |
||
| 1886 | } |
||
| 1887 | |||
| 1888 | /** |
||
| 1889 | * @brief Clear Channel 4 half transfer flag. |
||
| 1890 | * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 |
||
| 1891 | * @param DMAx DMAx Instance |
||
| 1892 | * @retval None |
||
| 1893 | */ |
||
| 1894 | __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) |
||
| 1895 | { |
||
| 1896 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); |
||
| 1897 | } |
||
| 1898 | |||
| 1899 | /** |
||
| 1900 | * @brief Clear Channel 5 half transfer flag. |
||
| 1901 | * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 |
||
| 1902 | * @param DMAx DMAx Instance |
||
| 1903 | * @retval None |
||
| 1904 | */ |
||
| 1905 | __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) |
||
| 1906 | { |
||
| 1907 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); |
||
| 1908 | } |
||
| 1909 | |||
| 1910 | #if defined(DMA1_Channel6) |
||
| 1911 | /** |
||
| 1912 | * @brief Clear Channel 6 half transfer flag. |
||
| 1913 | * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 |
||
| 1914 | * @param DMAx DMAx Instance |
||
| 1915 | * @retval None |
||
| 1916 | */ |
||
| 1917 | __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) |
||
| 1918 | { |
||
| 1919 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); |
||
| 1920 | } |
||
| 1921 | #endif |
||
| 1922 | |||
| 1923 | #if defined(DMA1_Channel7) |
||
| 1924 | /** |
||
| 1925 | * @brief Clear Channel 7 half transfer flag. |
||
| 1926 | * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 |
||
| 1927 | * @param DMAx DMAx Instance |
||
| 1928 | * @retval None |
||
| 1929 | */ |
||
| 1930 | __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) |
||
| 1931 | { |
||
| 1932 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); |
||
| 1933 | } |
||
| 1934 | #endif |
||
| 1935 | |||
| 1936 | /** |
||
| 1937 | * @brief Clear Channel 1 transfer error flag. |
||
| 1938 | * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 |
||
| 1939 | * @param DMAx DMAx Instance |
||
| 1940 | * @retval None |
||
| 1941 | */ |
||
| 1942 | __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) |
||
| 1943 | { |
||
| 1944 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); |
||
| 1945 | } |
||
| 1946 | |||
| 1947 | /** |
||
| 1948 | * @brief Clear Channel 2 transfer error flag. |
||
| 1949 | * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 |
||
| 1950 | * @param DMAx DMAx Instance |
||
| 1951 | * @retval None |
||
| 1952 | */ |
||
| 1953 | __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) |
||
| 1954 | { |
||
| 1955 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); |
||
| 1956 | } |
||
| 1957 | |||
| 1958 | /** |
||
| 1959 | * @brief Clear Channel 3 transfer error flag. |
||
| 1960 | * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 |
||
| 1961 | * @param DMAx DMAx Instance |
||
| 1962 | * @retval None |
||
| 1963 | */ |
||
| 1964 | __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) |
||
| 1965 | { |
||
| 1966 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); |
||
| 1967 | } |
||
| 1968 | |||
| 1969 | /** |
||
| 1970 | * @brief Clear Channel 4 transfer error flag. |
||
| 1971 | * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 |
||
| 1972 | * @param DMAx DMAx Instance |
||
| 1973 | * @retval None |
||
| 1974 | */ |
||
| 1975 | __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) |
||
| 1976 | { |
||
| 1977 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); |
||
| 1978 | } |
||
| 1979 | |||
| 1980 | /** |
||
| 1981 | * @brief Clear Channel 5 transfer error flag. |
||
| 1982 | * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 |
||
| 1983 | * @param DMAx DMAx Instance |
||
| 1984 | * @retval None |
||
| 1985 | */ |
||
| 1986 | __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) |
||
| 1987 | { |
||
| 1988 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); |
||
| 1989 | } |
||
| 1990 | |||
| 1991 | #if defined(DMA1_Channel6) |
||
| 1992 | /** |
||
| 1993 | * @brief Clear Channel 6 transfer error flag. |
||
| 1994 | * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 |
||
| 1995 | * @param DMAx DMAx Instance |
||
| 1996 | * @retval None |
||
| 1997 | */ |
||
| 1998 | __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) |
||
| 1999 | { |
||
| 2000 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); |
||
| 2001 | } |
||
| 2002 | #endif |
||
| 2003 | |||
| 2004 | #if defined(DMA1_Channel7) |
||
| 2005 | /** |
||
| 2006 | * @brief Clear Channel 7 transfer error flag. |
||
| 2007 | * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 |
||
| 2008 | * @param DMAx DMAx Instance |
||
| 2009 | * @retval None |
||
| 2010 | */ |
||
| 2011 | __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) |
||
| 2012 | { |
||
| 2013 | WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); |
||
| 2014 | } |
||
| 2015 | #endif |
||
| 2016 | |||
| 2017 | /** |
||
| 2018 | * @} |
||
| 2019 | */ |
||
| 2020 | |||
| 2021 | /** @defgroup DMA_LL_EF_IT_Management IT_Management |
||
| 2022 | * @{ |
||
| 2023 | */ |
||
| 2024 | /** |
||
| 2025 | * @brief Enable Transfer complete interrupt. |
||
| 2026 | * @rmtoll CCR TCIE LL_DMA_EnableIT_TC |
||
| 2027 | * @param DMAx DMAx Instance |
||
| 2028 | * @param Channel This parameter can be one of the following values: |
||
| 2029 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2030 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2031 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2032 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2033 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2034 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2035 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2036 | * @retval None |
||
| 2037 | */ |
||
| 2038 | __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2039 | { |
||
| 2040 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); |
||
| 2041 | } |
||
| 2042 | |||
| 2043 | /** |
||
| 2044 | * @brief Enable Half transfer interrupt. |
||
| 2045 | * @rmtoll CCR HTIE LL_DMA_EnableIT_HT |
||
| 2046 | * @param DMAx DMAx Instance |
||
| 2047 | * @param Channel This parameter can be one of the following values: |
||
| 2048 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2049 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2050 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2051 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2052 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2053 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2054 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2055 | * @retval None |
||
| 2056 | */ |
||
| 2057 | __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2058 | { |
||
| 2059 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); |
||
| 2060 | } |
||
| 2061 | |||
| 2062 | /** |
||
| 2063 | * @brief Enable Transfer error interrupt. |
||
| 2064 | * @rmtoll CCR TEIE LL_DMA_EnableIT_TE |
||
| 2065 | * @param DMAx DMAx Instance |
||
| 2066 | * @param Channel This parameter can be one of the following values: |
||
| 2067 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2068 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2069 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2070 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2071 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2072 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2073 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2074 | * @retval None |
||
| 2075 | */ |
||
| 2076 | __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2077 | { |
||
| 2078 | SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); |
||
| 2079 | } |
||
| 2080 | |||
| 2081 | /** |
||
| 2082 | * @brief Disable Transfer complete interrupt. |
||
| 2083 | * @rmtoll CCR TCIE LL_DMA_DisableIT_TC |
||
| 2084 | * @param DMAx DMAx Instance |
||
| 2085 | * @param Channel This parameter can be one of the following values: |
||
| 2086 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2087 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2088 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2089 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2090 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2091 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2092 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2093 | * @retval None |
||
| 2094 | */ |
||
| 2095 | __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2096 | { |
||
| 2097 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); |
||
| 2098 | } |
||
| 2099 | |||
| 2100 | /** |
||
| 2101 | * @brief Disable Half transfer interrupt. |
||
| 2102 | * @rmtoll CCR HTIE LL_DMA_DisableIT_HT |
||
| 2103 | * @param DMAx DMAx Instance |
||
| 2104 | * @param Channel This parameter can be one of the following values: |
||
| 2105 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2106 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2107 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2108 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2109 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2110 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2111 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2112 | * @retval None |
||
| 2113 | */ |
||
| 2114 | __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2115 | { |
||
| 2116 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); |
||
| 2117 | } |
||
| 2118 | |||
| 2119 | /** |
||
| 2120 | * @brief Disable Transfer error interrupt. |
||
| 2121 | * @rmtoll CCR TEIE LL_DMA_DisableIT_TE |
||
| 2122 | * @param DMAx DMAx Instance |
||
| 2123 | * @param Channel This parameter can be one of the following values: |
||
| 2124 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2125 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2126 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2127 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2128 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2129 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2130 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2131 | * @retval None |
||
| 2132 | */ |
||
| 2133 | __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2134 | { |
||
| 2135 | CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); |
||
| 2136 | } |
||
| 2137 | |||
| 2138 | /** |
||
| 2139 | * @brief Check if Transfer complete Interrupt is enabled. |
||
| 2140 | * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC |
||
| 2141 | * @param DMAx DMAx Instance |
||
| 2142 | * @param Channel This parameter can be one of the following values: |
||
| 2143 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2144 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2145 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2146 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2147 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2148 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2149 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2150 | * @retval State of bit (1 or 0). |
||
| 2151 | */ |
||
| 2152 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2153 | { |
||
| 2154 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 2155 | DMA_CCR_TCIE) == (DMA_CCR_TCIE)); |
||
| 2156 | } |
||
| 2157 | |||
| 2158 | /** |
||
| 2159 | * @brief Check if Half transfer Interrupt is enabled. |
||
| 2160 | * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT |
||
| 2161 | * @param DMAx DMAx Instance |
||
| 2162 | * @param Channel This parameter can be one of the following values: |
||
| 2163 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2164 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2165 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2166 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2167 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2168 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2169 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2170 | * @retval State of bit (1 or 0). |
||
| 2171 | */ |
||
| 2172 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2173 | { |
||
| 2174 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 2175 | DMA_CCR_HTIE) == (DMA_CCR_HTIE)); |
||
| 2176 | } |
||
| 2177 | |||
| 2178 | /** |
||
| 2179 | * @brief Check if Transfer error Interrupt is enabled. |
||
| 2180 | * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE |
||
| 2181 | * @param DMAx DMAx Instance |
||
| 2182 | * @param Channel This parameter can be one of the following values: |
||
| 2183 | * @arg @ref LL_DMA_CHANNEL_1 |
||
| 2184 | * @arg @ref LL_DMA_CHANNEL_2 |
||
| 2185 | * @arg @ref LL_DMA_CHANNEL_3 |
||
| 2186 | * @arg @ref LL_DMA_CHANNEL_4 |
||
| 2187 | * @arg @ref LL_DMA_CHANNEL_5 |
||
| 2188 | * @arg @ref LL_DMA_CHANNEL_6 |
||
| 2189 | * @arg @ref LL_DMA_CHANNEL_7 |
||
| 2190 | * @retval State of bit (1 or 0). |
||
| 2191 | */ |
||
| 2192 | __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) |
||
| 2193 | { |
||
| 2194 | return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, |
||
| 2195 | DMA_CCR_TEIE) == (DMA_CCR_TEIE)); |
||
| 2196 | } |
||
| 2197 | |||
| 2198 | /** |
||
| 2199 | * @} |
||
| 2200 | */ |
||
| 2201 | |||
| 2202 | #if defined(USE_FULL_LL_DRIVER) |
||
| 2203 | /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions |
||
| 2204 | * @{ |
||
| 2205 | */ |
||
| 2206 | |||
| 2207 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); |
||
| 2208 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); |
||
| 2209 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); |
||
| 2210 | |||
| 2211 | /** |
||
| 2212 | * @} |
||
| 2213 | */ |
||
| 2214 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 2215 | |||
| 2216 | /** |
||
| 2217 | * @} |
||
| 2218 | */ |
||
| 2219 | |||
| 2220 | /** |
||
| 2221 | * @} |
||
| 2222 | */ |
||
| 2223 | |||
| 2224 | #endif /* DMA1 || DMA2 */ |
||
| 2225 | |||
| 2226 | /** |
||
| 2227 | * @} |
||
| 2228 | */ |
||
| 2229 | |||
| 2230 | #ifdef __cplusplus |
||
| 2231 | } |
||
| 2232 | #endif |
||
| 2233 | |||
| 2234 | #endif /* __STM32F0xx_LL_DMA_H */ |
||
| 2235 | |||
| 2236 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |