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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_ll_crs.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of CRS LL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F0xx_LL_CRS_H |
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| 22 | #define __STM32F0xx_LL_CRS_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_LL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | #if defined(CRS) |
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| 36 | |||
| 37 | /** @defgroup CRS_LL CRS |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Private types -------------------------------------------------------------*/ |
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| 42 | /* Private variables ---------------------------------------------------------*/ |
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| 43 | /* Private constants ---------------------------------------------------------*/ |
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| 44 | /* Private macros ------------------------------------------------------------*/ |
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| 45 | |||
| 46 | /* Exported types ------------------------------------------------------------*/ |
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| 47 | /* Exported constants --------------------------------------------------------*/ |
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| 48 | /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants |
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| 49 | * @{ |
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| 50 | */ |
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| 51 | |||
| 52 | /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines |
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| 53 | * @brief Flags defines which can be used with LL_CRS_ReadReg function |
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| 54 | * @{ |
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| 55 | */ |
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| 56 | #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF |
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| 57 | #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF |
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| 58 | #define LL_CRS_ISR_ERRF CRS_ISR_ERRF |
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| 59 | #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF |
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| 60 | #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR |
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| 61 | #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS |
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| 62 | #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF |
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| 63 | /** |
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| 64 | * @} |
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| 65 | */ |
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| 66 | |||
| 67 | /** @defgroup CRS_LL_EC_IT IT Defines |
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| 68 | * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions |
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| 69 | * @{ |
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| 70 | */ |
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| 71 | #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE |
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| 72 | #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE |
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| 73 | #define LL_CRS_CR_ERRIE CRS_CR_ERRIE |
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| 74 | #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE |
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| 75 | /** |
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| 76 | * @} |
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| 77 | */ |
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| 78 | |||
| 79 | /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider |
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| 80 | * @{ |
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| 81 | */ |
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| 82 | #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ |
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| 83 | #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
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| 84 | #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
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| 85 | #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
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| 86 | #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
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| 87 | #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
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| 88 | #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
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| 89 | #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
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| 90 | /** |
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| 91 | * @} |
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| 92 | */ |
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| 93 | |||
| 94 | /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source |
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| 95 | * @{ |
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| 96 | */ |
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| 97 | #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ |
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| 98 | #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
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| 99 | #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
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| 100 | /** |
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| 101 | * @} |
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| 102 | */ |
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| 103 | |||
| 104 | /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity |
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| 105 | * @{ |
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| 106 | */ |
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| 107 | #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ |
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| 108 | #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
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| 109 | /** |
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| 110 | * @} |
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| 111 | */ |
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| 112 | |||
| 113 | /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction |
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| 114 | * @{ |
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| 115 | */ |
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| 116 | #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ |
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| 117 | #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ |
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| 118 | /** |
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| 119 | * @} |
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| 120 | */ |
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| 121 | |||
| 122 | /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values |
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| 123 | * @{ |
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| 124 | */ |
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| 125 | /** |
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| 126 | * @brief Reset value of the RELOAD field |
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| 127 | * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz |
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| 128 | * and a synchronization signal frequency of 1 kHz (SOF signal from USB) |
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| 129 | */ |
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| 130 | #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) |
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| 131 | |||
| 132 | /** |
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| 133 | * @brief Reset value of Frequency error limit. |
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| 134 | */ |
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| 135 | #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) |
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| 136 | |||
| 137 | /** |
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| 138 | * @brief Reset value of the HSI48 Calibration field |
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| 139 | * @note The default value is 32, which corresponds to the middle of the trimming interval. |
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| 140 | * The trimming step is around 67 kHz between two consecutive TRIM steps. |
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| 141 | * A higher TRIM value corresponds to a higher output frequency |
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| 142 | */ |
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| 143 | #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) |
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| 144 | /** |
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| 145 | * @} |
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| 146 | */ |
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| 147 | |||
| 148 | /** |
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| 149 | * @} |
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| 150 | */ |
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| 151 | |||
| 152 | /* Exported macro ------------------------------------------------------------*/ |
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| 153 | /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros |
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| 154 | * @{ |
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| 155 | */ |
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| 156 | |||
| 157 | /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros |
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| 158 | * @{ |
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| 159 | */ |
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| 160 | |||
| 161 | /** |
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| 162 | * @brief Write a value in CRS register |
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| 163 | * @param __INSTANCE__ CRS Instance |
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| 164 | * @param __REG__ Register to be written |
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| 165 | * @param __VALUE__ Value to be written in the register |
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| 166 | * @retval None |
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| 167 | */ |
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| 168 | #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
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| 169 | |||
| 170 | /** |
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| 171 | * @brief Read a value in CRS register |
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| 172 | * @param __INSTANCE__ CRS Instance |
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| 173 | * @param __REG__ Register to be read |
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| 174 | * @retval Register value |
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| 175 | */ |
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| 176 | #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
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| 177 | /** |
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| 178 | * @} |
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| 179 | */ |
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| 180 | |||
| 181 | /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload |
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| 182 | * @{ |
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| 183 | */ |
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| 184 | |||
| 185 | /** |
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| 186 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
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| 187 | * @note The RELOAD value should be selected according to the ratio between |
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| 188 | * the target frequency and the frequency of the synchronization source after |
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| 189 | * prescaling. It is then decreased by one in order to reach the expected |
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| 190 | * synchronization on the zero value. The formula is the following: |
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| 191 | * RELOAD = (fTARGET / fSYNC) -1 |
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| 192 | * @param __FTARGET__ Target frequency (value in Hz) |
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| 193 | * @param __FSYNC__ Synchronization signal frequency (value in Hz) |
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| 194 | * @retval Reload value (in Hz) |
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| 195 | */ |
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| 196 | #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) |
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| 197 | |||
| 198 | /** |
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| 199 | * @} |
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| 200 | */ |
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| 201 | |||
| 202 | /** |
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| 203 | * @} |
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| 204 | */ |
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| 205 | |||
| 206 | /* Exported functions --------------------------------------------------------*/ |
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| 207 | /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions |
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| 208 | * @{ |
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| 209 | */ |
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| 210 | |||
| 211 | /** @defgroup CRS_LL_EF_Configuration Configuration |
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| 212 | * @{ |
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| 213 | */ |
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| 214 | |||
| 215 | /** |
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| 216 | * @brief Enable Frequency error counter |
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| 217 | * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified |
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| 218 | * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter |
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| 219 | * @retval None |
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| 220 | */ |
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| 221 | __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) |
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| 222 | { |
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| 223 | SET_BIT(CRS->CR, CRS_CR_CEN); |
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| 224 | } |
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| 225 | |||
| 226 | /** |
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| 227 | * @brief Disable Frequency error counter |
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| 228 | * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter |
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| 229 | * @retval None |
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| 230 | */ |
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| 231 | __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) |
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| 232 | { |
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| 233 | CLEAR_BIT(CRS->CR, CRS_CR_CEN); |
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| 234 | } |
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| 235 | |||
| 236 | /** |
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| 237 | * @brief Check if Frequency error counter is enabled or not |
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| 238 | * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter |
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| 239 | * @retval State of bit (1 or 0). |
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| 240 | */ |
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| 241 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) |
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| 242 | { |
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| 243 | return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); |
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| 244 | } |
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| 245 | |||
| 246 | /** |
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| 247 | * @brief Enable Automatic trimming counter |
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| 248 | * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming |
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| 249 | * @retval None |
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| 250 | */ |
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| 251 | __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) |
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| 252 | { |
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| 253 | SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); |
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| 254 | } |
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| 255 | |||
| 256 | /** |
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| 257 | * @brief Disable Automatic trimming counter |
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| 258 | * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming |
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| 259 | * @retval None |
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| 260 | */ |
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| 261 | __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) |
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| 262 | { |
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| 263 | CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); |
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| 264 | } |
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| 265 | |||
| 266 | /** |
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| 267 | * @brief Check if Automatic trimming is enabled or not |
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| 268 | * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming |
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| 269 | * @retval State of bit (1 or 0). |
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| 270 | */ |
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| 271 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) |
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| 272 | { |
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| 273 | return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); |
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| 274 | } |
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| 275 | |||
| 276 | /** |
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| 277 | * @brief Set HSI48 oscillator smooth trimming |
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| 278 | * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only |
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| 279 | * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming |
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| 280 | * @param Value a number between Min_Data = 0 and Max_Data = 63 |
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| 281 | * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT |
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| 282 | * @retval None |
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| 283 | */ |
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| 284 | __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) |
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| 285 | { |
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| 286 | MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); |
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| 287 | } |
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| 288 | |||
| 289 | /** |
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| 290 | * @brief Get HSI48 oscillator smooth trimming |
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| 291 | * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming |
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| 292 | * @retval a number between Min_Data = 0 and Max_Data = 63 |
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| 293 | */ |
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| 294 | __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) |
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| 295 | { |
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| 296 | return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); |
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| 297 | } |
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| 298 | |||
| 299 | /** |
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| 300 | * @brief Set counter reload value |
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| 301 | * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter |
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| 302 | * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF |
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| 303 | * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT |
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| 304 | * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) |
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| 305 | * @retval None |
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| 306 | */ |
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| 307 | __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) |
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| 308 | { |
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| 309 | MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); |
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| 310 | } |
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| 311 | |||
| 312 | /** |
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| 313 | * @brief Get counter reload value |
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| 314 | * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter |
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| 315 | * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF |
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| 316 | */ |
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| 317 | __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) |
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| 318 | { |
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| 319 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); |
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| 320 | } |
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| 321 | |||
| 322 | /** |
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| 323 | * @brief Set frequency error limit |
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| 324 | * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit |
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| 325 | * @param Value a number between Min_Data = 0 and Max_Data = 255 |
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| 326 | * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT |
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| 327 | * @retval None |
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| 328 | */ |
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| 329 | __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) |
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| 330 | { |
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| 331 | MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); |
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| 332 | } |
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| 333 | |||
| 334 | /** |
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| 335 | * @brief Get frequency error limit |
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| 336 | * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit |
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| 337 | * @retval A number between Min_Data = 0 and Max_Data = 255 |
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| 338 | */ |
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| 339 | __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) |
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| 340 | { |
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| 341 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); |
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| 342 | } |
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| 343 | |||
| 344 | /** |
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| 345 | * @brief Set division factor for SYNC signal |
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| 346 | * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider |
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| 347 | * @param Divider This parameter can be one of the following values: |
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| 348 | * @arg @ref LL_CRS_SYNC_DIV_1 |
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| 349 | * @arg @ref LL_CRS_SYNC_DIV_2 |
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| 350 | * @arg @ref LL_CRS_SYNC_DIV_4 |
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| 351 | * @arg @ref LL_CRS_SYNC_DIV_8 |
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| 352 | * @arg @ref LL_CRS_SYNC_DIV_16 |
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| 353 | * @arg @ref LL_CRS_SYNC_DIV_32 |
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| 354 | * @arg @ref LL_CRS_SYNC_DIV_64 |
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| 355 | * @arg @ref LL_CRS_SYNC_DIV_128 |
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| 356 | * @retval None |
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| 357 | */ |
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| 358 | __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) |
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| 359 | { |
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| 360 | MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); |
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| 361 | } |
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| 362 | |||
| 363 | /** |
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| 364 | * @brief Get division factor for SYNC signal |
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| 365 | * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider |
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| 366 | * @retval Returned value can be one of the following values: |
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| 367 | * @arg @ref LL_CRS_SYNC_DIV_1 |
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| 368 | * @arg @ref LL_CRS_SYNC_DIV_2 |
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| 369 | * @arg @ref LL_CRS_SYNC_DIV_4 |
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| 370 | * @arg @ref LL_CRS_SYNC_DIV_8 |
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| 371 | * @arg @ref LL_CRS_SYNC_DIV_16 |
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| 372 | * @arg @ref LL_CRS_SYNC_DIV_32 |
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| 373 | * @arg @ref LL_CRS_SYNC_DIV_64 |
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| 374 | * @arg @ref LL_CRS_SYNC_DIV_128 |
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| 375 | */ |
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| 376 | __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) |
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| 377 | { |
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| 378 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); |
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| 379 | } |
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| 380 | |||
| 381 | /** |
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| 382 | * @brief Set SYNC signal source |
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| 383 | * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource |
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| 384 | * @param Source This parameter can be one of the following values: |
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| 385 | * @arg @ref LL_CRS_SYNC_SOURCE_GPIO |
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| 386 | * @arg @ref LL_CRS_SYNC_SOURCE_LSE |
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| 387 | * @arg @ref LL_CRS_SYNC_SOURCE_USB |
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| 388 | * @retval None |
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| 389 | */ |
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| 390 | __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) |
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| 391 | { |
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| 392 | MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); |
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| 393 | } |
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| 394 | |||
| 395 | /** |
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| 396 | * @brief Get SYNC signal source |
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| 397 | * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource |
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| 398 | * @retval Returned value can be one of the following values: |
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| 399 | * @arg @ref LL_CRS_SYNC_SOURCE_GPIO |
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| 400 | * @arg @ref LL_CRS_SYNC_SOURCE_LSE |
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| 401 | * @arg @ref LL_CRS_SYNC_SOURCE_USB |
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| 402 | */ |
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| 403 | __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) |
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| 404 | { |
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| 405 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); |
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| 406 | } |
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| 407 | |||
| 408 | /** |
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| 409 | * @brief Set input polarity for the SYNC signal source |
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| 410 | * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity |
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| 411 | * @param Polarity This parameter can be one of the following values: |
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| 412 | * @arg @ref LL_CRS_SYNC_POLARITY_RISING |
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| 413 | * @arg @ref LL_CRS_SYNC_POLARITY_FALLING |
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| 414 | * @retval None |
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| 415 | */ |
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| 416 | __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) |
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| 417 | { |
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| 418 | MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); |
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| 419 | } |
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| 420 | |||
| 421 | /** |
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| 422 | * @brief Get input polarity for the SYNC signal source |
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| 423 | * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity |
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| 424 | * @retval Returned value can be one of the following values: |
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| 425 | * @arg @ref LL_CRS_SYNC_POLARITY_RISING |
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| 426 | * @arg @ref LL_CRS_SYNC_POLARITY_FALLING |
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| 427 | */ |
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| 428 | __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) |
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| 429 | { |
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| 430 | return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); |
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| 431 | } |
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| 432 | |||
| 433 | /** |
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| 434 | * @brief Configure CRS for the synchronization |
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| 435 | * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n |
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| 436 | * CFGR RELOAD LL_CRS_ConfigSynchronization\n |
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| 437 | * CFGR FELIM LL_CRS_ConfigSynchronization\n |
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| 438 | * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n |
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| 439 | * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n |
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| 440 | * CFGR SYNCPOL LL_CRS_ConfigSynchronization |
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| 441 | * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 |
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| 442 | * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF |
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| 443 | * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 |
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| 444 | * @param Settings This parameter can be a combination of the following values: |
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| 445 | * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 |
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| 446 | * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 |
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| 447 | * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB |
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| 448 | * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING |
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| 449 | * @retval None |
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| 450 | */ |
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| 451 | __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) |
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| 452 | { |
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| 453 | MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); |
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| 454 | MODIFY_REG(CRS->CFGR, |
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| 455 | CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, |
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| 456 | ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); |
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| 457 | } |
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| 458 | |||
| 459 | /** |
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| 460 | * @} |
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| 461 | */ |
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| 462 | |||
| 463 | /** @defgroup CRS_LL_EF_CRS_Management CRS_Management |
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| 464 | * @{ |
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| 465 | */ |
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| 466 | |||
| 467 | /** |
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| 468 | * @brief Generate software SYNC event |
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| 469 | * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC |
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| 470 | * @retval None |
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| 471 | */ |
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| 472 | __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) |
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| 473 | { |
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| 474 | SET_BIT(CRS->CR, CRS_CR_SWSYNC); |
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| 475 | } |
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| 476 | |||
| 477 | /** |
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| 478 | * @brief Get the frequency error direction latched in the time of the last |
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| 479 | * SYNC event |
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| 480 | * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection |
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| 481 | * @retval Returned value can be one of the following values: |
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| 482 | * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP |
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| 483 | * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN |
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| 484 | */ |
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| 485 | __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) |
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| 486 | { |
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| 487 | return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); |
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| 488 | } |
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| 489 | |||
| 490 | /** |
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| 491 | * @brief Get the frequency error counter value latched in the time of the last SYNC event |
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| 492 | * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture |
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| 493 | * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF |
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| 494 | */ |
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| 495 | __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) |
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| 496 | { |
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| 497 | return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); |
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| 498 | } |
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| 499 | |||
| 500 | /** |
||
| 501 | * @} |
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| 502 | */ |
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| 503 | |||
| 504 | /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management |
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| 505 | * @{ |
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| 506 | */ |
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| 507 | |||
| 508 | /** |
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| 509 | * @brief Check if SYNC event OK signal occurred or not |
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| 510 | * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK |
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| 511 | * @retval State of bit (1 or 0). |
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| 512 | */ |
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| 513 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) |
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| 514 | { |
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| 515 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); |
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| 516 | } |
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| 517 | |||
| 518 | /** |
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| 519 | * @brief Check if SYNC warning signal occurred or not |
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| 520 | * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN |
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| 521 | * @retval State of bit (1 or 0). |
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| 522 | */ |
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| 523 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) |
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| 524 | { |
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| 525 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); |
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| 526 | } |
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| 527 | |||
| 528 | /** |
||
| 529 | * @brief Check if Synchronization or trimming error signal occurred or not |
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| 530 | * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR |
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| 531 | * @retval State of bit (1 or 0). |
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| 532 | */ |
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| 533 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) |
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| 534 | { |
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| 535 | return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); |
||
| 536 | } |
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| 537 | |||
| 538 | /** |
||
| 539 | * @brief Check if Expected SYNC signal occurred or not |
||
| 540 | * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC |
||
| 541 | * @retval State of bit (1 or 0). |
||
| 542 | */ |
||
| 543 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) |
||
| 544 | { |
||
| 545 | return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); |
||
| 546 | } |
||
| 547 | |||
| 548 | /** |
||
| 549 | * @brief Check if SYNC error signal occurred or not |
||
| 550 | * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR |
||
| 551 | * @retval State of bit (1 or 0). |
||
| 552 | */ |
||
| 553 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) |
||
| 554 | { |
||
| 555 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); |
||
| 556 | } |
||
| 557 | |||
| 558 | /** |
||
| 559 | * @brief Check if SYNC missed error signal occurred or not |
||
| 560 | * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS |
||
| 561 | * @retval State of bit (1 or 0). |
||
| 562 | */ |
||
| 563 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) |
||
| 564 | { |
||
| 565 | return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); |
||
| 566 | } |
||
| 567 | |||
| 568 | /** |
||
| 569 | * @brief Check if Trimming overflow or underflow occurred or not |
||
| 570 | * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF |
||
| 571 | * @retval State of bit (1 or 0). |
||
| 572 | */ |
||
| 573 | __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) |
||
| 574 | { |
||
| 575 | return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); |
||
| 576 | } |
||
| 577 | |||
| 578 | /** |
||
| 579 | * @brief Clear the SYNC event OK flag |
||
| 580 | * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK |
||
| 581 | * @retval None |
||
| 582 | */ |
||
| 583 | __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) |
||
| 584 | { |
||
| 585 | WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); |
||
| 586 | } |
||
| 587 | |||
| 588 | /** |
||
| 589 | * @brief Clear the SYNC warning flag |
||
| 590 | * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN |
||
| 591 | * @retval None |
||
| 592 | */ |
||
| 593 | __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) |
||
| 594 | { |
||
| 595 | WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); |
||
| 596 | } |
||
| 597 | |||
| 598 | /** |
||
| 599 | * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also |
||
| 600 | * the ERR flag |
||
| 601 | * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR |
||
| 602 | * @retval None |
||
| 603 | */ |
||
| 604 | __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) |
||
| 605 | { |
||
| 606 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC); |
||
| 607 | } |
||
| 608 | |||
| 609 | /** |
||
| 610 | * @brief Clear Expected SYNC flag |
||
| 611 | * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC |
||
| 612 | * @retval None |
||
| 613 | */ |
||
| 614 | __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) |
||
| 615 | { |
||
| 616 | WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); |
||
| 617 | } |
||
| 618 | |||
| 619 | /** |
||
| 620 | * @} |
||
| 621 | */ |
||
| 622 | |||
| 623 | /** @defgroup CRS_LL_EF_IT_Management IT_Management |
||
| 624 | * @{ |
||
| 625 | */ |
||
| 626 | |||
| 627 | /** |
||
| 628 | * @brief Enable SYNC event OK interrupt |
||
| 629 | * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK |
||
| 630 | * @retval None |
||
| 631 | */ |
||
| 632 | __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) |
||
| 633 | { |
||
| 634 | SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); |
||
| 635 | } |
||
| 636 | |||
| 637 | /** |
||
| 638 | * @brief Disable SYNC event OK interrupt |
||
| 639 | * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK |
||
| 640 | * @retval None |
||
| 641 | */ |
||
| 642 | __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) |
||
| 643 | { |
||
| 644 | CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); |
||
| 645 | } |
||
| 646 | |||
| 647 | /** |
||
| 648 | * @brief Check if SYNC event OK interrupt is enabled or not |
||
| 649 | * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK |
||
| 650 | * @retval State of bit (1 or 0). |
||
| 651 | */ |
||
| 652 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) |
||
| 653 | { |
||
| 654 | return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); |
||
| 655 | } |
||
| 656 | |||
| 657 | /** |
||
| 658 | * @brief Enable SYNC warning interrupt |
||
| 659 | * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN |
||
| 660 | * @retval None |
||
| 661 | */ |
||
| 662 | __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) |
||
| 663 | { |
||
| 664 | SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); |
||
| 665 | } |
||
| 666 | |||
| 667 | /** |
||
| 668 | * @brief Disable SYNC warning interrupt |
||
| 669 | * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN |
||
| 670 | * @retval None |
||
| 671 | */ |
||
| 672 | __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) |
||
| 673 | { |
||
| 674 | CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); |
||
| 675 | } |
||
| 676 | |||
| 677 | /** |
||
| 678 | * @brief Check if SYNC warning interrupt is enabled or not |
||
| 679 | * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN |
||
| 680 | * @retval State of bit (1 or 0). |
||
| 681 | */ |
||
| 682 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) |
||
| 683 | { |
||
| 684 | return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); |
||
| 685 | } |
||
| 686 | |||
| 687 | /** |
||
| 688 | * @brief Enable Synchronization or trimming error interrupt |
||
| 689 | * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR |
||
| 690 | * @retval None |
||
| 691 | */ |
||
| 692 | __STATIC_INLINE void LL_CRS_EnableIT_ERR(void) |
||
| 693 | { |
||
| 694 | SET_BIT(CRS->CR, CRS_CR_ERRIE); |
||
| 695 | } |
||
| 696 | |||
| 697 | /** |
||
| 698 | * @brief Disable Synchronization or trimming error interrupt |
||
| 699 | * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR |
||
| 700 | * @retval None |
||
| 701 | */ |
||
| 702 | __STATIC_INLINE void LL_CRS_DisableIT_ERR(void) |
||
| 703 | { |
||
| 704 | CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); |
||
| 705 | } |
||
| 706 | |||
| 707 | /** |
||
| 708 | * @brief Check if Synchronization or trimming error interrupt is enabled or not |
||
| 709 | * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR |
||
| 710 | * @retval State of bit (1 or 0). |
||
| 711 | */ |
||
| 712 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) |
||
| 713 | { |
||
| 714 | return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); |
||
| 715 | } |
||
| 716 | |||
| 717 | /** |
||
| 718 | * @brief Enable Expected SYNC interrupt |
||
| 719 | * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC |
||
| 720 | * @retval None |
||
| 721 | */ |
||
| 722 | __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) |
||
| 723 | { |
||
| 724 | SET_BIT(CRS->CR, CRS_CR_ESYNCIE); |
||
| 725 | } |
||
| 726 | |||
| 727 | /** |
||
| 728 | * @brief Disable Expected SYNC interrupt |
||
| 729 | * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC |
||
| 730 | * @retval None |
||
| 731 | */ |
||
| 732 | __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) |
||
| 733 | { |
||
| 734 | CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); |
||
| 735 | } |
||
| 736 | |||
| 737 | /** |
||
| 738 | * @brief Check if Expected SYNC interrupt is enabled or not |
||
| 739 | * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC |
||
| 740 | * @retval State of bit (1 or 0). |
||
| 741 | */ |
||
| 742 | __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) |
||
| 743 | { |
||
| 744 | return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); |
||
| 745 | } |
||
| 746 | |||
| 747 | /** |
||
| 748 | * @} |
||
| 749 | */ |
||
| 750 | |||
| 751 | #if defined(USE_FULL_LL_DRIVER) |
||
| 752 | /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions |
||
| 753 | * @{ |
||
| 754 | */ |
||
| 755 | |||
| 756 | ErrorStatus LL_CRS_DeInit(void); |
||
| 757 | |||
| 758 | /** |
||
| 759 | * @} |
||
| 760 | */ |
||
| 761 | #endif /* USE_FULL_LL_DRIVER */ |
||
| 762 | |||
| 763 | /** |
||
| 764 | * @} |
||
| 765 | */ |
||
| 766 | |||
| 767 | /** |
||
| 768 | * @} |
||
| 769 | */ |
||
| 770 | |||
| 771 | #endif /* defined(CRS) */ |
||
| 772 | |||
| 773 | /** |
||
| 774 | * @} |
||
| 775 | */ |
||
| 776 | |||
| 777 | #ifdef __cplusplus |
||
| 778 | } |
||
| 779 | #endif |
||
| 780 | |||
| 781 | #endif /* __STM32F0xx_LL_CRS_H */ |
||
| 782 | |||
| 783 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |