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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_ll_cortex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of CORTEX LL module. |
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| 6 | @verbatim |
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| 7 | ============================================================================== |
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| 8 | ##### How to use this driver ##### |
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| 9 | ============================================================================== |
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| 10 | [..] |
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| 11 | The LL CORTEX driver contains a set of generic APIs that can be |
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| 12 | used by user: |
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| 6 | mjames | 13 | (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick |
| 2 | mjames | 14 | functions |
| 15 | (+) Low power mode configuration (SCB register of Cortex-MCU) |
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| 16 | (+) API to access to MCU info (CPUID register) |
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| 17 | |||
| 18 | @endverbatim |
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| 19 | ****************************************************************************** |
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| 20 | * @attention |
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| 21 | * |
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| 22 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 23 | * All rights reserved.</center></h2> |
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| 24 | * |
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| 25 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 26 | * the "License"; You may not use this file except in compliance with the |
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| 27 | * License. You may obtain a copy of the License at: |
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| 28 | * opensource.org/licenses/BSD-3-Clause |
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| 29 | * |
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| 30 | ****************************************************************************** |
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| 31 | */ |
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| 32 | |||
| 33 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 34 | #ifndef __STM32F0xx_LL_CORTEX_H |
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| 35 | #define __STM32F0xx_LL_CORTEX_H |
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| 36 | |||
| 37 | #ifdef __cplusplus |
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| 38 | extern "C" { |
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| 39 | #endif |
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| 40 | |||
| 41 | /* Includes ------------------------------------------------------------------*/ |
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| 42 | #include "stm32f0xx.h" |
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| 43 | |||
| 44 | /** @addtogroup STM32F0xx_LL_Driver |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | |||
| 48 | /** @defgroup CORTEX_LL CORTEX |
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| 49 | * @{ |
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| 50 | */ |
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| 51 | |||
| 52 | /* Private types -------------------------------------------------------------*/ |
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| 53 | /* Private variables ---------------------------------------------------------*/ |
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| 54 | |||
| 55 | /* Private constants ---------------------------------------------------------*/ |
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| 56 | |||
| 57 | /* Private macros ------------------------------------------------------------*/ |
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| 58 | |||
| 59 | /* Exported types ------------------------------------------------------------*/ |
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| 60 | /* Exported constants --------------------------------------------------------*/ |
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| 61 | /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
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| 62 | * @{ |
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| 63 | */ |
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| 64 | |||
| 65 | /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
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| 66 | * @{ |
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| 67 | */ |
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| 68 | #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
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| 69 | #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ |
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| 70 | /** |
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| 71 | * @} |
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| 72 | */ |
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| 73 | |||
| 74 | /** |
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| 75 | * @} |
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| 76 | */ |
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| 77 | |||
| 78 | /* Exported macro ------------------------------------------------------------*/ |
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| 79 | |||
| 80 | /* Exported functions --------------------------------------------------------*/ |
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| 81 | /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
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| 82 | * @{ |
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| 83 | */ |
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| 84 | |||
| 85 | /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
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| 86 | * @{ |
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| 87 | */ |
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| 88 | |||
| 89 | /** |
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| 90 | * @brief This function checks if the Systick counter flag is active or not. |
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| 91 | * @note It can be used in timeout function on application side. |
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| 92 | * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
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| 93 | * @retval State of bit (1 or 0). |
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| 94 | */ |
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| 95 | __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
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| 96 | { |
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| 97 | return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
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| 98 | } |
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| 99 | |||
| 100 | /** |
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| 101 | * @brief Configures the SysTick clock source |
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| 102 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
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| 103 | * @param Source This parameter can be one of the following values: |
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| 104 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
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| 105 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
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| 106 | * @retval None |
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| 107 | */ |
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| 108 | __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
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| 109 | { |
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| 110 | if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
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| 111 | { |
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| 112 | SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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| 113 | } |
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| 114 | else |
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| 115 | { |
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| 116 | CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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| 117 | } |
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| 118 | } |
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| 119 | |||
| 120 | /** |
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| 121 | * @brief Get the SysTick clock source |
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| 122 | * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
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| 123 | * @retval Returned value can be one of the following values: |
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| 124 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
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| 125 | * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
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| 126 | */ |
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| 127 | __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
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| 128 | { |
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| 129 | return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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| 130 | } |
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| 131 | |||
| 132 | /** |
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| 133 | * @brief Enable SysTick exception request |
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| 134 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
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| 135 | * @retval None |
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| 136 | */ |
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| 137 | __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
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| 138 | { |
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| 139 | SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
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| 140 | } |
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| 141 | |||
| 142 | /** |
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| 143 | * @brief Disable SysTick exception request |
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| 144 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
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| 145 | * @retval None |
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| 146 | */ |
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| 147 | __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
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| 148 | { |
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| 149 | CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
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| 150 | } |
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| 151 | |||
| 152 | /** |
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| 153 | * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
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| 154 | * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
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| 155 | * @retval State of bit (1 or 0). |
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| 156 | */ |
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| 157 | __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
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| 158 | { |
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| 159 | return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
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| 160 | } |
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| 161 | |||
| 162 | /** |
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| 163 | * @} |
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| 164 | */ |
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| 165 | |||
| 166 | /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
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| 167 | * @{ |
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| 168 | */ |
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| 169 | |||
| 170 | /** |
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| 171 | * @brief Processor uses sleep as its low power mode |
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| 172 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
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| 173 | * @retval None |
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| 174 | */ |
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| 175 | __STATIC_INLINE void LL_LPM_EnableSleep(void) |
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| 176 | { |
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| 177 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
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| 178 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 179 | } |
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| 180 | |||
| 181 | /** |
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| 182 | * @brief Processor uses deep sleep as its low power mode |
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| 183 | * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
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| 184 | * @retval None |
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| 185 | */ |
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| 186 | __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
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| 187 | { |
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| 188 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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| 189 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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| 190 | } |
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| 191 | |||
| 192 | /** |
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| 193 | * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
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| 194 | * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
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| 195 | * empty main application. |
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| 196 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
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| 197 | * @retval None |
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| 198 | */ |
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| 199 | __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
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| 200 | { |
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| 201 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
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| 202 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 203 | } |
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| 204 | |||
| 205 | /** |
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| 206 | * @brief Do not sleep when returning to Thread mode. |
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| 207 | * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
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| 208 | * @retval None |
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| 209 | */ |
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| 210 | __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
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| 211 | { |
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| 212 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
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| 213 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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| 214 | } |
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| 215 | |||
| 216 | /** |
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| 217 | * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
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| 218 | * processor. |
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| 219 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
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| 220 | * @retval None |
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| 221 | */ |
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| 222 | __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
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| 223 | { |
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| 224 | /* Set SEVEONPEND bit of Cortex System Control Register */ |
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| 225 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 226 | } |
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| 227 | |||
| 228 | /** |
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| 229 | * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
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| 230 | * excluded |
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| 231 | * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
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| 232 | * @retval None |
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| 233 | */ |
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| 234 | __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
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| 235 | { |
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| 236 | /* Clear SEVEONPEND bit of Cortex System Control Register */ |
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| 237 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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| 238 | } |
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| 239 | |||
| 240 | /** |
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| 241 | * @} |
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| 242 | */ |
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| 243 | |||
| 244 | /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
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| 245 | * @{ |
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| 246 | */ |
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| 247 | |||
| 248 | /** |
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| 249 | * @brief Get Implementer code |
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| 250 | * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
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| 251 | * @retval Value should be equal to 0x41 for ARM |
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| 252 | */ |
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| 253 | __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
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| 254 | { |
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| 255 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
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| 256 | } |
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| 257 | |||
| 258 | /** |
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| 259 | * @brief Get Variant number (The r value in the rnpn product revision identifier) |
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| 260 | * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
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| 261 | * @retval Value between 0 and 255 (0x0: revision 0) |
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| 262 | */ |
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| 263 | __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
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| 264 | { |
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| 265 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
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| 266 | } |
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| 267 | |||
| 268 | /** |
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| 269 | * @brief Get Architecture number |
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| 270 | * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture |
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| 271 | * @retval Value should be equal to 0xC for Cortex-M0 devices |
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| 272 | */ |
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| 273 | __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) |
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| 274 | { |
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| 275 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
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| 276 | } |
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| 277 | |||
| 278 | /** |
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| 279 | * @brief Get Part number |
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| 280 | * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
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| 281 | * @retval Value should be equal to 0xC20 for Cortex-M0 |
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| 282 | */ |
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| 283 | __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
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| 284 | { |
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| 285 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
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| 286 | } |
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| 287 | |||
| 288 | /** |
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| 289 | * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
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| 290 | * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
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| 291 | * @retval Value between 0 and 255 (0x1: patch 1) |
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| 292 | */ |
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| 293 | __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
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| 294 | { |
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| 295 | return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
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| 296 | } |
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| 297 | |||
| 298 | /** |
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| 299 | * @} |
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| 300 | */ |
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| 301 | |||
| 302 | /** |
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| 303 | * @} |
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| 304 | */ |
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| 305 | |||
| 306 | /** |
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| 307 | * @} |
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| 308 | */ |
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| 309 | |||
| 310 | /** |
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| 311 | * @} |
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| 312 | */ |
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| 313 | |||
| 314 | #ifdef __cplusplus |
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| 315 | } |
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| 316 | #endif |
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| 317 | |||
| 318 | #endif /* __STM32F0xx_LL_CORTEX_H */ |
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| 319 | |||
| 320 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |