WebSVN – ScreenTimer – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_bus.h
		4	* @author MCD Application Team
		5	* @brief Header file of BUS LL module.
		6
		7	@verbatim
		8	##### RCC Limitations #####
		9	==============================================================================
		10	[..]
		11	A delay between an RCC peripheral clock enable and the effective peripheral
		12	enabling should be taken into account in order to manage the peripheral read/write
		13	from/to registers.
		14	(+) This delay depends on the peripheral mapping.
		15	(++) AHB & APB peripherals, 1 dummy read is necessary
		16
		17	[..]
		18	Workarounds:
		19	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
		20	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
		21
		22	@endverbatim
		23	******************************************************************************
		24	* @attention
		25	*
		26	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		27	* All rights reserved.</center></h2>
		28	*
		29	* This software component is licensed by ST under BSD 3-Clause license,
		30	* the "License"; You may not use this file except in compliance with the
		31	* License. You may obtain a copy of the License at:
		32	* opensource.org/licenses/BSD-3-Clause
		33	*
		34	******************************************************************************
		35	*/
		36
		37	/* Define to prevent recursive inclusion -------------------------------------*/
		38	#ifndef __STM32F0xx_LL_BUS_H
		39	#define __STM32F0xx_LL_BUS_H
		40
		41	#ifdef __cplusplus
		42	extern "C" {
		43	#endif
		44
		45	/* Includes ------------------------------------------------------------------*/
		46	#include "stm32f0xx.h"
		47
		48	/** @addtogroup STM32F0xx_LL_Driver
		49	* @{
		50	*/
		51
		52	#if defined(RCC)
		53
		54	/** @defgroup BUS_LL BUS
		55	* @{
		56	*/
		57
		58	/* Private types -------------------------------------------------------------*/
		59	/* Private variables ---------------------------------------------------------*/
		60
		61	/* Private constants ---------------------------------------------------------*/
		62
		63	/* Private macros ------------------------------------------------------------*/
		64
		65	/* Exported types ------------------------------------------------------------*/
		66	/* Exported constants --------------------------------------------------------*/
		67	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
		68	* @{
		69	*/
		70
		71	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
		72	* @{
		73	*/
		74	#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
		75	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
		76	#if defined(DMA2)
		77	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
		78	#endif /DMA2/
		79	#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
		80	#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
		81	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
		82	#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
		83	#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
		84	#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
		85	#if defined(GPIOD)
		86	#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
		87	#endif /GPIOD/
		88	#if defined(GPIOE)
		89	#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
		90	#endif /GPIOE/
		91	#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
		92	#if defined(TSC)
		93	#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
		94	#endif /TSC/
		95	/**
		96	* @}
		97	*/
		98
		99	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
		100	* @{
		101	*/
		102	#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
		103	#if defined(TIM2)
		104	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
		105	#endif /TIM2/
		106	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
		107	#if defined(TIM6)
		108	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
		109	#endif /TIM6/
		110	#if defined(TIM7)
		111	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
		112	#endif /TIM7/
		113	#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
		114	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
		115	#if defined(SPI2)
		116	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
		117	#endif /SPI2/
		118	#if defined(USART2)
		119	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
		120	#endif /* USART2 */
		121	#if defined(USART3)
		122	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
		123	#endif /* USART3 */
		124	#if defined(USART4)
		125	#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN
		126	#endif /* USART4 */
		127	#if defined(USART5)
		128	#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN
		129	#endif /* USART5 */
		130	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
		131	#if defined(I2C2)
		132	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
		133	#endif /I2C2/
		134	#if defined(USB)
		135	#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
		136	#endif /* USB */
		137	#if defined(CAN)
		138	#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
		139	#endif /CAN/
		140	#if defined(CRS)
		141	#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN
		142	#endif /CRS/
		143	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
		144	#if defined(DAC)
		145	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
		146	#endif /DAC/
		147	#if defined(CEC)
		148	#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
		149	#endif /CEC/
		150	/**
		151	* @}
		152	*/
		153
		154	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
		155	* @{
		156	*/
		157	#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU
		158	#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
		159	#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
		160	#if defined(USART8)
		161	#define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN
		162	#endif /USART8/
		163	#if defined(USART7)
		164	#define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN
		165	#endif /USART7/
		166	#if defined(USART6)
		167	#define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN
		168	#endif /USART6/
		169	#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
		170	#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
		171	#define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN
		172	#if defined(TIM15)
		173	#define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
		174	#endif /TIM15/
		175	#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
		176	#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
		177	#define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN
		178	/**
		179	* @}
		180	*/
		181
		182	/**
		183	* @}
		184	*/
		185
		186	/* Exported macro ------------------------------------------------------------*/
		187	/* Exported functions --------------------------------------------------------*/
		188	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
		189	* @{
		190	*/
		191
		192	/** @defgroup BUS_LL_EF_AHB1 AHB1
		193	* @{
		194	*/
		195
		196	/**
		197	* @brief Enable AHB1 peripherals clock.
		198	* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
		199	* AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
		200	* AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
		201	* AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
		202	* AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
		203	* AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
		204	* AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
		205	* AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
		206	* AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
		207	* AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
		208	* AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
		209	* AHBENR TSCEN LL_AHB1_GRP1_EnableClock
		210	* @param Periphs This parameter can be a combination of the following values:
		211	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
		212	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
		213	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
		214	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
		215	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
		216	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
		217	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
		218	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
		219	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
		220	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
		221	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
		222	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
		223	*
		224	* (*) value not defined in all devices.
		225	* @retval None
		226	*/
		227	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
		228	{
		229	__IO uint32_t tmpreg;
		230	SET_BIT(RCC->AHBENR, Periphs);
		231	/* Delay after an RCC peripheral clock enabling */
		232	tmpreg = READ_BIT(RCC->AHBENR, Periphs);
		233	(void)tmpreg;
		234	}
		235
		236	/**
		237	* @brief Check if AHB1 peripheral clock is enabled or not
		238	* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
		239	* AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
		240	* AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
		241	* AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
		242	* AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
		243	* AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
		244	* AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
		245	* AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
		246	* AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
		247	* AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
		248	* AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
		249	* AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock
		250	* @param Periphs This parameter can be a combination of the following values:
		251	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
		252	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
		253	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
		254	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
		255	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
		256	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
		257	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
		258	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
		259	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
		260	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
		261	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
		262	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
		263	*
		264	* (*) value not defined in all devices.
		265	* @retval State of Periphs (1 or 0).
		266	*/
		267	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
		268	{
		269	return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
		270	}
		271
		272	/**
		273	* @brief Disable AHB1 peripherals clock.
		274	* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
		275	* AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
		276	* AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
		277	* AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
		278	* AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
		279	* AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
		280	* AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
		281	* AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
		282	* AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
		283	* AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
		284	* AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
		285	* AHBENR TSCEN LL_AHB1_GRP1_DisableClock
		286	* @param Periphs This parameter can be a combination of the following values:
		287	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
		288	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
		289	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
		290	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
		291	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
		292	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
		293	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
		294	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
		295	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
		296	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
		297	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
		298	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
		299	*
		300	* (*) value not defined in all devices.
		301	* @retval None
		302	*/
		303	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
		304	{
		305	CLEAR_BIT(RCC->AHBENR, Periphs);
		306	}
		307
		308	/**
		309	* @brief Force AHB1 peripherals reset.
		310	* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
		311	* AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
		312	* AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
		313	* AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
		314	* AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
		315	* AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
		316	* AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset
		317	* @param Periphs This parameter can be a combination of the following values:
		318	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
		319	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
		320	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
		321	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
		322	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
		323	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
		324	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
		325	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
		326	*
		327	* (*) value not defined in all devices.
		328	* @retval None
		329	*/
		330	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
		331	{
		332	SET_BIT(RCC->AHBRSTR, Periphs);
		333	}
		334
		335	/**
		336	* @brief Release AHB1 peripherals reset.
		337	* @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
		338	* AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
		339	* AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
		340	* AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
		341	* AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
		342	* AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
		343	* AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset
		344	* @param Periphs This parameter can be a combination of the following values:
		345	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
		346	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
		347	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
		348	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
		349	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
		350	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
		351	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
		352	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)
		353	*
		354	* (*) value not defined in all devices.
		355	* @retval None
		356	*/
		357	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
		358	{
		359	CLEAR_BIT(RCC->AHBRSTR, Periphs);
		360	}
		361
		362	/**
		363	* @}
		364	*/
		365
		366	/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
		367	* @{
		368	*/
		369
		370	/**
		371	* @brief Enable APB1 peripherals clock (available in register 1).
		372	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
		373	* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
		374	* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
		375	* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
		376	* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
		377	* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
		378	* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
		379	* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
		380	* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
		381	* APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n
		382	* APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n
		383	* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
		384	* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
		385	* APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
		386	* APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
		387	* APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n
		388	* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
		389	* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
		390	* APB1ENR CECEN LL_APB1_GRP1_EnableClock
		391	* @param Periphs This parameter can be a combination of the following values:
		392	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
		393	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
		394	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
		395	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
		396	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
		397	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
		398	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
		399	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
		400	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
		401	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
		402	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
		403	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
		404	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
		405	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
		406	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
		407	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
		408	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
		409	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
		410	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
		411	*
		412	* (*) value not defined in all devices.
		413	* @retval None
		414	*/
		415	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
		416	{
		417	__IO uint32_t tmpreg;
		418	SET_BIT(RCC->APB1ENR, Periphs);
		419	/* Delay after an RCC peripheral clock enabling */
		420	tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
		421	(void)tmpreg;
		422	}
		423
		424	/**
		425	* @brief Check if APB1 peripheral clock is enabled or not (available in register 1).
		426	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
		427	* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
		428	* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
		429	* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
		430	* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
		431	* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
		432	* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
		433	* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
		434	* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
		435	* APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n
		436	* APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n
		437	* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
		438	* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
		439	* APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
		440	* APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
		441	* APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n
		442	* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
		443	* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
		444	* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
		445	* @param Periphs This parameter can be a combination of the following values:
		446	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
		447	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
		448	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
		449	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
		450	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
		451	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
		452	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
		453	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
		454	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
		455	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
		456	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
		457	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
		458	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
		459	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
		460	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
		461	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
		462	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
		463	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
		464	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
		465	*
		466	* (*) value not defined in all devices.
		467	* @retval State of Periphs (1 or 0).
		468	*/
		469	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
		470	{
		471	return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
		472	}
		473
		474	/**
		475	* @brief Disable APB1 peripherals clock (available in register 1).
		476	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
		477	* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
		478	* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
		479	* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
		480	* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
		481	* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
		482	* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
		483	* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
		484	* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
		485	* APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n
		486	* APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n
		487	* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
		488	* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
		489	* APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
		490	* APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
		491	* APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n
		492	* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
		493	* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
		494	* APB1ENR CECEN LL_APB1_GRP1_DisableClock
		495	* @param Periphs This parameter can be a combination of the following values:
		496	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
		497	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
		498	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
		499	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
		500	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
		501	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
		502	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
		503	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
		504	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
		505	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
		506	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
		507	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
		508	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
		509	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
		510	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
		511	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
		512	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
		513	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
		514	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
		515	*
		516	* (*) value not defined in all devices.
		517	* @retval None
		518	*/
		519	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
		520	{
		521	CLEAR_BIT(RCC->APB1ENR, Periphs);
		522	}
		523
		524	/**
		525	* @brief Force APB1 peripherals reset (available in register 1).
		526	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
		527	* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
		528	* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
		529	* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
		530	* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
		531	* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
		532	* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
		533	* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
		534	* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
		535	* APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n
		536	* APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n
		537	* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
		538	* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
		539	* APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
		540	* APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
		541	* APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n
		542	* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
		543	* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
		544	* APB1RSTR CECRST LL_APB1_GRP1_ForceReset
		545	* @param Periphs This parameter can be a combination of the following values:
		546	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
		547	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
		548	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
		549	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
		550	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
		551	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
		552	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
		553	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
		554	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
		555	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
		556	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
		557	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
		558	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
		559	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
		560	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
		561	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
		562	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
		563	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
		564	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
		565	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
		566	*
		567	* (*) value not defined in all devices.
		568	* @retval None
		569	*/
		570	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
		571	{
		572	SET_BIT(RCC->APB1RSTR, Periphs);
		573	}
		574
		575	/**
		576	* @brief Release APB1 peripherals reset (available in register 1).
		577	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
		578	* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
		579	* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
		580	* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
		581	* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
		582	* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
		583	* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
		584	* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
		585	* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
		586	* APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n
		587	* APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n
		588	* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
		589	* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
		590	* APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
		591	* APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
		592	* APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n
		593	* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
		594	* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
		595	* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
		596	* @param Periphs This parameter can be a combination of the following values:
		597	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
		598	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
		599	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
		600	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
		601	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
		602	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
		603	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
		604	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
		605	* @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*)
		606	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
		607	* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)
		608	* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)
		609	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
		610	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
		611	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
		612	* @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
		613	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
		614	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
		615	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
		616	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
		617	*
		618	* (*) value not defined in all devices.
		619	* @retval None
		620	*/
		621	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
		622	{
		623	CLEAR_BIT(RCC->APB1RSTR, Periphs);
		624	}
		625
		626	/**
		627	* @}
		628	*/
		629
		630	/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
		631	* @{
		632	*/
		633
		634	/**
		635	* @brief Enable APB1 peripherals clock (available in register 2).
		636	* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n
		637	* APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n
		638	* APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n
		639	* APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n
		640	* APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n
		641	* APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n
		642	* APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n
		643	* APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n
		644	* APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n
		645	* APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n
		646	* APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n
		647	* APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock
		648	* @param Periphs This parameter can be a combination of the following values:
		649	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
		650	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
		651	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
		652	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
		653	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
		654	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
		655	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
		656	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
		657	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
		658	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
		659	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
		660	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
		661	*
		662	* (*) value not defined in all devices.
		663	* @retval None
		664	*/
		665	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
		666	{
		667	__IO uint32_t tmpreg;
		668	SET_BIT(RCC->APB2ENR, Periphs);
		669	/* Delay after an RCC peripheral clock enabling */
		670	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
		671	(void)tmpreg;
		672	}
		673
		674	/**
		675	* @brief Check if APB1 peripheral clock is enabled or not (available in register 2).
		676	* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n
		677	* APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n
		678	* APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n
		679	* APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n
		680	* APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n
		681	* APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n
		682	* APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n
		683	* APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n
		684	* APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n
		685	* APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n
		686	* APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n
		687	* APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock
		688	* @param Periphs This parameter can be a combination of the following values:
		689	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
		690	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
		691	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
		692	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
		693	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
		694	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
		695	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
		696	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
		697	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
		698	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
		699	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
		700	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
		701	*
		702	* (*) value not defined in all devices.
		703	* @retval State of Periphs (1 or 0).
		704	*/
		705	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
		706	{
		707	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
		708	}
		709
		710	/**
		711	* @brief Disable APB1 peripherals clock (available in register 2).
		712	* @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n
		713	* APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n
		714	* APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n
		715	* APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n
		716	* APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n
		717	* APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n
		718	* APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n
		719	* APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n
		720	* APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n
		721	* APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n
		722	* APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n
		723	* APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock
		724	* @param Periphs This parameter can be a combination of the following values:
		725	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
		726	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
		727	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
		728	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
		729	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
		730	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
		731	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
		732	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
		733	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
		734	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
		735	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
		736	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
		737	*
		738	* (*) value not defined in all devices.
		739	* @retval None
		740	*/
		741	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
		742	{
		743	CLEAR_BIT(RCC->APB2ENR, Periphs);
		744	}
		745
		746	/**
		747	* @brief Force APB1 peripherals reset (available in register 2).
		748	* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n
		749	* APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n
		750	* APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n
		751	* APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n
		752	* APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n
		753	* APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n
		754	* APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n
		755	* APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n
		756	* APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n
		757	* APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n
		758	* APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n
		759	* APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset
		760	* @param Periphs This parameter can be a combination of the following values:
		761	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
		762	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
		763	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
		764	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
		765	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
		766	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
		767	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
		768	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
		769	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
		770	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
		771	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
		772	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
		773	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
		774	*
		775	* (*) value not defined in all devices.
		776	* @retval None
		777	*/
		778	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
		779	{
		780	SET_BIT(RCC->APB2RSTR, Periphs);
		781	}
		782
		783	/**
		784	* @brief Release APB1 peripherals reset (available in register 2).
		785	* @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n
		786	* APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n
		787	* APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n
		788	* APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n
		789	* APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n
		790	* APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n
		791	* APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n
		792	* APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n
		793	* APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n
		794	* APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n
		795	* APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n
		796	* APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset
		797	* @param Periphs This parameter can be a combination of the following values:
		798	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
		799	* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
		800	* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
		801	* @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*)
		802	* @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*)
		803	* @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*)
		804	* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
		805	* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
		806	* @arg @ref LL_APB1_GRP2_PERIPH_USART1
		807	* @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*)
		808	* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
		809	* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
		810	* @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU
		811	*
		812	* (*) value not defined in all devices.
		813	* @retval None
		814	*/
		815	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
		816	{
		817	CLEAR_BIT(RCC->APB2RSTR, Periphs);
		818	}
		819
		820	/**
		821	* @}
		822	*/
		823
		824
		825	/**
		826	* @}
		827	*/
		828
		829	/**
		830	* @}
		831	*/
		832
		833	#endif /* defined(RCC) */
		834
		835	/**
		836	* @}
		837	*/
		838
		839	#ifdef __cplusplus
		840	}
		841	#endif
		842
		843	#endif /* __STM32F0xx_LL_BUS_H */
		844
		845	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_bus.h – Rev 2