WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_adc.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_ll_adc.h
		4	* @author MCD Application Team
		5	* @brief Header file of ADC LL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef __STM32F0xx_LL_ADC_H
		22	#define __STM32F0xx_LL_ADC_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f0xx.h"
		30
		31	/** @addtogroup STM32F0xx_LL_Driver
		32	* @{
		33	*/
		34
		35	#if defined (ADC1)
		36
		37	/** @defgroup ADC_LL ADC
		38	* @{
		39	*/
		40
		41	/* Private types -------------------------------------------------------------*/
		42	/* Private variables ---------------------------------------------------------*/
		43
		44	/* Private constants ---------------------------------------------------------*/
		45	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
		46	* @{
		47	*/
		48
		49	/* Internal mask for ADC group regular trigger: */
		50	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
		51	/* - regular trigger source */
		52	/* - regular trigger edge */
		53	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
		54
		55	/* Mask containing trigger source masks for each of possible */
		56	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
		57	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
		58	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) \| \
		59	((ADC_CFGR1_EXTSEL) << (4U * 1U)) \| \
		60	((ADC_CFGR1_EXTSEL) << (4U * 2U)) \| \
		61	((ADC_CFGR1_EXTSEL) << (4U * 3U)) )
		62
		63	/* Mask containing trigger edge masks for each of possible */
		64	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
		65	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
		66	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) \| \
		67	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) \| \
		68	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) \| \
		69	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
		70
		71	/* Definition of ADC group regular trigger bits information. */
		72	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
		73	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
		74
		75
		76
		77	/* Internal mask for ADC channel: */
		78	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
		79	/* - channel identifier defined by number */
		80	/* - channel identifier defined by bitfield */
		81	/* - channel differentiation between external channels (connected to */
		82	/* GPIO pins) and internal channels (connected to internal paths) */
		83	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH)
		84	#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
		85	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
		86	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
		87	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
		88	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
		89
		90	/* Channel differentiation between external and internal channels */
		91	#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
		92	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
		93
		94	/* Definition of channels ID number information to be inserted into */
		95	/* channels literals definition. */
		96	#define ADC_CHANNEL_0_NUMBER (0x00000000U)
		97	#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0)
		98	#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 )
		99	#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
		100	#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 )
		101	#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_0)
		102	#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 )
		103	#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
		104	#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 )
		105	#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_0)
		106	#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_1 )
		107	#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
		108	#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 )
		109	#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_0)
		110	#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 )
		111	#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
		112	#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 )
		113	#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 \| ADC_CFGR1_AWDCH_0)
		114	#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 \| ADC_CFGR1_AWDCH_1 )
		115
		116	/* Definition of channels ID bitfield information to be inserted into */
		117	/* channels literals definition. */
		118	#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
		119	#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
		120	#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
		121	#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
		122	#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
		123	#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
		124	#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
		125	#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
		126	#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
		127	#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
		128	#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
		129	#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
		130	#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
		131	#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
		132	#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
		133	#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
		134	#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
		135	#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
		136	#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
		137
		138	/* Internal mask for ADC analog watchdog: */
		139	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
		140	/* (concatenation of multiple bits used in different analog watchdogs, */
		141	/* (feature of several watchdogs not available on all STM32 families)). */
		142	/* - analog watchdog 1: monitored channel defined by number, */
		143	/* selection of ADC group (ADC group regular). */
		144
		145	/* Internal register offset for ADC analog watchdog channel configuration */
		146	#define ADC_AWD_CR1_REGOFFSET (0x00000000U)
		147
		148	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
		149
		150	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL)
		151	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
		152
		153	/* Internal register offset for ADC analog watchdog threshold configuration */
		154	#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
		155	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET)
		156
		157
		158	/* ADC registers bits positions */
		159	#define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
		160	#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
		161	#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
		162	#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
		163	#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
		164	#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
		165	#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
		166	#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
		167	#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
		168	#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
		169	#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
		170	#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
		171	#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
		172	#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
		173	#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
		174	#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
		175	#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
		176	#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
		177	#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
		178	#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
		179	#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
		180	#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
		181
		182
		183	/* ADC registers bits groups */
		184	#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
		185
		186
		187	/* ADC internal channels related definitions */
		188	/* Internal voltage reference VrefInt */
		189	#define VREFINT_CAL_ADDR ((uint16_t) (0x1FFFF7BAU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
		190	#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
		191	/* Temperature sensor */
		192	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FFFF7B8U)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
		193	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FFFF7C2U)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
		194	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
		195	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
		196	#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
		197
		198
		199	/**
		200	* @}
		201	*/
		202
		203
		204	/* Exported types ------------------------------------------------------------*/
		205	#if defined(USE_FULL_LL_DRIVER)
		206	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
		207	* @{
		208	*/
		209
		210	/**
		211	* @brief Structure definition of some features of ADC instance.
		212	* @note These parameters have an impact on ADC scope: ADC instance.
		213	* Refer to corresponding unitary functions into
		214	* @ref ADC_LL_EF_Configuration_ADC_Instance .
		215	* @note The setting of these parameters by function @ref LL_ADC_Init()
		216	* is conditioned to ADC state:
		217	* ADC instance must be disabled.
		218	* This condition is applied to all ADC features, for efficiency
		219	* and compatibility over all STM32 families. However, the different
		220	* features can be set under different ADC state conditions
		221	* (setting possible with ADC enabled without conversion on going,
		222	* ADC enabled with conversion on going, ...)
		223	* Each feature can be updated afterwards with a unitary function
		224	* and potentially with ADC in a different state than disabled,
		225	* refer to description of each function for setting
		226	* conditioned to ADC state.
		227	*/
		228	typedef struct
		229	{
		230	uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
		231	This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
		232	@note On this STM32 serie, this parameter has some clock ratio constraints:
		233	ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
		234	(APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
		235
		236
		237	This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
		238	For more details, refer to description of this function. */
		239
		240	uint32_t Resolution; /*!< Set ADC resolution.
		241	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
		242
		243	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
		244
		245	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
		246	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
		247
		248	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
		249
		250	uint32_t LowPowerMode; /*!< Set ADC low power mode.
		251	This parameter can be a value of @ref ADC_LL_EC_LP_MODE
		252
		253	This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
		254
		255	} LL_ADC_InitTypeDef;
		256
		257	/**
		258	* @brief Structure definition of some features of ADC group regular.
		259	* @note These parameters have an impact on ADC scope: ADC group regular.
		260	* Refer to corresponding unitary functions into
		261	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
		262	* (functions with prefix "REG").
		263	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
		264	* is conditioned to ADC state:
		265	* ADC instance must be disabled.
		266	* This condition is applied to all ADC features, for efficiency
		267	* and compatibility over all STM32 families. However, the different
		268	* features can be set under different ADC state conditions
		269	* (setting possible with ADC enabled without conversion on going,
		270	* ADC enabled with conversion on going, ...)
		271	* Each feature can be updated afterwards with a unitary function
		272	* and potentially with ADC in a different state than disabled,
		273	* refer to description of each function for setting
		274	* conditioned to ADC state.
		275	*/
		276	typedef struct
		277	{
		278	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
		279	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
		280	@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
		281	(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
		282	In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
		283
		284	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
		285
		286	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
		287	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
		288	@note This parameter has an effect only if group regular sequencer is enabled
		289	(several ADC channels enabled in group regular sequencer).
		290
		291	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
		292
		293	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
		294	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
		295	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
		296
		297	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
		298
		299	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
		300	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
		301
		302	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
		303
		304	uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
		305	data preserved or overwritten.
		306	This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
		307
		308	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
		309
		310	} LL_ADC_REG_InitTypeDef;
		311
		312	/**
		313	* @}
		314	*/
		315	#endif /* USE_FULL_LL_DRIVER */
		316
		317	/* Exported constants --------------------------------------------------------*/
		318	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
		319	* @{
		320	*/
		321
		322	/** @defgroup ADC_LL_EC_FLAG ADC flags
		323	* @brief Flags defines which can be used with LL_ADC_ReadReg function
		324	* @{
		325	*/
		326	#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /!< ADC flag ADC instance ready /
		327	#define LL_ADC_FLAG_EOC ADC_ISR_EOC /!< ADC flag ADC group regular end of unitary conversion /
		328	#define LL_ADC_FLAG_EOS ADC_ISR_EOS /!< ADC flag ADC group regular end of sequence conversions /
		329	#define LL_ADC_FLAG_OVR ADC_ISR_OVR /!< ADC flag ADC group regular overrun /
		330	#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC flag ADC group regular end of sampling phase /
		331	#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /!< ADC flag ADC analog watchdog 1 /
		332	/**
		333	* @}
		334	*/
		335
		336	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
		337	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
		338	* @{
		339	*/
		340	#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /!< ADC interruption ADC instance ready /
		341	#define LL_ADC_IT_EOC ADC_IER_EOCIE /!< ADC interruption ADC group regular end of unitary conversion /
		342	#define LL_ADC_IT_EOS ADC_IER_EOSIE /!< ADC interruption ADC group regular end of sequence conversions /
		343	#define LL_ADC_IT_OVR ADC_IER_OVRIE /!< ADC interruption ADC group regular overrun /
		344	#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC interruption ADC group regular end of sampling phase /
		345	#define LL_ADC_IT_AWD1 ADC_IER_AWDIE /!< ADC interruption ADC analog watchdog 1 /
		346	/**
		347	* @}
		348	*/
		349
		350	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
		351	* @{
		352	*/
		353	/* List of ADC registers intended to be used (most commonly) with */
		354	/* DMA transfer. */
		355	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
		356	#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
		357	/**
		358	* @}
		359	*/
		360
		361	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
		362	* @{
		363	*/
		364	/* Note: Other measurement paths to internal channels may be available */
		365	/* (connections to other peripherals). */
		366	/* If they are not listed below, they do not require any specific */
		367	/* path enable. In this case, Access to measurement path is done */
		368	/* only by selecting the corresponding ADC internal channel. */
		369	#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/!< ADC measurement pathes all disabled /
		370	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /!< ADC measurement path to internal channel VrefInt /
		371	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /!< ADC measurement path to internal channel temperature sensor /
		372	#if defined(ADC_CCR_VBATEN)
		373	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /!< ADC measurement path to internal channel Vbat /
		374	#endif
		375	/**
		376	* @}
		377	*/
		378
		379	/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
		380	* @{
		381	*/
		382	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /!< ADC synchronous clock derived from AHB clock divided by 4 /
		383	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /!< ADC synchronous clock derived from AHB clock divided by 2 /
		384	#define LL_ADC_CLOCK_ASYNC (0x00000000U) /!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. /
		385	/**
		386	* @}
		387	*/
		388
		389	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
		390	* @{
		391	*/
		392	#define LL_ADC_RESOLUTION_12B (0x00000000U) /!< ADC resolution 12 bits /
		393	#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /!< ADC resolution 10 bits /
		394	#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /!< ADC resolution 8 bits /
		395	#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 \| ADC_CFGR1_RES_0) /!< ADC resolution 6 bits /
		396	/**
		397	* @}
		398	*/
		399
		400	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
		401	* @{
		402	*/
		403	#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
		404	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
		405	/**
		406	* @}
		407	*/
		408
		409	/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
		410	* @{
		411	*/
		412	#define LL_ADC_LP_MODE_NONE (0x00000000U) /!< No ADC low power mode activated /
		413	#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). /
		414	#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. /
		415	#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF) /!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). /
		416	/**
		417	* @}
		418	*/
		419
		420	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
		421	* @{
		422	*/
		423	#define LL_ADC_GROUP_REGULAR (0x00000001U) /!< ADC group regular (available on all STM32 devices) /
		424	/**
		425	* @}
		426	*/
		427
		428	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
		429	* @{
		430	*/
		431	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
		432	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
		433	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
		434	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
		435	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
		436	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
		437	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
		438	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
		439	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
		440	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
		441	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
		442	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
		443	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
		444	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
		445	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
		446	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
		447	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
		448	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
		449	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. /
		450	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. /
		451	#if defined(ADC_CCR_VBATEN)
		452	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
		453	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. /
		454	#endif
		455	/**
		456	* @}
		457	*/
		458
		459	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
		460	* @{
		461	*/
		462	#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
		463	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
		464	#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
		465	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
		466	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 \| ADC_CFGR1_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
		467	#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). /
		468	/**
		469	* @}
		470	*/
		471
		472	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
		473	* @{
		474	*/
		475	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
		476	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
		477	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 \| ADC_CFGR1_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
		478	/**
		479	* @}
		480	*/
		481
		482	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
		483	* @{
		484	*/
		485	#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
		486	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
		487	/**
		488	* @}
		489	*/
		490
		491	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
		492	* @{
		493	*/
		494	#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /!< ADC conversions are not transferred by DMA /
		495	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
		496	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
		497	/**
		498	* @}
		499	*/
		500
		501	/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
		502	* @{
		503	*/
		504	#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U)/!< ADC group regular behavior in case of overrun: data preserved /
		505	#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /!< ADC group regular behavior in case of overrun: data overwritten /
		506	/**
		507	* @}
		508	*/
		509
		510	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
		511	* @{
		512	*/
		513	#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U)/!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. /
		514	#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) /
		515	/**
		516	* @}
		517	*/
		518
		519	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
		520	* @{
		521	*/
		522	#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
		523	#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
		524	/**
		525	* @}
		526	*/
		527
		528	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
		529	* @{
		530	*/
		531	#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /!< Sampling time 1.5 ADC clock cycle /
		532	#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /!< Sampling time 7.5 ADC clock cycles /
		533	#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /!< Sampling time 13.5 ADC clock cycles /
		534	#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 \| ADC_SMPR_SMP_0) /!< Sampling time 28.5 ADC clock cycles /
		535	#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2) /!< Sampling time 41.5 ADC clock cycles /
		536	#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_0) /!< Sampling time 55.5 ADC clock cycles /
		537	#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_1) /!< Sampling time 71.5 ADC clock cycles /
		538	#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_1 \| ADC_SMPR_SMP_0) /!< Sampling time 239.5 ADC clock cycles /
		539	/**
		540	* @}
		541	*/
		542
		543	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
		544	* @{
		545	*/
		546	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
		547	/**
		548	* @}
		549	*/
		550
		551	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
		552	* @{
		553	*/
		554	#define LL_ADC_AWD_DISABLE (0x00000000U) /!< ADC analog watchdog monitoring disabled /
		555	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
		556	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
		557	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
		558	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
		559	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
		560	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
		561	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
		562	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
		563	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
		564	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
		565	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
		566	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
		567	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
		568	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
		569	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
		570	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
		571	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
		572	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
		573	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
		574	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
		575	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only /
		576	#if defined(ADC_CCR_VBATEN)
		577	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
		578	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
		579	#endif
		580	/**
		581	* @}
		582	*/
		583
		584	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
		585	* @{
		586	*/
		587	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /!< ADC analog watchdog threshold high /
		588	#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /!< ADC analog watchdog threshold low /
		589	#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT \| ADC_TR_LT) /!< ADC analog watchdog both thresholds high and low concatenated into the same data /
		590	/**
		591	* @}
		592	*/
		593
		594
		595	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
		596	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
		597	* not timeout values.
		598	* For details on delays values, refer to descriptions in source code
		599	* above each literal definition.
		600	* @{
		601	*/
		602
		603	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
		604	/* not timeout values. */
		605	/* Timeout values for ADC operations are dependent to device clock */
		606	/* configuration (system clock versus ADC clock), */
		607	/* and therefore must be defined in user application. */
		608	/* Indications for estimation of ADC timeout delays, for this */
		609	/* STM32 serie: */
		610	/* - ADC calibration time: maximum delay is 83/fADC. */
		611	/* (refer to device datasheet, parameter "tCAL") */
		612	/* - ADC enable time: maximum delay is 1 conversion cycle. */
		613	/* (refer to device datasheet, parameter "tSTAB") */
		614	/* - ADC disable time: maximum delay should be a few ADC clock cycles */
		615	/* - ADC stop conversion time: maximum delay should be a few ADC clock */
		616	/* cycles */
		617	/* - ADC conversion time: duration depending on ADC clock and ADC */
		618	/* configuration. */
		619	/* (refer to device reference manual, section "Timing") */
		620
		621
		622	/* Delay for internal voltage reference stabilization time. */
		623	/* Delay set to maximum value (refer to device datasheet, */
		624	/* parameter "tSTART"). */
		625	/* Unit: us */
		626	#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /!< Delay for internal voltage reference stabilization time /
		627
		628	/* Delay for temperature sensor stabilization time. */
		629	/* Literal set to maximum value (refer to device datasheet, */
		630	/* parameter "tSTART"). */
		631	/* Unit: us */
		632	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /!< Delay for temperature sensor stabilization time /
		633
		634	/* Delay required between ADC end of calibration and ADC enable. */
		635	/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
		636	/* are required between ADC end of calibration and ADC enable. */
		637	/* Wait time can be computed in user application by waiting for the */
		638	/* equivalent number of CPU cycles, by taking into account */
		639	/* ratio of CPU clock versus ADC clock prescalers. */
		640	/* Unit: ADC clock cycles. */
		641	#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2U) /!< Delay required between ADC end of calibration and ADC enable /
		642
		643	/**
		644	* @}
		645	*/
		646
		647	/**
		648	* @}
		649	*/
		650
		651
		652	/* Exported macro ------------------------------------------------------------*/
		653	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
		654	* @{
		655	*/
		656
		657	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
		658	* @{
		659	*/
		660
		661	/**
		662	* @brief Write a value in ADC register
		663	* @param __INSTANCE__ ADC Instance
		664	* @param __REG__ Register to be written
		665	* @param __VALUE__ Value to be written in the register
		666	* @retval None
		667	*/
		668	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
		669
		670	/**
		671	* @brief Read a value in ADC register
		672	* @param __INSTANCE__ ADC Instance
		673	* @param __REG__ Register to be read
		674	* @retval Register value
		675	*/
		676	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
		677	/**
		678	* @}
		679	*/
		680
		681	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
		682	* @{
		683	*/
		684
		685	/**
		686	* @brief Helper macro to get ADC channel number in decimal format
		687	* from literals LL_ADC_CHANNEL_x.
		688	* @note Example:
		689	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
		690	* will return decimal number "4".
		691	* @note The input can be a value from functions where a channel
		692	* number is returned, either defined with number
		693	* or with bitfield (only one bit must be set).
		694	* @param __CHANNEL__ This parameter can be one of the following values:
		695	* @arg @ref LL_ADC_CHANNEL_0
		696	* @arg @ref LL_ADC_CHANNEL_1
		697	* @arg @ref LL_ADC_CHANNEL_2
		698	* @arg @ref LL_ADC_CHANNEL_3
		699	* @arg @ref LL_ADC_CHANNEL_4
		700	* @arg @ref LL_ADC_CHANNEL_5
		701	* @arg @ref LL_ADC_CHANNEL_6
		702	* @arg @ref LL_ADC_CHANNEL_7
		703	* @arg @ref LL_ADC_CHANNEL_8
		704	* @arg @ref LL_ADC_CHANNEL_9
		705	* @arg @ref LL_ADC_CHANNEL_10
		706	* @arg @ref LL_ADC_CHANNEL_11
		707	* @arg @ref LL_ADC_CHANNEL_12
		708	* @arg @ref LL_ADC_CHANNEL_13
		709	* @arg @ref LL_ADC_CHANNEL_14
		710	* @arg @ref LL_ADC_CHANNEL_15
		711	* @arg @ref LL_ADC_CHANNEL_16
		712	* @arg @ref LL_ADC_CHANNEL_17
		713	* @arg @ref LL_ADC_CHANNEL_18 (1)
		714	* @arg @ref LL_ADC_CHANNEL_VREFINT
		715	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		716	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		717	*
		718	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		719	* @retval Value between Min_Data=0 and Max_Data=18
		720	*/
		721	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
		722	((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
		723	? ( \
		724	((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
		725	) \
		726	: \
		727	( \
		728	(((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
		729	( \
		730	(((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
		731	( \
		732	(((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
		733	( \
		734	(((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
		735	( \
		736	(((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
		737	( \
		738	(((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
		739	( \
		740	(((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
		741	( \
		742	(((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
		743	( \
		744	(((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
		745	( \
		746	(((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
		747	( \
		748	(((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
		749	( \
		750	(((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
		751	( \
		752	(((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
		753	( \
		754	(((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
		755	( \
		756	(((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
		757	( \
		758	(((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
		759	( \
		760	(((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) : \
		761	( \
		762	(((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
		763	( \
		764	(((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
		765	(0U) \
		766	) \
		767	) \
		768	) \
		769	) \
		770	) \
		771	) \
		772	) \
		773	) \
		774	) \
		775	) \
		776	) \
		777	) \
		778	) \
		779	) \
		780	) \
		781	) \
		782	) \
		783	) \
		784	) \
		785	)
		786
		787	/**
		788	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
		789	* from number in decimal format.
		790	* @note Example:
		791	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
		792	* will return a data equivalent to "LL_ADC_CHANNEL_4".
		793	* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
		794	* @retval Returned value can be one of the following values:
		795	* @arg @ref LL_ADC_CHANNEL_0
		796	* @arg @ref LL_ADC_CHANNEL_1
		797	* @arg @ref LL_ADC_CHANNEL_2
		798	* @arg @ref LL_ADC_CHANNEL_3
		799	* @arg @ref LL_ADC_CHANNEL_4
		800	* @arg @ref LL_ADC_CHANNEL_5
		801	* @arg @ref LL_ADC_CHANNEL_6
		802	* @arg @ref LL_ADC_CHANNEL_7
		803	* @arg @ref LL_ADC_CHANNEL_8
		804	* @arg @ref LL_ADC_CHANNEL_9
		805	* @arg @ref LL_ADC_CHANNEL_10
		806	* @arg @ref LL_ADC_CHANNEL_11
		807	* @arg @ref LL_ADC_CHANNEL_12
		808	* @arg @ref LL_ADC_CHANNEL_13
		809	* @arg @ref LL_ADC_CHANNEL_14
		810	* @arg @ref LL_ADC_CHANNEL_15
		811	* @arg @ref LL_ADC_CHANNEL_16
		812	* @arg @ref LL_ADC_CHANNEL_17
		813	* @arg @ref LL_ADC_CHANNEL_18 (1)
		814	* @arg @ref LL_ADC_CHANNEL_VREFINT (2)
		815	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
		816	* @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
		817	*
		818	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
		819	* (2) For ADC channel read back from ADC register,
		820	* comparison with internal channel parameter to be done
		821	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
		822	*/
		823	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
		824	( \
		825	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
		826	(ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
		827	)
		828
		829	/**
		830	* @brief Helper macro to determine whether the selected channel
		831	* corresponds to literal definitions of driver.
		832	* @note The different literal definitions of ADC channels are:
		833	* - ADC internal channel:
		834	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
		835	* - ADC external channel (channel connected to a GPIO pin):
		836	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
		837	* @note The channel parameter must be a value defined from literal
		838	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
		839	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
		840	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
		841	* must not be a value from functions where a channel number is
		842	* returned from ADC registers,
		843	* because internal and external channels share the same channel
		844	* number in ADC registers. The differentiation is made only with
		845	* parameters definitions of driver.
		846	* @param __CHANNEL__ This parameter can be one of the following values:
		847	* @arg @ref LL_ADC_CHANNEL_0
		848	* @arg @ref LL_ADC_CHANNEL_1
		849	* @arg @ref LL_ADC_CHANNEL_2
		850	* @arg @ref LL_ADC_CHANNEL_3
		851	* @arg @ref LL_ADC_CHANNEL_4
		852	* @arg @ref LL_ADC_CHANNEL_5
		853	* @arg @ref LL_ADC_CHANNEL_6
		854	* @arg @ref LL_ADC_CHANNEL_7
		855	* @arg @ref LL_ADC_CHANNEL_8
		856	* @arg @ref LL_ADC_CHANNEL_9
		857	* @arg @ref LL_ADC_CHANNEL_10
		858	* @arg @ref LL_ADC_CHANNEL_11
		859	* @arg @ref LL_ADC_CHANNEL_12
		860	* @arg @ref LL_ADC_CHANNEL_13
		861	* @arg @ref LL_ADC_CHANNEL_14
		862	* @arg @ref LL_ADC_CHANNEL_15
		863	* @arg @ref LL_ADC_CHANNEL_16
		864	* @arg @ref LL_ADC_CHANNEL_17
		865	* @arg @ref LL_ADC_CHANNEL_18 (1)
		866	* @arg @ref LL_ADC_CHANNEL_VREFINT
		867	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		868	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		869	*
		870	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		871	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
		872	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
		873	*/
		874	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
		875	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
		876
		877	/**
		878	* @brief Helper macro to convert a channel defined from parameter
		879	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
		880	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
		881	* to its equivalent parameter definition of a ADC external channel
		882	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
		883	* @note The channel parameter can be, additionally to a value
		884	* defined from parameter definition of a ADC internal channel
		885	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
		886	* a value defined from parameter definition of
		887	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
		888	* or a value from functions where a channel number is returned
		889	* from ADC registers.
		890	* @param __CHANNEL__ This parameter can be one of the following values:
		891	* @arg @ref LL_ADC_CHANNEL_0
		892	* @arg @ref LL_ADC_CHANNEL_1
		893	* @arg @ref LL_ADC_CHANNEL_2
		894	* @arg @ref LL_ADC_CHANNEL_3
		895	* @arg @ref LL_ADC_CHANNEL_4
		896	* @arg @ref LL_ADC_CHANNEL_5
		897	* @arg @ref LL_ADC_CHANNEL_6
		898	* @arg @ref LL_ADC_CHANNEL_7
		899	* @arg @ref LL_ADC_CHANNEL_8
		900	* @arg @ref LL_ADC_CHANNEL_9
		901	* @arg @ref LL_ADC_CHANNEL_10
		902	* @arg @ref LL_ADC_CHANNEL_11
		903	* @arg @ref LL_ADC_CHANNEL_12
		904	* @arg @ref LL_ADC_CHANNEL_13
		905	* @arg @ref LL_ADC_CHANNEL_14
		906	* @arg @ref LL_ADC_CHANNEL_15
		907	* @arg @ref LL_ADC_CHANNEL_16
		908	* @arg @ref LL_ADC_CHANNEL_17
		909	* @arg @ref LL_ADC_CHANNEL_18 (1)
		910	* @arg @ref LL_ADC_CHANNEL_VREFINT
		911	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		912	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		913	*
		914	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		915	* @retval Returned value can be one of the following values:
		916	* @arg @ref LL_ADC_CHANNEL_0
		917	* @arg @ref LL_ADC_CHANNEL_1
		918	* @arg @ref LL_ADC_CHANNEL_2
		919	* @arg @ref LL_ADC_CHANNEL_3
		920	* @arg @ref LL_ADC_CHANNEL_4
		921	* @arg @ref LL_ADC_CHANNEL_5
		922	* @arg @ref LL_ADC_CHANNEL_6
		923	* @arg @ref LL_ADC_CHANNEL_7
		924	* @arg @ref LL_ADC_CHANNEL_8
		925	* @arg @ref LL_ADC_CHANNEL_9
		926	* @arg @ref LL_ADC_CHANNEL_10
		927	* @arg @ref LL_ADC_CHANNEL_11
		928	* @arg @ref LL_ADC_CHANNEL_12
		929	* @arg @ref LL_ADC_CHANNEL_13
		930	* @arg @ref LL_ADC_CHANNEL_14
		931	* @arg @ref LL_ADC_CHANNEL_15
		932	* @arg @ref LL_ADC_CHANNEL_16
		933	* @arg @ref LL_ADC_CHANNEL_17
		934	* @arg @ref LL_ADC_CHANNEL_18
		935	*/
		936	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
		937	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
		938
		939	/**
		940	* @brief Helper macro to determine whether the internal channel
		941	* selected is available on the ADC instance selected.
		942	* @note The channel parameter must be a value defined from parameter
		943	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
		944	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
		945	* must not be a value defined from parameter definition of
		946	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
		947	* or a value from functions where a channel number is
		948	* returned from ADC registers,
		949	* because internal and external channels share the same channel
		950	* number in ADC registers. The differentiation is made only with
		951	* parameters definitions of driver.
		952	* @param __ADC_INSTANCE__ ADC instance
		953	* @param __CHANNEL__ This parameter can be one of the following values:
		954	* @arg @ref LL_ADC_CHANNEL_VREFINT
		955	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		956	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		957	*
		958	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		959	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
		960	* Value "1" if the internal channel selected is available on the ADC instance selected.
		961	*/
		962	#if defined(ADC_CCR_VBATEN)
		963	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
		964	( \
		965	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
		966	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
		967	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
		968	)
		969	#else
		970	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
		971	( \
		972	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
		973	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
		974	)
		975	#endif
		976
		977	/**
		978	* @brief Helper macro to define ADC analog watchdog parameter:
		979	* define a single channel to monitor with analog watchdog
		980	* from sequencer channel and groups definition.
		981	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
		982	* Example:
		983	* LL_ADC_SetAnalogWDMonitChannels(
		984	* ADC1, LL_ADC_AWD1,
		985	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
		986	* @param __CHANNEL__ This parameter can be one of the following values:
		987	* @arg @ref LL_ADC_CHANNEL_0
		988	* @arg @ref LL_ADC_CHANNEL_1
		989	* @arg @ref LL_ADC_CHANNEL_2
		990	* @arg @ref LL_ADC_CHANNEL_3
		991	* @arg @ref LL_ADC_CHANNEL_4
		992	* @arg @ref LL_ADC_CHANNEL_5
		993	* @arg @ref LL_ADC_CHANNEL_6
		994	* @arg @ref LL_ADC_CHANNEL_7
		995	* @arg @ref LL_ADC_CHANNEL_8
		996	* @arg @ref LL_ADC_CHANNEL_9
		997	* @arg @ref LL_ADC_CHANNEL_10
		998	* @arg @ref LL_ADC_CHANNEL_11
		999	* @arg @ref LL_ADC_CHANNEL_12
		1000	* @arg @ref LL_ADC_CHANNEL_13
		1001	* @arg @ref LL_ADC_CHANNEL_14
		1002	* @arg @ref LL_ADC_CHANNEL_15
		1003	* @arg @ref LL_ADC_CHANNEL_16
		1004	* @arg @ref LL_ADC_CHANNEL_17
		1005	* @arg @ref LL_ADC_CHANNEL_18 (1)
		1006	* @arg @ref LL_ADC_CHANNEL_VREFINT (2)
		1007	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
		1008	* @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
		1009	*
		1010	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
		1011	* (2) For ADC channel read back from ADC register,
		1012	* comparison with internal channel parameter to be done
		1013	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
		1014	* @param __GROUP__ This parameter can be one of the following values:
		1015	* @arg @ref LL_ADC_GROUP_REGULAR
		1016	* @retval Returned value can be one of the following values:
		1017	* @arg @ref LL_ADC_AWD_DISABLE
		1018	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
		1019	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
		1020	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
		1021	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
		1022	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
		1023	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
		1024	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
		1025	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
		1026	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
		1027	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
		1028	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
		1029	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
		1030	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
		1031	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
		1032	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
		1033	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
		1034	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
		1035	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
		1036	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
		1037	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
		1038	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG
		1039	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
		1040	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
		1041	*
		1042	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		1043	*/
		1044	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
		1045	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL)
		1046
		1047	/**
		1048	* @brief Helper macro to set the value of ADC analog watchdog threshold high
		1049	* or low in function of ADC resolution, when ADC resolution is
		1050	* different of 12 bits.
		1051	* @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
		1052	* or @ref LL_ADC_SetAnalogWDThresholds().
		1053	* Example, with a ADC resolution of 8 bits, to set the value of
		1054	* analog watchdog threshold high (on 8 bits):
		1055	* LL_ADC_SetAnalogWDThresholds
		1056	* (< ADCx param >,
		1057	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
		1058	* );
		1059	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1060	* @arg @ref LL_ADC_RESOLUTION_12B
		1061	* @arg @ref LL_ADC_RESOLUTION_10B
		1062	* @arg @ref LL_ADC_RESOLUTION_8B
		1063	* @arg @ref LL_ADC_RESOLUTION_6B
		1064	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
		1065	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		1066	*/
		1067	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
		1068	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
		1069
		1070	/**
		1071	* @brief Helper macro to get the value of ADC analog watchdog threshold high
		1072	* or low in function of ADC resolution, when ADC resolution is
		1073	* different of 12 bits.
		1074	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
		1075	* Example, with a ADC resolution of 8 bits, to get the value of
		1076	* analog watchdog threshold high (on 8 bits):
		1077	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
		1078	* (LL_ADC_RESOLUTION_8B,
		1079	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
		1080	* );
		1081	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1082	* @arg @ref LL_ADC_RESOLUTION_12B
		1083	* @arg @ref LL_ADC_RESOLUTION_10B
		1084	* @arg @ref LL_ADC_RESOLUTION_8B
		1085	* @arg @ref LL_ADC_RESOLUTION_6B
		1086	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
		1087	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		1088	*/
		1089	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
		1090	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
		1091
		1092	/**
		1093	* @brief Helper macro to get the ADC analog watchdog threshold high
		1094	* or low from raw value containing both thresholds concatenated.
		1095	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
		1096	* Example, to get analog watchdog threshold high from the register raw value:
		1097	* __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
		1098	* @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
		1099	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
		1100	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
		1101	* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
		1102	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		1103	*/
		1104	#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
		1105	(((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \
		1106	? ( \
		1107	(__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \
		1108	) \
		1109	: \
		1110	( \
		1111	((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \
		1112	) \
		1113	)
		1114
		1115	/**
		1116	* @brief Helper macro to select the ADC common instance
		1117	* to which is belonging the selected ADC instance.
		1118	* @note ADC common register instance can be used for:
		1119	* - Set parameters common to several ADC instances
		1120	* - Multimode (for devices with several ADC instances)
		1121	* Refer to functions having argument "ADCxy_COMMON" as parameter.
		1122	* @param __ADCx__ ADC instance
		1123	* @retval ADC common register instance
		1124	*/
		1125	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
		1126	(ADC1_COMMON)
		1127
		1128	/**
		1129	* @brief Helper macro to check if all ADC instances sharing the same
		1130	* ADC common instance are disabled.
		1131	* @note This check is required by functions with setting conditioned to
		1132	* ADC state:
		1133	* All ADC instances of the ADC common group must be disabled.
		1134	* Refer to functions having argument "ADCxy_COMMON" as parameter.
		1135	* @note On devices with only 1 ADC common instance, parameter of this macro
		1136	* is useless and can be ignored (parameter kept for compatibility
		1137	* with devices featuring several ADC common instances).
		1138	* @param __ADCXY_COMMON__ ADC common instance
		1139	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		1140	* @retval Value "0" if all ADC instances sharing the same ADC common instance
		1141	* are disabled.
		1142	* Value "1" if at least one ADC instance sharing the same ADC common instance
		1143	* is enabled.
		1144	*/
		1145	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
		1146	LL_ADC_IsEnabled(ADC1)
		1147
		1148	/**
		1149	* @brief Helper macro to define the ADC conversion data full-scale digital
		1150	* value corresponding to the selected ADC resolution.
		1151	* @note ADC conversion data full-scale corresponds to voltage range
		1152	* determined by analog voltage references Vref+ and Vref-
		1153	* (refer to reference manual).
		1154	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1155	* @arg @ref LL_ADC_RESOLUTION_12B
		1156	* @arg @ref LL_ADC_RESOLUTION_10B
		1157	* @arg @ref LL_ADC_RESOLUTION_8B
		1158	* @arg @ref LL_ADC_RESOLUTION_6B
		1159	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
		1160	*/
		1161	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
		1162	(0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
		1163
		1164	/**
		1165	* @brief Helper macro to convert the ADC conversion data from
		1166	* a resolution to another resolution.
		1167	* @param __DATA__ ADC conversion data to be converted
		1168	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
		1169	* This parameter can be one of the following values:
		1170	* @arg @ref LL_ADC_RESOLUTION_12B
		1171	* @arg @ref LL_ADC_RESOLUTION_10B
		1172	* @arg @ref LL_ADC_RESOLUTION_8B
		1173	* @arg @ref LL_ADC_RESOLUTION_6B
		1174	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
		1175	* This parameter can be one of the following values:
		1176	* @arg @ref LL_ADC_RESOLUTION_12B
		1177	* @arg @ref LL_ADC_RESOLUTION_10B
		1178	* @arg @ref LL_ADC_RESOLUTION_8B
		1179	* @arg @ref LL_ADC_RESOLUTION_6B
		1180	* @retval ADC conversion data to the requested resolution
		1181	*/
		1182	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
		1183	(((__DATA__) \
		1184	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \
		1185	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \
		1186	)
		1187
		1188	/**
		1189	* @brief Helper macro to calculate the voltage (unit: mVolt)
		1190	* corresponding to a ADC conversion data (unit: digital value).
		1191	* @note Analog reference voltage (Vref+) must be either known from
		1192	* user board environment or can be calculated using ADC measurement
		1193	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
		1194	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
		1195	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
		1196	* (unit: digital value).
		1197	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1198	* @arg @ref LL_ADC_RESOLUTION_12B
		1199	* @arg @ref LL_ADC_RESOLUTION_10B
		1200	* @arg @ref LL_ADC_RESOLUTION_8B
		1201	* @arg @ref LL_ADC_RESOLUTION_6B
		1202	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
		1203	*/
		1204	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
		1205	__ADC_DATA__,\
		1206	__ADC_RESOLUTION__) \
		1207	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
		1208	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
		1209	)
		1210
		1211	/**
		1212	* @brief Helper macro to calculate analog reference voltage (Vref+)
		1213	* (unit: mVolt) from ADC conversion data of internal voltage
		1214	* reference VrefInt.
		1215	* @note Computation is using VrefInt calibration value
		1216	* stored in system memory for each device during production.
		1217	* @note This voltage depends on user board environment: voltage level
		1218	* connected to pin Vref+.
		1219	* On devices with small package, the pin Vref+ is not present
		1220	* and internally bonded to pin Vdda.
		1221	* @note On this STM32 serie, calibration data of internal voltage reference
		1222	* VrefInt corresponds to a resolution of 12 bits,
		1223	* this is the recommended ADC resolution to convert voltage of
		1224	* internal voltage reference VrefInt.
		1225	* Otherwise, this macro performs the processing to scale
		1226	* ADC conversion data to 12 bits.
		1227	* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
		1228	* of internal voltage reference VrefInt (unit: digital value).
		1229	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
		1230	* @arg @ref LL_ADC_RESOLUTION_12B
		1231	* @arg @ref LL_ADC_RESOLUTION_10B
		1232	* @arg @ref LL_ADC_RESOLUTION_8B
		1233	* @arg @ref LL_ADC_RESOLUTION_6B
		1234	* @retval Analog reference voltage (unit: mV)
		1235	*/
		1236	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
		1237	__ADC_RESOLUTION__) \
		1238	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
		1239	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
		1240	(__ADC_RESOLUTION__), \
		1241	LL_ADC_RESOLUTION_12B) \
		1242	)
		1243
		1244	/**
		1245	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
		1246	* from ADC conversion data of internal temperature sensor.
		1247	* @note Computation is using temperature sensor calibration values
		1248	* stored in system memory for each device during production.
		1249	* @note Calculation formula:
		1250	* Temperature = ((TS_ADC_DATA - TS_CAL1)
		1251	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
		1252	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
		1253	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
		1254	* Avg_Slope = (TS_CAL2 - TS_CAL1)
		1255	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
		1256	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
		1257	* TEMP_DEGC_CAL1 (calibrated in factory)
		1258	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
		1259	* TEMP_DEGC_CAL2 (calibrated in factory)
		1260	* Caution: Calculation relevancy under reserve that calibration
		1261	* parameters are correct (address and data).
		1262	* To calculate temperature using temperature sensor
		1263	* datasheet typical values (generic values less, therefore
		1264	* less accurate than calibrated values),
		1265	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
		1266	* @note As calculation input, the analog reference voltage (Vref+) must be
		1267	* defined as it impacts the ADC LSB equivalent voltage.
		1268	* @note Analog reference voltage (Vref+) must be either known from
		1269	* user board environment or can be calculated using ADC measurement
		1270	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
		1271	* @note On this STM32 serie, calibration data of temperature sensor
		1272	* corresponds to a resolution of 12 bits,
		1273	* this is the recommended ADC resolution to convert voltage of
		1274	* temperature sensor.
		1275	* Otherwise, this macro performs the processing to scale
		1276	* ADC conversion data to 12 bits.
		1277	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
		1278	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
		1279	* temperature sensor (unit: digital value).
		1280	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
		1281	* sensor voltage has been measured.
		1282	* This parameter can be one of the following values:
		1283	* @arg @ref LL_ADC_RESOLUTION_12B
		1284	* @arg @ref LL_ADC_RESOLUTION_10B
		1285	* @arg @ref LL_ADC_RESOLUTION_8B
		1286	* @arg @ref LL_ADC_RESOLUTION_6B
		1287	* @retval Temperature (unit: degree Celsius)
		1288	*/
		1289	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
		1290	__TEMPSENSOR_ADC_DATA__,\
		1291	__ADC_RESOLUTION__) \
		1292	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
		1293	(__ADC_RESOLUTION__), \
		1294	LL_ADC_RESOLUTION_12B) \
		1295	* (__VREFANALOG_VOLTAGE__)) \
		1296	/ TEMPSENSOR_CAL_VREFANALOG) \
		1297	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
		1298	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
		1299	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
		1300	) + TEMPSENSOR_CAL1_TEMP \
		1301	)
		1302
		1303	/**
		1304	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
		1305	* from ADC conversion data of internal temperature sensor.
		1306	* @note Computation is using temperature sensor typical values
		1307	* (refer to device datasheet).
		1308	* @note Calculation formula:
		1309	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
		1310	* / Avg_Slope + CALx_TEMP
		1311	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
		1312	* (unit: digital value)
		1313	* Avg_Slope = temperature sensor slope
		1314	* (unit: uV/Degree Celsius)
		1315	* TS_TYP_CALx_VOLT = temperature sensor digital value at
		1316	* temperature CALx_TEMP (unit: mV)
		1317	* Caution: Calculation relevancy under reserve the temperature sensor
		1318	* of the current device has characteristics in line with
		1319	* datasheet typical values.
		1320	* If temperature sensor calibration values are available on
		1321	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
		1322	* temperature calculation will be more accurate using
		1323	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
		1324	* @note As calculation input, the analog reference voltage (Vref+) must be
		1325	* defined as it impacts the ADC LSB equivalent voltage.
		1326	* @note Analog reference voltage (Vref+) must be either known from
		1327	* user board environment or can be calculated using ADC measurement
		1328	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
		1329	* @note ADC measurement data must correspond to a resolution of 12bits
		1330	* (full scale digital value 4095). If not the case, the data must be
		1331	* preliminarily rescaled to an equivalent resolution of 12 bits.
		1332	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
		1333	* On STM32F0, refer to device datasheet parameter "Avg_Slope".
		1334	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
		1335	* On STM32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
		1336	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
		1337	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
		1338	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
		1339	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
		1340	* This parameter can be one of the following values:
		1341	* @arg @ref LL_ADC_RESOLUTION_12B
		1342	* @arg @ref LL_ADC_RESOLUTION_10B
		1343	* @arg @ref LL_ADC_RESOLUTION_8B
		1344	* @arg @ref LL_ADC_RESOLUTION_6B
		1345	* @retval Temperature (unit: degree Celsius)
		1346	*/
		1347	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
		1348	__TEMPSENSOR_TYP_CALX_V__,\
		1349	__TEMPSENSOR_CALX_TEMP__,\
		1350	__VREFANALOG_VOLTAGE__,\
		1351	__TEMPSENSOR_ADC_DATA__,\
		1352	__ADC_RESOLUTION__) \
		1353	((( ( \
		1354	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
		1355	* 1000) \
		1356	- \
		1357	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
		1358	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
		1359	* 1000) \
		1360	) \
		1361	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
		1362	) + (__TEMPSENSOR_CALX_TEMP__) \
		1363	)
		1364
		1365	/**
		1366	* @}
		1367	*/
		1368
		1369	/**
		1370	* @}
		1371	*/
		1372
		1373
		1374	/* Exported functions --------------------------------------------------------*/
		1375	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
		1376	* @{
		1377	*/
		1378
		1379	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
		1380	* @{
		1381	*/
		1382	/* Note: LL ADC functions to set DMA transfer are located into sections of */
		1383	/* configuration of ADC instance, groups and multimode (if available): */
		1384	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
		1385
		1386	/**
		1387	* @brief Function to help to configure DMA transfer from ADC: retrieve the
		1388	* ADC register address from ADC instance and a list of ADC registers
		1389	* intended to be used (most commonly) with DMA transfer.
		1390	* @note These ADC registers are data registers:
		1391	* when ADC conversion data is available in ADC data registers,
		1392	* ADC generates a DMA transfer request.
		1393	* @note This macro is intended to be used with LL DMA driver, refer to
		1394	* function "LL_DMA_ConfigAddresses()".
		1395	* Example:
		1396	* LL_DMA_ConfigAddresses(DMA1,
		1397	* LL_DMA_CHANNEL_1,
		1398	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
		1399	* (uint32_t)&< array or variable >,
		1400	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
		1401	* @note For devices with several ADC: in multimode, some devices
		1402	* use a different data register outside of ADC instance scope
		1403	* (common data register). This macro manages this register difference,
		1404	* only ADC instance has to be set as parameter.
		1405	* @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
		1406	* @param ADCx ADC instance
		1407	* @param Register This parameter can be one of the following values:
		1408	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
		1409	* @retval ADC register address
		1410	*/
		1411	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
		1412	{
		1413	/* Retrieve address of register DR */
		1414	return (uint32_t)&(ADCx->DR);
		1415	}
		1416
		1417	/**
		1418	* @}
		1419	*/
		1420
		1421	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
		1422	* @{
		1423	*/
		1424
		1425	/**
		1426	* @brief Set parameter common to several ADC: measurement path to internal
		1427	* channels (VrefInt, temperature sensor, ...).
		1428	* @note One or several values can be selected.
		1429	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
		1430	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
		1431	* @note Stabilization time of measurement path to internal channel:
		1432	* After enabling internal paths, before starting ADC conversion,
		1433	* a delay is required for internal voltage reference and
		1434	* temperature sensor stabilization time.
		1435	* Refer to device datasheet.
		1436	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
		1437	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
		1438	* @note ADC internal channel sampling time constraint:
		1439	* For ADC conversion of internal channels,
		1440	* a sampling time minimum value is required.
		1441	* Refer to device datasheet.
		1442	* @note On this STM32 serie, setting of this feature is conditioned to
		1443	* ADC state:
		1444	* All ADC instances of the ADC common group must be disabled.
		1445	* This check can be done with function @ref LL_ADC_IsEnabled() for each
		1446	* ADC instance or by using helper macro helper macro
		1447	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
		1448	* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
		1449	* CCR TSEN LL_ADC_SetCommonPathInternalCh\n
		1450	* CCR VBATEN LL_ADC_SetCommonPathInternalCh
		1451	* @param ADCxy_COMMON ADC common instance
		1452	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		1453	* @param PathInternal This parameter can be a combination of the following values:
		1454	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
		1455	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
		1456	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
		1457	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
		1458	*
		1459	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		1460	* @retval None
		1461	*/
		1462	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
		1463	{
		1464	#if defined(ADC_CCR_VBATEN)
		1465	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN, PathInternal);
		1466	#else
		1467	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN, PathInternal);
		1468	#endif
		1469	}
		1470
		1471	/**
		1472	* @brief Get parameter common to several ADC: measurement path to internal
		1473	* channels (VrefInt, temperature sensor, ...).
		1474	* @note One or several values can be selected.
		1475	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
		1476	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
		1477	* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
		1478	* CCR TSEN LL_ADC_GetCommonPathInternalCh\n
		1479	* CCR VBATEN LL_ADC_GetCommonPathInternalCh
		1480	* @param ADCxy_COMMON ADC common instance
		1481	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
		1482	* @retval Returned value can be a combination of the following values:
		1483	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
		1484	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
		1485	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
		1486	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
		1487	*
		1488	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		1489	*/
		1490	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
		1491	{
		1492	#if defined(ADC_CCR_VBATEN)
		1493	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN));
		1494	#else
		1495	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN));
		1496	#endif
		1497	}
		1498
		1499	/**
		1500	* @}
		1501	*/
		1502
		1503	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
		1504	* @{
		1505	*/
		1506
		1507	/**
		1508	* @brief Set ADC instance clock source and prescaler.
		1509	* @note On this STM32 serie, setting of this feature is conditioned to
		1510	* ADC state:
		1511	* ADC must be disabled.
		1512	* @rmtoll CFGR2 CKMODE LL_ADC_SetClock
		1513	* @param ADCx ADC instance
		1514	* @param ClockSource This parameter can be one of the following values:
		1515	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
		1516	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
		1517	* @arg @ref LL_ADC_CLOCK_ASYNC (1)
		1518	*
		1519	* (1) On this STM32 serie, synchronous clock has no prescaler.
		1520	* @retval None
		1521	*/
		1522	__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
		1523	{
		1524	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
		1525	}
		1526
		1527	/**
		1528	* @brief Get ADC instance clock source and prescaler.
		1529	* @rmtoll CFGR2 CKMODE LL_ADC_GetClock
		1530	* @param ADCx ADC instance
		1531	* @retval Returned value can be one of the following values:
		1532	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
		1533	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
		1534	* @arg @ref LL_ADC_CLOCK_ASYNC (1)
		1535	*
		1536	* (1) On this STM32 serie, synchronous clock has no prescaler.
		1537	*/
		1538	__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
		1539	{
		1540	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
		1541	}
		1542
		1543	/**
		1544	* @brief Set ADC resolution.
		1545	* Refer to reference manual for alignments formats
		1546	* dependencies to ADC resolutions.
		1547	* @note On this STM32 serie, setting of this feature is conditioned to
		1548	* ADC state:
		1549	* ADC must be disabled or enabled without conversion on going
		1550	* on group regular.
		1551	* @rmtoll CFGR1 RES LL_ADC_SetResolution
		1552	* @param ADCx ADC instance
		1553	* @param Resolution This parameter can be one of the following values:
		1554	* @arg @ref LL_ADC_RESOLUTION_12B
		1555	* @arg @ref LL_ADC_RESOLUTION_10B
		1556	* @arg @ref LL_ADC_RESOLUTION_8B
		1557	* @arg @ref LL_ADC_RESOLUTION_6B
		1558	* @retval None
		1559	*/
		1560	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
		1561	{
		1562	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
		1563	}
		1564
		1565	/**
		1566	* @brief Get ADC resolution.
		1567	* Refer to reference manual for alignments formats
		1568	* dependencies to ADC resolutions.
		1569	* @rmtoll CFGR1 RES LL_ADC_GetResolution
		1570	* @param ADCx ADC instance
		1571	* @retval Returned value can be one of the following values:
		1572	* @arg @ref LL_ADC_RESOLUTION_12B
		1573	* @arg @ref LL_ADC_RESOLUTION_10B
		1574	* @arg @ref LL_ADC_RESOLUTION_8B
		1575	* @arg @ref LL_ADC_RESOLUTION_6B
		1576	*/
		1577	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
		1578	{
		1579	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
		1580	}
		1581
		1582	/**
		1583	* @brief Set ADC conversion data alignment.
		1584	* @note Refer to reference manual for alignments formats
		1585	* dependencies to ADC resolutions.
		1586	* @note On this STM32 serie, setting of this feature is conditioned to
		1587	* ADC state:
		1588	* ADC must be disabled or enabled without conversion on going
		1589	* on group regular.
		1590	* @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
		1591	* @param ADCx ADC instance
		1592	* @param DataAlignment This parameter can be one of the following values:
		1593	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
		1594	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
		1595	* @retval None
		1596	*/
		1597	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
		1598	{
		1599	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
		1600	}
		1601
		1602	/**
		1603	* @brief Get ADC conversion data alignment.
		1604	* @note Refer to reference manual for alignments formats
		1605	* dependencies to ADC resolutions.
		1606	* @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
		1607	* @param ADCx ADC instance
		1608	* @retval Returned value can be one of the following values:
		1609	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
		1610	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
		1611	*/
		1612	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
		1613	{
		1614	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
		1615	}
		1616
		1617	/**
		1618	* @brief Set ADC low power mode.
		1619	* @note Description of ADC low power modes:
		1620	* - ADC low power mode "auto wait": Dynamic low power mode,
		1621	* ADC conversions occurrences are limited to the minimum necessary
		1622	* in order to reduce power consumption.
		1623	* New ADC conversion starts only when the previous
		1624	* unitary conversion data (for ADC group regular)
		1625	* has been retrieved by user software.
		1626	* In the meantime, ADC remains idle: does not performs any
		1627	* other conversion.
		1628	* This mode allows to automatically adapt the ADC conversions
		1629	* triggers to the speed of the software that reads the data.
		1630	* Moreover, this avoids risk of overrun for low frequency
		1631	* applications.
		1632	* How to use this low power mode:
		1633	* - Do not use with interruption or DMA since these modes
		1634	* have to clear immediately the EOC flag to free the
		1635	* IRQ vector sequencer.
		1636	* - Do use with polling: 1. Start conversion,
		1637	* 2. Later on, when conversion data is needed: poll for end of
		1638	* conversion to ensure that conversion is completed and
		1639	* retrieve ADC conversion data. This will trig another
		1640	* ADC conversion start.
		1641	* - ADC low power mode "auto power-off" (feature available on
		1642	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
		1643	* the ADC automatically powers-off after a conversion and
		1644	* automatically wakes up when a new conversion is triggered
		1645	* (with startup time between trigger and start of sampling).
		1646	* This feature can be combined with low power mode "auto wait".
		1647	* @note With ADC low power mode "auto wait", the ADC conversion data read
		1648	* is corresponding to previous ADC conversion start, independently
		1649	* of delay during which ADC was idle.
		1650	* Therefore, the ADC conversion data may be outdated: does not
		1651	* correspond to the current voltage level on the selected
		1652	* ADC channel.
		1653	* @note On this STM32 serie, setting of this feature is conditioned to
		1654	* ADC state:
		1655	* ADC must be disabled or enabled without conversion on going
		1656	* on group regular.
		1657	* @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
		1658	* CFGR1 AUTOFF LL_ADC_SetLowPowerMode
		1659	* @param ADCx ADC instance
		1660	* @param LowPowerMode This parameter can be one of the following values:
		1661	* @arg @ref LL_ADC_LP_MODE_NONE
		1662	* @arg @ref LL_ADC_LP_AUTOWAIT
		1663	* @arg @ref LL_ADC_LP_AUTOPOWEROFF
		1664	* @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
		1665	* @retval None
		1666	*/
		1667	__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
		1668	{
		1669	MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF), LowPowerMode);
		1670	}
		1671
		1672	/**
		1673	* @brief Get ADC low power mode:
		1674	* @note Description of ADC low power modes:
		1675	* - ADC low power mode "auto wait": Dynamic low power mode,
		1676	* ADC conversions occurrences are limited to the minimum necessary
		1677	* in order to reduce power consumption.
		1678	* New ADC conversion starts only when the previous
		1679	* unitary conversion data (for ADC group regular)
		1680	* has been retrieved by user software.
		1681	* In the meantime, ADC remains idle: does not performs any
		1682	* other conversion.
		1683	* This mode allows to automatically adapt the ADC conversions
		1684	* triggers to the speed of the software that reads the data.
		1685	* Moreover, this avoids risk of overrun for low frequency
		1686	* applications.
		1687	* How to use this low power mode:
		1688	* - Do not use with interruption or DMA since these modes
		1689	* have to clear immediately the EOC flag to free the
		1690	* IRQ vector sequencer.
		1691	* - Do use with polling: 1. Start conversion,
		1692	* 2. Later on, when conversion data is needed: poll for end of
		1693	* conversion to ensure that conversion is completed and
		1694	* retrieve ADC conversion data. This will trig another
		1695	* ADC conversion start.
		1696	* - ADC low power mode "auto power-off" (feature available on
		1697	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
		1698	* the ADC automatically powers-off after a conversion and
		1699	* automatically wakes up when a new conversion is triggered
		1700	* (with startup time between trigger and start of sampling).
		1701	* This feature can be combined with low power mode "auto wait".
		1702	* @note With ADC low power mode "auto wait", the ADC conversion data read
		1703	* is corresponding to previous ADC conversion start, independently
		1704	* of delay during which ADC was idle.
		1705	* Therefore, the ADC conversion data may be outdated: does not
		1706	* correspond to the current voltage level on the selected
		1707	* ADC channel.
		1708	* @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
		1709	* CFGR1 AUTOFF LL_ADC_GetLowPowerMode
		1710	* @param ADCx ADC instance
		1711	* @retval Returned value can be one of the following values:
		1712	* @arg @ref LL_ADC_LP_MODE_NONE
		1713	* @arg @ref LL_ADC_LP_AUTOWAIT
		1714	* @arg @ref LL_ADC_LP_AUTOPOWEROFF
		1715	* @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
		1716	*/
		1717	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
		1718	{
		1719	return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF)));
		1720	}
		1721
		1722	/**
		1723	* @brief Set sampling time common to a group of channels.
		1724	* @note Unit: ADC clock cycles.
		1725	* @note On this STM32 serie, sampling time scope is on ADC instance:
		1726	* Sampling time common to all channels.
		1727	* (on some other STM32 families, sampling time is channel wise)
		1728	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
		1729	* converted:
		1730	* sampling time constraints must be respected (sampling time can be
		1731	* adjusted in function of ADC clock frequency and sampling time
		1732	* setting).
		1733	* Refer to device datasheet for timings values (parameters TS_vrefint,
		1734	* TS_temp, ...).
		1735	* @note Conversion time is the addition of sampling time and processing time.
		1736	* On this STM32 serie, ADC processing time is:
		1737	* - 12.5 ADC clock cycles at ADC resolution 12 bits
		1738	* - 10.5 ADC clock cycles at ADC resolution 10 bits
		1739	* - 8.5 ADC clock cycles at ADC resolution 8 bits
		1740	* - 6.5 ADC clock cycles at ADC resolution 6 bits
		1741	* @note In case of ADC conversion of internal channel (VrefInt,
		1742	* temperature sensor, ...), a sampling time minimum value
		1743	* is required.
		1744	* Refer to device datasheet.
		1745	* @note On this STM32 serie, setting of this feature is conditioned to
		1746	* ADC state:
		1747	* ADC must be disabled or enabled without conversion on going
		1748	* on group regular.
		1749	* @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels
		1750	* @param ADCx ADC instance
		1751	* @param SamplingTime This parameter can be one of the following values:
		1752	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
		1753	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
		1754	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
		1755	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
		1756	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
		1757	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
		1758	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
		1759	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
		1760	* @retval None
		1761	*/
		1762	__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
		1763	{
		1764	MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
		1765	}
		1766
		1767	/**
		1768	* @brief Get sampling time common to a group of channels.
		1769	* @note Unit: ADC clock cycles.
		1770	* @note On this STM32 serie, sampling time scope is on ADC instance:
		1771	* Sampling time common to all channels.
		1772	* (on some other STM32 families, sampling time is channel wise)
		1773	* @note Conversion time is the addition of sampling time and processing time.
		1774	* Refer to reference manual for ADC processing time of
		1775	* this STM32 serie.
		1776	* @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
		1777	* @param ADCx ADC instance
		1778	* @retval Returned value can be one of the following values:
		1779	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
		1780	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
		1781	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
		1782	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
		1783	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
		1784	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
		1785	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
		1786	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
		1787	*/
		1788	__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
		1789	{
		1790	return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
		1791	}
		1792
		1793	/**
		1794	* @}
		1795	*/
		1796
		1797	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
		1798	* @{
		1799	*/
		1800
		1801	/**
		1802	* @brief Set ADC group regular conversion trigger source:
		1803	* internal (SW start) or from external IP (timer event,
		1804	* external interrupt line).
		1805	* @note On this STM32 serie, setting trigger source to external trigger
		1806	* also set trigger polarity to rising edge
		1807	* (default setting for compatibility with some ADC on other
		1808	* STM32 families having this setting set by HW default value).
		1809	* In case of need to modify trigger edge, use
		1810	* function @ref LL_ADC_REG_SetTriggerEdge().
		1811	* @note Availability of parameters of trigger sources from timer
		1812	* depends on timers availability on the selected device.
		1813	* @note On this STM32 serie, setting of this feature is conditioned to
		1814	* ADC state:
		1815	* ADC must be disabled or enabled without conversion on going
		1816	* on group regular.
		1817	* @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
		1818	* CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
		1819	* @param ADCx ADC instance
		1820	* @param TriggerSource This parameter can be one of the following values:
		1821	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
		1822	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
		1823	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
		1824	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
		1825	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
		1826	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
		1827	*
		1828	* (1) On STM32F0, parameter not available on all devices
		1829	* @retval None
		1830	*/
		1831	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
		1832	{
		1833	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL, TriggerSource);
		1834	}
		1835
		1836	/**
		1837	* @brief Get ADC group regular conversion trigger source:
		1838	* internal (SW start) or from external IP (timer event,
		1839	* external interrupt line).
		1840	* @note To determine whether group regular trigger source is
		1841	* internal (SW start) or external, without detail
		1842	* of which peripheral is selected as external trigger,
		1843	* (equivalent to
		1844	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
		1845	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
		1846	* @note Availability of parameters of trigger sources from timer
		1847	* depends on timers availability on the selected device.
		1848	* @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
		1849	* CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
		1850	* @param ADCx ADC instance
		1851	* @retval Returned value can be one of the following values:
		1852	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
		1853	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
		1854	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
		1855	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
		1856	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
		1857	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
		1858	*
		1859	* (1) On STM32F0, parameter not available on all devices
		1860	*/
		1861	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
		1862	{
		1863	register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL \| ADC_CFGR1_EXTEN);
		1864
		1865	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
		1866	/* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
		1867	register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
		1868
		1869	/* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
		1870	/* to match with triggers literals definition. */
		1871	return ((TriggerSource
		1872	& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
		1873	\| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
		1874	);
		1875	}
		1876
		1877	/**
		1878	* @brief Get ADC group regular conversion trigger source internal (SW start)
		1879	or external.
		1880	* @note In case of group regular trigger source set to external trigger,
		1881	* to determine which peripheral is selected as external trigger,
		1882	* use function @ref LL_ADC_REG_GetTriggerSource().
		1883	* @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
		1884	* @param ADCx ADC instance
		1885	* @retval Value "0" if trigger source external trigger
		1886	* Value "1" if trigger source SW start.
		1887	*/
		1888	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
		1889	{
		1890	return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
		1891	}
		1892
		1893	/**
		1894	* @brief Set ADC group regular conversion trigger polarity.
		1895	* @note Applicable only for trigger source set to external trigger.
		1896	* @note On this STM32 serie, setting of this feature is conditioned to
		1897	* ADC state:
		1898	* ADC must be disabled or enabled without conversion on going
		1899	* on group regular.
		1900	* @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
		1901	* @param ADCx ADC instance
		1902	* @param ExternalTriggerEdge This parameter can be one of the following values:
		1903	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
		1904	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
		1905	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
		1906	* @retval None
		1907	*/
		1908	__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
		1909	{
		1910	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
		1911	}
		1912
		1913	/**
		1914	* @brief Get ADC group regular conversion trigger polarity.
		1915	* @note Applicable only for trigger source set to external trigger.
		1916	* @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
		1917	* @param ADCx ADC instance
		1918	* @retval Returned value can be one of the following values:
		1919	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
		1920	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
		1921	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
		1922	*/
		1923	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
		1924	{
		1925	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
		1926	}
		1927
		1928
		1929	/**
		1930	* @brief Set ADC group regular sequencer scan direction.
		1931	* @note On some other STM32 families, this setting is not available and
		1932	* the default scan direction is forward.
		1933	* @note On this STM32 serie, setting of this feature is conditioned to
		1934	* ADC state:
		1935	* ADC must be disabled or enabled without conversion on going
		1936	* on group regular.
		1937	* @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
		1938	* @param ADCx ADC instance
		1939	* @param ScanDirection This parameter can be one of the following values:
		1940	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
		1941	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
		1942	* @retval None
		1943	*/
		1944	__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
		1945	{
		1946	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
		1947	}
		1948
		1949	/**
		1950	* @brief Get ADC group regular sequencer scan direction.
		1951	* @note On some other STM32 families, this setting is not available and
		1952	* the default scan direction is forward.
		1953	* @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
		1954	* @param ADCx ADC instance
		1955	* @retval Returned value can be one of the following values:
		1956	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
		1957	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
		1958	*/
		1959	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
		1960	{
		1961	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
		1962	}
		1963
		1964	/**
		1965	* @brief Set ADC group regular sequencer discontinuous mode:
		1966	* sequence subdivided and scan conversions interrupted every selected
		1967	* number of ranks.
		1968	* @note It is not possible to enable both ADC group regular
		1969	* continuous mode and sequencer discontinuous mode.
		1970	* @note On this STM32 serie, setting of this feature is conditioned to
		1971	* ADC state:
		1972	* ADC must be disabled or enabled without conversion on going
		1973	* on group regular.
		1974	* @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
		1975	* @param ADCx ADC instance
		1976	* @param SeqDiscont This parameter can be one of the following values:
		1977	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
		1978	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
		1979	* @retval None
		1980	*/
		1981	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
		1982	{
		1983	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
		1984	}
		1985
		1986	/**
		1987	* @brief Get ADC group regular sequencer discontinuous mode:
		1988	* sequence subdivided and scan conversions interrupted every selected
		1989	* number of ranks.
		1990	* @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
		1991	* @param ADCx ADC instance
		1992	* @retval Returned value can be one of the following values:
		1993	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
		1994	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
		1995	*/
		1996	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
		1997	{
		1998	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
		1999	}
		2000
		2001	/**
		2002	* @brief Set ADC group regular sequence: channel on rank corresponding to
		2003	* channel number.
		2004	* @note This function performs:
		2005	* - Channels ordering into each rank of scan sequence:
		2006	* rank of each channel is fixed by channel HW number
		2007	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
		2008	* - Set channels selected by overwriting the current sequencer
		2009	* configuration.
		2010	* @note On this STM32 serie, ADC group regular sequencer is
		2011	* not fully configurable: sequencer length and each rank
		2012	* affectation to a channel are fixed by channel HW number.
		2013	* @note Depending on devices and packages, some channels may not be available.
		2014	* Refer to device datasheet for channels availability.
		2015	* @note On this STM32 serie, to measure internal channels (VrefInt,
		2016	* TempSensor, ...), measurement paths to internal channels must be
		2017	* enabled separately.
		2018	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
		2019	* @note On this STM32 serie, setting of this feature is conditioned to
		2020	* ADC state:
		2021	* ADC must be disabled or enabled without conversion on going
		2022	* on group regular.
		2023	* @note One or several values can be selected.
		2024	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
		2025	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
		2026	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
		2027	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
		2028	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
		2029	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
		2030	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
		2031	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
		2032	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
		2033	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
		2034	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
		2035	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
		2036	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
		2037	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
		2038	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
		2039	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
		2040	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
		2041	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
		2042	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
		2043	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
		2044	* @param ADCx ADC instance
		2045	* @param Channel This parameter can be a combination of the following values:
		2046	* @arg @ref LL_ADC_CHANNEL_0
		2047	* @arg @ref LL_ADC_CHANNEL_1
		2048	* @arg @ref LL_ADC_CHANNEL_2
		2049	* @arg @ref LL_ADC_CHANNEL_3
		2050	* @arg @ref LL_ADC_CHANNEL_4
		2051	* @arg @ref LL_ADC_CHANNEL_5
		2052	* @arg @ref LL_ADC_CHANNEL_6
		2053	* @arg @ref LL_ADC_CHANNEL_7
		2054	* @arg @ref LL_ADC_CHANNEL_8
		2055	* @arg @ref LL_ADC_CHANNEL_9
		2056	* @arg @ref LL_ADC_CHANNEL_10
		2057	* @arg @ref LL_ADC_CHANNEL_11
		2058	* @arg @ref LL_ADC_CHANNEL_12
		2059	* @arg @ref LL_ADC_CHANNEL_13
		2060	* @arg @ref LL_ADC_CHANNEL_14
		2061	* @arg @ref LL_ADC_CHANNEL_15
		2062	* @arg @ref LL_ADC_CHANNEL_16
		2063	* @arg @ref LL_ADC_CHANNEL_17
		2064	* @arg @ref LL_ADC_CHANNEL_18 (1)
		2065	* @arg @ref LL_ADC_CHANNEL_VREFINT
		2066	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		2067	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		2068	*
		2069	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		2070	* @retval None
		2071	*/
		2072	__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
		2073	{
		2074	/* Parameter "Channel" is used with masks because containing */
		2075	/* other bits reserved for other purpose. */
		2076	WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
		2077	}
		2078
		2079	/**
		2080	* @brief Add channel to ADC group regular sequence: channel on rank corresponding to
		2081	* channel number.
		2082	* @note This function performs:
		2083	* - Channels ordering into each rank of scan sequence:
		2084	* rank of each channel is fixed by channel HW number
		2085	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
		2086	* - Set channels selected by adding them to the current sequencer
		2087	* configuration.
		2088	* @note On this STM32 serie, ADC group regular sequencer is
		2089	* not fully configurable: sequencer length and each rank
		2090	* affectation to a channel are fixed by channel HW number.
		2091	* @note Depending on devices and packages, some channels may not be available.
		2092	* Refer to device datasheet for channels availability.
		2093	* @note On this STM32 serie, to measure internal channels (VrefInt,
		2094	* TempSensor, ...), measurement paths to internal channels must be
		2095	* enabled separately.
		2096	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
		2097	* @note On this STM32 serie, setting of this feature is conditioned to
		2098	* ADC state:
		2099	* ADC must be disabled or enabled without conversion on going
		2100	* on group regular.
		2101	* @note One or several values can be selected.
		2102	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
		2103	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
		2104	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
		2105	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
		2106	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
		2107	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
		2108	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
		2109	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
		2110	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
		2111	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
		2112	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
		2113	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
		2114	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
		2115	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
		2116	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
		2117	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
		2118	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
		2119	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
		2120	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
		2121	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
		2122	* @param ADCx ADC instance
		2123	* @param Channel This parameter can be a combination of the following values:
		2124	* @arg @ref LL_ADC_CHANNEL_0
		2125	* @arg @ref LL_ADC_CHANNEL_1
		2126	* @arg @ref LL_ADC_CHANNEL_2
		2127	* @arg @ref LL_ADC_CHANNEL_3
		2128	* @arg @ref LL_ADC_CHANNEL_4
		2129	* @arg @ref LL_ADC_CHANNEL_5
		2130	* @arg @ref LL_ADC_CHANNEL_6
		2131	* @arg @ref LL_ADC_CHANNEL_7
		2132	* @arg @ref LL_ADC_CHANNEL_8
		2133	* @arg @ref LL_ADC_CHANNEL_9
		2134	* @arg @ref LL_ADC_CHANNEL_10
		2135	* @arg @ref LL_ADC_CHANNEL_11
		2136	* @arg @ref LL_ADC_CHANNEL_12
		2137	* @arg @ref LL_ADC_CHANNEL_13
		2138	* @arg @ref LL_ADC_CHANNEL_14
		2139	* @arg @ref LL_ADC_CHANNEL_15
		2140	* @arg @ref LL_ADC_CHANNEL_16
		2141	* @arg @ref LL_ADC_CHANNEL_17
		2142	* @arg @ref LL_ADC_CHANNEL_18 (1)
		2143	* @arg @ref LL_ADC_CHANNEL_VREFINT
		2144	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		2145	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		2146	*
		2147	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		2148	* @retval None
		2149	*/
		2150	__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
		2151	{
		2152	/* Parameter "Channel" is used with masks because containing */
		2153	/* other bits reserved for other purpose. */
		2154	SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
		2155	}
		2156
		2157	/**
		2158	* @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
		2159	* channel number.
		2160	* @note This function performs:
		2161	* - Channels ordering into each rank of scan sequence:
		2162	* rank of each channel is fixed by channel HW number
		2163	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
		2164	* - Set channels selected by removing them to the current sequencer
		2165	* configuration.
		2166	* @note On this STM32 serie, ADC group regular sequencer is
		2167	* not fully configurable: sequencer length and each rank
		2168	* affectation to a channel are fixed by channel HW number.
		2169	* @note Depending on devices and packages, some channels may not be available.
		2170	* Refer to device datasheet for channels availability.
		2171	* @note On this STM32 serie, to measure internal channels (VrefInt,
		2172	* TempSensor, ...), measurement paths to internal channels must be
		2173	* enabled separately.
		2174	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
		2175	* @note On this STM32 serie, setting of this feature is conditioned to
		2176	* ADC state:
		2177	* ADC must be disabled or enabled without conversion on going
		2178	* on group regular.
		2179	* @note One or several values can be selected.
		2180	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
		2181	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
		2182	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
		2183	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
		2184	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
		2185	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
		2186	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
		2187	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
		2188	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
		2189	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
		2190	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
		2191	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
		2192	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
		2193	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
		2194	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
		2195	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
		2196	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
		2197	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
		2198	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
		2199	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
		2200	* @param ADCx ADC instance
		2201	* @param Channel This parameter can be a combination of the following values:
		2202	* @arg @ref LL_ADC_CHANNEL_0
		2203	* @arg @ref LL_ADC_CHANNEL_1
		2204	* @arg @ref LL_ADC_CHANNEL_2
		2205	* @arg @ref LL_ADC_CHANNEL_3
		2206	* @arg @ref LL_ADC_CHANNEL_4
		2207	* @arg @ref LL_ADC_CHANNEL_5
		2208	* @arg @ref LL_ADC_CHANNEL_6
		2209	* @arg @ref LL_ADC_CHANNEL_7
		2210	* @arg @ref LL_ADC_CHANNEL_8
		2211	* @arg @ref LL_ADC_CHANNEL_9
		2212	* @arg @ref LL_ADC_CHANNEL_10
		2213	* @arg @ref LL_ADC_CHANNEL_11
		2214	* @arg @ref LL_ADC_CHANNEL_12
		2215	* @arg @ref LL_ADC_CHANNEL_13
		2216	* @arg @ref LL_ADC_CHANNEL_14
		2217	* @arg @ref LL_ADC_CHANNEL_15
		2218	* @arg @ref LL_ADC_CHANNEL_16
		2219	* @arg @ref LL_ADC_CHANNEL_17
		2220	* @arg @ref LL_ADC_CHANNEL_18 (1)
		2221	* @arg @ref LL_ADC_CHANNEL_VREFINT
		2222	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		2223	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		2224	*
		2225	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		2226	* @retval None
		2227	*/
		2228	__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
		2229	{
		2230	/* Parameter "Channel" is used with masks because containing */
		2231	/* other bits reserved for other purpose. */
		2232	CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
		2233	}
		2234
		2235	/**
		2236	* @brief Get ADC group regular sequence: channel on rank corresponding to
		2237	* channel number.
		2238	* @note This function performs:
		2239	* - Channels order reading into each rank of scan sequence:
		2240	* rank of each channel is fixed by channel HW number
		2241	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
		2242	* @note On this STM32 serie, ADC group regular sequencer is
		2243	* not fully configurable: sequencer length and each rank
		2244	* affectation to a channel are fixed by channel HW number.
		2245	* @note Depending on devices and packages, some channels may not be available.
		2246	* Refer to device datasheet for channels availability.
		2247	* @note On this STM32 serie, to measure internal channels (VrefInt,
		2248	* TempSensor, ...), measurement paths to internal channels must be
		2249	* enabled separately.
		2250	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
		2251	* @note On this STM32 serie, setting of this feature is conditioned to
		2252	* ADC state:
		2253	* ADC must be disabled or enabled without conversion on going
		2254	* on group regular.
		2255	* @note One or several values can be retrieved.
		2256	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
		2257	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
		2258	* CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
		2259	* CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
		2260	* CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
		2261	* CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
		2262	* CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
		2263	* CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
		2264	* CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
		2265	* CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
		2266	* CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
		2267	* CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
		2268	* CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
		2269	* CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
		2270	* CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
		2271	* CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
		2272	* CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
		2273	* CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
		2274	* CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
		2275	* CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
		2276	* @param ADCx ADC instance
		2277	* @retval Returned value can be a combination of the following values:
		2278	* @arg @ref LL_ADC_CHANNEL_0
		2279	* @arg @ref LL_ADC_CHANNEL_1
		2280	* @arg @ref LL_ADC_CHANNEL_2
		2281	* @arg @ref LL_ADC_CHANNEL_3
		2282	* @arg @ref LL_ADC_CHANNEL_4
		2283	* @arg @ref LL_ADC_CHANNEL_5
		2284	* @arg @ref LL_ADC_CHANNEL_6
		2285	* @arg @ref LL_ADC_CHANNEL_7
		2286	* @arg @ref LL_ADC_CHANNEL_8
		2287	* @arg @ref LL_ADC_CHANNEL_9
		2288	* @arg @ref LL_ADC_CHANNEL_10
		2289	* @arg @ref LL_ADC_CHANNEL_11
		2290	* @arg @ref LL_ADC_CHANNEL_12
		2291	* @arg @ref LL_ADC_CHANNEL_13
		2292	* @arg @ref LL_ADC_CHANNEL_14
		2293	* @arg @ref LL_ADC_CHANNEL_15
		2294	* @arg @ref LL_ADC_CHANNEL_16
		2295	* @arg @ref LL_ADC_CHANNEL_17
		2296	* @arg @ref LL_ADC_CHANNEL_18 (1)
		2297	* @arg @ref LL_ADC_CHANNEL_VREFINT
		2298	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
		2299	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
		2300	*
		2301	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		2302	*/
		2303	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
		2304	{
		2305	register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
		2306
		2307	return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
		2308	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
		2309	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
		2310	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
		2311	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
		2312	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
		2313	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
		2314	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
		2315	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
		2316	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
		2317	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
		2318	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
		2319	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
		2320	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
		2321	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
		2322	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
		2323	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
		2324	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
		2325	#if defined(ADC_CCR_VBATEN)
		2326	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
		2327	#endif
		2328	);
		2329	}
		2330	/**
		2331	* @brief Set ADC continuous conversion mode on ADC group regular.
		2332	* @note Description of ADC continuous conversion mode:
		2333	* - single mode: one conversion per trigger
		2334	* - continuous mode: after the first trigger, following
		2335	* conversions launched successively automatically.
		2336	* @note It is not possible to enable both ADC group regular
		2337	* continuous mode and sequencer discontinuous mode.
		2338	* @note On this STM32 serie, setting of this feature is conditioned to
		2339	* ADC state:
		2340	* ADC must be disabled or enabled without conversion on going
		2341	* on group regular.
		2342	* @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
		2343	* @param ADCx ADC instance
		2344	* @param Continuous This parameter can be one of the following values:
		2345	* @arg @ref LL_ADC_REG_CONV_SINGLE
		2346	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
		2347	* @retval None
		2348	*/
		2349	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
		2350	{
		2351	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
		2352	}
		2353
		2354	/**
		2355	* @brief Get ADC continuous conversion mode on ADC group regular.
		2356	* @note Description of ADC continuous conversion mode:
		2357	* - single mode: one conversion per trigger
		2358	* - continuous mode: after the first trigger, following
		2359	* conversions launched successively automatically.
		2360	* @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
		2361	* @param ADCx ADC instance
		2362	* @retval Returned value can be one of the following values:
		2363	* @arg @ref LL_ADC_REG_CONV_SINGLE
		2364	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
		2365	*/
		2366	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
		2367	{
		2368	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
		2369	}
		2370
		2371	/**
		2372	* @brief Set ADC group regular conversion data transfer: no transfer or
		2373	* transfer by DMA, and DMA requests mode.
		2374	* @note If transfer by DMA selected, specifies the DMA requests
		2375	* mode:
		2376	* - Limited mode (One shot mode): DMA transfer requests are stopped
		2377	* when number of DMA data transfers (number of
		2378	* ADC conversions) is reached.
		2379	* This ADC mode is intended to be used with DMA mode non-circular.
		2380	* - Unlimited mode: DMA transfer requests are unlimited,
		2381	* whatever number of DMA data transfers (number of
		2382	* ADC conversions).
		2383	* This ADC mode is intended to be used with DMA mode circular.
		2384	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
		2385	* mode non-circular:
		2386	* when DMA transfers size will be reached, DMA will stop transfers of
		2387	* ADC conversions data ADC will raise an overrun error
		2388	* (overrun flag and interruption if enabled).
		2389	* @note To configure DMA source address (peripheral address),
		2390	* use function @ref LL_ADC_DMA_GetRegAddr().
		2391	* @note On this STM32 serie, setting of this feature is conditioned to
		2392	* ADC state:
		2393	* ADC must be disabled or enabled without conversion on going
		2394	* on group regular.
		2395	* @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
		2396	* CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
		2397	* @param ADCx ADC instance
		2398	* @param DMATransfer This parameter can be one of the following values:
		2399	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
		2400	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
		2401	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
		2402	* @retval None
		2403	*/
		2404	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
		2405	{
		2406	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN \| ADC_CFGR1_DMACFG, DMATransfer);
		2407	}
		2408
		2409	/**
		2410	* @brief Get ADC group regular conversion data transfer: no transfer or
		2411	* transfer by DMA, and DMA requests mode.
		2412	* @note If transfer by DMA selected, specifies the DMA requests
		2413	* mode:
		2414	* - Limited mode (One shot mode): DMA transfer requests are stopped
		2415	* when number of DMA data transfers (number of
		2416	* ADC conversions) is reached.
		2417	* This ADC mode is intended to be used with DMA mode non-circular.
		2418	* - Unlimited mode: DMA transfer requests are unlimited,
		2419	* whatever number of DMA data transfers (number of
		2420	* ADC conversions).
		2421	* This ADC mode is intended to be used with DMA mode circular.
		2422	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
		2423	* mode non-circular:
		2424	* when DMA transfers size will be reached, DMA will stop transfers of
		2425	* ADC conversions data ADC will raise an overrun error
		2426	* (overrun flag and interruption if enabled).
		2427	* @note To configure DMA source address (peripheral address),
		2428	* use function @ref LL_ADC_DMA_GetRegAddr().
		2429	* @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
		2430	* CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
		2431	* @param ADCx ADC instance
		2432	* @retval Returned value can be one of the following values:
		2433	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
		2434	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
		2435	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
		2436	*/
		2437	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
		2438	{
		2439	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN \| ADC_CFGR1_DMACFG));
		2440	}
		2441
		2442	/**
		2443	* @brief Set ADC group regular behavior in case of overrun:
		2444	* data preserved or overwritten.
		2445	* @note Compatibility with devices without feature overrun:
		2446	* other devices without this feature have a behavior
		2447	* equivalent to data overwritten.
		2448	* The default setting of overrun is data preserved.
		2449	* Therefore, for compatibility with all devices, parameter
		2450	* overrun should be set to data overwritten.
		2451	* @note On this STM32 serie, setting of this feature is conditioned to
		2452	* ADC state:
		2453	* ADC must be disabled or enabled without conversion on going
		2454	* on group regular.
		2455	* @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
		2456	* @param ADCx ADC instance
		2457	* @param Overrun This parameter can be one of the following values:
		2458	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
		2459	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
		2460	* @retval None
		2461	*/
		2462	__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
		2463	{
		2464	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
		2465	}
		2466
		2467	/**
		2468	* @brief Get ADC group regular behavior in case of overrun:
		2469	* data preserved or overwritten.
		2470	* @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
		2471	* @param ADCx ADC instance
		2472	* @retval Returned value can be one of the following values:
		2473	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
		2474	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
		2475	*/
		2476	__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
		2477	{
		2478	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
		2479	}
		2480
		2481	/**
		2482	* @}
		2483	*/
		2484
		2485
		2486	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
		2487	* @{
		2488	*/
		2489
		2490	/**
		2491	* @brief Set ADC analog watchdog monitored channels:
		2492	* a single channel or all channels,
		2493	* on ADC group regular.
		2494	* @note Once monitored channels are selected, analog watchdog
		2495	* is enabled.
		2496	* @note In case of need to define a single channel to monitor
		2497	* with analog watchdog from sequencer channel definition,
		2498	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
		2499	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		2500	* instance:
		2501	* - AWD standard (instance AWD1):
		2502	* - channels monitored: can monitor 1 channel or all channels.
		2503	* - groups monitored: ADC group regular.
		2504	* - resolution: resolution is not limited (corresponds to
		2505	* ADC resolution configured).
		2506	* @note On this STM32 serie, setting of this feature is conditioned to
		2507	* ADC state:
		2508	* ADC must be disabled or enabled without conversion on going
		2509	* on group regular.
		2510	* @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n
		2511	* CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n
		2512	* CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels
		2513	* @param ADCx ADC instance
		2514	* @param AWDChannelGroup This parameter can be one of the following values:
		2515	* @arg @ref LL_ADC_AWD_DISABLE
		2516	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
		2517	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
		2518	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
		2519	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
		2520	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
		2521	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
		2522	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
		2523	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
		2524	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
		2525	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
		2526	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
		2527	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
		2528	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
		2529	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
		2530	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
		2531	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
		2532	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
		2533	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
		2534	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
		2535	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
		2536	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG
		2537	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
		2538	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
		2539	*
		2540	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
		2541	* @retval None
		2542	*/
		2543	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
		2544	{
		2545	MODIFY_REG(ADCx->CFGR1,
		2546	(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN),
		2547	(AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
		2548	}
		2549
		2550	/**
		2551	* @brief Get ADC analog watchdog monitored channel.
		2552	* @note Usage of the returned channel number:
		2553	* - To reinject this channel into another function LL_ADC_xxx:
		2554	* the returned channel number is only partly formatted on definition
		2555	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
		2556	* with parts of literals LL_ADC_CHANNEL_x or using
		2557	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		2558	* Then the selected literal LL_ADC_CHANNEL_x can be used
		2559	* as parameter for another function.
		2560	* - To get the channel number in decimal format:
		2561	* process the returned value with the helper macro
		2562	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
		2563	* Applicable only when the analog watchdog is set to monitor
		2564	* one channel.
		2565	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		2566	* instance:
		2567	* - AWD standard (instance AWD1):
		2568	* - channels monitored: can monitor 1 channel or all channels.
		2569	* - groups monitored: ADC group regular.
		2570	* - resolution: resolution is not limited (corresponds to
		2571	* ADC resolution configured).
		2572	* @note On this STM32 serie, setting of this feature is conditioned to
		2573	* ADC state:
		2574	* ADC must be disabled or enabled without conversion on going
		2575	* on group regular.
		2576	* @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n
		2577	* CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n
		2578	* CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels
		2579	* @param ADCx ADC instance
		2580	* @retval Returned value can be one of the following values:
		2581	* @arg @ref LL_ADC_AWD_DISABLE
		2582	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
		2583	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
		2584	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
		2585	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
		2586	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
		2587	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
		2588	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
		2589	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
		2590	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
		2591	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
		2592	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
		2593	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
		2594	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
		2595	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
		2596	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
		2597	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
		2598	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
		2599	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
		2600	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
		2601	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
		2602	*/
		2603	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
		2604	{
		2605	register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN));
		2606
		2607	/* Note: Set variable according to channel definition including channel ID */
		2608	/* with bitfield. */
		2609	register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
		2610	register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
		2611
		2612	return (AWDChannelGroup \| (AWDChannelBitField * AWDChannelSingle));
		2613	}
		2614
		2615	/**
		2616	* @brief Set ADC analog watchdog thresholds value of both thresholds
		2617	* high and low.
		2618	* @note If value of only one threshold high or low must be set,
		2619	* use function @ref LL_ADC_SetAnalogWDThresholds().
		2620	* @note In case of ADC resolution different of 12 bits,
		2621	* analog watchdog thresholds data require a specific shift.
		2622	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
		2623	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		2624	* instance:
		2625	* - AWD standard (instance AWD1):
		2626	* - channels monitored: can monitor 1 channel or all channels.
		2627	* - groups monitored: ADC group regular.
		2628	* - resolution: resolution is not limited (corresponds to
		2629	* ADC resolution configured).
		2630	* @note On this STM32 serie, setting of this feature is conditioned to
		2631	* ADC state:
		2632	* ADC must be disabled or enabled without conversion on going
		2633	* on group regular.
		2634	* @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n
		2635	* TR LT LL_ADC_ConfigAnalogWDThresholds
		2636	* @param ADCx ADC instance
		2637	* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
		2638	* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
		2639	* @retval None
		2640	*/
		2641	__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
		2642	{
		2643	MODIFY_REG(ADCx->TR,
		2644	ADC_TR_HT \| ADC_TR_LT,
		2645	(AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) \| AWDThresholdLowValue);
		2646	}
		2647
		2648	/**
		2649	* @brief Set ADC analog watchdog threshold value of threshold
		2650	* high or low.
		2651	* @note If values of both thresholds high or low must be set,
		2652	* use function @ref LL_ADC_ConfigAnalogWDThresholds().
		2653	* @note In case of ADC resolution different of 12 bits,
		2654	* analog watchdog thresholds data require a specific shift.
		2655	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
		2656	* @note On this STM32 serie, there is only 1 kind of analog watchdog
		2657	* instance:
		2658	* - AWD standard (instance AWD1):
		2659	* - channels monitored: can monitor 1 channel or all channels.
		2660	* - groups monitored: ADC group regular.
		2661	* - resolution: resolution is not limited (corresponds to
		2662	* ADC resolution configured).
		2663	* @note On this STM32 serie, setting of this feature is conditioned to
		2664	* ADC state:
		2665	* ADC must be disabled or enabled without conversion on going
		2666	* on group regular.
		2667	* @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n
		2668	* TR LT LL_ADC_SetAnalogWDThresholds
		2669	* @param ADCx ADC instance
		2670	* @param AWDThresholdsHighLow This parameter can be one of the following values:
		2671	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
		2672	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
		2673	* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
		2674	* @retval None
		2675	*/
		2676	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
		2677	{
		2678	/* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
		2679	/* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
		2680	/* high is selected, then data is shifted to LSB. Else(threshold low), */
		2681	/* data is not shifted. */
		2682	MODIFY_REG(ADCx->TR,
		2683	AWDThresholdsHighLow,
		2684	AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U));
		2685	}
		2686
		2687	/**
		2688	* @brief Get ADC analog watchdog threshold value of threshold high,
		2689	* threshold low or raw data with ADC thresholds high and low
		2690	* concatenated.
		2691	* @note If raw data with ADC thresholds high and low is retrieved,
		2692	* the data of each threshold high or low can be isolated
		2693	* using helper macro:
		2694	* @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
		2695	* @note In case of ADC resolution different of 12 bits,
		2696	* analog watchdog thresholds data require a specific shift.
		2697	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
		2698	* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
		2699	* TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
		2700	* TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
		2701	* TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
		2702	* TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
		2703	* TR3 LT3 LL_ADC_GetAnalogWDThresholds
		2704	* @param ADCx ADC instance
		2705	* @param AWDThresholdsHighLow This parameter can be one of the following values:
		2706	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
		2707	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
		2708	* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
		2709	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		2710	*/
		2711	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
		2712	{
		2713	/* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
		2714	/* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
		2715	/* high is selected, then data is shifted to LSB. Else(threshold low or */
		2716	/* both thresholds), data is not shifted. */
		2717	return (uint32_t)(READ_BIT(ADCx->TR,
		2718	(AWDThresholdsHighLow \| ADC_TR_LT))
		2719	>> ((~AWDThresholdsHighLow) & 0x00000010U)
		2720	);
		2721	}
		2722
		2723	/**
		2724	* @}
		2725	*/
		2726
		2727	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
		2728	* @{
		2729	*/
		2730
		2731	/**
		2732	* @brief Enable the selected ADC instance.
		2733	* @note On this STM32 serie, after ADC enable, a delay for
		2734	* ADC internal analog stabilization is required before performing a
		2735	* ADC conversion start.
		2736	* Refer to device datasheet, parameter tSTAB.
		2737	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
		2738	* is enabled and when conversion clock is active.
		2739	* (not only core clock: this ADC has a dual clock domain)
		2740	* @note On this STM32 serie, setting of this feature is conditioned to
		2741	* ADC state:
		2742	* ADC must be ADC disabled and ADC internal voltage regulator enabled.
		2743	* @rmtoll CR ADEN LL_ADC_Enable
		2744	* @param ADCx ADC instance
		2745	* @retval None
		2746	*/
		2747	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
		2748	{
		2749	/* Note: Write register with some additional bits forced to state reset */
		2750	/* instead of modifying only the selected bit for this function, */
		2751	/* to not interfere with bits with HW property "rs". */
		2752	MODIFY_REG(ADCx->CR,
		2753	ADC_CR_BITS_PROPERTY_RS,
		2754	ADC_CR_ADEN);
		2755	}
		2756
		2757	/**
		2758	* @brief Disable the selected ADC instance.
		2759	* @note On this STM32 serie, setting of this feature is conditioned to
		2760	* ADC state:
		2761	* ADC must be not disabled. Must be enabled without conversion on going
		2762	* on group regular.
		2763	* @rmtoll CR ADDIS LL_ADC_Disable
		2764	* @param ADCx ADC instance
		2765	* @retval None
		2766	*/
		2767	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
		2768	{
		2769	/* Note: Write register with some additional bits forced to state reset */
		2770	/* instead of modifying only the selected bit for this function, */
		2771	/* to not interfere with bits with HW property "rs". */
		2772	MODIFY_REG(ADCx->CR,
		2773	ADC_CR_BITS_PROPERTY_RS,
		2774	ADC_CR_ADDIS);
		2775	}
		2776
		2777	/**
		2778	* @brief Get the selected ADC instance enable state.
		2779	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
		2780	* is enabled and when conversion clock is active.
		2781	* (not only core clock: this ADC has a dual clock domain)
		2782	* @rmtoll CR ADEN LL_ADC_IsEnabled
		2783	* @param ADCx ADC instance
		2784	* @retval 0: ADC is disabled, 1: ADC is enabled.
		2785	*/
		2786	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
		2787	{
		2788	return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
		2789	}
		2790
		2791	/**
		2792	* @brief Get the selected ADC instance disable state.
		2793	* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
		2794	* @param ADCx ADC instance
		2795	* @retval 0: no ADC disable command on going.
		2796	*/
		2797	__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
		2798	{
		2799	return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
		2800	}
		2801
		2802	/**
		2803	* @brief Start ADC calibration in the mode single-ended
		2804	* or differential (for devices with differential mode available).
		2805	* @note On this STM32 serie, a minimum number of ADC clock cycles
		2806	* are required between ADC end of calibration and ADC enable.
		2807	* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
		2808	* @note In case of usage of ADC with DMA transfer:
		2809	* On this STM32 serie, ADC DMA transfer request should be disabled
		2810	* during calibration:
		2811	* Calibration factor is available in data register
		2812	* and also transfered by DMA.
		2813	* To not insert ADC calibration factor among ADC conversion data
		2814	* in array variable, DMA transfer must be disabled during
		2815	* calibration.
		2816	* (DMA transfer setting backup and disable before calibration,
		2817	* DMA transfer setting restore after calibration.
		2818	* Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
		2819	* @ref LL_ADC_REG_SetDMATransfer() ).
		2820	* @note On this STM32 serie, setting of this feature is conditioned to
		2821	* ADC state:
		2822	* ADC must be ADC disabled.
		2823	* @rmtoll CR ADCAL LL_ADC_StartCalibration
		2824	* @param ADCx ADC instance
		2825	* @retval None
		2826	*/
		2827	__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
		2828	{
		2829	/* Note: Write register with some additional bits forced to state reset */
		2830	/* instead of modifying only the selected bit for this function, */
		2831	/* to not interfere with bits with HW property "rs". */
		2832	MODIFY_REG(ADCx->CR,
		2833	ADC_CR_BITS_PROPERTY_RS,
		2834	ADC_CR_ADCAL);
		2835	}
		2836
		2837	/**
		2838	* @brief Get ADC calibration state.
		2839	* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
		2840	* @param ADCx ADC instance
		2841	* @retval 0: calibration complete, 1: calibration in progress.
		2842	*/
		2843	__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
		2844	{
		2845	return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
		2846	}
		2847
		2848	/**
		2849	* @}
		2850	*/
		2851
		2852	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
		2853	* @{
		2854	*/
		2855
		2856	/**
		2857	* @brief Start ADC group regular conversion.
		2858	* @note On this STM32 serie, this function is relevant for both
		2859	* internal trigger (SW start) and external trigger:
		2860	* - If ADC trigger has been set to software start, ADC conversion
		2861	* starts immediately.
		2862	* - If ADC trigger has been set to external trigger, ADC conversion
		2863	* will start at next trigger event (on the selected trigger edge)
		2864	* following the ADC start conversion command.
		2865	* @note On this STM32 serie, setting of this feature is conditioned to
		2866	* ADC state:
		2867	* ADC must be enabled without conversion on going on group regular,
		2868	* without conversion stop command on going on group regular,
		2869	* without ADC disable command on going.
		2870	* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
		2871	* @param ADCx ADC instance
		2872	* @retval None
		2873	*/
		2874	__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
		2875	{
		2876	/* Note: Write register with some additional bits forced to state reset */
		2877	/* instead of modifying only the selected bit for this function, */
		2878	/* to not interfere with bits with HW property "rs". */
		2879	MODIFY_REG(ADCx->CR,
		2880	ADC_CR_BITS_PROPERTY_RS,
		2881	ADC_CR_ADSTART);
		2882	}
		2883
		2884	/**
		2885	* @brief Stop ADC group regular conversion.
		2886	* @note On this STM32 serie, setting of this feature is conditioned to
		2887	* ADC state:
		2888	* ADC must be enabled with conversion on going on group regular,
		2889	* without ADC disable command on going.
		2890	* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
		2891	* @param ADCx ADC instance
		2892	* @retval None
		2893	*/
		2894	__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
		2895	{
		2896	/* Note: Write register with some additional bits forced to state reset */
		2897	/* instead of modifying only the selected bit for this function, */
		2898	/* to not interfere with bits with HW property "rs". */
		2899	MODIFY_REG(ADCx->CR,
		2900	ADC_CR_BITS_PROPERTY_RS,
		2901	ADC_CR_ADSTP);
		2902	}
		2903
		2904	/**
		2905	* @brief Get ADC group regular conversion state.
		2906	* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
		2907	* @param ADCx ADC instance
		2908	* @retval 0: no conversion is on going on ADC group regular.
		2909	*/
		2910	__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
		2911	{
		2912	return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
		2913	}
		2914
		2915	/**
		2916	* @brief Get ADC group regular command of conversion stop state
		2917	* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
		2918	* @param ADCx ADC instance
		2919	* @retval 0: no command of conversion stop is on going on ADC group regular.
		2920	*/
		2921	__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
		2922	{
		2923	return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
		2924	}
		2925
		2926	/**
		2927	* @brief Get ADC group regular conversion data, range fit for
		2928	* all ADC configurations: all ADC resolutions and
		2929	* all oversampling increased data width (for devices
		2930	* with feature oversampling).
		2931	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
		2932	* @param ADCx ADC instance
		2933	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
		2934	*/
		2935	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
		2936	{
		2937	return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		2938	}
		2939
		2940	/**
		2941	* @brief Get ADC group regular conversion data, range fit for
		2942	* ADC resolution 12 bits.
		2943	* @note For devices with feature oversampling: Oversampling
		2944	* can increase data width, function for extended range
		2945	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
		2946	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
		2947	* @param ADCx ADC instance
		2948	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
		2949	*/
		2950	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
		2951	{
		2952	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		2953	}
		2954
		2955	/**
		2956	* @brief Get ADC group regular conversion data, range fit for
		2957	* ADC resolution 10 bits.
		2958	* @note For devices with feature oversampling: Oversampling
		2959	* can increase data width, function for extended range
		2960	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
		2961	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
		2962	* @param ADCx ADC instance
		2963	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
		2964	*/
		2965	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
		2966	{
		2967	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		2968	}
		2969
		2970	/**
		2971	* @brief Get ADC group regular conversion data, range fit for
		2972	* ADC resolution 8 bits.
		2973	* @note For devices with feature oversampling: Oversampling
		2974	* can increase data width, function for extended range
		2975	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
		2976	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
		2977	* @param ADCx ADC instance
		2978	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
		2979	*/
		2980	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
		2981	{
		2982	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		2983	}
		2984
		2985	/**
		2986	* @brief Get ADC group regular conversion data, range fit for
		2987	* ADC resolution 6 bits.
		2988	* @note For devices with feature oversampling: Oversampling
		2989	* can increase data width, function for extended range
		2990	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
		2991	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
		2992	* @param ADCx ADC instance
		2993	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
		2994	*/
		2995	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
		2996	{
		2997	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
		2998	}
		2999
		3000	/**
		3001	* @}
		3002	*/
		3003
		3004	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
		3005	* @{
		3006	*/
		3007
		3008	/**
		3009	* @brief Get flag ADC ready.
		3010	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
		3011	* is enabled and when conversion clock is active.
		3012	* (not only core clock: this ADC has a dual clock domain)
		3013	* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
		3014	* @param ADCx ADC instance
		3015	* @retval State of bit (1 or 0).
		3016	*/
		3017	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
		3018	{
		3019	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
		3020	}
		3021
		3022	/**
		3023	* @brief Get flag ADC group regular end of unitary conversion.
		3024	* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
		3025	* @param ADCx ADC instance
		3026	* @retval State of bit (1 or 0).
		3027	*/
		3028	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
		3029	{
		3030	return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
		3031	}
		3032
		3033	/**
		3034	* @brief Get flag ADC group regular end of sequence conversions.
		3035	* @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS
		3036	* @param ADCx ADC instance
		3037	* @retval State of bit (1 or 0).
		3038	*/
		3039	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
		3040	{
		3041	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
		3042	}
		3043
		3044	/**
		3045	* @brief Get flag ADC group regular overrun.
		3046	* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
		3047	* @param ADCx ADC instance
		3048	* @retval State of bit (1 or 0).
		3049	*/
		3050	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
		3051	{
		3052	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
		3053	}
		3054
		3055	/**
		3056	* @brief Get flag ADC group regular end of sampling phase.
		3057	* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
		3058	* @param ADCx ADC instance
		3059	* @retval State of bit (1 or 0).
		3060	*/
		3061	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
		3062	{
		3063	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
		3064	}
		3065
		3066	/**
		3067	* @brief Get flag ADC analog watchdog 1 flag
		3068	* @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD1
		3069	* @param ADCx ADC instance
		3070	* @retval State of bit (1 or 0).
		3071	*/
		3072	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
		3073	{
		3074	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
		3075	}
		3076
		3077	/**
		3078	* @brief Clear flag ADC ready.
		3079	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
		3080	* is enabled and when conversion clock is active.
		3081	* (not only core clock: this ADC has a dual clock domain)
		3082	* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
		3083	* @param ADCx ADC instance
		3084	* @retval None
		3085	*/
		3086	__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
		3087	{
		3088	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
		3089	}
		3090
		3091	/**
		3092	* @brief Clear flag ADC group regular end of unitary conversion.
		3093	* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
		3094	* @param ADCx ADC instance
		3095	* @retval None
		3096	*/
		3097	__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
		3098	{
		3099	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
		3100	}
		3101
		3102	/**
		3103	* @brief Clear flag ADC group regular end of sequence conversions.
		3104	* @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS
		3105	* @param ADCx ADC instance
		3106	* @retval None
		3107	*/
		3108	__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
		3109	{
		3110	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
		3111	}
		3112
		3113	/**
		3114	* @brief Clear flag ADC group regular overrun.
		3115	* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
		3116	* @param ADCx ADC instance
		3117	* @retval None
		3118	*/
		3119	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
		3120	{
		3121	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
		3122	}
		3123
		3124	/**
		3125	* @brief Clear flag ADC group regular end of sampling phase.
		3126	* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
		3127	* @param ADCx ADC instance
		3128	* @retval None
		3129	*/
		3130	__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
		3131	{
		3132	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
		3133	}
		3134
		3135	/**
		3136	* @brief Clear flag ADC analog watchdog 1.
		3137	* @rmtoll ISR AWD LL_ADC_ClearFlag_AWD1
		3138	* @param ADCx ADC instance
		3139	* @retval None
		3140	*/
		3141	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
		3142	{
		3143	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
		3144	}
		3145
		3146	/**
		3147	* @}
		3148	*/
		3149
		3150	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
		3151	* @{
		3152	*/
		3153
		3154	/**
		3155	* @brief Enable ADC ready.
		3156	* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
		3157	* @param ADCx ADC instance
		3158	* @retval None
		3159	*/
		3160	__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
		3161	{
		3162	SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
		3163	}
		3164
		3165	/**
		3166	* @brief Enable interruption ADC group regular end of unitary conversion.
		3167	* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
		3168	* @param ADCx ADC instance
		3169	* @retval None
		3170	*/
		3171	__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
		3172	{
		3173	SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
		3174	}
		3175
		3176	/**
		3177	* @brief Enable interruption ADC group regular end of sequence conversions.
		3178	* @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS
		3179	* @param ADCx ADC instance
		3180	* @retval None
		3181	*/
		3182	__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
		3183	{
		3184	SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
		3185	}
		3186
		3187	/**
		3188	* @brief Enable ADC group regular interruption overrun.
		3189	* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
		3190	* @param ADCx ADC instance
		3191	* @retval None
		3192	*/
		3193	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
		3194	{
		3195	SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
		3196	}
		3197
		3198	/**
		3199	* @brief Enable interruption ADC group regular end of sampling.
		3200	* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
		3201	* @param ADCx ADC instance
		3202	* @retval None
		3203	*/
		3204	__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
		3205	{
		3206	SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
		3207	}
		3208
		3209	/**
		3210	* @brief Enable interruption ADC analog watchdog 1.
		3211	* @rmtoll IER AWDIE LL_ADC_EnableIT_AWD1
		3212	* @param ADCx ADC instance
		3213	* @retval None
		3214	*/
		3215	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
		3216	{
		3217	SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
		3218	}
		3219
		3220	/**
		3221	* @brief Disable interruption ADC ready.
		3222	* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
		3223	* @param ADCx ADC instance
		3224	* @retval None
		3225	*/
		3226	__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
		3227	{
		3228	CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
		3229	}
		3230
		3231	/**
		3232	* @brief Disable interruption ADC group regular end of unitary conversion.
		3233	* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
		3234	* @param ADCx ADC instance
		3235	* @retval None
		3236	*/
		3237	__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
		3238	{
		3239	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
		3240	}
		3241
		3242	/**
		3243	* @brief Disable interruption ADC group regular end of sequence conversions.
		3244	* @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS
		3245	* @param ADCx ADC instance
		3246	* @retval None
		3247	*/
		3248	__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
		3249	{
		3250	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
		3251	}
		3252
		3253	/**
		3254	* @brief Disable interruption ADC group regular overrun.
		3255	* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
		3256	* @param ADCx ADC instance
		3257	* @retval None
		3258	*/
		3259	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
		3260	{
		3261	CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
		3262	}
		3263
		3264	/**
		3265	* @brief Disable interruption ADC group regular end of sampling.
		3266	* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
		3267	* @param ADCx ADC instance
		3268	* @retval None
		3269	*/
		3270	__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
		3271	{
		3272	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
		3273	}
		3274
		3275	/**
		3276	* @brief Disable interruption ADC analog watchdog 1.
		3277	* @rmtoll IER AWDIE LL_ADC_DisableIT_AWD1
		3278	* @param ADCx ADC instance
		3279	* @retval None
		3280	*/
		3281	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
		3282	{
		3283	CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
		3284	}
		3285
		3286	/**
		3287	* @brief Get state of interruption ADC ready
		3288	* (0: interrupt disabled, 1: interrupt enabled).
		3289	* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
		3290	* @param ADCx ADC instance
		3291	* @retval State of bit (1 or 0).
		3292	*/
		3293	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
		3294	{
		3295	return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
		3296	}
		3297
		3298	/**
		3299	* @brief Get state of interruption ADC group regular end of unitary conversion
		3300	* (0: interrupt disabled, 1: interrupt enabled).
		3301	* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
		3302	* @param ADCx ADC instance
		3303	* @retval State of bit (1 or 0).
		3304	*/
		3305	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
		3306	{
		3307	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
		3308	}
		3309
		3310	/**
		3311	* @brief Get state of interruption ADC group regular end of sequence conversions
		3312	* (0: interrupt disabled, 1: interrupt enabled).
		3313	* @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS
		3314	* @param ADCx ADC instance
		3315	* @retval State of bit (1 or 0).
		3316	*/
		3317	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
		3318	{
		3319	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
		3320	}
		3321
		3322	/**
		3323	* @brief Get state of interruption ADC group regular overrun
		3324	* (0: interrupt disabled, 1: interrupt enabled).
		3325	* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
		3326	* @param ADCx ADC instance
		3327	* @retval State of bit (1 or 0).
		3328	*/
		3329	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
		3330	{
		3331	return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
		3332	}
		3333
		3334	/**
		3335	* @brief Get state of interruption ADC group regular end of sampling
		3336	* (0: interrupt disabled, 1: interrupt enabled).
		3337	* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
		3338	* @param ADCx ADC instance
		3339	* @retval State of bit (1 or 0).
		3340	*/
		3341	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
		3342	{
		3343	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
		3344	}
		3345
		3346	/**
		3347	* @brief Get state of interruption ADC analog watchdog 1
		3348	* (0: interrupt disabled, 1: interrupt enabled).
		3349	* @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD1
		3350	* @param ADCx ADC instance
		3351	* @retval State of bit (1 or 0).
		3352	*/
		3353	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
		3354	{
		3355	return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
		3356	}
		3357
		3358	/**
		3359	* @}
		3360	*/
		3361
		3362	#if defined(USE_FULL_LL_DRIVER)
		3363	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
		3364	* @{
		3365	*/
		3366
		3367	/* Initialization of some features of ADC common parameters and multimode */
		3368	/* Note: On this STM32 serie, there is no ADC common initialization */
		3369	/* function. */
		3370	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
		3371
		3372	/* De-initialization of ADC instance */
		3373	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
		3374
		3375	/* Initialization of some features of ADC instance */
		3376	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
		3377	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
		3378
		3379	/* Initialization of some features of ADC instance and ADC group regular */
		3380	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
		3381	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
		3382
		3383	/**
		3384	* @}
		3385	*/
		3386	#endif /* USE_FULL_LL_DRIVER */
		3387
		3388	/**
		3389	* @}
		3390	*/
		3391
		3392	/**
		3393	* @}
		3394	*/
		3395
		3396	#endif /* ADC1 */
		3397
		3398	/**
		3399	* @}
		3400	*/
		3401
		3402	#ifdef __cplusplus
		3403	}
		3404	#endif
		3405
		3406	#endif /* __STM32F0xx_LL_ADC_H */
		3407
		3408	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_adc.h – Rev 2