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2 | mjames | 1 | /** |
2 | ****************************************************************************** |
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3 | * @file stm32f0xx_hal_uart.h |
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4 | * @author MCD Application Team |
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5 | * @brief Header file of UART HAL module. |
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6 | ****************************************************************************** |
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7 | * @attention |
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8 | * |
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9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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10 | * All rights reserved.</center></h2> |
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11 | * |
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12 | * This software component is licensed by ST under BSD 3-Clause license, |
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13 | * the "License"; You may not use this file except in compliance with the |
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14 | * License. You may obtain a copy of the License at: |
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15 | * opensource.org/licenses/BSD-3-Clause |
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16 | * |
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17 | ****************************************************************************** |
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18 | */ |
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19 | |||
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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21 | #ifndef STM32F0xx_HAL_UART_H |
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22 | #define STM32F0xx_HAL_UART_H |
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23 | |||
24 | #ifdef __cplusplus |
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25 | extern "C" { |
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26 | #endif |
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27 | |||
28 | /* Includes ------------------------------------------------------------------*/ |
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29 | #include "stm32f0xx_hal_def.h" |
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30 | |||
31 | /** @addtogroup STM32F0xx_HAL_Driver |
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32 | * @{ |
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33 | */ |
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34 | |||
35 | /** @addtogroup UART |
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36 | * @{ |
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37 | */ |
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38 | |||
39 | /* Exported types ------------------------------------------------------------*/ |
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40 | /** @defgroup UART_Exported_Types UART Exported Types |
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41 | * @{ |
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42 | */ |
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43 | |||
44 | /** |
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45 | * @brief UART Init Structure definition |
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46 | */ |
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47 | typedef struct |
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48 | { |
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6 | mjames | 49 | uint32_t BaudRate; /*!< This member configures the UART communication baud rate. |
50 | The baud rate register is computed using the following formula: |
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51 | - If oversampling is 16 or in LIN mode, |
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52 | Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) |
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53 | - If oversampling is 8, |
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54 | Baud Rate Register[15:4] = ((2 * uart_ker_ck) / |
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55 | ((huart->Init.BaudRate)))[15:4] |
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56 | Baud Rate Register[3] = 0 |
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57 | Baud Rate Register[2:0] = (((2 * uart_ker_ck) / |
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58 | ((huart->Init.BaudRate)))[3:0]) >> 1 |
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59 | where uart_ker_ck is the UART input clock */ |
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2 | mjames | 60 | |
6 | mjames | 61 | uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. |
62 | This parameter can be a value of @ref UARTEx_Word_Length. */ |
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2 | mjames | 63 | |
6 | mjames | 64 | uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. |
65 | This parameter can be a value of @ref UART_Stop_Bits. */ |
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2 | mjames | 66 | |
6 | mjames | 67 | uint32_t Parity; /*!< Specifies the parity mode. |
68 | This parameter can be a value of @ref UART_Parity |
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69 | @note When parity is enabled, the computed parity is inserted |
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70 | at the MSB position of the transmitted data (9th bit when |
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71 | the word length is set to 9 data bits; 8th bit when the |
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72 | word length is set to 8 data bits). */ |
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2 | mjames | 73 | |
6 | mjames | 74 | uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. |
75 | This parameter can be a value of @ref UART_Mode. */ |
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2 | mjames | 76 | |
6 | mjames | 77 | uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled |
78 | or disabled. |
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79 | This parameter can be a value of @ref UART_Hardware_Flow_Control. */ |
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2 | mjames | 80 | |
6 | mjames | 81 | uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, |
82 | to achieve higher speed (up to f_PCLK/8). |
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83 | This parameter can be a value of @ref UART_Over_Sampling. */ |
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2 | mjames | 84 | |
6 | mjames | 85 | uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. |
86 | Selecting the single sample method increases the receiver tolerance to clock |
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87 | deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ |
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2 | mjames | 88 | |
89 | |||
90 | } UART_InitTypeDef; |
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91 | |||
92 | /** |
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93 | * @brief UART Advanced Features initialization structure definition |
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94 | */ |
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95 | typedef struct |
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96 | { |
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97 | uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several |
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98 | Advanced Features may be initialized at the same time . |
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6 | mjames | 99 | This parameter can be a value of |
100 | @ref UART_Advanced_Features_Initialization_Type. */ |
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2 | mjames | 101 | |
102 | uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. |
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103 | This parameter can be a value of @ref UART_Tx_Inv. */ |
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104 | |||
105 | uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. |
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106 | This parameter can be a value of @ref UART_Rx_Inv. */ |
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107 | |||
108 | uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic |
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109 | vs negative/inverted logic). |
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110 | This parameter can be a value of @ref UART_Data_Inv. */ |
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111 | |||
112 | uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. |
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113 | This parameter can be a value of @ref UART_Rx_Tx_Swap. */ |
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114 | |||
115 | uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. |
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116 | This parameter can be a value of @ref UART_Overrun_Disable. */ |
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117 | |||
118 | uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. |
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119 | This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ |
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120 | |||
121 | uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. |
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122 | This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ |
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123 | |||
124 | uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate |
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125 | detection is carried out. |
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126 | This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ |
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127 | |||
128 | uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. |
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129 | This parameter can be a value of @ref UART_MSB_First. */ |
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130 | } UART_AdvFeatureInitTypeDef; |
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131 | |||
132 | /** |
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133 | * @brief HAL UART State definition |
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6 | mjames | 134 | * @note HAL UART State value is a combination of 2 different substates: |
135 | * gState and RxState (see @ref UART_State_Definition). |
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2 | mjames | 136 | * - gState contains UART state information related to global Handle management |
137 | * and also information related to Tx operations. |
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138 | * gState value coding follow below described bitmap : |
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139 | * b7-b6 Error information |
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140 | * 00 : No Error |
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141 | * 01 : (Not Used) |
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142 | * 10 : Timeout |
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143 | * 11 : Error |
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144 | * b5 Peripheral initialization status |
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145 | * 0 : Reset (Peripheral not initialized) |
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6 | mjames | 146 | * 1 : Init done (Peripheral initialized. HAL UART Init function already called) |
2 | mjames | 147 | * b4-b3 (not used) |
148 | * xx : Should be set to 00 |
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149 | * b2 Intrinsic process state |
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150 | * 0 : Ready |
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151 | * 1 : Busy (Peripheral busy with some configuration or internal operations) |
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152 | * b1 (not used) |
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153 | * x : Should be set to 0 |
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154 | * b0 Tx state |
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155 | * 0 : Ready (no Tx operation ongoing) |
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156 | * 1 : Busy (Tx operation ongoing) |
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157 | * - RxState contains information related to Rx operations. |
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158 | * RxState value coding follow below described bitmap : |
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159 | * b7-b6 (not used) |
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160 | * xx : Should be set to 00 |
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161 | * b5 Peripheral initialization status |
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162 | * 0 : Reset (Peripheral not initialized) |
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6 | mjames | 163 | * 1 : Init done (Peripheral initialized) |
2 | mjames | 164 | * b4-b2 (not used) |
165 | * xxx : Should be set to 000 |
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166 | * b1 Rx state |
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167 | * 0 : Ready (no Rx operation ongoing) |
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168 | * 1 : Busy (Rx operation ongoing) |
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169 | * b0 (not used) |
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170 | * x : Should be set to 0. |
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171 | */ |
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172 | typedef uint32_t HAL_UART_StateTypeDef; |
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173 | |||
174 | /** |
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175 | * @brief UART clock sources definition |
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176 | */ |
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177 | typedef enum |
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178 | { |
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179 | UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ |
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180 | UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ |
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181 | UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ |
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182 | UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ |
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183 | UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ |
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184 | } UART_ClockSourceTypeDef; |
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185 | |||
186 | /** |
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6 | mjames | 187 | * @brief HAL UART Reception type definition |
188 | * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. |
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189 | * It is expected to admit following values : |
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190 | * HAL_UART_RECEPTION_STANDARD = 0x00U, |
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191 | * HAL_UART_RECEPTION_TOIDLE = 0x01U, |
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192 | * HAL_UART_RECEPTION_TORTO = 0x02U, |
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193 | * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, |
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194 | */ |
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195 | typedef uint32_t HAL_UART_RxTypeTypeDef; |
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196 | |||
197 | /** |
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2 | mjames | 198 | * @brief UART handle Structure definition |
199 | */ |
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200 | typedef struct __UART_HandleTypeDef |
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201 | { |
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202 | USART_TypeDef *Instance; /*!< UART registers base address */ |
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203 | |||
204 | UART_InitTypeDef Init; /*!< UART communication parameters */ |
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205 | |||
206 | UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ |
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207 | |||
208 | uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ |
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209 | |||
210 | uint16_t TxXferSize; /*!< UART Tx Transfer size */ |
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211 | |||
212 | __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ |
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213 | |||
214 | uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ |
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215 | |||
216 | uint16_t RxXferSize; /*!< UART Rx Transfer size */ |
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217 | |||
218 | __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ |
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219 | |||
220 | uint16_t Mask; /*!< UART Rx RDR register mask */ |
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221 | |||
6 | mjames | 222 | __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ |
223 | |||
2 | mjames | 224 | void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ |
225 | |||
226 | void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ |
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227 | |||
228 | DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ |
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229 | |||
230 | DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ |
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231 | |||
232 | HAL_LockTypeDef Lock; /*!< Locking object */ |
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233 | |||
234 | __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management |
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6 | mjames | 235 | and also related to Tx operations. This parameter |
236 | can be a value of @ref HAL_UART_StateTypeDef */ |
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2 | mjames | 237 | |
6 | mjames | 238 | __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This |
239 | parameter can be a value of @ref HAL_UART_StateTypeDef */ |
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2 | mjames | 240 | |
241 | __IO uint32_t ErrorCode; /*!< UART Error code */ |
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242 | |||
243 | #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
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244 | void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ |
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245 | void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ |
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246 | void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ |
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247 | void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ |
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248 | void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ |
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249 | void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ |
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250 | void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ |
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251 | void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ |
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6 | mjames | 252 | #if defined(USART_CR1_UESM) |
253 | #if defined(USART_CR3_WUFIE) |
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2 | mjames | 254 | void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ |
6 | mjames | 255 | #endif /* USART_CR3_WUFIE */ |
256 | #endif /* USART_CR1_UESM */ |
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257 | void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ |
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2 | mjames | 258 | |
259 | void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ |
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260 | void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ |
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261 | #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
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262 | |||
263 | } UART_HandleTypeDef; |
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264 | |||
265 | #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
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266 | /** |
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267 | * @brief HAL UART Callback ID enumeration definition |
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268 | */ |
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269 | typedef enum |
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270 | { |
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271 | HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ |
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272 | HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ |
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273 | HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ |
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274 | HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ |
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275 | HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ |
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276 | HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ |
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277 | HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ |
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278 | HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ |
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279 | HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ |
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280 | |||
281 | HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ |
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282 | HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ |
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283 | |||
284 | } HAL_UART_CallbackIDTypeDef; |
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285 | |||
286 | /** |
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287 | * @brief HAL UART Callback pointer definition |
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288 | */ |
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6 | mjames | 289 | typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ |
290 | typedef void (*pUART_RxEventCallbackTypeDef) |
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291 | (struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ |
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2 | mjames | 292 | |
293 | #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
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294 | |||
295 | /** |
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296 | * @} |
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297 | */ |
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298 | |||
299 | /* Exported constants --------------------------------------------------------*/ |
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300 | /** @defgroup UART_Exported_Constants UART Exported Constants |
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301 | * @{ |
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302 | */ |
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303 | |||
304 | /** @defgroup UART_State_Definition UART State Code Definition |
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305 | * @{ |
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306 | */ |
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307 | #define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized |
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308 | Value is allowed for gState and RxState */ |
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309 | #define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use |
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310 | Value is allowed for gState and RxState */ |
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311 | #define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing |
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312 | Value is allowed for gState only */ |
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313 | #define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing |
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314 | Value is allowed for gState only */ |
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315 | #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing |
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316 | Value is allowed for RxState only */ |
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317 | #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing |
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6 | mjames | 318 | Not to be used for neither gState nor RxState.Value is result |
319 | of combination (Or) between gState and RxState values */ |
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2 | mjames | 320 | #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state |
321 | Value is allowed for gState only */ |
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322 | #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error |
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323 | Value is allowed for gState only */ |
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324 | /** |
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325 | * @} |
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326 | */ |
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327 | |||
328 | /** @defgroup UART_Error_Definition UART Error Definition |
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329 | * @{ |
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330 | */ |
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6 | mjames | 331 | #define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ |
332 | #define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ |
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333 | #define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ |
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334 | #define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ |
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335 | #define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ |
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336 | #define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
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337 | #define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ |
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2 | mjames | 338 | |
339 | #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
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6 | mjames | 340 | #define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ |
2 | mjames | 341 | #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
342 | /** |
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343 | * @} |
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344 | */ |
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345 | |||
346 | /** @defgroup UART_Stop_Bits UART Number of Stop Bits |
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347 | * @{ |
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348 | */ |
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349 | #define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ |
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350 | #define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ |
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351 | #define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ |
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352 | #define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ |
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353 | /** |
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354 | * @} |
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355 | */ |
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356 | |||
357 | /** @defgroup UART_Parity UART Parity |
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358 | * @{ |
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359 | */ |
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360 | #define UART_PARITY_NONE 0x00000000U /*!< No parity */ |
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361 | #define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ |
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362 | #define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ |
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363 | /** |
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364 | * @} |
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365 | */ |
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366 | |||
367 | /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control |
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368 | * @{ |
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369 | */ |
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370 | #define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ |
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371 | #define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ |
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372 | #define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ |
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373 | #define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ |
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374 | /** |
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375 | * @} |
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376 | */ |
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377 | |||
378 | /** @defgroup UART_Mode UART Transfer Mode |
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379 | * @{ |
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380 | */ |
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381 | #define UART_MODE_RX USART_CR1_RE /*!< RX mode */ |
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382 | #define UART_MODE_TX USART_CR1_TE /*!< TX mode */ |
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383 | #define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ |
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384 | /** |
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385 | * @} |
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386 | */ |
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387 | |||
388 | /** @defgroup UART_State UART State |
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389 | * @{ |
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390 | */ |
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391 | #define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ |
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392 | #define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ |
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393 | /** |
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394 | * @} |
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395 | */ |
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396 | |||
397 | /** @defgroup UART_Over_Sampling UART Over Sampling |
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398 | * @{ |
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399 | */ |
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400 | #define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ |
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401 | #define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ |
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402 | /** |
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403 | * @} |
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404 | */ |
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405 | |||
406 | /** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method |
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407 | * @{ |
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408 | */ |
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409 | #define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ |
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410 | #define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ |
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411 | /** |
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412 | * @} |
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413 | */ |
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414 | |||
415 | /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode |
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416 | * @{ |
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417 | */ |
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6 | mjames | 418 | #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection |
419 | on start bit */ |
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420 | #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection |
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421 | on falling edge */ |
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422 | #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection |
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423 | on 0x7F frame detection */ |
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424 | #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection |
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425 | on 0x55 frame detection */ |
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2 | mjames | 426 | /** |
427 | * @} |
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428 | */ |
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429 | |||
430 | /** @defgroup UART_Receiver_Timeout UART Receiver Timeout |
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431 | * @{ |
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432 | */ |
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433 | #define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ |
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434 | #define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ |
||
435 | /** |
||
436 | * @} |
||
437 | */ |
||
438 | |||
439 | /** @defgroup UART_LIN UART Local Interconnection Network mode |
||
440 | * @{ |
||
441 | */ |
||
442 | #define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ |
||
443 | #define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ |
||
444 | /** |
||
445 | * @} |
||
446 | */ |
||
447 | |||
448 | /** @defgroup UART_LIN_Break_Detection UART LIN Break Detection |
||
449 | * @{ |
||
450 | */ |
||
451 | #define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ |
||
452 | #define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ |
||
453 | /** |
||
454 | * @} |
||
455 | */ |
||
456 | |||
457 | /** @defgroup UART_DMA_Tx UART DMA Tx |
||
458 | * @{ |
||
459 | */ |
||
460 | #define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ |
||
461 | #define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ |
||
462 | /** |
||
463 | * @} |
||
464 | */ |
||
465 | |||
466 | /** @defgroup UART_DMA_Rx UART DMA Rx |
||
467 | * @{ |
||
468 | */ |
||
469 | #define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ |
||
470 | #define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ |
||
471 | /** |
||
472 | * @} |
||
473 | */ |
||
474 | |||
475 | /** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection |
||
476 | * @{ |
||
477 | */ |
||
478 | #define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ |
||
479 | #define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ |
||
480 | /** |
||
481 | * @} |
||
482 | */ |
||
483 | |||
484 | /** @defgroup UART_WakeUp_Methods UART WakeUp Methods |
||
485 | * @{ |
||
486 | */ |
||
487 | #define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ |
||
488 | #define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ |
||
489 | /** |
||
490 | * @} |
||
491 | */ |
||
492 | |||
493 | /** @defgroup UART_Request_Parameters UART Request Parameters |
||
494 | * @{ |
||
495 | */ |
||
496 | #define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ |
||
497 | #define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ |
||
498 | #define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ |
||
499 | #define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ |
||
500 | #define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ |
||
501 | /** |
||
502 | * @} |
||
503 | */ |
||
504 | |||
505 | /** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type |
||
506 | * @{ |
||
507 | */ |
||
508 | #define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ |
||
509 | #define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ |
||
510 | #define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ |
||
511 | #define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ |
||
512 | #define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ |
||
513 | #define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ |
||
514 | #define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ |
||
515 | #define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ |
||
516 | #define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ |
||
517 | /** |
||
518 | * @} |
||
519 | */ |
||
520 | |||
521 | /** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion |
||
522 | * @{ |
||
523 | */ |
||
524 | #define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ |
||
525 | #define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ |
||
526 | /** |
||
527 | * @} |
||
528 | */ |
||
529 | |||
530 | /** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion |
||
531 | * @{ |
||
532 | */ |
||
533 | #define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ |
||
534 | #define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ |
||
535 | /** |
||
536 | * @} |
||
537 | */ |
||
538 | |||
539 | /** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion |
||
540 | * @{ |
||
541 | */ |
||
542 | #define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ |
||
543 | #define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ |
||
544 | /** |
||
545 | * @} |
||
546 | */ |
||
547 | |||
548 | /** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap |
||
549 | * @{ |
||
550 | */ |
||
551 | #define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ |
||
552 | #define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ |
||
553 | /** |
||
554 | * @} |
||
555 | */ |
||
556 | |||
557 | /** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable |
||
558 | * @{ |
||
559 | */ |
||
560 | #define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ |
||
561 | #define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ |
||
562 | /** |
||
563 | * @} |
||
564 | */ |
||
565 | |||
566 | /** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable |
||
567 | * @{ |
||
568 | */ |
||
569 | #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ |
||
570 | #define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ |
||
571 | /** |
||
572 | * @} |
||
573 | */ |
||
574 | |||
575 | /** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error |
||
576 | * @{ |
||
577 | */ |
||
578 | #define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ |
||
579 | #define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ |
||
580 | /** |
||
581 | * @} |
||
582 | */ |
||
583 | |||
584 | /** @defgroup UART_MSB_First UART Advanced Feature MSB First |
||
585 | * @{ |
||
586 | */ |
||
6 | mjames | 587 | #define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received |
588 | first disable */ |
||
589 | #define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received |
||
590 | first enable */ |
||
2 | mjames | 591 | /** |
592 | * @} |
||
593 | */ |
||
594 | #if defined(USART_CR1_UESM) |
||
595 | |||
596 | /** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable |
||
597 | * @{ |
||
598 | */ |
||
599 | #define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ |
||
600 | #define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ |
||
601 | /** |
||
602 | * @} |
||
603 | */ |
||
604 | #endif /* USART_CR1_UESM */ |
||
605 | |||
606 | /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable |
||
607 | * @{ |
||
608 | */ |
||
609 | #define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ |
||
610 | #define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ |
||
611 | /** |
||
612 | * @} |
||
613 | */ |
||
614 | |||
615 | /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register |
||
616 | * @{ |
||
617 | */ |
||
6 | mjames | 618 | #define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ |
2 | mjames | 619 | /** |
620 | * @} |
||
621 | */ |
||
622 | #if defined(USART_CR1_UESM) |
||
623 | |||
624 | /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection |
||
625 | * @{ |
||
626 | */ |
||
6 | mjames | 627 | #if defined(USART_CR3_WUS) |
628 | #define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ |
||
629 | #define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ |
||
630 | #define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register |
||
631 | not empty or RXFIFO is not empty */ |
||
632 | #else |
||
633 | #define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ |
||
634 | #define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register |
||
635 | not empty or RXFIFO is not empty */ |
||
636 | #endif /* USART_CR3_WUS */ |
||
2 | mjames | 637 | /** |
638 | * @} |
||
639 | */ |
||
640 | #endif /* USART_CR1_UESM */ |
||
641 | |||
642 | /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity |
||
643 | * @{ |
||
644 | */ |
||
645 | #define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ |
||
646 | #define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ |
||
647 | /** |
||
648 | * @} |
||
649 | */ |
||
650 | |||
651 | /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register |
||
652 | * @{ |
||
653 | */ |
||
6 | mjames | 654 | #define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB |
655 | position in CR1 register */ |
||
2 | mjames | 656 | /** |
657 | * @} |
||
658 | */ |
||
659 | |||
660 | /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register |
||
661 | * @{ |
||
662 | */ |
||
6 | mjames | 663 | #define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB |
664 | position in CR1 register */ |
||
2 | mjames | 665 | /** |
666 | * @} |
||
667 | */ |
||
668 | |||
669 | /** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask |
||
670 | * @{ |
||
671 | */ |
||
672 | #define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ |
||
673 | /** |
||
674 | * @} |
||
675 | */ |
||
676 | |||
677 | /** @defgroup UART_TimeOut_Value UART polling-based communications time-out value |
||
678 | * @{ |
||
679 | */ |
||
680 | #define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ |
||
681 | /** |
||
682 | * @} |
||
683 | */ |
||
684 | |||
685 | /** @defgroup UART_Flags UART Status Flags |
||
686 | * Elements values convention: 0xXXXX |
||
687 | * - 0xXXXX : Flag mask in the ISR register |
||
688 | * @{ |
||
689 | */ |
||
690 | #define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ |
||
691 | #define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ |
||
692 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 693 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 694 | #define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ |
6 | mjames | 695 | #endif /* USART_CR3_WUFIE */ |
2 | mjames | 696 | #endif /* USART_CR1_UESM */ |
697 | #define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ |
||
698 | #define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ |
||
699 | #define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ |
||
700 | #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ |
||
701 | #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ |
||
702 | #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ |
||
703 | #define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ |
||
704 | #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ |
||
705 | #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ |
||
706 | #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ |
||
707 | #define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ |
||
708 | #define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ |
||
709 | #define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ |
||
710 | #define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ |
||
711 | #define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ |
||
712 | #define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ |
||
713 | #define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ |
||
714 | #define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ |
||
715 | /** |
||
716 | * @} |
||
717 | */ |
||
718 | |||
719 | /** @defgroup UART_Interrupt_definition UART Interrupts Definition |
||
720 | * Elements values convention: 000ZZZZZ0XXYYYYYb |
||
721 | * - YYYYY : Interrupt source position in the XX register (5bits) |
||
722 | * - XX : Interrupt source register (2bits) |
||
723 | * - 01: CR1 register |
||
724 | * - 10: CR2 register |
||
725 | * - 11: CR3 register |
||
726 | * - ZZZZZ : Flag position in the ISR register(5bits) |
||
727 | * Elements values convention: 000000000XXYYYYYb |
||
728 | * - YYYYY : Interrupt source position in the XX register (5bits) |
||
729 | * - XX : Interrupt source register (2bits) |
||
730 | * - 01: CR1 register |
||
731 | * - 10: CR2 register |
||
732 | * - 11: CR3 register |
||
733 | * Elements values convention: 0000ZZZZ00000000b |
||
734 | * - ZZZZ : Flag position in the ISR register(4bits) |
||
735 | * @{ |
||
736 | */ |
||
6 | mjames | 737 | #define UART_IT_PE 0x0028U /*!< UART parity error interruption */ |
738 | #define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ |
||
739 | #define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ |
||
740 | #define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ |
||
741 | #define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ |
||
742 | #define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ |
||
743 | #define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ |
||
744 | #define UART_IT_CM 0x112EU /*!< UART character match interruption */ |
||
2 | mjames | 745 | #if defined(USART_CR1_UESM) |
6 | mjames | 746 | #if defined(USART_CR3_WUFIE) |
747 | #define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ |
||
748 | #endif /* USART_CR3_WUFIE */ |
||
2 | mjames | 749 | #endif /* USART_CR1_UESM */ |
6 | mjames | 750 | #define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ |
2 | mjames | 751 | |
6 | mjames | 752 | #define UART_IT_ERR 0x0060U /*!< UART error interruption */ |
2 | mjames | 753 | |
6 | mjames | 754 | #define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ |
755 | #define UART_IT_NE 0x0200U /*!< UART noise error interruption */ |
||
756 | #define UART_IT_FE 0x0100U /*!< UART frame error interruption */ |
||
2 | mjames | 757 | /** |
758 | * @} |
||
759 | */ |
||
760 | |||
761 | /** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags |
||
762 | * @{ |
||
763 | */ |
||
764 | #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ |
||
765 | #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ |
||
766 | #define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ |
||
767 | #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ |
||
768 | #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ |
||
769 | #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ |
||
770 | #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ |
||
771 | #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ |
||
772 | #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ |
||
773 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 774 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 775 | #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ |
6 | mjames | 776 | #endif /* USART_CR3_WUFIE */ |
2 | mjames | 777 | #endif /* USART_CR1_UESM */ |
778 | #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ |
||
779 | /** |
||
780 | * @} |
||
781 | */ |
||
782 | |||
6 | mjames | 783 | /** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values |
784 | * @{ |
||
785 | */ |
||
786 | #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ |
||
787 | #define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ |
||
788 | #define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ |
||
789 | #define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ |
||
790 | /** |
||
791 | * @} |
||
792 | */ |
||
2 | mjames | 793 | |
794 | /** |
||
795 | * @} |
||
796 | */ |
||
797 | |||
798 | /* Exported macros -----------------------------------------------------------*/ |
||
799 | /** @defgroup UART_Exported_Macros UART Exported Macros |
||
800 | * @{ |
||
801 | */ |
||
802 | |||
803 | /** @brief Reset UART handle states. |
||
804 | * @param __HANDLE__ UART handle. |
||
805 | * @retval None |
||
806 | */ |
||
807 | #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||
808 | #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
||
809 | (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ |
||
810 | (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ |
||
811 | (__HANDLE__)->MspInitCallback = NULL; \ |
||
812 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
||
813 | } while(0U) |
||
814 | #else |
||
815 | #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
||
816 | (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ |
||
817 | (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ |
||
818 | } while(0U) |
||
819 | #endif /*USE_HAL_UART_REGISTER_CALLBACKS */ |
||
820 | |||
821 | /** @brief Flush the UART Data registers. |
||
822 | * @param __HANDLE__ specifies the UART Handle. |
||
823 | * @retval None |
||
824 | */ |
||
825 | #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ |
||
826 | do{ \ |
||
827 | SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ |
||
828 | SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ |
||
829 | } while(0U) |
||
830 | |||
831 | /** @brief Clear the specified UART pending flag. |
||
832 | * @param __HANDLE__ specifies the UART Handle. |
||
833 | * @param __FLAG__ specifies the flag to check. |
||
834 | * This parameter can be any combination of the following values: |
||
835 | * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag |
||
836 | * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag |
||
837 | * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag |
||
838 | * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag |
||
839 | * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag |
||
840 | * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag |
||
841 | * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag |
||
842 | * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag |
||
843 | * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag |
||
844 | * @arg @ref UART_CLEAR_CMF Character Match Clear Flag |
||
845 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 846 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 847 | * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag |
848 | #endif |
||
6 | mjames | 849 | #endif |
2 | mjames | 850 | * @retval None |
851 | */ |
||
852 | #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
||
853 | |||
854 | /** @brief Clear the UART PE pending flag. |
||
855 | * @param __HANDLE__ specifies the UART Handle. |
||
856 | * @retval None |
||
857 | */ |
||
858 | #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) |
||
859 | |||
860 | /** @brief Clear the UART FE pending flag. |
||
861 | * @param __HANDLE__ specifies the UART Handle. |
||
862 | * @retval None |
||
863 | */ |
||
864 | #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) |
||
865 | |||
866 | /** @brief Clear the UART NE pending flag. |
||
867 | * @param __HANDLE__ specifies the UART Handle. |
||
868 | * @retval None |
||
869 | */ |
||
870 | #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) |
||
871 | |||
872 | /** @brief Clear the UART ORE pending flag. |
||
873 | * @param __HANDLE__ specifies the UART Handle. |
||
874 | * @retval None |
||
875 | */ |
||
876 | #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) |
||
877 | |||
878 | /** @brief Clear the UART IDLE pending flag. |
||
879 | * @param __HANDLE__ specifies the UART Handle. |
||
880 | * @retval None |
||
881 | */ |
||
882 | #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) |
||
883 | |||
884 | |||
885 | /** @brief Check whether the specified UART flag is set or not. |
||
886 | * @param __HANDLE__ specifies the UART Handle. |
||
887 | * @param __FLAG__ specifies the flag to check. |
||
888 | * This parameter can be one of the following values: |
||
889 | * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag |
||
890 | * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag |
||
6 | mjames | 891 | #if defined(USART_CR1_UESM) |
892 | #if defined(USART_CR3_WUFIE) |
||
2 | mjames | 893 | * @arg @ref UART_FLAG_WUF Wake up from stop mode flag |
6 | mjames | 894 | #endif |
895 | #endif |
||
2 | mjames | 896 | * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) |
897 | * @arg @ref UART_FLAG_SBKF Send Break flag |
||
898 | * @arg @ref UART_FLAG_CMF Character match flag |
||
899 | * @arg @ref UART_FLAG_BUSY Busy flag |
||
900 | * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag |
||
901 | * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag |
||
902 | * @arg @ref UART_FLAG_CTS CTS Change flag |
||
903 | * @arg @ref UART_FLAG_LBDF LIN Break detection flag |
||
904 | * @arg @ref UART_FLAG_TXE Transmit data register empty flag |
||
905 | * @arg @ref UART_FLAG_TC Transmission Complete flag |
||
906 | * @arg @ref UART_FLAG_RXNE Receive data register not empty flag |
||
907 | * @arg @ref UART_FLAG_RTOF Receiver Timeout flag |
||
908 | * @arg @ref UART_FLAG_IDLE Idle Line detection flag |
||
909 | * @arg @ref UART_FLAG_ORE Overrun Error flag |
||
910 | * @arg @ref UART_FLAG_NE Noise Error flag |
||
911 | * @arg @ref UART_FLAG_FE Framing Error flag |
||
912 | * @arg @ref UART_FLAG_PE Parity Error flag |
||
913 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
||
914 | */ |
||
915 | #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) |
||
916 | |||
917 | /** @brief Enable the specified UART interrupt. |
||
918 | * @param __HANDLE__ specifies the UART Handle. |
||
919 | * @param __INTERRUPT__ specifies the UART interrupt source to enable. |
||
920 | * This parameter can be one of the following values: |
||
921 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 922 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 923 | * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt |
924 | #endif |
||
6 | mjames | 925 | #endif |
2 | mjames | 926 | * @arg @ref UART_IT_CM Character match interrupt |
927 | * @arg @ref UART_IT_CTS CTS change interrupt |
||
928 | * @arg @ref UART_IT_LBD LIN Break detection interrupt |
||
929 | * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt |
||
930 | * @arg @ref UART_IT_TC Transmission complete interrupt |
||
931 | * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt |
||
932 | * @arg @ref UART_IT_RTO Receive Timeout interrupt |
||
933 | * @arg @ref UART_IT_IDLE Idle line detection interrupt |
||
934 | * @arg @ref UART_IT_PE Parity Error interrupt |
||
935 | * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) |
||
936 | * @retval None |
||
937 | */ |
||
6 | mjames | 938 | #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ |
939 | ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ |
||
940 | ((__HANDLE__)->Instance->CR1 |= (1U <<\ |
||
941 | ((__INTERRUPT__) & UART_IT_MASK))): \ |
||
942 | ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ |
||
943 | ((__HANDLE__)->Instance->CR2 |= (1U <<\ |
||
944 | ((__INTERRUPT__) & UART_IT_MASK))): \ |
||
945 | ((__HANDLE__)->Instance->CR3 |= (1U <<\ |
||
946 | ((__INTERRUPT__) & UART_IT_MASK)))) |
||
2 | mjames | 947 | |
948 | /** @brief Disable the specified UART interrupt. |
||
949 | * @param __HANDLE__ specifies the UART Handle. |
||
950 | * @param __INTERRUPT__ specifies the UART interrupt source to disable. |
||
951 | * This parameter can be one of the following values: |
||
952 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 953 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 954 | * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt |
955 | #endif |
||
6 | mjames | 956 | #endif |
2 | mjames | 957 | * @arg @ref UART_IT_CM Character match interrupt |
958 | * @arg @ref UART_IT_CTS CTS change interrupt |
||
959 | * @arg @ref UART_IT_LBD LIN Break detection interrupt |
||
960 | * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt |
||
961 | * @arg @ref UART_IT_TC Transmission complete interrupt |
||
962 | * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt |
||
963 | * @arg @ref UART_IT_RTO Receive Timeout interrupt |
||
964 | * @arg @ref UART_IT_IDLE Idle line detection interrupt |
||
965 | * @arg @ref UART_IT_PE Parity Error interrupt |
||
966 | * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) |
||
967 | * @retval None |
||
968 | */ |
||
6 | mjames | 969 | #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ |
970 | ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ |
||
971 | ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ |
||
972 | ((__INTERRUPT__) & UART_IT_MASK))): \ |
||
973 | ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ |
||
974 | ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ |
||
975 | ((__INTERRUPT__) & UART_IT_MASK))): \ |
||
976 | ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ |
||
977 | ((__INTERRUPT__) & UART_IT_MASK)))) |
||
2 | mjames | 978 | |
979 | /** @brief Check whether the specified UART interrupt has occurred or not. |
||
980 | * @param __HANDLE__ specifies the UART Handle. |
||
981 | * @param __INTERRUPT__ specifies the UART interrupt to check. |
||
982 | * This parameter can be one of the following values: |
||
983 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 984 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 985 | * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt |
986 | #endif |
||
6 | mjames | 987 | #endif |
2 | mjames | 988 | * @arg @ref UART_IT_CM Character match interrupt |
989 | * @arg @ref UART_IT_CTS CTS change interrupt |
||
990 | * @arg @ref UART_IT_LBD LIN Break detection interrupt |
||
991 | * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt |
||
992 | * @arg @ref UART_IT_TC Transmission complete interrupt |
||
993 | * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt |
||
994 | * @arg @ref UART_IT_RTO Receive Timeout interrupt |
||
995 | * @arg @ref UART_IT_IDLE Idle line detection interrupt |
||
996 | * @arg @ref UART_IT_PE Parity Error interrupt |
||
997 | * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) |
||
998 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
||
999 | */ |
||
1000 | #define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ |
||
1001 | & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) |
||
1002 | |||
1003 | /** @brief Check whether the specified UART interrupt source is enabled or not. |
||
1004 | * @param __HANDLE__ specifies the UART Handle. |
||
1005 | * @param __INTERRUPT__ specifies the UART interrupt source to check. |
||
1006 | * This parameter can be one of the following values: |
||
1007 | #if defined(USART_CR1_UESM) |
||
6 | mjames | 1008 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 1009 | * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt |
1010 | #endif |
||
6 | mjames | 1011 | #endif |
2 | mjames | 1012 | * @arg @ref UART_IT_CM Character match interrupt |
1013 | * @arg @ref UART_IT_CTS CTS change interrupt |
||
1014 | * @arg @ref UART_IT_LBD LIN Break detection interrupt |
||
1015 | * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt |
||
1016 | * @arg @ref UART_IT_TC Transmission complete interrupt |
||
1017 | * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt |
||
1018 | * @arg @ref UART_IT_RTO Receive Timeout interrupt |
||
1019 | * @arg @ref UART_IT_IDLE Idle line detection interrupt |
||
1020 | * @arg @ref UART_IT_PE Parity Error interrupt |
||
1021 | * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) |
||
1022 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
||
1023 | */ |
||
6 | mjames | 1024 | #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ |
1025 | (__HANDLE__)->Instance->CR1 : \ |
||
1026 | (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ |
||
1027 | (__HANDLE__)->Instance->CR2 : \ |
||
1028 | (__HANDLE__)->Instance->CR3)) & (1U <<\ |
||
1029 | (((uint16_t)(__INTERRUPT__)) &\ |
||
1030 | UART_IT_MASK))) != RESET) ? SET : RESET) |
||
2 | mjames | 1031 | |
1032 | /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. |
||
1033 | * @param __HANDLE__ specifies the UART Handle. |
||
1034 | * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set |
||
1035 | * to clear the corresponding interrupt |
||
1036 | * This parameter can be one of the following values: |
||
1037 | * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag |
||
1038 | * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag |
||
1039 | * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag |
||
1040 | * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag |
||
1041 | * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag |
||
1042 | * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag |
||
1043 | * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag |
||
1044 | * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag |
||
1045 | * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag |
||
1046 | * @arg @ref UART_CLEAR_CMF Character Match Clear Flag |
||
6 | mjames | 1047 | #if defined(USART_CR1_UESM) |
1048 | #if defined(USART_CR3_WUFIE) |
||
2 | mjames | 1049 | * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag |
1050 | #endif |
||
6 | mjames | 1051 | #endif |
2 | mjames | 1052 | * @retval None |
1053 | */ |
||
1054 | #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) |
||
1055 | |||
1056 | /** @brief Set a specific UART request flag. |
||
1057 | * @param __HANDLE__ specifies the UART Handle. |
||
1058 | * @param __REQ__ specifies the request flag to set |
||
1059 | * This parameter can be one of the following values: |
||
1060 | * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request |
||
1061 | * @arg @ref UART_SENDBREAK_REQUEST Send Break Request |
||
1062 | * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request |
||
1063 | * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request |
||
1064 | * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request |
||
1065 | * @retval None |
||
1066 | */ |
||
1067 | #define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) |
||
1068 | |||
1069 | /** @brief Enable the UART one bit sample method. |
||
1070 | * @param __HANDLE__ specifies the UART Handle. |
||
1071 | * @retval None |
||
1072 | */ |
||
1073 | #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) |
||
1074 | |||
1075 | /** @brief Disable the UART one bit sample method. |
||
1076 | * @param __HANDLE__ specifies the UART Handle. |
||
1077 | * @retval None |
||
1078 | */ |
||
1079 | #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) |
||
1080 | |||
1081 | /** @brief Enable UART. |
||
1082 | * @param __HANDLE__ specifies the UART Handle. |
||
1083 | * @retval None |
||
1084 | */ |
||
1085 | #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) |
||
1086 | |||
1087 | /** @brief Disable UART. |
||
1088 | * @param __HANDLE__ specifies the UART Handle. |
||
1089 | * @retval None |
||
1090 | */ |
||
1091 | #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) |
||
1092 | |||
1093 | /** @brief Enable CTS flow control. |
||
1094 | * @note This macro allows to enable CTS hardware flow control for a given UART instance, |
||
1095 | * without need to call HAL_UART_Init() function. |
||
1096 | * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||
1097 | * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need |
||
1098 | * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||
1099 | * - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||
6 | mjames | 1100 | * - macro could only be called when corresponding UART instance is disabled |
1101 | * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable |
||
1102 | * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). |
||
2 | mjames | 1103 | * @param __HANDLE__ specifies the UART Handle. |
1104 | * @retval None |
||
1105 | */ |
||
6 | mjames | 1106 | #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ |
1107 | do{ \ |
||
1108 | ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ |
||
1109 | (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ |
||
2 | mjames | 1110 | } while(0U) |
1111 | |||
1112 | /** @brief Disable CTS flow control. |
||
1113 | * @note This macro allows to disable CTS hardware flow control for a given UART instance, |
||
1114 | * without need to call HAL_UART_Init() function. |
||
1115 | * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||
1116 | * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need |
||
1117 | * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||
1118 | * - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||
6 | mjames | 1119 | * - macro could only be called when corresponding UART instance is disabled |
1120 | * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable |
||
1121 | * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). |
||
2 | mjames | 1122 | * @param __HANDLE__ specifies the UART Handle. |
1123 | * @retval None |
||
1124 | */ |
||
6 | mjames | 1125 | #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ |
1126 | do{ \ |
||
1127 | ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ |
||
1128 | (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ |
||
2 | mjames | 1129 | } while(0U) |
1130 | |||
1131 | /** @brief Enable RTS flow control. |
||
1132 | * @note This macro allows to enable RTS hardware flow control for a given UART instance, |
||
1133 | * without need to call HAL_UART_Init() function. |
||
1134 | * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||
1135 | * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need |
||
1136 | * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||
1137 | * - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||
6 | mjames | 1138 | * - macro could only be called when corresponding UART instance is disabled |
1139 | * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable |
||
1140 | * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). |
||
2 | mjames | 1141 | * @param __HANDLE__ specifies the UART Handle. |
1142 | * @retval None |
||
1143 | */ |
||
6 | mjames | 1144 | #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ |
1145 | do{ \ |
||
1146 | ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ |
||
1147 | (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ |
||
2 | mjames | 1148 | } while(0U) |
1149 | |||
1150 | /** @brief Disable RTS flow control. |
||
1151 | * @note This macro allows to disable RTS hardware flow control for a given UART instance, |
||
1152 | * without need to call HAL_UART_Init() function. |
||
1153 | * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. |
||
1154 | * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need |
||
1155 | * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : |
||
1156 | * - UART instance should have already been initialised (through call of HAL_UART_Init() ) |
||
6 | mjames | 1157 | * - macro could only be called when corresponding UART instance is disabled |
1158 | * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable |
||
1159 | * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). |
||
2 | mjames | 1160 | * @param __HANDLE__ specifies the UART Handle. |
1161 | * @retval None |
||
1162 | */ |
||
6 | mjames | 1163 | #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ |
1164 | do{ \ |
||
1165 | ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ |
||
1166 | (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ |
||
2 | mjames | 1167 | } while(0U) |
1168 | /** |
||
1169 | * @} |
||
1170 | */ |
||
1171 | |||
1172 | /* Private macros --------------------------------------------------------*/ |
||
1173 | /** @defgroup UART_Private_Macros UART Private Macros |
||
1174 | * @{ |
||
1175 | */ |
||
1176 | |||
1177 | |||
1178 | /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. |
||
1179 | * @param __PCLK__ UART clock. |
||
1180 | * @param __BAUD__ Baud rate set by the user. |
||
1181 | * @retval Division result |
||
1182 | */ |
||
1183 | #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) |
||
1184 | |||
1185 | /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. |
||
1186 | * @param __PCLK__ UART clock. |
||
1187 | * @param __BAUD__ Baud rate set by the user. |
||
1188 | * @retval Division result |
||
1189 | */ |
||
1190 | #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) |
||
1191 | |||
1192 | |||
1193 | /** @brief Check UART Baud rate. |
||
1194 | * @param __BAUDRATE__ Baudrate specified by the user. |
||
1195 | * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz) |
||
1196 | * divided by the smallest oversampling used on the USART (i.e. 8) |
||
1197 | * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) |
||
1198 | */ |
||
1199 | #define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U) |
||
1200 | |||
1201 | /** @brief Check UART assertion time. |
||
1202 | * @param __TIME__ 5-bit value assertion time. |
||
1203 | * @retval Test result (TRUE or FALSE). |
||
1204 | */ |
||
1205 | #define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) |
||
1206 | |||
1207 | /** @brief Check UART deassertion time. |
||
1208 | * @param __TIME__ 5-bit value deassertion time. |
||
1209 | * @retval Test result (TRUE or FALSE). |
||
1210 | */ |
||
1211 | #define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) |
||
1212 | |||
1213 | /** |
||
1214 | * @brief Ensure that UART frame number of stop bits is valid. |
||
1215 | * @param __STOPBITS__ UART frame number of stop bits. |
||
1216 | * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) |
||
1217 | */ |
||
1218 | #define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ |
||
1219 | ((__STOPBITS__) == UART_STOPBITS_1) || \ |
||
1220 | ((__STOPBITS__) == UART_STOPBITS_1_5) || \ |
||
1221 | ((__STOPBITS__) == UART_STOPBITS_2)) |
||
1222 | |||
1223 | |||
1224 | /** |
||
1225 | * @brief Ensure that UART frame parity is valid. |
||
1226 | * @param __PARITY__ UART frame parity. |
||
1227 | * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) |
||
1228 | */ |
||
1229 | #define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ |
||
1230 | ((__PARITY__) == UART_PARITY_EVEN) || \ |
||
1231 | ((__PARITY__) == UART_PARITY_ODD)) |
||
1232 | |||
1233 | /** |
||
1234 | * @brief Ensure that UART hardware flow control is valid. |
||
1235 | * @param __CONTROL__ UART hardware flow control. |
||
1236 | * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) |
||
1237 | */ |
||
1238 | #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ |
||
1239 | (((__CONTROL__) == UART_HWCONTROL_NONE) || \ |
||
1240 | ((__CONTROL__) == UART_HWCONTROL_RTS) || \ |
||
1241 | ((__CONTROL__) == UART_HWCONTROL_CTS) || \ |
||
1242 | ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) |
||
1243 | |||
1244 | /** |
||
1245 | * @brief Ensure that UART communication mode is valid. |
||
1246 | * @param __MODE__ UART communication mode. |
||
1247 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) |
||
1248 | */ |
||
1249 | #define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) |
||
1250 | |||
1251 | /** |
||
1252 | * @brief Ensure that UART state is valid. |
||
1253 | * @param __STATE__ UART state. |
||
1254 | * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) |
||
1255 | */ |
||
1256 | #define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ |
||
1257 | ((__STATE__) == UART_STATE_ENABLE)) |
||
1258 | |||
1259 | /** |
||
1260 | * @brief Ensure that UART oversampling is valid. |
||
1261 | * @param __SAMPLING__ UART oversampling. |
||
1262 | * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) |
||
1263 | */ |
||
1264 | #define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ |
||
1265 | ((__SAMPLING__) == UART_OVERSAMPLING_8)) |
||
1266 | |||
1267 | /** |
||
1268 | * @brief Ensure that UART frame sampling is valid. |
||
1269 | * @param __ONEBIT__ UART frame sampling. |
||
1270 | * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) |
||
1271 | */ |
||
1272 | #define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ |
||
1273 | ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) |
||
1274 | |||
1275 | /** |
||
1276 | * @brief Ensure that UART auto Baud rate detection mode is valid. |
||
1277 | * @param __MODE__ UART auto Baud rate detection mode. |
||
1278 | * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) |
||
1279 | */ |
||
1280 | #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ |
||
1281 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ |
||
1282 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ |
||
1283 | ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) |
||
1284 | |||
1285 | /** |
||
1286 | * @brief Ensure that UART receiver timeout setting is valid. |
||
1287 | * @param __TIMEOUT__ UART receiver timeout setting. |
||
1288 | * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) |
||
1289 | */ |
||
1290 | #define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ |
||
1291 | ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) |
||
1292 | |||
1293 | /** @brief Check the receiver timeout value. |
||
1294 | * @note The maximum UART receiver timeout value is 0xFFFFFF. |
||
1295 | * @param __TIMEOUTVALUE__ receiver timeout value. |
||
1296 | * @retval Test result (TRUE or FALSE) |
||
1297 | */ |
||
1298 | #define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) |
||
1299 | |||
1300 | /** |
||
1301 | * @brief Ensure that UART LIN state is valid. |
||
1302 | * @param __LIN__ UART LIN state. |
||
1303 | * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) |
||
1304 | */ |
||
1305 | #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ |
||
1306 | ((__LIN__) == UART_LIN_ENABLE)) |
||
1307 | |||
1308 | /** |
||
1309 | * @brief Ensure that UART LIN break detection length is valid. |
||
1310 | * @param __LENGTH__ UART LIN break detection length. |
||
1311 | * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) |
||
1312 | */ |
||
1313 | #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ |
||
1314 | ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) |
||
1315 | |||
1316 | /** |
||
1317 | * @brief Ensure that UART DMA TX state is valid. |
||
1318 | * @param __DMATX__ UART DMA TX state. |
||
1319 | * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) |
||
1320 | */ |
||
1321 | #define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ |
||
1322 | ((__DMATX__) == UART_DMA_TX_ENABLE)) |
||
1323 | |||
1324 | /** |
||
1325 | * @brief Ensure that UART DMA RX state is valid. |
||
1326 | * @param __DMARX__ UART DMA RX state. |
||
1327 | * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) |
||
1328 | */ |
||
1329 | #define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ |
||
1330 | ((__DMARX__) == UART_DMA_RX_ENABLE)) |
||
1331 | |||
1332 | /** |
||
1333 | * @brief Ensure that UART half-duplex state is valid. |
||
1334 | * @param __HDSEL__ UART half-duplex state. |
||
1335 | * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) |
||
1336 | */ |
||
1337 | #define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ |
||
1338 | ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) |
||
1339 | |||
1340 | /** |
||
1341 | * @brief Ensure that UART wake-up method is valid. |
||
1342 | * @param __WAKEUP__ UART wake-up method . |
||
1343 | * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) |
||
1344 | */ |
||
1345 | #define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ |
||
1346 | ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) |
||
1347 | |||
1348 | /** |
||
1349 | * @brief Ensure that UART request parameter is valid. |
||
1350 | * @param __PARAM__ UART request parameter. |
||
1351 | * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) |
||
1352 | */ |
||
1353 | #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ |
||
1354 | ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ |
||
1355 | ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ |
||
1356 | ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ |
||
1357 | ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) |
||
1358 | |||
1359 | /** |
||
1360 | * @brief Ensure that UART advanced features initialization is valid. |
||
1361 | * @param __INIT__ UART advanced features initialization. |
||
1362 | * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) |
||
1363 | */ |
||
1364 | #define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ |
||
1365 | UART_ADVFEATURE_TXINVERT_INIT | \ |
||
1366 | UART_ADVFEATURE_RXINVERT_INIT | \ |
||
1367 | UART_ADVFEATURE_DATAINVERT_INIT | \ |
||
1368 | UART_ADVFEATURE_SWAP_INIT | \ |
||
1369 | UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ |
||
1370 | UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ |
||
1371 | UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ |
||
1372 | UART_ADVFEATURE_MSBFIRST_INIT)) |
||
1373 | |||
1374 | /** |
||
1375 | * @brief Ensure that UART frame TX inversion setting is valid. |
||
1376 | * @param __TXINV__ UART frame TX inversion setting. |
||
1377 | * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) |
||
1378 | */ |
||
1379 | #define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ |
||
1380 | ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) |
||
1381 | |||
1382 | /** |
||
1383 | * @brief Ensure that UART frame RX inversion setting is valid. |
||
1384 | * @param __RXINV__ UART frame RX inversion setting. |
||
1385 | * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) |
||
1386 | */ |
||
1387 | #define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ |
||
1388 | ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) |
||
1389 | |||
1390 | /** |
||
1391 | * @brief Ensure that UART frame data inversion setting is valid. |
||
1392 | * @param __DATAINV__ UART frame data inversion setting. |
||
1393 | * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) |
||
1394 | */ |
||
1395 | #define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ |
||
1396 | ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) |
||
1397 | |||
1398 | /** |
||
1399 | * @brief Ensure that UART frame RX/TX pins swap setting is valid. |
||
1400 | * @param __SWAP__ UART frame RX/TX pins swap setting. |
||
1401 | * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) |
||
1402 | */ |
||
1403 | #define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ |
||
1404 | ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) |
||
1405 | |||
1406 | /** |
||
1407 | * @brief Ensure that UART frame overrun setting is valid. |
||
1408 | * @param __OVERRUN__ UART frame overrun setting. |
||
1409 | * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) |
||
1410 | */ |
||
1411 | #define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ |
||
1412 | ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) |
||
1413 | |||
1414 | /** |
||
1415 | * @brief Ensure that UART auto Baud rate state is valid. |
||
1416 | * @param __AUTOBAUDRATE__ UART auto Baud rate state. |
||
1417 | * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) |
||
1418 | */ |
||
6 | mjames | 1419 | #define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ |
1420 | UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ |
||
1421 | ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) |
||
2 | mjames | 1422 | |
1423 | /** |
||
1424 | * @brief Ensure that UART DMA enabling or disabling on error setting is valid. |
||
1425 | * @param __DMA__ UART DMA enabling or disabling on error setting. |
||
1426 | * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) |
||
1427 | */ |
||
1428 | #define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ |
||
1429 | ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) |
||
1430 | |||
1431 | /** |
||
1432 | * @brief Ensure that UART frame MSB first setting is valid. |
||
1433 | * @param __MSBFIRST__ UART frame MSB first setting. |
||
1434 | * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) |
||
1435 | */ |
||
1436 | #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ |
||
1437 | ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) |
||
1438 | |||
1439 | #if defined(USART_CR1_UESM) |
||
1440 | /** |
||
1441 | * @brief Ensure that UART stop mode state is valid. |
||
1442 | * @param __STOPMODE__ UART stop mode state. |
||
1443 | * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) |
||
1444 | */ |
||
1445 | #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ |
||
1446 | ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) |
||
1447 | |||
1448 | #endif /* USART_CR1_UESM */ |
||
1449 | /** |
||
1450 | * @brief Ensure that UART mute mode state is valid. |
||
1451 | * @param __MUTE__ UART mute mode state. |
||
1452 | * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) |
||
1453 | */ |
||
1454 | #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ |
||
1455 | ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) |
||
1456 | #if defined(USART_CR1_UESM) |
||
1457 | |||
1458 | /** |
||
1459 | * @brief Ensure that UART wake-up selection is valid. |
||
1460 | * @param __WAKE__ UART wake-up selection. |
||
1461 | * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) |
||
1462 | */ |
||
6 | mjames | 1463 | #if defined(USART_CR3_WUFIE) |
2 | mjames | 1464 | #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ |
1465 | ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ |
||
1466 | ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) |
||
6 | mjames | 1467 | #else |
1468 | #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ |
||
1469 | ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) |
||
1470 | #endif /* USART_CR3_WUFIE */ |
||
2 | mjames | 1471 | #endif /* USART_CR1_UESM */ |
1472 | |||
1473 | /** |
||
1474 | * @brief Ensure that UART driver enable polarity is valid. |
||
1475 | * @param __POLARITY__ UART driver enable polarity. |
||
1476 | * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) |
||
1477 | */ |
||
1478 | #define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ |
||
1479 | ((__POLARITY__) == UART_DE_POLARITY_LOW)) |
||
1480 | |||
1481 | |||
1482 | /** |
||
1483 | * @} |
||
1484 | */ |
||
1485 | |||
1486 | /* Include UART HAL Extended module */ |
||
1487 | #include "stm32f0xx_hal_uart_ex.h" |
||
1488 | |||
1489 | /* Exported functions --------------------------------------------------------*/ |
||
1490 | /** @addtogroup UART_Exported_Functions UART Exported Functions |
||
1491 | * @{ |
||
1492 | */ |
||
1493 | |||
1494 | /** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions |
||
1495 | * @{ |
||
1496 | */ |
||
1497 | |||
1498 | /* Initialization and de-initialization functions ****************************/ |
||
1499 | HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); |
||
1500 | HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); |
||
1501 | #if defined(USART_CR2_LINEN) |
||
1502 | HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); |
||
1503 | #endif /* USART_CR2_LINEN */ |
||
1504 | HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); |
||
1505 | HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); |
||
1506 | void HAL_UART_MspInit(UART_HandleTypeDef *huart); |
||
1507 | void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); |
||
1508 | |||
1509 | /* Callbacks Register/UnRegister functions ***********************************/ |
||
1510 | #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
||
1511 | HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, |
||
1512 | pUART_CallbackTypeDef pCallback); |
||
1513 | HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); |
||
6 | mjames | 1514 | |
1515 | HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); |
||
1516 | HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); |
||
2 | mjames | 1517 | #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
1518 | |||
1519 | /** |
||
1520 | * @} |
||
1521 | */ |
||
1522 | |||
1523 | /** @addtogroup UART_Exported_Functions_Group2 IO operation functions |
||
1524 | * @{ |
||
1525 | */ |
||
1526 | |||
1527 | /* IO operation functions *****************************************************/ |
||
1528 | HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||
1529 | HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||
1530 | HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||
1531 | HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||
1532 | HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||
1533 | HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
||
1534 | HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); |
||
1535 | HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); |
||
1536 | HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); |
||
1537 | /* Transfer Abort functions */ |
||
1538 | HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); |
||
1539 | HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); |
||
1540 | HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); |
||
1541 | HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); |
||
1542 | HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); |
||
1543 | HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); |
||
1544 | |||
1545 | void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); |
||
1546 | void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); |
||
1547 | void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); |
||
1548 | void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); |
||
1549 | void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); |
||
1550 | void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); |
||
1551 | void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); |
||
1552 | void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); |
||
1553 | void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); |
||
1554 | |||
6 | mjames | 1555 | void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); |
1556 | |||
2 | mjames | 1557 | /** |
1558 | * @} |
||
1559 | */ |
||
1560 | |||
1561 | /** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions |
||
1562 | * @{ |
||
1563 | */ |
||
1564 | |||
1565 | /* Peripheral Control functions ************************************************/ |
||
1566 | void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); |
||
1567 | HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); |
||
1568 | HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); |
||
1569 | |||
1570 | #if defined(USART_CR2_LINEN) |
||
1571 | HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); |
||
1572 | #endif /* USART_CR2_LINEN */ |
||
1573 | HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); |
||
1574 | HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); |
||
1575 | void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); |
||
1576 | HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); |
||
1577 | HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); |
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1578 | |||
1579 | /** |
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1580 | * @} |
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1581 | */ |
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1582 | |||
1583 | /** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions |
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1584 | * @{ |
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1585 | */ |
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1586 | |||
1587 | /* Peripheral State and Errors functions **************************************************/ |
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1588 | HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); |
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1589 | uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); |
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1590 | |||
1591 | /** |
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1592 | * @} |
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1593 | */ |
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1594 | |||
1595 | /** |
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1596 | * @} |
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1597 | */ |
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1598 | |||
1599 | /* Private functions -----------------------------------------------------------*/ |
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1600 | /** @addtogroup UART_Private_Functions UART Private Functions |
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1601 | * @{ |
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1602 | */ |
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1603 | #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) |
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6 | mjames | 1604 | void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); |
2 | mjames | 1605 | #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ |
1606 | HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); |
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1607 | HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); |
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1608 | HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, |
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1609 | uint32_t Tickstart, uint32_t Timeout); |
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6 | mjames | 1610 | void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); |
1611 | HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
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1612 | HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); |
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2 | mjames | 1613 | |
1614 | /** |
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1615 | * @} |
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1616 | */ |
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1617 | |||
6 | mjames | 1618 | /* Private variables -----------------------------------------------------------*/ |
2 | mjames | 1619 | /** |
1620 | * @} |
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1621 | */ |
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1622 | |||
1623 | /** |
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1624 | * @} |
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1625 | */ |
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1626 | |||
1627 | #ifdef __cplusplus |
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1628 | } |
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1629 | #endif |
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1630 | |||
1631 | #endif /* STM32F0xx_HAL_UART_H */ |
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1632 | |||
1633 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |