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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_tsc.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of TSC HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F0xx_HAL_TSC_H |
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| 22 | #define STM32F0xx_HAL_TSC_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx_hal_def.h" |
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| 30 | |||
| 31 | #if defined(TSC) |
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| 32 | |||
| 33 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 34 | * @{ |
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| 35 | */ |
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| 36 | |||
| 37 | /** @addtogroup TSC |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |||
| 41 | /* Exported types ------------------------------------------------------------*/ |
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| 42 | /** @defgroup TSC_Exported_Types TSC Exported Types |
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| 43 | * @{ |
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| 44 | */ |
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| 45 | |||
| 46 | /** |
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| 47 | * @brief TSC state structure definition |
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| 48 | */ |
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| 49 | typedef enum |
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| 50 | { |
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| 51 | HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ |
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| 52 | HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ |
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| 53 | HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ |
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| 54 | HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ |
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| 55 | } HAL_TSC_StateTypeDef; |
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| 56 | |||
| 57 | /** |
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| 58 | * @brief TSC group status structure definition |
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| 59 | */ |
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| 60 | typedef enum |
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| 61 | { |
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| 62 | TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ |
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| 63 | TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ |
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| 64 | } TSC_GroupStatusTypeDef; |
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| 65 | |||
| 66 | /** |
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| 67 | * @brief TSC init structure definition |
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| 68 | */ |
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| 69 | typedef struct |
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| 70 | { |
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| 71 | uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length |
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| 72 | This parameter can be a value of @ref TSC_CTPulseHL_Config */ |
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| 73 | uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length |
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| 74 | This parameter can be a value of @ref TSC_CTPulseLL_Config */ |
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| 75 | FunctionalState SpreadSpectrum; /*!< Spread spectrum activation |
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| 76 | This parameter can be set to ENABLE or DISABLE. */ |
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| 77 | uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation |
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| 78 | This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ |
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| 79 | uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler |
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| 80 | This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ |
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| 81 | uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler |
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| 82 | This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ |
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| 83 | uint32_t MaxCountValue; /*!< Max count value |
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| 84 | This parameter can be a value of @ref TSC_MaxCount_Value */ |
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| 85 | uint32_t IODefaultMode; /*!< IO default mode |
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| 86 | This parameter can be a value of @ref TSC_IO_Default_Mode */ |
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| 87 | uint32_t SynchroPinPolarity; /*!< Synchro pin polarity |
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| 88 | This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ |
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| 89 | uint32_t AcquisitionMode; /*!< Acquisition mode |
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| 90 | This parameter can be a value of @ref TSC_Acquisition_Mode */ |
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| 91 | FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation |
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| 92 | This parameter can be set to ENABLE or DISABLE. */ |
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| 93 | uint32_t ChannelIOs; /*!< Channel IOs mask */ |
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| 94 | uint32_t ShieldIOs; /*!< Shield IOs mask */ |
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| 95 | uint32_t SamplingIOs; /*!< Sampling IOs mask */ |
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| 96 | } TSC_InitTypeDef; |
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| 97 | |||
| 98 | /** |
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| 99 | * @brief TSC IOs configuration structure definition |
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| 100 | */ |
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| 101 | typedef struct |
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| 102 | { |
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| 103 | uint32_t ChannelIOs; /*!< Channel IOs mask */ |
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| 104 | uint32_t ShieldIOs; /*!< Shield IOs mask */ |
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| 105 | uint32_t SamplingIOs; /*!< Sampling IOs mask */ |
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| 106 | } TSC_IOConfigTypeDef; |
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| 107 | |||
| 108 | /** |
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| 109 | * @brief TSC handle Structure definition |
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| 110 | */ |
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| 111 | #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) |
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| 112 | typedef struct __TSC_HandleTypeDef |
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| 113 | #else |
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| 114 | typedef struct |
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| 115 | #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ |
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| 116 | { |
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| 117 | TSC_TypeDef *Instance; /*!< Register base address */ |
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| 118 | TSC_InitTypeDef Init; /*!< Initialization parameters */ |
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| 119 | __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ |
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| 120 | HAL_LockTypeDef Lock; /*!< Lock feature */ |
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| 121 | __IO uint32_t ErrorCode; /*!< TSC Error code */ |
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| 122 | |||
| 123 | #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) |
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| 124 | void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ |
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| 125 | void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ |
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| 126 | |||
| 127 | void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ |
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| 128 | void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ |
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| 129 | |||
| 130 | #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ |
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| 131 | } TSC_HandleTypeDef; |
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| 132 | |||
| 133 | enum |
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| 134 | { |
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| 135 | TSC_GROUP1_IDX = 0x00UL, |
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| 136 | TSC_GROUP2_IDX, |
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| 137 | TSC_GROUP3_IDX, |
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| 138 | TSC_GROUP4_IDX, |
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| 139 | TSC_GROUP5_IDX, |
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| 140 | TSC_GROUP6_IDX, |
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| 141 | TSC_GROUP7_IDX, |
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| 142 | TSC_GROUP8_IDX, |
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| 143 | TSC_NB_OF_GROUPS |
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| 144 | }; |
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| 145 | |||
| 146 | #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) |
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| 147 | /** |
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| 148 | * @brief HAL TSC Callback ID enumeration definition |
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| 149 | */ |
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| 150 | typedef enum |
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| 151 | { |
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| 152 | HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ |
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| 153 | HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ |
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| 154 | |||
| 155 | HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ |
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| 156 | HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ |
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| 157 | |||
| 158 | } HAL_TSC_CallbackIDTypeDef; |
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| 159 | |||
| 160 | /** |
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| 161 | * @brief HAL TSC Callback pointer definition |
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| 162 | */ |
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| 163 | typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ |
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| 164 | |||
| 165 | #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ |
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| 166 | |||
| 167 | /** |
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| 168 | * @} |
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| 169 | */ |
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| 170 | |||
| 171 | /* Exported constants --------------------------------------------------------*/ |
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| 172 | /** @defgroup TSC_Exported_Constants TSC Exported Constants |
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| 173 | * @{ |
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| 174 | */ |
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| 175 | |||
| 176 | /** @defgroup TSC_Error_Code_definition TSC Error Code definition |
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| 177 | * @brief TSC Error Code definition |
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| 178 | * @{ |
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| 179 | */ |
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| 180 | #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ |
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| 181 | #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) |
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| 182 | #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ |
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| 183 | #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ |
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| 184 | /** |
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| 185 | * @} |
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| 186 | */ |
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| 187 | |||
| 188 | /** @defgroup TSC_CTPulseHL_Config CTPulse High Length |
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| 189 | * @{ |
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| 190 | */ |
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| 191 | #define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ |
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| 192 | #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ |
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| 193 | #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ |
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| 194 | #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ |
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| 195 | #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ |
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| 196 | #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ |
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| 197 | #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ |
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| 198 | #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ |
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| 199 | #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ |
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| 200 | #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ |
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| 201 | #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ |
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| 202 | #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ |
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| 203 | #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ |
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| 204 | #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ |
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| 205 | #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ |
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| 206 | #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ |
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| 207 | /** |
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| 208 | * @} |
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| 209 | */ |
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| 210 | |||
| 211 | /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length |
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| 212 | * @{ |
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| 213 | */ |
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| 214 | #define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ |
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| 215 | #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ |
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| 216 | #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ |
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| 217 | #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ |
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| 218 | #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ |
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| 219 | #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ |
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| 220 | #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ |
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| 221 | #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ |
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| 222 | #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ |
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| 223 | #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ |
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| 224 | #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ |
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| 225 | #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ |
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| 226 | #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ |
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| 227 | #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ |
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| 228 | #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ |
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| 229 | #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ |
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| 230 | /** |
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| 231 | * @} |
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| 232 | */ |
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| 233 | |||
| 234 | /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler |
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| 235 | * @{ |
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| 236 | */ |
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| 237 | #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ |
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| 238 | #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ |
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| 239 | /** |
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| 240 | * @} |
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| 241 | */ |
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| 242 | |||
| 243 | /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler |
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| 244 | * @{ |
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| 245 | */ |
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| 246 | #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ |
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| 247 | #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ |
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| 248 | #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ |
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| 249 | #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ |
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| 250 | #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ |
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| 251 | #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ |
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| 252 | #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ |
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| 253 | #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ |
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| 254 | /** |
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| 255 | * @} |
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| 256 | */ |
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| 257 | |||
| 258 | /** @defgroup TSC_MaxCount_Value Max Count Value |
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| 259 | * @{ |
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| 260 | */ |
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| 261 | #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ |
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| 262 | #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ |
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| 263 | #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ |
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| 264 | #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ |
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| 265 | #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ |
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| 266 | #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ |
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| 267 | #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ |
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| 268 | /** |
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| 269 | * @} |
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| 270 | */ |
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| 271 | |||
| 272 | /** @defgroup TSC_IO_Default_Mode IO Default Mode |
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| 273 | * @{ |
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| 274 | */ |
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| 275 | #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ |
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| 276 | #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ |
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| 277 | /** |
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| 278 | * @} |
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| 279 | */ |
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| 280 | |||
| 281 | /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity |
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| 282 | * @{ |
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| 283 | */ |
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| 284 | #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ |
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| 285 | #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ |
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| 286 | /** |
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| 287 | * @} |
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| 288 | */ |
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| 289 | |||
| 290 | /** @defgroup TSC_Acquisition_Mode Acquisition Mode |
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| 291 | * @{ |
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| 292 | */ |
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| 293 | #define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ |
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| 294 | #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ |
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| 295 | /** |
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| 296 | * @} |
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| 297 | */ |
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| 298 | |||
| 299 | /** @defgroup TSC_interrupts_definition Interrupts definition |
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| 300 | * @{ |
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| 301 | */ |
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| 302 | #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ |
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| 303 | #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ |
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| 304 | /** |
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| 305 | * @} |
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| 306 | */ |
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| 307 | |||
| 308 | /** @defgroup TSC_flags_definition Flags definition |
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| 309 | * @{ |
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| 310 | */ |
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| 311 | #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ |
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| 312 | #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ |
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| 313 | /** |
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| 314 | * @} |
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| 315 | */ |
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| 316 | |||
| 317 | /** @defgroup TSC_Group_definition Group definition |
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| 318 | * @{ |
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| 319 | */ |
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| 320 | #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) |
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| 321 | #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) |
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| 322 | #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) |
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| 323 | #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) |
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| 324 | #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) |
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| 325 | #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) |
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| 326 | #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) |
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| 327 | #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) |
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| 328 | |||
| 329 | #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ |
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| 330 | #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ |
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| 331 | #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ |
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| 332 | #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ |
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| 333 | |||
| 334 | #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ |
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| 335 | #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ |
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| 336 | #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ |
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| 337 | #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ |
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| 338 | |||
| 339 | #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ |
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| 340 | #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ |
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| 341 | #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ |
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| 342 | #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ |
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| 343 | |||
| 344 | #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ |
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| 345 | #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ |
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| 346 | #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ |
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| 347 | #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ |
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| 348 | |||
| 349 | #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ |
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| 350 | #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ |
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| 351 | #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ |
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| 352 | #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ |
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| 353 | |||
| 354 | #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ |
||
| 355 | #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ |
||
| 356 | #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ |
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| 357 | #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ |
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| 358 | |||
| 359 | #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ |
||
| 360 | #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ |
||
| 361 | #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ |
||
| 362 | #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ |
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| 363 | |||
| 364 | #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ |
||
| 365 | #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ |
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| 366 | #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ |
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| 367 | #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ |
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| 368 | /** |
||
| 369 | * @} |
||
| 370 | */ |
||
| 371 | |||
| 372 | /** |
||
| 373 | * @} |
||
| 374 | */ |
||
| 375 | |||
| 376 | /* Exported macros -----------------------------------------------------------*/ |
||
| 377 | |||
| 378 | /** @defgroup TSC_Exported_Macros TSC Exported Macros |
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| 379 | * @{ |
||
| 380 | */ |
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| 381 | |||
| 382 | /** @brief Reset TSC handle state. |
||
| 383 | * @param __HANDLE__ TSC handle |
||
| 384 | * @retval None |
||
| 385 | */ |
||
| 386 | #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) |
||
| 387 | #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
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| 388 | (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ |
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| 389 | (__HANDLE__)->MspInitCallback = NULL; \ |
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| 390 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
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| 391 | } while(0) |
||
| 392 | #else |
||
| 393 | #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) |
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| 394 | #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ |
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| 395 | |||
| 396 | /** |
||
| 397 | * @brief Enable the TSC peripheral. |
||
| 398 | * @param __HANDLE__ TSC handle |
||
| 399 | * @retval None |
||
| 400 | */ |
||
| 401 | #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) |
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| 402 | |||
| 403 | /** |
||
| 404 | * @brief Disable the TSC peripheral. |
||
| 405 | * @param __HANDLE__ TSC handle |
||
| 406 | * @retval None |
||
| 407 | */ |
||
| 408 | #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) |
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| 409 | |||
| 410 | /** |
||
| 411 | * @brief Start acquisition. |
||
| 412 | * @param __HANDLE__ TSC handle |
||
| 413 | * @retval None |
||
| 414 | */ |
||
| 415 | #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) |
||
| 416 | |||
| 417 | /** |
||
| 418 | * @brief Stop acquisition. |
||
| 419 | * @param __HANDLE__ TSC handle |
||
| 420 | * @retval None |
||
| 421 | */ |
||
| 422 | #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) |
||
| 423 | |||
| 424 | /** |
||
| 425 | * @brief Set IO default mode to output push-pull low. |
||
| 426 | * @param __HANDLE__ TSC handle |
||
| 427 | * @retval None |
||
| 428 | */ |
||
| 429 | #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) |
||
| 430 | |||
| 431 | /** |
||
| 432 | * @brief Set IO default mode to input floating. |
||
| 433 | * @param __HANDLE__ TSC handle |
||
| 434 | * @retval None |
||
| 435 | */ |
||
| 436 | #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) |
||
| 437 | |||
| 438 | /** |
||
| 439 | * @brief Set synchronization polarity to falling edge. |
||
| 440 | * @param __HANDLE__ TSC handle |
||
| 441 | * @retval None |
||
| 442 | */ |
||
| 443 | #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) |
||
| 444 | |||
| 445 | /** |
||
| 446 | * @brief Set synchronization polarity to rising edge and high level. |
||
| 447 | * @param __HANDLE__ TSC handle |
||
| 448 | * @retval None |
||
| 449 | */ |
||
| 450 | #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) |
||
| 451 | |||
| 452 | /** |
||
| 453 | * @brief Enable TSC interrupt. |
||
| 454 | * @param __HANDLE__ TSC handle |
||
| 455 | * @param __INTERRUPT__ TSC interrupt |
||
| 456 | * @retval None |
||
| 457 | */ |
||
| 458 | #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) |
||
| 459 | |||
| 460 | /** |
||
| 461 | * @brief Disable TSC interrupt. |
||
| 462 | * @param __HANDLE__ TSC handle |
||
| 463 | * @param __INTERRUPT__ TSC interrupt |
||
| 464 | * @retval None |
||
| 465 | */ |
||
| 466 | #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) |
||
| 467 | |||
| 468 | /** @brief Check whether the specified TSC interrupt source is enabled or not. |
||
| 469 | * @param __HANDLE__ TSC Handle |
||
| 470 | * @param __INTERRUPT__ TSC interrupt |
||
| 471 | * @retval SET or RESET |
||
| 472 | */ |
||
| 473 | #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ |
||
| 474 | & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ |
||
| 475 | RESET) |
||
| 476 | |||
| 477 | /** |
||
| 478 | * @brief Check whether the specified TSC flag is set or not. |
||
| 479 | * @param __HANDLE__ TSC handle |
||
| 480 | * @param __FLAG__ TSC flag |
||
| 481 | * @retval SET or RESET |
||
| 482 | */ |
||
| 483 | #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ |
||
| 484 | & (__FLAG__)) == (__FLAG__)) ? SET : RESET) |
||
| 485 | |||
| 486 | /** |
||
| 487 | * @brief Clear the TSC's pending flag. |
||
| 488 | * @param __HANDLE__ TSC handle |
||
| 489 | * @param __FLAG__ TSC flag |
||
| 490 | * @retval None |
||
| 491 | */ |
||
| 492 | #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
||
| 493 | |||
| 494 | /** |
||
| 495 | * @brief Enable schmitt trigger hysteresis on a group of IOs. |
||
| 496 | * @param __HANDLE__ TSC handle |
||
| 497 | * @param __GX_IOY_MASK__ IOs mask |
||
| 498 | * @retval None |
||
| 499 | */ |
||
| 500 | #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) |
||
| 501 | |||
| 502 | /** |
||
| 503 | * @brief Disable schmitt trigger hysteresis on a group of IOs. |
||
| 504 | * @param __HANDLE__ TSC handle |
||
| 505 | * @param __GX_IOY_MASK__ IOs mask |
||
| 506 | * @retval None |
||
| 507 | */ |
||
| 508 | #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ |
||
| 509 | &= (~(__GX_IOY_MASK__))) |
||
| 510 | |||
| 511 | /** |
||
| 512 | * @brief Open analog switch on a group of IOs. |
||
| 513 | * @param __HANDLE__ TSC handle |
||
| 514 | * @param __GX_IOY_MASK__ IOs mask |
||
| 515 | * @retval None |
||
| 516 | */ |
||
| 517 | #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ |
||
| 518 | &= (~(__GX_IOY_MASK__))) |
||
| 519 | |||
| 520 | /** |
||
| 521 | * @brief Close analog switch on a group of IOs. |
||
| 522 | * @param __HANDLE__ TSC handle |
||
| 523 | * @param __GX_IOY_MASK__ IOs mask |
||
| 524 | * @retval None |
||
| 525 | */ |
||
| 526 | #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) |
||
| 527 | |||
| 528 | /** |
||
| 529 | * @brief Enable a group of IOs in channel mode. |
||
| 530 | * @param __HANDLE__ TSC handle |
||
| 531 | * @param __GX_IOY_MASK__ IOs mask |
||
| 532 | * @retval None |
||
| 533 | */ |
||
| 534 | #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) |
||
| 535 | |||
| 536 | /** |
||
| 537 | * @brief Disable a group of channel IOs. |
||
| 538 | * @param __HANDLE__ TSC handle |
||
| 539 | * @param __GX_IOY_MASK__ IOs mask |
||
| 540 | * @retval None |
||
| 541 | */ |
||
| 542 | #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ |
||
| 543 | &= (~(__GX_IOY_MASK__))) |
||
| 544 | |||
| 545 | /** |
||
| 546 | * @brief Enable a group of IOs in sampling mode. |
||
| 547 | * @param __HANDLE__ TSC handle |
||
| 548 | * @param __GX_IOY_MASK__ IOs mask |
||
| 549 | * @retval None |
||
| 550 | */ |
||
| 551 | #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) |
||
| 552 | |||
| 553 | /** |
||
| 554 | * @brief Disable a group of sampling IOs. |
||
| 555 | * @param __HANDLE__ TSC handle |
||
| 556 | * @param __GX_IOY_MASK__ IOs mask |
||
| 557 | * @retval None |
||
| 558 | */ |
||
| 559 | #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) |
||
| 560 | |||
| 561 | /** |
||
| 562 | * @brief Enable acquisition groups. |
||
| 563 | * @param __HANDLE__ TSC handle |
||
| 564 | * @param __GX_MASK__ Groups mask |
||
| 565 | * @retval None |
||
| 566 | */ |
||
| 567 | #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) |
||
| 568 | |||
| 569 | /** |
||
| 570 | * @brief Disable acquisition groups. |
||
| 571 | * @param __HANDLE__ TSC handle |
||
| 572 | * @param __GX_MASK__ Groups mask |
||
| 573 | * @retval None |
||
| 574 | */ |
||
| 575 | #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) |
||
| 576 | |||
| 577 | /** @brief Gets acquisition group status. |
||
| 578 | * @param __HANDLE__ TSC Handle |
||
| 579 | * @param __GX_INDEX__ Group index |
||
| 580 | * @retval SET or RESET |
||
| 581 | */ |
||
| 582 | #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ |
||
| 583 | ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ |
||
| 584 | (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) |
||
| 585 | |||
| 586 | /** |
||
| 587 | * @} |
||
| 588 | */ |
||
| 589 | |||
| 590 | /* Private macros ------------------------------------------------------------*/ |
||
| 591 | |||
| 592 | /** @defgroup TSC_Private_Macros TSC Private Macros |
||
| 593 | * @{ |
||
| 594 | */ |
||
| 595 | |||
| 596 | #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ |
||
| 597 | ((__VALUE__) == TSC_CTPH_2CYCLES) || \ |
||
| 598 | ((__VALUE__) == TSC_CTPH_3CYCLES) || \ |
||
| 599 | ((__VALUE__) == TSC_CTPH_4CYCLES) || \ |
||
| 600 | ((__VALUE__) == TSC_CTPH_5CYCLES) || \ |
||
| 601 | ((__VALUE__) == TSC_CTPH_6CYCLES) || \ |
||
| 602 | ((__VALUE__) == TSC_CTPH_7CYCLES) || \ |
||
| 603 | ((__VALUE__) == TSC_CTPH_8CYCLES) || \ |
||
| 604 | ((__VALUE__) == TSC_CTPH_9CYCLES) || \ |
||
| 605 | ((__VALUE__) == TSC_CTPH_10CYCLES) || \ |
||
| 606 | ((__VALUE__) == TSC_CTPH_11CYCLES) || \ |
||
| 607 | ((__VALUE__) == TSC_CTPH_12CYCLES) || \ |
||
| 608 | ((__VALUE__) == TSC_CTPH_13CYCLES) || \ |
||
| 609 | ((__VALUE__) == TSC_CTPH_14CYCLES) || \ |
||
| 610 | ((__VALUE__) == TSC_CTPH_15CYCLES) || \ |
||
| 611 | ((__VALUE__) == TSC_CTPH_16CYCLES)) |
||
| 612 | |||
| 613 | #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ |
||
| 614 | ((__VALUE__) == TSC_CTPL_2CYCLES) || \ |
||
| 615 | ((__VALUE__) == TSC_CTPL_3CYCLES) || \ |
||
| 616 | ((__VALUE__) == TSC_CTPL_4CYCLES) || \ |
||
| 617 | ((__VALUE__) == TSC_CTPL_5CYCLES) || \ |
||
| 618 | ((__VALUE__) == TSC_CTPL_6CYCLES) || \ |
||
| 619 | ((__VALUE__) == TSC_CTPL_7CYCLES) || \ |
||
| 620 | ((__VALUE__) == TSC_CTPL_8CYCLES) || \ |
||
| 621 | ((__VALUE__) == TSC_CTPL_9CYCLES) || \ |
||
| 622 | ((__VALUE__) == TSC_CTPL_10CYCLES) || \ |
||
| 623 | ((__VALUE__) == TSC_CTPL_11CYCLES) || \ |
||
| 624 | ((__VALUE__) == TSC_CTPL_12CYCLES) || \ |
||
| 625 | ((__VALUE__) == TSC_CTPL_13CYCLES) || \ |
||
| 626 | ((__VALUE__) == TSC_CTPL_14CYCLES) || \ |
||
| 627 | ((__VALUE__) == TSC_CTPL_15CYCLES) || \ |
||
| 628 | ((__VALUE__) == TSC_CTPL_16CYCLES)) |
||
| 629 | |||
| 630 | #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ |
||
| 631 | || ((FunctionalState)(__VALUE__) == ENABLE)) |
||
| 632 | |||
| 633 | #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) |
||
| 634 | |||
| 635 | #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) |
||
| 636 | |||
| 637 | #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ |
||
| 638 | ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ |
||
| 639 | ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ |
||
| 640 | ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ |
||
| 641 | ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ |
||
| 642 | ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ |
||
| 643 | ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ |
||
| 644 | ((__VALUE__) == TSC_PG_PRESC_DIV128)) |
||
| 645 | |||
| 646 | #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ |
||
| 647 | ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ |
||
| 648 | (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ |
||
| 649 | ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ |
||
| 650 | (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ |
||
| 651 | (((__CTPL__) == TSC_CTPL_1CYCLE) || \ |
||
| 652 | ((__CTPL__) > TSC_CTPL_1CYCLE)))) |
||
| 653 | |||
| 654 | #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ |
||
| 655 | ((__VALUE__) == TSC_MCV_511) || \ |
||
| 656 | ((__VALUE__) == TSC_MCV_1023) || \ |
||
| 657 | ((__VALUE__) == TSC_MCV_2047) || \ |
||
| 658 | ((__VALUE__) == TSC_MCV_4095) || \ |
||
| 659 | ((__VALUE__) == TSC_MCV_8191) || \ |
||
| 660 | ((__VALUE__) == TSC_MCV_16383)) |
||
| 661 | |||
| 662 | #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) |
||
| 663 | |||
| 664 | #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ |
||
| 665 | || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) |
||
| 666 | |||
| 667 | #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) |
||
| 668 | |||
| 669 | #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ |
||
| 670 | || ((FunctionalState)(__VALUE__) == ENABLE)) |
||
| 671 | |||
| 672 | #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ |
||
| 673 | || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) |
||
| 674 | |||
| 675 | #define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ |
||
| 676 | (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ |
||
| 677 | (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ |
||
| 678 | (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ |
||
| 679 | (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ |
||
| 680 | (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ |
||
| 681 | (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ |
||
| 682 | (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ |
||
| 683 | (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ |
||
| 684 | (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ |
||
| 685 | (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ |
||
| 686 | (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ |
||
| 687 | (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ |
||
| 688 | (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ |
||
| 689 | (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ |
||
| 690 | (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ |
||
| 691 | (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ |
||
| 692 | (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ |
||
| 693 | (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ |
||
| 694 | (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ |
||
| 695 | (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ |
||
| 696 | (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ |
||
| 697 | (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ |
||
| 698 | (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ |
||
| 699 | (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ |
||
| 700 | (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ |
||
| 701 | (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ |
||
| 702 | (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ |
||
| 703 | (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ |
||
| 704 | (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ |
||
| 705 | (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ |
||
| 706 | (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ |
||
| 707 | (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4)) |
||
| 708 | /** |
||
| 709 | * @} |
||
| 710 | */ |
||
| 711 | |||
| 712 | /* Exported functions --------------------------------------------------------*/ |
||
| 713 | /** @addtogroup TSC_Exported_Functions |
||
| 714 | * @{ |
||
| 715 | */ |
||
| 716 | |||
| 717 | /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions |
||
| 718 | * @{ |
||
| 719 | */ |
||
| 720 | /* Initialization and de-initialization functions *****************************/ |
||
| 721 | HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); |
||
| 722 | HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); |
||
| 723 | void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); |
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| 724 | void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); |
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| 725 | |||
| 726 | /* Callbacks Register/UnRegister functions ***********************************/ |
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| 727 | #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) |
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| 728 | HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, |
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| 729 | pTSC_CallbackTypeDef pCallback); |
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| 730 | HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); |
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| 731 | #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ |
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| 732 | /** |
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| 733 | * @} |
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| 734 | */ |
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| 735 | |||
| 736 | /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions |
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| 737 | * @{ |
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| 738 | */ |
||
| 739 | /* IO operation functions *****************************************************/ |
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| 740 | HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); |
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| 741 | HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); |
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| 742 | HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); |
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| 743 | HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); |
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| 744 | HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); |
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| 745 | TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); |
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| 746 | uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); |
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| 747 | /** |
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| 748 | * @} |
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| 749 | */ |
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| 750 | |||
| 751 | /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions |
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| 752 | * @{ |
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| 753 | */ |
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| 754 | /* Peripheral Control functions ***********************************************/ |
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| 755 | HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); |
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| 756 | HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); |
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| 757 | /** |
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| 758 | * @} |
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| 759 | */ |
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| 760 | |||
| 761 | /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions |
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| 762 | * @{ |
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| 763 | */ |
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| 764 | /* Peripheral State and Error functions ***************************************/ |
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| 765 | HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); |
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| 766 | /** |
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| 767 | * @} |
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| 768 | */ |
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| 769 | |||
| 770 | /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
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| 771 | * @{ |
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| 772 | */ |
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| 773 | /******* TSC IRQHandler and Callbacks used in Interrupt mode */ |
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| 774 | void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); |
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| 775 | void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); |
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| 776 | void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); |
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| 777 | /** |
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| 778 | * @} |
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| 779 | */ |
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| 780 | |||
| 781 | /** |
||
| 782 | * @} |
||
| 783 | */ |
||
| 784 | |||
| 785 | /** |
||
| 786 | * @} |
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| 787 | */ |
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| 788 | |||
| 789 | /** |
||
| 790 | * @} |
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| 791 | */ |
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| 792 | #endif /* TSC */ |
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| 793 | |||
| 794 | #ifdef __cplusplus |
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| 795 | } |
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| 796 | #endif |
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| 797 | |||
| 798 | #endif /* STM32F0xx_HAL_TSC_H */ |
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| 799 | |||
| 800 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |