WebSVN – FuelGauge – Blame – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32f0xx_hal_tim.h
		4	* @author MCD Application Team
		5	* @brief Header file of TIM HAL module.
		6	******************************************************************************
		7	* @attention
		8	*
		9	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
		10	* All rights reserved.</center></h2>
		11	*
		12	* This software component is licensed by ST under BSD 3-Clause license,
		13	* the "License"; You may not use this file except in compliance with the
		14	* License. You may obtain a copy of the License at:
		15	* opensource.org/licenses/BSD-3-Clause
		16	*
		17	******************************************************************************
		18	*/
		19
		20	/* Define to prevent recursive inclusion -------------------------------------*/
		21	#ifndef STM32F0xx_HAL_TIM_H
		22	#define STM32F0xx_HAL_TIM_H
		23
		24	#ifdef __cplusplus
		25	extern "C" {
		26	#endif
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "stm32f0xx_hal_def.h"
		30
		31	/** @addtogroup STM32F0xx_HAL_Driver
		32	* @{
		33	*/
		34
		35	/** @addtogroup TIM
		36	* @{
		37	*/
		38
		39	/* Exported types ------------------------------------------------------------*/
		40	/** @defgroup TIM_Exported_Types TIM Exported Types
		41	* @{
		42	*/
		43
		44	/**
		45	* @brief TIM Time base Configuration Structure definition
		46	*/
		47	typedef struct
		48	{
		49	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
		50	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		51
		52	uint32_t CounterMode; /*!< Specifies the counter mode.
		53	This parameter can be a value of @ref TIM_Counter_Mode */
		54
		55	uint32_t Period; /*!< Specifies the period value to be loaded into the active
		56	Auto-Reload Register at the next update event.
		57	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		58
		59	uint32_t ClockDivision; /*!< Specifies the clock division.
		60	This parameter can be a value of @ref TIM_ClockDivision */
		61
		62	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
		63	reaches zero, an update event is generated and counting restarts
		64	from the RCR value (N).
		65	This means in PWM mode that (N+1) corresponds to:
		66	- the number of PWM periods in edge-aligned mode
		67	- the number of half PWM period in center-aligned mode
		68	GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
		69	Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
		70
		71	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
		72	This parameter can be a value of @ref TIM_AutoReloadPreload */
		73	} TIM_Base_InitTypeDef;
		74
		75	/**
		76	* @brief TIM Output Compare Configuration Structure definition
		77	*/
		78	typedef struct
		79	{
		80	uint32_t OCMode; /*!< Specifies the TIM mode.
		81	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		82
		83	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		84	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		85
		86	uint32_t OCPolarity; /*!< Specifies the output polarity.
		87	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		88
		89	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		90	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
		91	@note This parameter is valid only for timer instances supporting break feature. */
		92
		93	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
		94	This parameter can be a value of @ref TIM_Output_Fast_State
		95	@note This parameter is valid only in PWM1 and PWM2 mode. */
		96
		97
		98	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		99	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
		100	@note This parameter is valid only for timer instances supporting break feature. */
		101
		102	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		103	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
		104	@note This parameter is valid only for timer instances supporting break feature. */
		105	} TIM_OC_InitTypeDef;
		106
		107	/**
		108	* @brief TIM One Pulse Mode Configuration Structure definition
		109	*/
		110	typedef struct
		111	{
		112	uint32_t OCMode; /*!< Specifies the TIM mode.
		113	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
		114
		115	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
		116	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
		117
		118	uint32_t OCPolarity; /*!< Specifies the output polarity.
		119	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
		120
		121	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
		122	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
		123	@note This parameter is valid only for timer instances supporting break feature. */
		124
		125	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		126	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
		127	@note This parameter is valid only for timer instances supporting break feature. */
		128
		129	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
		130	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
		131	@note This parameter is valid only for timer instances supporting break feature. */
		132
		133	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		134	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		135
		136	uint32_t ICSelection; /*!< Specifies the input.
		137	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		138
		139	uint32_t ICFilter; /*!< Specifies the input capture filter.
		140	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		141	} TIM_OnePulse_InitTypeDef;
		142
		143	/**
		144	* @brief TIM Input Capture Configuration Structure definition
		145	*/
		146	typedef struct
		147	{
		148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
		149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
		150
		151	uint32_t ICSelection; /*!< Specifies the input.
		152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		153
		154	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
		155	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		156
		157	uint32_t ICFilter; /*!< Specifies the input capture filter.
		158	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		159	} TIM_IC_InitTypeDef;
		160
		161	/**
		162	* @brief TIM Encoder Configuration Structure definition
		163	*/
		164	typedef struct
		165	{
		166	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
		167	This parameter can be a value of @ref TIM_Encoder_Mode */
		168
		169	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
		170	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
		171
		172	uint32_t IC1Selection; /*!< Specifies the input.
		173	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		174
		175	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
		176	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		177
		178	uint32_t IC1Filter; /*!< Specifies the input capture filter.
		179	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		180
		181	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
		182	This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
		183
		184	uint32_t IC2Selection; /*!< Specifies the input.
		185	This parameter can be a value of @ref TIM_Input_Capture_Selection */
		186
		187	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
		188	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
		189
		190	uint32_t IC2Filter; /*!< Specifies the input capture filter.
		191	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		192	} TIM_Encoder_InitTypeDef;
		193
		194	/**
		195	* @brief Clock Configuration Handle Structure definition
		196	*/
		197	typedef struct
		198	{
		199	uint32_t ClockSource; /*!< TIM clock sources
		200	This parameter can be a value of @ref TIM_Clock_Source */
		201	uint32_t ClockPolarity; /*!< TIM clock polarity
		202	This parameter can be a value of @ref TIM_Clock_Polarity */
		203	uint32_t ClockPrescaler; /*!< TIM clock prescaler
		204	This parameter can be a value of @ref TIM_Clock_Prescaler */
		205	uint32_t ClockFilter; /*!< TIM clock filter
		206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		207	} TIM_ClockConfigTypeDef;
		208
		209	/**
		210	* @brief TIM Clear Input Configuration Handle Structure definition
		211	*/
		212	typedef struct
		213	{
		214	uint32_t ClearInputState; /*!< TIM clear Input state
		215	This parameter can be ENABLE or DISABLE */
		216	uint32_t ClearInputSource; /*!< TIM clear Input sources
		217	This parameter can be a value of @ref TIM_ClearInput_Source */
		218	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
		219	This parameter can be a value of @ref TIM_ClearInput_Polarity */
		220	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
		221	This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
		222	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
		223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		224	} TIM_ClearInputConfigTypeDef;
		225
		226	/**
		227	* @brief TIM Master configuration Structure definition
		228	*/
		229	typedef struct
		230	{
		231	uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
		232	This parameter can be a value of @ref TIM_Master_Mode_Selection */
		233	uint32_t MasterSlaveMode; /*!< Master/slave mode selection
		234	This parameter can be a value of @ref TIM_Master_Slave_Mode
		235	@note When the Master/slave mode is enabled, the effect of
		236	an event on the trigger input (TRGI) is delayed to allow a
		237	perfect synchronization between the current timer and its
		238	slaves (through TRGO). It is not mandatory in case of timer
		239	synchronization mode. */
		240	} TIM_MasterConfigTypeDef;
		241
		242	/**
		243	* @brief TIM Slave configuration Structure definition
		244	*/
		245	typedef struct
		246	{
		247	uint32_t SlaveMode; /*!< Slave mode selection
		248	This parameter can be a value of @ref TIM_Slave_Mode */
		249	uint32_t InputTrigger; /*!< Input Trigger source
		250	This parameter can be a value of @ref TIM_Trigger_Selection */
		251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
		252	This parameter can be a value of @ref TIM_Trigger_Polarity */
		253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
		254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
		255	uint32_t TriggerFilter; /*!< Input trigger filter
		256	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		257
		258	} TIM_SlaveConfigTypeDef;
		259
		260	/**
		261	* @brief TIM Break input(s) and Dead time configuration Structure definition
		262	* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
		263	* filter and polarity.
		264	*/
		265	typedef struct
		266	{
		267	uint32_t OffStateRunMode; /*!< TIM off state in run mode
		268	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
		269	uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
		270	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
		271	uint32_t LockLevel; /*!< TIM Lock level
		272	This parameter can be a value of @ref TIM_Lock_level */
		273	uint32_t DeadTime; /*!< TIM dead Time
		274	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
		275	uint32_t BreakState; /*!< TIM Break State
		276	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
		277	uint32_t BreakPolarity; /*!< TIM Break input polarity
		278	This parameter can be a value of @ref TIM_Break_Polarity */
		279	uint32_t BreakFilter; /*!< Specifies the break input filter.
		280	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
		281	uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
		282	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
		283	} TIM_BreakDeadTimeConfigTypeDef;
		284
		285	/**
		286	* @brief HAL State structures definition
		287	*/
		288	typedef enum
		289	{
		290	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
		291	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
		292	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
		293	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
		294	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
		295	} HAL_TIM_StateTypeDef;
		296
		297	/**
		298	* @brief HAL Active channel structures definition
		299	*/
		300	typedef enum
		301	{
		302	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
		303	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
		304	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
		305	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
		306	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
		307	} HAL_TIM_ActiveChannel;
		308
		309	/**
		310	* @brief TIM Time Base Handle Structure definition
		311	*/
		312	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		313	typedef struct __TIM_HandleTypeDef
		314	#else
		315	typedef struct
		316	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		317	{
		318	TIM_TypeDef Instance; /!< Register base address */
		319	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
		320	HAL_TIM_ActiveChannel Channel; /!< Active channel /
		321	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
		322	This array is accessed by a @ref DMA_Handle_index */
		323	HAL_LockTypeDef Lock; /!< Locking object /
		324	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
		325
		326	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		327	void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp Init Callback */
		328	void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Base Msp DeInit Callback */
		329	void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp Init Callback */
		330	void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM IC Msp DeInit Callback */
		331	void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp Init Callback */
		332	void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM OC Msp DeInit Callback */
		333	void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp Init Callback */
		334	void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Msp DeInit Callback */
		335	void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp Init Callback */
		336	void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM One Pulse Msp DeInit Callback */
		337	void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp Init Callback */
		338	void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Encoder Msp DeInit Callback */
		339	void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp Init Callback */
		340	void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Hall Sensor Msp DeInit Callback */
		341	void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed Callback */
		342	void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Period Elapsed half complete Callback */
		343	void (* TriggerCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger Callback */
		344	void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Trigger half complete Callback */
		345	void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture Callback */
		346	void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Input Capture half complete Callback */
		347	void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Output Compare Delay Elapsed Callback */
		348	void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished Callback */
		349	void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM PWM Pulse Finished half complete Callback */
		350	void (* ErrorCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Error Callback */
		351	void (* CommutationCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation Callback */
		352	void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Commutation half complete Callback */
		353	void (* BreakCallback)(struct __TIM_HandleTypeDef htim); /!< TIM Break Callback */
		354	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		355	} TIM_HandleTypeDef;
		356
		357	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		358	/**
		359	* @brief HAL TIM Callback ID enumeration definition
		360	*/
		361	typedef enum
		362	{
		363	HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /!< TIM Base MspInit Callback ID /
		364	,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /!< TIM Base MspDeInit Callback ID /
		365	,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /!< TIM IC MspInit Callback ID /
		366	,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /!< TIM IC MspDeInit Callback ID /
		367	,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /!< TIM OC MspInit Callback ID /
		368	,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /!< TIM OC MspDeInit Callback ID /
		369	,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /!< TIM PWM MspInit Callback ID /
		370	,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /!< TIM PWM MspDeInit Callback ID /
		371	,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /!< TIM One Pulse MspInit Callback ID /
		372	,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /!< TIM One Pulse MspDeInit Callback ID /
		373	,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /!< TIM Encoder MspInit Callback ID /
		374	,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /!< TIM Encoder MspDeInit Callback ID /
		375	,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /!< TIM Hall Sensor MspDeInit Callback ID /
		376	,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /!< TIM Hall Sensor MspDeInit Callback ID /
		377	,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /!< TIM Period Elapsed Callback ID /
		378	,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /!< TIM Period Elapsed half complete Callback ID /
		379	,HAL_TIM_TRIGGER_CB_ID = 0x10U /!< TIM Trigger Callback ID /
		380	,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /!< TIM Trigger half complete Callback ID /
		381
		382	,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /!< TIM Input Capture Callback ID /
		383	,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /!< TIM Input Capture half complete Callback ID /
		384	,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /!< TIM Output Compare Delay Elapsed Callback ID /
		385	,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /!< TIM PWM Pulse Finished Callback ID /
		386	,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /!< TIM PWM Pulse Finished half complete Callback ID /
		387	,HAL_TIM_ERROR_CB_ID = 0x17U /!< TIM Error Callback ID /
		388	,HAL_TIM_COMMUTATION_CB_ID = 0x18U /!< TIM Commutation Callback ID /
		389	,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /!< TIM Commutation half complete Callback ID /
		390	,HAL_TIM_BREAK_CB_ID = 0x1AU /!< TIM Break Callback ID /
		391	} HAL_TIM_CallbackIDTypeDef;
		392
		393	/**
		394	* @brief HAL TIM Callback pointer definition
		395	*/
		396	typedef void (pTIM_CallbackTypeDef)(TIM_HandleTypeDef htim); /!< pointer to the TIM callback function /
		397
		398	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		399
		400	/**
		401	* @}
		402	*/
		403	/* End of exported types -----------------------------------------------------*/
		404
		405	/* Exported constants --------------------------------------------------------*/
		406	/** @defgroup TIM_Exported_Constants TIM Exported Constants
		407	* @{
		408	*/
		409
		410	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
		411	* @{
		412	*/
		413	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /!< OCREF_CLR is disabled /
		414	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /!< OCREF_CLR is connected to ETRF input /
		415	#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /!< OCREF_CLR is connected to OCREF_CLR_INT /
		416	/**
		417	* @}
		418	*/
		419
		420	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
		421	* @{
		422	*/
		423	#define TIM_DMABASE_CR1 0x00000000U
		424	#define TIM_DMABASE_CR2 0x00000001U
		425	#define TIM_DMABASE_SMCR 0x00000002U
		426	#define TIM_DMABASE_DIER 0x00000003U
		427	#define TIM_DMABASE_SR 0x00000004U
		428	#define TIM_DMABASE_EGR 0x00000005U
		429	#define TIM_DMABASE_CCMR1 0x00000006U
		430	#define TIM_DMABASE_CCMR2 0x00000007U
		431	#define TIM_DMABASE_CCER 0x00000008U
		432	#define TIM_DMABASE_CNT 0x00000009U
		433	#define TIM_DMABASE_PSC 0x0000000AU
		434	#define TIM_DMABASE_ARR 0x0000000BU
		435	#define TIM_DMABASE_RCR 0x0000000CU
		436	#define TIM_DMABASE_CCR1 0x0000000DU
		437	#define TIM_DMABASE_CCR2 0x0000000EU
		438	#define TIM_DMABASE_CCR3 0x0000000FU
		439	#define TIM_DMABASE_CCR4 0x00000010U
		440	#define TIM_DMABASE_BDTR 0x00000011U
		441	#define TIM_DMABASE_DCR 0x00000012U
		442	#define TIM_DMABASE_DMAR 0x00000013U
		443	/**
		444	* @}
		445	*/
		446
		447	/** @defgroup TIM_Event_Source TIM Event Source
		448	* @{
		449	*/
		450	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /!< Reinitialize the counter and generates an update of the registers /
		451	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /!< A capture/compare event is generated on channel 1 /
		452	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /!< A capture/compare event is generated on channel 2 /
		453	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /!< A capture/compare event is generated on channel 3 /
		454	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /!< A capture/compare event is generated on channel 4 /
		455	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /!< A commutation event is generated /
		456	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /!< A trigger event is generated /
		457	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /!< A break event is generated /
		458	/**
		459	* @}
		460	*/
		461
		462	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
		463	* @{
		464	*/
		465	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
		466	#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /!< Polarity for TIx source /
		467	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
		468	/**
		469	* @}
		470	*/
		471
		472	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
		473	* @{
		474	*/
		475	#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /!< Polarity for ETR source /
		476	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
		477	/**
		478	* @}
		479	*/
		480
		481	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
		482	* @{
		483	*/
		484	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
		485	#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR input source is divided by 2 /
		486	#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR input source is divided by 4 /
		487	#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR input source is divided by 8 /
		488	/**
		489	* @}
		490	*/
		491
		492	/** @defgroup TIM_Counter_Mode TIM Counter Mode
		493	* @{
		494	*/
		495	#define TIM_COUNTERMODE_UP 0x00000000U /!< Counter used as up-counter /
		496	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as down-counter /
		497	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /!< Center-aligned mode 1 /
		498	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /!< Center-aligned mode 2 /
		499	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /!< Center-aligned mode 3 /
		500	/**
		501	* @}
		502	*/
		503
		504	/** @defgroup TIM_ClockDivision TIM Clock Division
		505	* @{
		506	*/
		507	#define TIM_CLOCKDIVISION_DIV1 0x00000000U /!< Clock division: tDTS=tCK_INT /
		508	#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< Clock division: tDTS=2tCK_INT */
		509	#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< Clock division: tDTS=4tCK_INT */
		510	/**
		511	* @}
		512	*/
		513
		514	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
		515	* @{
		516	*/
		517	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /!< Capture/Compare 1 output disabled /
		518	#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /!< Capture/Compare 1 output enabled /
		519	/**
		520	* @}
		521	*/
		522
		523	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
		524	* @{
		525	*/
		526	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /!< TIMx_ARR register is not buffered /
		527	#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /!< TIMx_ARR register is buffered /
		528
		529	/**
		530	* @}
		531	*/
		532
		533	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
		534	* @{
		535	*/
		536	#define TIM_OCFAST_DISABLE 0x00000000U /!< Output Compare fast disable /
		537	#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /!< Output Compare fast enable /
		538	/**
		539	* @}
		540	*/
		541
		542	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
		543	* @{
		544	*/
		545	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /!< OCxN is disabled /
		546	#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /!< OCxN is enabled /
		547	/**
		548	* @}
		549	*/
		550
		551	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
		552	* @{
		553	*/
		554	#define TIM_OCPOLARITY_HIGH 0x00000000U /!< Capture/Compare output polarity /
		555	#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< Capture/Compare output polarity /
		556	/**
		557	* @}
		558	*/
		559
		560	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
		561	* @{
		562	*/
		563	#define TIM_OCNPOLARITY_HIGH 0x00000000U /!< Capture/Compare complementary output polarity /
		564	#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /!< Capture/Compare complementary output polarity /
		565	/**
		566	* @}
		567	*/
		568
		569	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
		570	* @{
		571	*/
		572	#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /!< Output Idle state: OCx=1 when MOE=0 /
		573	#define TIM_OCIDLESTATE_RESET 0x00000000U /!< Output Idle state: OCx=0 when MOE=0 /
		574	/**
		575	* @}
		576	*/
		577
		578	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
		579	* @{
		580	*/
		581	#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /!< Complementary output Idle state: OCxN=1 when MOE=0 /
		582	#define TIM_OCNIDLESTATE_RESET 0x00000000U /!< Complementary output Idle state: OCxN=0 when MOE=0 /
		583	/**
		584	* @}
		585	*/
		586
		587	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
		588	* @{
		589	*/
		590	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Capture triggered by rising edge on timer input /
		591	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Capture triggered by falling edge on timer input /
		592	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Capture triggered by both rising and falling edges on timer input/
		593	/**
		594	* @}
		595	*/
		596
		597	/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
		598	* @{
		599	*/
		600	#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Encoder input with rising edge polarity /
		601	#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Encoder input with falling edge polarity /
		602	/**
		603	* @}
		604	*/
		605
		606	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
		607	* @{
		608	*/
		609	#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
		610	connected to IC1, IC2, IC3 or IC4, respectively */
		611	#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
		612	connected to IC2, IC1, IC4 or IC3, respectively */
		613	#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
		614	/**
		615	* @}
		616	*/
		617
		618	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
		619	* @{
		620	*/
		621	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
		622	#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /!< Capture performed once every 2 events /
		623	#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /!< Capture performed once every 4 events /
		624	#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /!< Capture performed once every 8 events /
		625	/**
		626	* @}
		627	*/
		628
		629	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
		630	* @{
		631	*/
		632	#define TIM_OPMODE_SINGLE TIM_CR1_OPM /!< Counter stops counting at the next update event /
		633	#define TIM_OPMODE_REPETITIVE 0x00000000U /!< Counter is not stopped at update event /
		634	/**
		635	* @}
		636	*/
		637
		638	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
		639	* @{
		640	*/
		641	#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level /
		642	#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. /
		643	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. /
		644	/**
		645	* @}
		646	*/
		647
		648	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
		649	* @{
		650	*/
		651	#define TIM_IT_UPDATE TIM_DIER_UIE /!< Update interrupt /
		652	#define TIM_IT_CC1 TIM_DIER_CC1IE /!< Capture/Compare 1 interrupt /
		653	#define TIM_IT_CC2 TIM_DIER_CC2IE /!< Capture/Compare 2 interrupt /
		654	#define TIM_IT_CC3 TIM_DIER_CC3IE /!< Capture/Compare 3 interrupt /
		655	#define TIM_IT_CC4 TIM_DIER_CC4IE /!< Capture/Compare 4 interrupt /
		656	#define TIM_IT_COM TIM_DIER_COMIE /!< Commutation interrupt /
		657	#define TIM_IT_TRIGGER TIM_DIER_TIE /!< Trigger interrupt /
		658	#define TIM_IT_BREAK TIM_DIER_BIE /!< Break interrupt /
		659	/**
		660	* @}
		661	*/
		662
		663	/** @defgroup TIM_Commutation_Source TIM Commutation Source
		664	* @{
		665	*/
		666	#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input /
		667	#define TIM_COMMUTATION_SOFTWARE 0x00000000U /!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit /
		668	/**
		669	* @}
		670	*/
		671
		672	/** @defgroup TIM_DMA_sources TIM DMA Sources
		673	* @{
		674	*/
		675	#define TIM_DMA_UPDATE TIM_DIER_UDE /!< DMA request is triggered by the update event /
		676	#define TIM_DMA_CC1 TIM_DIER_CC1DE /!< DMA request is triggered by the capture/compare macth 1 event /
		677	#define TIM_DMA_CC2 TIM_DIER_CC2DE /!< DMA request is triggered by the capture/compare macth 2 event event /
		678	#define TIM_DMA_CC3 TIM_DIER_CC3DE /!< DMA request is triggered by the capture/compare macth 3 event event /
		679	#define TIM_DMA_CC4 TIM_DIER_CC4DE /!< DMA request is triggered by the capture/compare macth 4 event event /
		680	#define TIM_DMA_COM TIM_DIER_COMDE /!< DMA request is triggered by the commutation event /
		681	#define TIM_DMA_TRIGGER TIM_DIER_TDE /!< DMA request is triggered by the trigger event /
		682	/**
		683	* @}
		684	*/
		685
		686	/** @defgroup TIM_Flag_definition TIM Flag Definition
		687	* @{
		688	*/
		689	#define TIM_FLAG_UPDATE TIM_SR_UIF /!< Update interrupt flag /
		690	#define TIM_FLAG_CC1 TIM_SR_CC1IF /!< Capture/Compare 1 interrupt flag /
		691	#define TIM_FLAG_CC2 TIM_SR_CC2IF /!< Capture/Compare 2 interrupt flag /
		692	#define TIM_FLAG_CC3 TIM_SR_CC3IF /!< Capture/Compare 3 interrupt flag /
		693	#define TIM_FLAG_CC4 TIM_SR_CC4IF /!< Capture/Compare 4 interrupt flag /
		694	#define TIM_FLAG_COM TIM_SR_COMIF /!< Commutation interrupt flag /
		695	#define TIM_FLAG_TRIGGER TIM_SR_TIF /!< Trigger interrupt flag /
		696	#define TIM_FLAG_BREAK TIM_SR_BIF /!< Break interrupt flag /
		697	#define TIM_FLAG_CC1OF TIM_SR_CC1OF /!< Capture 1 overcapture flag /
		698	#define TIM_FLAG_CC2OF TIM_SR_CC2OF /!< Capture 2 overcapture flag /
		699	#define TIM_FLAG_CC3OF TIM_SR_CC3OF /!< Capture 3 overcapture flag /
		700	#define TIM_FLAG_CC4OF TIM_SR_CC4OF /!< Capture 4 overcapture flag /
		701	/**
		702	* @}
		703	*/
		704
		705	/** @defgroup TIM_Channel TIM Channel
		706	* @{
		707	*/
		708	#define TIM_CHANNEL_1 0x00000000U /!< Capture/compare channel 1 identifier /
		709	#define TIM_CHANNEL_2 0x00000004U /!< Capture/compare channel 2 identifier /
		710	#define TIM_CHANNEL_3 0x00000008U /!< Capture/compare channel 3 identifier /
		711	#define TIM_CHANNEL_4 0x0000000CU /!< Capture/compare channel 4 identifier /
		712	#define TIM_CHANNEL_ALL 0x0000003CU /!< Global Capture/compare channel identifier /
		713	/**
		714	* @}
		715	*/
		716
		717	/** @defgroup TIM_Clock_Source TIM Clock Source
		718	* @{
		719	*/
		720	#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /!< External clock source mode 2 /
		721	#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /!< Internal clock source /
		722	#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /!< External clock source mode 1 (ITR0) /
		723	#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /!< External clock source mode 1 (ITR1) /
		724	#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /!< External clock source mode 1 (ITR2) /
		725	#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /!< External clock source mode 1 (ITR3) /
		726	#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /!< External clock source mode 1 (TTI1FP1 + edge detect.) /
		727	#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /!< External clock source mode 1 (TTI1FP1) /
		728	#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /!< External clock source mode 1 (TTI2FP2) /
		729	#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /!< External clock source mode 1 (ETRF) /
		730	/**
		731	* @}
		732	*/
		733
		734	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
		735	* @{
		736	*/
		737	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
		738	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
		739	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
		740	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
		741	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
		742	/**
		743	* @}
		744	*/
		745
		746	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
		747	* @{
		748	*/
		749	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		750	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
		751	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
		752	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
		753	/**
		754	* @}
		755	*/
		756
		757	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
		758	* @{
		759	*/
		760	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
		761	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
		762	/**
		763	* @}
		764	*/
		765
		766	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
		767	* @{
		768	*/
		769	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		770	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
		771	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
		772	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
		773	/**
		774	* @}
		775	*/
		776
		777	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
		778	* @{
		779	*/
		780	#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		781	#define TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
		782	/**
		783	* @}
		784	*/
		785
		786	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
		787	* @{
		788	*/
		789	#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) /
		790	#define TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) /
		791	/**
		792	* @}
		793	*/
		794	/** @defgroup TIM_Lock_level TIM Lock level
		795	* @{
		796	*/
		797	#define TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF /
		798	#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
		799	#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
		800	#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
		801	/**
		802	* @}
		803	*/
		804
		805	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
		806	* @{
		807	*/
		808	#define TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break input BRK is enabled /
		809	#define TIM_BREAK_DISABLE 0x00000000U /!< Break input BRK is disabled /
		810	/**
		811	* @}
		812	*/
		813
		814	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
		815	* @{
		816	*/
		817	#define TIM_BREAKPOLARITY_LOW 0x00000000U /!< Break input BRK is active low /
		818	#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
		819	/**
		820	* @}
		821	*/
		822
		823	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
		824	* @{
		825	*/
		826	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
		827	#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
		828	(if none of the break inputs BRK and BRK2 is active) */
		829	/**
		830	* @}
		831	*/
		832
		833	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
		834	* @{
		835	*/
		836	#define TIM_TRGO_RESET 0x00000000U /!< TIMx_EGR.UG bit is used as trigger output (TRGO) /
		837	#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< TIMx_CR1.CEN bit is used as trigger output (TRGO) /
		838	#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output (TRGO) /
		839	#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< Capture or a compare match 1 is used as trigger output (TRGO) /
		840	#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output (TRGO) /
		841	#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output(TRGO) /
		842	#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output(TRGO) /
		843	#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output(TRGO) /
		844	/**
		845	* @}
		846	*/
		847
		848	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
		849	* @{
		850	*/
		851	#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /!< No action /
		852	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /!< Master/slave mode is selected /
		853	/**
		854	* @}
		855	*/
		856
		857	/** @defgroup TIM_Slave_Mode TIM Slave mode
		858	* @{
		859	*/
		860	#define TIM_SLAVEMODE_DISABLE 0x00000000U /!< Slave mode disabled /
		861	#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode /
		862	#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode /
		863	#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode /
		864	#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< External Clock Mode 1 /
		865	/**
		866	* @}
		867	*/
		868
		869	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
		870	* @{
		871	*/
		872	#define TIM_OCMODE_TIMING 0x00000000U /!< Frozen /
		873	#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!< Set channel to active level on match /
		874	#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!< Set channel to inactive level on match /
		875	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< Toggle /
		876	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!< PWM mode 1 /
		877	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!< PWM mode 2 /
		878	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!< Force active level /
		879	#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!< Force inactive level /
		880	/**
		881	* @}
		882	*/
		883
		884	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
		885	* @{
		886	*/
		887	#define TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) /
		888	#define TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) /
		889	#define TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) /
		890	#define TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) /
		891	#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) /
		892	#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 1 (TI1FP1) /
		893	#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered Timer Input 2 (TI2FP2) /
		894	#define TIM_TS_ETRF (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_2) /!< Filtered External Trigger input (ETRF) /
		895	#define TIM_TS_NONE 0x0000FFFFU /!< No trigger selected /
		896	/**
		897	* @}
		898	*/
		899
		900	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
		901	* @{
		902	*/
		903	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
		904	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
		905	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		906	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
		907	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
		908	/**
		909	* @}
		910	*/
		911
		912	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
		913	* @{
		914	*/
		915	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
		916	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
		917	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
		918	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
		919	/**
		920	* @}
		921	*/
		922
		923	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
		924	* @{
		925	*/
		926	#define TIM_TI1SELECTION_CH1 0x00000000U /!< The TIMx_CH1 pin is connected to TI1 input /
		927	#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) /
		928	/**
		929	* @}
		930	*/
		931
		932	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
		933	* @{
		934	*/
		935	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA /
		936	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		937	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		938	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		939	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		940	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		941	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		942	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		943	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		944	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		945	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		946	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		947	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		948	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		949	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		950	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		951	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		952	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA /
		953	/**
		954	* @}
		955	*/
		956
		957	/** @defgroup DMA_Handle_index TIM DMA Handle Index
		958	* @{
		959	*/
		960	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /!< Index of the DMA handle used for Update DMA requests /
		961	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
		962	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
		963	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
		964	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
		965	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /!< Index of the DMA handle used for Commutation DMA requests /
		966	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /!< Index of the DMA handle used for Trigger DMA requests /
		967	/**
		968	* @}
		969	*/
		970
		971	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
		972	* @{
		973	*/
		974	#define TIM_CCx_ENABLE 0x00000001U /!< Input or output channel is enabled /
		975	#define TIM_CCx_DISABLE 0x00000000U /!< Input or output channel is disabled /
		976	#define TIM_CCxN_ENABLE 0x00000004U /!< Complementary output channel is enabled /
		977	#define TIM_CCxN_DISABLE 0x00000000U /!< Complementary output channel is enabled /
		978	/**
		979	* @}
		980	*/
		981
		982	/**
		983	* @}
		984	*/
		985	/* End of exported constants -------------------------------------------------*/
		986
		987	/* Exported macros -----------------------------------------------------------*/
		988	/** @defgroup TIM_Exported_Macros TIM Exported Macros
		989	* @{
		990	*/
		991
		992	/** @brief Reset TIM handle state.
		993	* @param __HANDLE__ TIM handle.
		994	* @retval None
		995	*/
		996	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		997	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
		998	(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
		999	(__HANDLE__)->Base_MspInitCallback = NULL; \
		1000	(__HANDLE__)->Base_MspDeInitCallback = NULL; \
		1001	(__HANDLE__)->IC_MspInitCallback = NULL; \
		1002	(__HANDLE__)->IC_MspDeInitCallback = NULL; \
		1003	(__HANDLE__)->OC_MspInitCallback = NULL; \
		1004	(__HANDLE__)->OC_MspDeInitCallback = NULL; \
		1005	(__HANDLE__)->PWM_MspInitCallback = NULL; \
		1006	(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
		1007	(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
		1008	(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
		1009	(__HANDLE__)->Encoder_MspInitCallback = NULL; \
		1010	(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
		1011	(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
		1012	(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
		1013	} while(0)
		1014	#else
		1015	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
		1016	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1017
		1018	/**
		1019	* @brief Enable the TIM peripheral.
		1020	* @param __HANDLE__ TIM handle
		1021	* @retval None
		1022	*/
		1023	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
		1024
		1025	/**
		1026	* @brief Enable the TIM main Output.
		1027	* @param __HANDLE__ TIM handle
		1028	* @retval None
		1029	*/
		1030	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
		1031
		1032	/**
		1033	* @brief Disable the TIM peripheral.
		1034	* @param __HANDLE__ TIM handle
		1035	* @retval None
		1036	*/
		1037	#define __HAL_TIM_DISABLE(__HANDLE__) \
		1038	do { \
		1039	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1040	{ \
		1041	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1042	{ \
		1043	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
		1044	} \
		1045	} \
		1046	} while(0)
		1047
		1048	/**
		1049	* @brief Disable the TIM main Output.
		1050	* @param __HANDLE__ TIM handle
		1051	* @retval None
		1052	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
		1053	*/
		1054	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
		1055	do { \
		1056	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
		1057	{ \
		1058	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
		1059	{ \
		1060	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
		1061	} \
		1062	} \
		1063	} while(0)
		1064
		1065	/**
		1066	* @brief Disable the TIM main Output.
		1067	* @param __HANDLE__ TIM handle
		1068	* @retval None
		1069	* @note The Main Output Enable of a timer instance is disabled unconditionally
		1070	*/
		1071	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
		1072
		1073	/** @brief Enable the specified TIM interrupt.
		1074	* @param __HANDLE__ specifies the TIM Handle.
		1075	* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
		1076	* This parameter can be one of the following values:
		1077	* @arg TIM_IT_UPDATE: Update interrupt
		1078	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1079	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1080	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1081	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1082	* @arg TIM_IT_COM: Commutation interrupt
		1083	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1084	* @arg TIM_IT_BREAK: Break interrupt
		1085	* @retval None
		1086	*/
		1087	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
		1088
		1089	/** @brief Disable the specified TIM interrupt.
		1090	* @param __HANDLE__ specifies the TIM Handle.
		1091	* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
		1092	* This parameter can be one of the following values:
		1093	* @arg TIM_IT_UPDATE: Update interrupt
		1094	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1095	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1096	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1097	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1098	* @arg TIM_IT_COM: Commutation interrupt
		1099	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1100	* @arg TIM_IT_BREAK: Break interrupt
		1101	* @retval None
		1102	*/
		1103	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
		1104
		1105	/** @brief Enable the specified DMA request.
		1106	* @param __HANDLE__ specifies the TIM Handle.
		1107	* @param __DMA__ specifies the TIM DMA request to enable.
		1108	* This parameter can be one of the following values:
		1109	* @arg TIM_DMA_UPDATE: Update DMA request
		1110	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		1111	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1112	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1113	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		1114	* @arg TIM_DMA_COM: Commutation DMA request
		1115	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1116	* @retval None
		1117	*/
		1118	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
		1119
		1120	/** @brief Disable the specified DMA request.
		1121	* @param __HANDLE__ specifies the TIM Handle.
		1122	* @param __DMA__ specifies the TIM DMA request to disable.
		1123	* This parameter can be one of the following values:
		1124	* @arg TIM_DMA_UPDATE: Update DMA request
		1125	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
		1126	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
		1127	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
		1128	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
		1129	* @arg TIM_DMA_COM: Commutation DMA request
		1130	* @arg TIM_DMA_TRIGGER: Trigger DMA request
		1131	* @retval None
		1132	*/
		1133	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
		1134
		1135	/** @brief Check whether the specified TIM interrupt flag is set or not.
		1136	* @param __HANDLE__ specifies the TIM Handle.
		1137	* @param __FLAG__ specifies the TIM interrupt flag to check.
		1138	* This parameter can be one of the following values:
		1139	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1140	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1141	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1142	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1143	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1144	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1145	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		1146	* @arg TIM_FLAG_BREAK: Break interrupt flag
		1147	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1148	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1149	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1150	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1151	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1152	*/
		1153	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
		1154
		1155	/** @brief Clear the specified TIM interrupt flag.
		1156	* @param __HANDLE__ specifies the TIM Handle.
		1157	* @param __FLAG__ specifies the TIM interrupt flag to clear.
		1158	* This parameter can be one of the following values:
		1159	* @arg TIM_FLAG_UPDATE: Update interrupt flag
		1160	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
		1161	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
		1162	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
		1163	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
		1164	* @arg TIM_FLAG_COM: Commutation interrupt flag
		1165	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
		1166	* @arg TIM_FLAG_BREAK: Break interrupt flag
		1167	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
		1168	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
		1169	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
		1170	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
		1171	* @retval The new state of __FLAG__ (TRUE or FALSE).
		1172	*/
		1173	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
		1174
		1175	/**
		1176	* @brief Check whether the specified TIM interrupt source is enabled or not.
		1177	* @param __HANDLE__ TIM handle
		1178	* @param __INTERRUPT__ specifies the TIM interrupt source to check.
		1179	* This parameter can be one of the following values:
		1180	* @arg TIM_IT_UPDATE: Update interrupt
		1181	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1182	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1183	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1184	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1185	* @arg TIM_IT_COM: Commutation interrupt
		1186	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1187	* @arg TIM_IT_BREAK: Break interrupt
		1188	* @retval The state of TIM_IT (SET or RESET).
		1189	*/
		1190	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
		1191	== (__INTERRUPT__)) ? SET : RESET)
		1192
		1193	/** @brief Clear the TIM interrupt pending bits.
		1194	* @param __HANDLE__ TIM handle
		1195	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
		1196	* This parameter can be one of the following values:
		1197	* @arg TIM_IT_UPDATE: Update interrupt
		1198	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
		1199	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
		1200	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
		1201	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
		1202	* @arg TIM_IT_COM: Commutation interrupt
		1203	* @arg TIM_IT_TRIGGER: Trigger interrupt
		1204	* @arg TIM_IT_BREAK: Break interrupt
		1205	* @retval None
		1206	*/
		1207	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
		1208
		1209	/**
		1210	* @brief Indicates whether or not the TIM Counter is used as downcounter.
		1211	* @param __HANDLE__ TIM handle.
		1212	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
		1213	* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
		1214	mode.
		1215	*/
		1216	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
		1217
		1218	/**
		1219	* @brief Set the TIM Prescaler on runtime.
		1220	* @param __HANDLE__ TIM handle.
		1221	* @param __PRESC__ specifies the Prescaler new value.
		1222	* @retval None
		1223	*/
		1224	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
		1225
		1226	/**
		1227	* @brief Set the TIM Counter Register value on runtime.
		1228	* @param __HANDLE__ TIM handle.
		1229	* @param __COUNTER__ specifies the Counter register new value.
		1230	* @retval None
		1231	*/
		1232	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
		1233
		1234	/**
		1235	* @brief Get the TIM Counter Register value on runtime.
		1236	* @param __HANDLE__ TIM handle.
		1237	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
		1238	*/
		1239	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
		1240
		1241	/**
		1242	* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
		1243	* @param __HANDLE__ TIM handle.
		1244	* @param __AUTORELOAD__ specifies the Counter register new value.
		1245	* @retval None
		1246	*/
		1247	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
		1248	do{ \
		1249	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
		1250	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
		1251	} while(0)
		1252
		1253	/**
		1254	* @brief Get the TIM Autoreload Register value on runtime.
		1255	* @param __HANDLE__ TIM handle.
		1256	* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
		1257	*/
		1258	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
		1259
		1260	/**
		1261	* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
		1262	* @param __HANDLE__ TIM handle.
		1263	* @param __CKD__ specifies the clock division value.
		1264	* This parameter can be one of the following value:
		1265	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1266	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1267	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
		1268	* @retval None
		1269	*/
		1270	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
		1271	do{ \
		1272	(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
		1273	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
		1274	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
		1275	} while(0)
		1276
		1277	/**
		1278	* @brief Get the TIM Clock Division value on runtime.
		1279	* @param __HANDLE__ TIM handle.
		1280	* @retval The clock division can be one of the following values:
		1281	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
		1282	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
		1283	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
		1284	*/
		1285	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
		1286
		1287	/**
		1288	* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
		1289	* @param __HANDLE__ TIM handle.
		1290	* @param __CHANNEL__ TIM Channels to be configured.
		1291	* This parameter can be one of the following values:
		1292	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1293	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1294	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1295	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1296	* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
		1297	* This parameter can be one of the following values:
		1298	* @arg TIM_ICPSC_DIV1: no prescaler
		1299	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1300	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1301	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1302	* @retval None
		1303	*/
		1304	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1305	do{ \
		1306	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
		1307	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
		1308	} while(0)
		1309
		1310	/**
		1311	* @brief Get the TIM Input Capture prescaler on runtime.
		1312	* @param __HANDLE__ TIM handle.
		1313	* @param __CHANNEL__ TIM Channels to be configured.
		1314	* This parameter can be one of the following values:
		1315	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
		1316	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
		1317	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
		1318	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
		1319	* @retval The input capture prescaler can be one of the following values:
		1320	* @arg TIM_ICPSC_DIV1: no prescaler
		1321	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
		1322	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
		1323	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
		1324	*/
		1325	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
		1326	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
		1327	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
		1328	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
		1329	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
		1330
		1331	/**
		1332	* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
		1333	* @param __HANDLE__ TIM handle.
		1334	* @param __CHANNEL__ TIM Channels to be configured.
		1335	* This parameter can be one of the following values:
		1336	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1337	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1338	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1339	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1340	* @param __COMPARE__ specifies the Capture Compare register new value.
		1341	* @retval None
		1342	*/
		1343	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
		1344	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
		1345	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
		1346	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
		1347	((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
		1348
		1349	/**
		1350	* @brief Get the TIM Capture Compare Register value on runtime.
		1351	* @param __HANDLE__ TIM handle.
		1352	* @param __CHANNEL__ TIM Channel associated with the capture compare register
		1353	* This parameter can be one of the following values:
		1354	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
		1355	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
		1356	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
		1357	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
		1358	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
		1359	*/
		1360	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
		1361	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
		1362	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
		1363	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
		1364	((__HANDLE__)->Instance->CCR4))
		1365
		1366	/**
		1367	* @brief Set the TIM Output compare preload.
		1368	* @param __HANDLE__ TIM handle.
		1369	* @param __CHANNEL__ TIM Channels to be configured.
		1370	* This parameter can be one of the following values:
		1371	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1372	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1373	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1374	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1375	* @retval None
		1376	*/
		1377	#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1378	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1PE) :\
		1379	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2PE) :\
		1380	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3PE) :\
		1381	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4PE))
		1382
		1383	/**
		1384	* @brief Reset the TIM Output compare preload.
		1385	* @param __HANDLE__ TIM handle.
		1386	* @param __CHANNEL__ TIM Channels to be configured.
		1387	* This parameter can be one of the following values:
		1388	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1389	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1390	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1391	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1392	* @retval None
		1393	*/
		1394	#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
		1395	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
		1396	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
		1397	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
		1398	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
		1399
		1400	/**
		1401	* @brief Enable fast mode for a given channel.
		1402	* @param __HANDLE__ TIM handle.
		1403	* @param __CHANNEL__ TIM Channels to be configured.
		1404	* This parameter can be one of the following values:
		1405	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1406	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1407	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1408	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1409	* @note When fast mode is enabled an active edge on the trigger input acts
		1410	* like a compare match on CCx output. Delay to sample the trigger
		1411	* input and to activate CCx output is reduced to 3 clock cycles.
		1412	* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
		1413	* @retval None
		1414	*/
		1415	#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1416	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC1FE) :\
		1417	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= TIM_CCMR1_OC2FE) :\
		1418	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC3FE) :\
		1419	((__HANDLE__)->Instance->CCMR2 \|= TIM_CCMR2_OC4FE))
		1420
		1421	/**
		1422	* @brief Disable fast mode for a given channel.
		1423	* @param __HANDLE__ TIM handle.
		1424	* @param __CHANNEL__ TIM Channels to be configured.
		1425	* This parameter can be one of the following values:
		1426	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1427	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1428	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1429	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1430	* @note When fast mode is disabled CCx output behaves normally depending
		1431	* on counter and CCRx values even when the trigger is ON. The minimum
		1432	* delay to activate CCx output when an active edge occurs on the
		1433	* trigger input is 5 clock cycles.
		1434	* @retval None
		1435	*/
		1436	#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
		1437	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
		1438	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
		1439	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
		1440	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
		1441
		1442	/**
		1443	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
		1444	* @param __HANDLE__ TIM handle.
		1445	* @note When the URS bit of the TIMx_CR1 register is set, only counter
		1446	* overflow/underflow generates an update interrupt or DMA request (if
		1447	* enabled)
		1448	* @retval None
		1449	*/
		1450	#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|= TIM_CR1_URS)
		1451
		1452	/**
		1453	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
		1454	* @param __HANDLE__ TIM handle.
		1455	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
		1456	* following events generate an update interrupt or DMA request (if
		1457	* enabled):
		1458	* _ Counter overflow underflow
		1459	* _ Setting the UG bit
		1460	* _ Update generation through the slave mode controller
		1461	* @retval None
		1462	*/
		1463	#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
		1464
		1465	/**
		1466	* @brief Set the TIM Capture x input polarity on runtime.
		1467	* @param __HANDLE__ TIM handle.
		1468	* @param __CHANNEL__ TIM Channels to be configured.
		1469	* This parameter can be one of the following values:
		1470	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
		1471	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
		1472	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
		1473	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
		1474	* @param __POLARITY__ Polarity for TIx source
		1475	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
		1476	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
		1477	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
		1478	* @retval None
		1479	*/
		1480	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1481	do{ \
		1482	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
		1483	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
		1484	}while(0)
		1485
		1486	/**
		1487	* @}
		1488	*/
		1489	/* End of exported macros ----------------------------------------------------*/
		1490
		1491	/* Private constants ---------------------------------------------------------*/
		1492	/** @defgroup TIM_Private_Constants TIM Private Constants
		1493	* @{
		1494	*/
		1495	/* The counter of a timer instance is disabled only if all the CCx and CCxN
		1496	channels have been disabled */
		1497	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
		1498	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
		1499	/**
		1500	* @}
		1501	*/
		1502	/* End of private constants --------------------------------------------------*/
		1503
		1504	/* Private macros ------------------------------------------------------------*/
		1505	/** @defgroup TIM_Private_Macros TIM Private Macros
		1506	* @{
		1507	*/
		1508	#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
		1509	((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
		1510	((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
		1511
		1512	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
		1513	((__BASE__) == TIM_DMABASE_CR2) \|\| \
		1514	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
		1515	((__BASE__) == TIM_DMABASE_DIER) \|\| \
		1516	((__BASE__) == TIM_DMABASE_SR) \|\| \
		1517	((__BASE__) == TIM_DMABASE_EGR) \|\| \
		1518	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
		1519	((__BASE__) == TIM_DMABASE_CCMR2) \|\| \
		1520	((__BASE__) == TIM_DMABASE_CCER) \|\| \
		1521	((__BASE__) == TIM_DMABASE_CNT) \|\| \
		1522	((__BASE__) == TIM_DMABASE_PSC) \|\| \
		1523	((__BASE__) == TIM_DMABASE_ARR) \|\| \
		1524	((__BASE__) == TIM_DMABASE_RCR) \|\| \
		1525	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
		1526	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
		1527	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
		1528	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
		1529	((__BASE__) == TIM_DMABASE_BDTR))
		1530
		1531	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1532
		1533	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
		1534	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
		1535	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
		1536	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
		1537	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
		1538
		1539	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
		1540	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
		1541	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
		1542
		1543	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
		1544	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
		1545
		1546	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
		1547	((__STATE__) == TIM_OCFAST_ENABLE))
		1548
		1549	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
		1550	((__POLARITY__) == TIM_OCPOLARITY_LOW))
		1551
		1552	#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) \|\| \
		1553	((__POLARITY__) == TIM_OCNPOLARITY_LOW))
		1554
		1555	#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) \|\| \
		1556	((__STATE__) == TIM_OCIDLESTATE_RESET))
		1557
		1558	#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) \|\| \
		1559	((__STATE__) == TIM_OCNIDLESTATE_RESET))
		1560
		1561	#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) \|\| \
		1562	((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
		1563
		1564	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
		1565	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
		1566	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
		1567
		1568	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
		1569	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
		1570	((__SELECTION__) == TIM_ICSELECTION_TRC))
		1571
		1572	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
		1573	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
		1574	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
		1575	((__PRESCALER__) == TIM_ICPSC_DIV8))
		1576
		1577	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
		1578	((__MODE__) == TIM_OPMODE_REPETITIVE))
		1579
		1580	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
		1581	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
		1582	((__MODE__) == TIM_ENCODERMODE_TI12))
		1583
		1584	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
		1585
		1586	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1587	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1588	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
		1589	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
		1590	((__CHANNEL__) == TIM_CHANNEL_ALL))
		1591
		1592	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1593	((__CHANNEL__) == TIM_CHANNEL_2))
		1594
		1595	#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
		1596	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
		1597	((__CHANNEL__) == TIM_CHANNEL_3))
		1598
		1599	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
		1600	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
		1601	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
		1602	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
		1603	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
		1604	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
		1605	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
		1606	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
		1607	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
		1608	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
		1609
		1610	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
		1611	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
		1612	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
		1613	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
		1614	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
		1615
		1616	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
		1617	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
		1618	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
		1619	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
		1620
		1621	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1622
		1623	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
		1624	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
		1625
		1626	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
		1627	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
		1628	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
		1629	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
		1630
		1631	#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1632
		1633	#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) \|\| \
		1634	((__STATE__) == TIM_OSSR_DISABLE))
		1635
		1636	#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) \|\| \
		1637	((__STATE__) == TIM_OSSI_DISABLE))
		1638
		1639	#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) \|\| \
		1640	((__LEVEL__) == TIM_LOCKLEVEL_1) \|\| \
		1641	((__LEVEL__) == TIM_LOCKLEVEL_2) \|\| \
		1642	((__LEVEL__) == TIM_LOCKLEVEL_3))
		1643
		1644	#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
		1645
		1646
		1647	#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) \|\| \
		1648	((__STATE__) == TIM_BREAK_DISABLE))
		1649
		1650	#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) \|\| \
		1651	((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
		1652
		1653	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
		1654	((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
		1655
		1656	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
		1657	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
		1658	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
		1659	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
		1660	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
		1661	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
		1662	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
		1663	((__SOURCE__) == TIM_TRGO_OC4REF))
		1664
		1665	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
		1666	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
		1667
		1668	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
		1669	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
		1670	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
		1671	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
		1672	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
		1673
		1674	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
		1675	((__MODE__) == TIM_OCMODE_PWM2))
		1676
		1677	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
		1678	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
		1679	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
		1680	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
		1681	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
		1682	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
		1683
		1684	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1685	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1686	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1687	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1688	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
		1689	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
		1690	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
		1691	((__SELECTION__) == TIM_TS_ETRF))
		1692
		1693	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
		1694	((__SELECTION__) == TIM_TS_ITR1) \|\| \
		1695	((__SELECTION__) == TIM_TS_ITR2) \|\| \
		1696	((__SELECTION__) == TIM_TS_ITR3) \|\| \
		1697	((__SELECTION__) == TIM_TS_NONE))
		1698
		1699	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
		1700	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
		1701	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
		1702	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
		1703	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
		1704
		1705	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
		1706	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
		1707	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
		1708	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
		1709
		1710	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1711
		1712	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
		1713	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
		1714
		1715	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
		1716	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
		1717	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
		1718	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
		1719	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
		1720	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
		1721	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
		1722	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
		1723	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
		1724	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
		1725	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
		1726	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
		1727	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
		1728	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
		1729	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
		1730	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
		1731	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
		1732	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
		1733
		1734	#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
		1735
		1736	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
		1737
		1738	#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
		1739
		1740	#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
		1741
		1742	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
		1743	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
		1744	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
		1745	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
		1746	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
		1747
		1748	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
		1749	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
		1750	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
		1751	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
		1752	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
		1753
		1754	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
		1755	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
		1756	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
		1757	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
		1758	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U))))
		1759
		1760	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
		1761	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
		1762	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
		1763	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
		1764	((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP)))
		1765
		1766	/**
		1767	* @}
		1768	*/
		1769	/* End of private macros -----------------------------------------------------*/
		1770
		1771	/* Include TIM HAL Extended module */
		1772	#include "stm32f0xx_hal_tim_ex.h"
		1773
		1774	/* Exported functions --------------------------------------------------------*/
		1775	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
		1776	* @{
		1777	*/
		1778
		1779	/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
		1780	* @brief Time Base functions
		1781	* @{
		1782	*/
		1783	/* Time Base functions ********************************************************/
		1784	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
		1785	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
		1786	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
		1787	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
		1788	/* Blocking mode: Polling */
		1789	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
		1790	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
		1791	/* Non-Blocking mode: Interrupt */
		1792	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
		1793	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
		1794	/* Non-Blocking mode: DMA */
		1795	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
		1796	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
		1797	/**
		1798	* @}
		1799	*/
		1800
		1801	/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
		1802	* @brief TIM Output Compare functions
		1803	* @{
		1804	*/
		1805	/* Timer Output Compare functions *********************************************/
		1806	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
		1807	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
		1808	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
		1809	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
		1810	/* Blocking mode: Polling */
		1811	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1812	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1813	/* Non-Blocking mode: Interrupt */
		1814	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1815	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1816	/* Non-Blocking mode: DMA */
		1817	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1818	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1819	/**
		1820	* @}
		1821	*/
		1822
		1823	/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
		1824	* @brief TIM PWM functions
		1825	* @{
		1826	*/
		1827	/* Timer PWM functions ********************************************************/
		1828	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
		1829	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
		1830	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
		1831	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
		1832	/* Blocking mode: Polling */
		1833	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1834	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1835	/* Non-Blocking mode: Interrupt */
		1836	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1837	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1838	/* Non-Blocking mode: DMA */
		1839	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1840	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1841	/**
		1842	* @}
		1843	*/
		1844
		1845	/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
		1846	* @brief TIM Input Capture functions
		1847	* @{
		1848	*/
		1849	/* Timer Input Capture functions **********************************************/
		1850	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
		1851	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
		1852	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
		1853	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
		1854	/* Blocking mode: Polling */
		1855	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1856	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1857	/* Non-Blocking mode: Interrupt */
		1858	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1859	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1860	/* Non-Blocking mode: DMA */
		1861	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
		1862	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1863	/**
		1864	* @}
		1865	*/
		1866
		1867	/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
		1868	* @brief TIM One Pulse functions
		1869	* @{
		1870	*/
		1871	/* Timer One Pulse functions **************************************************/
		1872	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
		1873	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
		1874	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
		1875	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
		1876	/* Blocking mode: Polling */
		1877	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1878	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1879	/* Non-Blocking mode: Interrupt */
		1880	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1881	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
		1882	/**
		1883	* @}
		1884	*/
		1885
		1886	/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
		1887	* @brief TIM Encoder functions
		1888	* @{
		1889	*/
		1890	/* Timer Encoder functions ****************************************************/
		1891	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
		1892	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
		1893	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
		1894	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
		1895	/* Blocking mode: Polling */
		1896	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
		1897	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
		1898	/* Non-Blocking mode: Interrupt */
		1899	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1900	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
		1901	/* Non-Blocking mode: DMA */
		1902	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1,
		1903	uint32_t *pData2, uint16_t Length);
		1904	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
		1905	/**
		1906	* @}
		1907	*/
		1908
		1909	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
		1910	* @brief IRQ handler management
		1911	* @{
		1912	*/
		1913	/* Interrupt Handler functions ***********************************************/
		1914	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
		1915	/**
		1916	* @}
		1917	*/
		1918
		1919	/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
		1920	* @brief Peripheral Control functions
		1921	* @{
		1922	*/
		1923	/* Control functions *********************************************************/
		1924	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		1925	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
		1926	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
		1927	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig,
		1928	uint32_t OutputChannel, uint32_t InputChannel);
		1929	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig,
		1930	uint32_t Channel);
		1931	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
		1932	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
		1933	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		1934	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
		1935	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1936	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		1937	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1938	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
		1939	uint32_t DataLength);
		1940	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		1941	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1942	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
		1943	HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
		1944	uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
		1945	uint32_t DataLength);
		1946	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
		1947	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
		1948	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
		1949	/**
		1950	* @}
		1951	*/
		1952
		1953	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
		1954	* @brief TIM Callbacks functions
		1955	* @{
		1956	*/
		1957	/* Callback in non blocking modes (Interrupt and DMA) *************************/
		1958	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
		1959	void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
		1960	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
		1961	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
		1962	void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
		1963	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
		1964	void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
		1965	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
		1966	void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
		1967	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
		1968
		1969	/* Callbacks Register/UnRegister functions ***********************************/
		1970	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		1971	HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
		1972	pTIM_CallbackTypeDef pCallback);
		1973	HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
		1974	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		1975
		1976	/**
		1977	* @}
		1978	*/
		1979
		1980	/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
		1981	* @brief Peripheral State functions
		1982	* @{
		1983	*/
		1984	/* Peripheral State functions ************************************************/
		1985	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
		1986	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
		1987	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
		1988	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
		1989	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
		1990	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
		1991	/**
		1992	* @}
		1993	*/
		1994
		1995	/**
		1996	* @}
		1997	*/
		1998	/* End of exported functions -------------------------------------------------*/
		1999
		2000	/* Private functions----------------------------------------------------------*/
		2001	/** @defgroup TIM_Private_Functions TIM Private Functions
		2002	* @{
		2003	*/
		2004	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
		2005	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
		2006	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
		2007	void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
		2008	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
		2009
		2010	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
		2011	void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
		2012	void TIM_DMAError(DMA_HandleTypeDef *hdma);
		2013	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
		2014	void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
		2015	void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
		2016
		2017	#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
		2018	void TIM_ResetCallback(TIM_HandleTypeDef *htim);
		2019	#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
		2020
		2021	/**
		2022	* @}
		2023	*/
		2024	/* End of private functions --------------------------------------------------*/
		2025
		2026	/**
		2027	* @}
		2028	*/
		2029
		2030	/**
		2031	* @}
		2032	*/
		2033
		2034	#ifdef __cplusplus
		2035	}
		2036	#endif
		2037
		2038	#endif /* STM32F0xx_HAL_TIM_H */
		2039
		2040	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim.h – Rev 2