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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_spi.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of SPI HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F0xx_HAL_SPI_H |
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| 22 | #define STM32F0xx_HAL_SPI_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup SPI |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
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| 40 | /** @defgroup SPI_Exported_Types SPI Exported Types |
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| 41 | * @{ |
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| 42 | */ |
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| 43 | |||
| 44 | /** |
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| 45 | * @brief SPI Configuration Structure definition |
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| 46 | */ |
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| 47 | typedef struct |
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| 48 | { |
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| 49 | uint32_t Mode; /*!< Specifies the SPI operating mode. |
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| 50 | This parameter can be a value of @ref SPI_Mode */ |
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| 51 | |||
| 52 | uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. |
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| 53 | This parameter can be a value of @ref SPI_Direction */ |
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| 54 | |||
| 55 | uint32_t DataSize; /*!< Specifies the SPI data size. |
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| 56 | This parameter can be a value of @ref SPI_Data_Size */ |
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| 57 | |||
| 58 | uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. |
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| 59 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
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| 60 | |||
| 61 | uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. |
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| 62 | This parameter can be a value of @ref SPI_Clock_Phase */ |
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| 63 | |||
| 64 | uint32_t NSS; /*!< Specifies whether the NSS signal is managed by |
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| 65 | hardware (NSS pin) or by software using the SSI bit. |
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| 66 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
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| 67 | |||
| 68 | uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
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| 69 | used to configure the transmit and receive SCK clock. |
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| 70 | This parameter can be a value of @ref SPI_BaudRate_Prescaler |
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| 71 | @note The communication clock is derived from the master |
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| 72 | clock. The slave clock does not need to be set. */ |
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| 73 | |||
| 74 | uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
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| 75 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
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| 76 | |||
| 77 | uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. |
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| 78 | This parameter can be a value of @ref SPI_TI_mode */ |
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| 79 | |||
| 80 | uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. |
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| 81 | This parameter can be a value of @ref SPI_CRC_Calculation */ |
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| 82 | |||
| 83 | uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. |
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| 84 | This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ |
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| 85 | |||
| 86 | uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. |
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| 87 | CRC Length is only used with Data8 and Data16, not other data size |
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| 88 | This parameter can be a value of @ref SPI_CRC_length */ |
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| 89 | |||
| 90 | uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . |
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| 91 | This parameter can be a value of @ref SPI_NSSP_Mode |
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| 92 | This mode is activated by the NSSP bit in the SPIx_CR2 register and |
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| 93 | it takes effect only if the SPI interface is configured as Motorola SPI |
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| 94 | master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, |
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| 95 | CPOL setting is ignored).. */ |
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| 96 | } SPI_InitTypeDef; |
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| 97 | |||
| 98 | /** |
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| 99 | * @brief HAL SPI State structure definition |
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| 100 | */ |
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| 101 | typedef enum |
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| 102 | { |
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| 103 | HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ |
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| 104 | HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
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| 105 | HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
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| 106 | HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
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| 107 | HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
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| 108 | HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ |
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| 109 | HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ |
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| 110 | HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ |
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| 111 | } HAL_SPI_StateTypeDef; |
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| 112 | |||
| 113 | /** |
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| 114 | * @brief SPI handle Structure definition |
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| 115 | */ |
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| 116 | typedef struct __SPI_HandleTypeDef |
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| 117 | { |
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| 118 | SPI_TypeDef *Instance; /*!< SPI registers base address */ |
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| 119 | |||
| 120 | SPI_InitTypeDef Init; /*!< SPI communication parameters */ |
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| 121 | |||
| 122 | uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ |
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| 123 | |||
| 124 | uint16_t TxXferSize; /*!< SPI Tx Transfer size */ |
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| 125 | |||
| 126 | __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ |
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| 127 | |||
| 128 | uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ |
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| 129 | |||
| 130 | uint16_t RxXferSize; /*!< SPI Rx Transfer size */ |
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| 131 | |||
| 132 | __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ |
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| 133 | |||
| 134 | uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ |
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| 135 | |||
| 136 | void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ |
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| 137 | |||
| 138 | void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ |
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| 139 | |||
| 140 | DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ |
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| 141 | |||
| 142 | DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ |
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| 143 | |||
| 144 | HAL_LockTypeDef Lock; /*!< Locking object */ |
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| 145 | |||
| 146 | __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ |
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| 147 | |||
| 148 | __IO uint32_t ErrorCode; /*!< SPI Error code */ |
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| 149 | |||
| 150 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
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| 151 | void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ |
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| 152 | void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ |
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| 153 | void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ |
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| 154 | void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ |
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| 155 | void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ |
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| 156 | void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ |
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| 157 | void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ |
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| 158 | void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ |
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| 159 | void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ |
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| 160 | void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ |
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| 161 | |||
| 162 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
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| 163 | } SPI_HandleTypeDef; |
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| 164 | |||
| 165 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
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| 166 | /** |
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| 167 | * @brief HAL SPI Callback ID enumeration definition |
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| 168 | */ |
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| 169 | typedef enum |
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| 170 | { |
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| 171 | HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ |
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| 172 | HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ |
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| 173 | HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ |
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| 174 | HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ |
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| 175 | HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ |
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| 176 | HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ |
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| 177 | HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ |
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| 178 | HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ |
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| 179 | HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ |
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| 180 | HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ |
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| 181 | |||
| 182 | } HAL_SPI_CallbackIDTypeDef; |
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| 183 | |||
| 184 | /** |
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| 185 | * @brief HAL SPI Callback pointer definition |
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| 186 | */ |
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| 187 | typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ |
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| 188 | |||
| 189 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
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| 190 | /** |
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| 191 | * @} |
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| 192 | */ |
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| 193 | |||
| 194 | /* Exported constants --------------------------------------------------------*/ |
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| 195 | /** @defgroup SPI_Exported_Constants SPI Exported Constants |
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| 196 | * @{ |
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| 197 | */ |
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| 198 | |||
| 199 | /** @defgroup SPI_Error_Code SPI Error Code |
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| 200 | * @{ |
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| 201 | */ |
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| 202 | #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ |
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| 203 | #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ |
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| 204 | #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ |
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| 205 | #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ |
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| 206 | #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ |
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| 207 | #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ |
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| 208 | #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ |
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| 209 | #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ |
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| 210 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
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| 211 | #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ |
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| 212 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
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| 213 | /** |
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| 214 | * @} |
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| 215 | */ |
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| 216 | |||
| 217 | /** @defgroup SPI_Mode SPI Mode |
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| 218 | * @{ |
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| 219 | */ |
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| 220 | #define SPI_MODE_SLAVE (0x00000000U) |
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| 221 | #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) |
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| 222 | /** |
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| 223 | * @} |
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| 224 | */ |
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| 225 | |||
| 226 | /** @defgroup SPI_Direction SPI Direction Mode |
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| 227 | * @{ |
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| 228 | */ |
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| 229 | #define SPI_DIRECTION_2LINES (0x00000000U) |
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| 230 | #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY |
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| 231 | #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE |
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| 232 | /** |
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| 233 | * @} |
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| 234 | */ |
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| 235 | |||
| 236 | /** @defgroup SPI_Data_Size SPI Data Size |
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| 237 | * @{ |
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| 238 | */ |
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| 239 | #define SPI_DATASIZE_4BIT (0x00000300U) |
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| 240 | #define SPI_DATASIZE_5BIT (0x00000400U) |
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| 241 | #define SPI_DATASIZE_6BIT (0x00000500U) |
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| 242 | #define SPI_DATASIZE_7BIT (0x00000600U) |
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| 243 | #define SPI_DATASIZE_8BIT (0x00000700U) |
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| 244 | #define SPI_DATASIZE_9BIT (0x00000800U) |
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| 245 | #define SPI_DATASIZE_10BIT (0x00000900U) |
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| 246 | #define SPI_DATASIZE_11BIT (0x00000A00U) |
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| 247 | #define SPI_DATASIZE_12BIT (0x00000B00U) |
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| 248 | #define SPI_DATASIZE_13BIT (0x00000C00U) |
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| 249 | #define SPI_DATASIZE_14BIT (0x00000D00U) |
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| 250 | #define SPI_DATASIZE_15BIT (0x00000E00U) |
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| 251 | #define SPI_DATASIZE_16BIT (0x00000F00U) |
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| 252 | /** |
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| 253 | * @} |
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| 254 | */ |
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| 255 | |||
| 256 | /** @defgroup SPI_Clock_Polarity SPI Clock Polarity |
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| 257 | * @{ |
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| 258 | */ |
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| 259 | #define SPI_POLARITY_LOW (0x00000000U) |
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| 260 | #define SPI_POLARITY_HIGH SPI_CR1_CPOL |
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| 261 | /** |
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| 262 | * @} |
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| 263 | */ |
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| 264 | |||
| 265 | /** @defgroup SPI_Clock_Phase SPI Clock Phase |
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| 266 | * @{ |
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| 267 | */ |
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| 268 | #define SPI_PHASE_1EDGE (0x00000000U) |
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| 269 | #define SPI_PHASE_2EDGE SPI_CR1_CPHA |
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| 270 | /** |
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| 271 | * @} |
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| 272 | */ |
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| 273 | |||
| 274 | /** @defgroup SPI_Slave_Select_management SPI Slave Select Management |
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| 275 | * @{ |
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| 276 | */ |
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| 277 | #define SPI_NSS_SOFT SPI_CR1_SSM |
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| 278 | #define SPI_NSS_HARD_INPUT (0x00000000U) |
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| 279 | #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) |
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| 280 | /** |
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| 281 | * @} |
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| 282 | */ |
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| 283 | |||
| 284 | /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode |
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| 285 | * @{ |
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| 286 | */ |
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| 287 | #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP |
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| 288 | #define SPI_NSS_PULSE_DISABLE (0x00000000U) |
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| 289 | /** |
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| 290 | * @} |
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| 291 | */ |
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| 292 | |||
| 293 | /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler |
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| 294 | * @{ |
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| 295 | */ |
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| 296 | #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) |
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| 297 | #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) |
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| 298 | #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) |
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| 299 | #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) |
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| 300 | #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) |
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| 301 | #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) |
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| 302 | #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) |
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| 303 | #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) |
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| 304 | /** |
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| 305 | * @} |
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| 306 | */ |
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| 307 | |||
| 308 | /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission |
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| 309 | * @{ |
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| 310 | */ |
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| 311 | #define SPI_FIRSTBIT_MSB (0x00000000U) |
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| 312 | #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST |
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| 313 | /** |
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| 314 | * @} |
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| 315 | */ |
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| 316 | |||
| 317 | /** @defgroup SPI_TI_mode SPI TI Mode |
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| 318 | * @{ |
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| 319 | */ |
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| 320 | #define SPI_TIMODE_DISABLE (0x00000000U) |
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| 321 | #define SPI_TIMODE_ENABLE SPI_CR2_FRF |
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| 322 | /** |
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| 323 | * @} |
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| 324 | */ |
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| 325 | |||
| 326 | /** @defgroup SPI_CRC_Calculation SPI CRC Calculation |
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| 327 | * @{ |
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| 328 | */ |
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| 329 | #define SPI_CRCCALCULATION_DISABLE (0x00000000U) |
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| 330 | #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN |
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| 331 | /** |
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| 332 | * @} |
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| 333 | */ |
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| 334 | |||
| 335 | /** @defgroup SPI_CRC_length SPI CRC Length |
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| 336 | * @{ |
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| 337 | * This parameter can be one of the following values: |
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| 338 | * SPI_CRC_LENGTH_DATASIZE: aligned with the data size |
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| 339 | * SPI_CRC_LENGTH_8BIT : CRC 8bit |
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| 340 | * SPI_CRC_LENGTH_16BIT : CRC 16bit |
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| 341 | */ |
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| 342 | #define SPI_CRC_LENGTH_DATASIZE (0x00000000U) |
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| 343 | #define SPI_CRC_LENGTH_8BIT (0x00000001U) |
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| 344 | #define SPI_CRC_LENGTH_16BIT (0x00000002U) |
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| 345 | /** |
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| 346 | * @} |
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| 347 | */ |
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| 348 | |||
| 349 | /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold |
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| 350 | * @{ |
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| 351 | * This parameter can be one of the following values: |
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| 352 | * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : |
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| 353 | * RXNE event is generated if the FIFO |
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| 354 | * level is greater or equal to 1/4(8-bits). |
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| 355 | * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO |
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| 356 | * level is greater or equal to 1/2(16 bits). */ |
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| 357 | #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH |
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| 358 | #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH |
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| 359 | #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) |
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| 360 | /** |
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| 361 | * @} |
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| 362 | */ |
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| 363 | |||
| 364 | /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition |
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| 365 | * @{ |
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| 366 | */ |
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| 367 | #define SPI_IT_TXE SPI_CR2_TXEIE |
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| 368 | #define SPI_IT_RXNE SPI_CR2_RXNEIE |
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| 369 | #define SPI_IT_ERR SPI_CR2_ERRIE |
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| 370 | /** |
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| 371 | * @} |
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| 372 | */ |
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| 373 | |||
| 374 | /** @defgroup SPI_Flags_definition SPI Flags Definition |
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| 375 | * @{ |
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| 376 | */ |
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| 377 | #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ |
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| 378 | #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ |
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| 379 | #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ |
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| 380 | #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ |
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| 381 | #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ |
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| 382 | #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ |
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| 383 | #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ |
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| 384 | #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ |
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| 385 | #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ |
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| 386 | #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ |
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| 387 | | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) |
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| 388 | /** |
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| 389 | * @} |
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| 390 | */ |
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| 391 | |||
| 392 | /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level |
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| 393 | * @{ |
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| 394 | */ |
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| 395 | #define SPI_FTLVL_EMPTY (0x00000000U) |
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| 396 | #define SPI_FTLVL_QUARTER_FULL (0x00000800U) |
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| 397 | #define SPI_FTLVL_HALF_FULL (0x00001000U) |
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| 398 | #define SPI_FTLVL_FULL (0x00001800U) |
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| 399 | |||
| 400 | /** |
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| 401 | * @} |
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| 402 | */ |
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| 403 | |||
| 404 | /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level |
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| 405 | * @{ |
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| 406 | */ |
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| 407 | #define SPI_FRLVL_EMPTY (0x00000000U) |
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| 408 | #define SPI_FRLVL_QUARTER_FULL (0x00000200U) |
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| 409 | #define SPI_FRLVL_HALF_FULL (0x00000400U) |
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| 410 | #define SPI_FRLVL_FULL (0x00000600U) |
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| 411 | /** |
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| 412 | * @} |
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| 413 | */ |
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| 414 | |||
| 415 | /** |
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| 416 | * @} |
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| 417 | */ |
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| 418 | |||
| 419 | /* Exported macros -----------------------------------------------------------*/ |
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| 420 | /** @defgroup SPI_Exported_Macros SPI Exported Macros |
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| 421 | * @{ |
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| 422 | */ |
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| 423 | |||
| 424 | /** @brief Reset SPI handle state. |
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| 425 | * @param __HANDLE__ specifies the SPI Handle. |
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| 426 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
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| 427 | * @retval None |
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| 428 | */ |
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| 429 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
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| 430 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
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| 431 | (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ |
||
| 432 | (__HANDLE__)->MspInitCallback = NULL; \ |
||
| 433 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
||
| 434 | } while(0) |
||
| 435 | #else |
||
| 436 | #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) |
||
| 437 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||
| 438 | |||
| 439 | /** @brief Enable the specified SPI interrupts. |
||
| 440 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 441 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 442 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
||
| 443 | * This parameter can be one of the following values: |
||
| 444 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||
| 445 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||
| 446 | * @arg SPI_IT_ERR: Error interrupt enable |
||
| 447 | * @retval None |
||
| 448 | */ |
||
| 449 | #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
||
| 450 | |||
| 451 | /** @brief Disable the specified SPI interrupts. |
||
| 452 | * @param __HANDLE__ specifies the SPI handle. |
||
| 453 | * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 454 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
||
| 455 | * This parameter can be one of the following values: |
||
| 456 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||
| 457 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||
| 458 | * @arg SPI_IT_ERR: Error interrupt enable |
||
| 459 | * @retval None |
||
| 460 | */ |
||
| 461 | #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
||
| 462 | |||
| 463 | /** @brief Check whether the specified SPI interrupt source is enabled or not. |
||
| 464 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 465 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 466 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
||
| 467 | * This parameter can be one of the following values: |
||
| 468 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||
| 469 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||
| 470 | * @arg SPI_IT_ERR: Error interrupt enable |
||
| 471 | * @retval The new state of __IT__ (TRUE or FALSE). |
||
| 472 | */ |
||
| 473 | #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
||
| 474 | & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||
| 475 | |||
| 476 | /** @brief Check whether the specified SPI flag is set or not. |
||
| 477 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 478 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 479 | * @param __FLAG__ specifies the flag to check. |
||
| 480 | * This parameter can be one of the following values: |
||
| 481 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
||
| 482 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
||
| 483 | * @arg SPI_FLAG_CRCERR: CRC error flag |
||
| 484 | * @arg SPI_FLAG_MODF: Mode fault flag |
||
| 485 | * @arg SPI_FLAG_OVR: Overrun flag |
||
| 486 | * @arg SPI_FLAG_BSY: Busy flag |
||
| 487 | * @arg SPI_FLAG_FRE: Frame format error flag |
||
| 488 | * @arg SPI_FLAG_FTLVL: SPI fifo transmission level |
||
| 489 | * @arg SPI_FLAG_FRLVL: SPI fifo reception level |
||
| 490 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
||
| 491 | */ |
||
| 492 | #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
||
| 493 | |||
| 494 | /** @brief Clear the SPI CRCERR pending flag. |
||
| 495 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 496 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 497 | * @retval None |
||
| 498 | */ |
||
| 499 | #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) |
||
| 500 | |||
| 501 | /** @brief Clear the SPI MODF pending flag. |
||
| 502 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 503 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 504 | * @retval None |
||
| 505 | */ |
||
| 506 | #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ |
||
| 507 | do{ \ |
||
| 508 | __IO uint32_t tmpreg_modf = 0x00U; \ |
||
| 509 | tmpreg_modf = (__HANDLE__)->Instance->SR; \ |
||
| 510 | CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ |
||
| 511 | UNUSED(tmpreg_modf); \ |
||
| 512 | } while(0U) |
||
| 513 | |||
| 514 | /** @brief Clear the SPI OVR pending flag. |
||
| 515 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 516 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 517 | * @retval None |
||
| 518 | */ |
||
| 519 | #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ |
||
| 520 | do{ \ |
||
| 521 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
||
| 522 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
||
| 523 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
||
| 524 | UNUSED(tmpreg_ovr); \ |
||
| 525 | } while(0U) |
||
| 526 | |||
| 527 | /** @brief Clear the SPI FRE pending flag. |
||
| 528 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 529 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 530 | * @retval None |
||
| 531 | */ |
||
| 532 | #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ |
||
| 533 | do{ \ |
||
| 534 | __IO uint32_t tmpreg_fre = 0x00U; \ |
||
| 535 | tmpreg_fre = (__HANDLE__)->Instance->SR; \ |
||
| 536 | UNUSED(tmpreg_fre); \ |
||
| 537 | }while(0U) |
||
| 538 | |||
| 539 | /** @brief Enable the SPI peripheral. |
||
| 540 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 541 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 542 | * @retval None |
||
| 543 | */ |
||
| 544 | #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
||
| 545 | |||
| 546 | /** @brief Disable the SPI peripheral. |
||
| 547 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 548 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 549 | * @retval None |
||
| 550 | */ |
||
| 551 | #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) |
||
| 552 | |||
| 553 | /** |
||
| 554 | * @} |
||
| 555 | */ |
||
| 556 | |||
| 557 | /* Private macros ------------------------------------------------------------*/ |
||
| 558 | /** @defgroup SPI_Private_Macros SPI Private Macros |
||
| 559 | * @{ |
||
| 560 | */ |
||
| 561 | |||
| 562 | /** @brief Set the SPI transmit-only mode. |
||
| 563 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 564 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 565 | * @retval None |
||
| 566 | */ |
||
| 567 | #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||
| 568 | |||
| 569 | /** @brief Set the SPI receive-only mode. |
||
| 570 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 571 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 572 | * @retval None |
||
| 573 | */ |
||
| 574 | #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) |
||
| 575 | |||
| 576 | /** @brief Reset the CRC calculation of the SPI. |
||
| 577 | * @param __HANDLE__ specifies the SPI Handle. |
||
| 578 | * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. |
||
| 579 | * @retval None |
||
| 580 | */ |
||
| 581 | #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ |
||
| 582 | SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) |
||
| 583 | |||
| 584 | /** @brief Check whether the specified SPI flag is set or not. |
||
| 585 | * @param __SR__ copy of SPI SR regsiter. |
||
| 586 | * @param __FLAG__ specifies the flag to check. |
||
| 587 | * This parameter can be one of the following values: |
||
| 588 | * @arg SPI_FLAG_RXNE: Receive buffer not empty flag |
||
| 589 | * @arg SPI_FLAG_TXE: Transmit buffer empty flag |
||
| 590 | * @arg SPI_FLAG_CRCERR: CRC error flag |
||
| 591 | * @arg SPI_FLAG_MODF: Mode fault flag |
||
| 592 | * @arg SPI_FLAG_OVR: Overrun flag |
||
| 593 | * @arg SPI_FLAG_BSY: Busy flag |
||
| 594 | * @arg SPI_FLAG_FRE: Frame format error flag |
||
| 595 | * @arg SPI_FLAG_FTLVL: SPI fifo transmission level |
||
| 596 | * @arg SPI_FLAG_FRLVL: SPI fifo reception level |
||
| 597 | * @retval SET or RESET. |
||
| 598 | */ |
||
| 599 | #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) |
||
| 600 | |||
| 601 | /** @brief Check whether the specified SPI Interrupt is set or not. |
||
| 602 | * @param __CR2__ copy of SPI CR2 regsiter. |
||
| 603 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
||
| 604 | * This parameter can be one of the following values: |
||
| 605 | * @arg SPI_IT_TXE: Tx buffer empty interrupt enable |
||
| 606 | * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable |
||
| 607 | * @arg SPI_IT_ERR: Error interrupt enable |
||
| 608 | * @retval SET or RESET. |
||
| 609 | */ |
||
| 610 | #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||
| 611 | |||
| 612 | /** @brief Checks if SPI Mode parameter is in allowed range. |
||
| 613 | * @param __MODE__ specifies the SPI Mode. |
||
| 614 | * This parameter can be a value of @ref SPI_Mode |
||
| 615 | * @retval None |
||
| 616 | */ |
||
| 617 | #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ |
||
| 618 | ((__MODE__) == SPI_MODE_MASTER)) |
||
| 619 | |||
| 620 | /** @brief Checks if SPI Direction Mode parameter is in allowed range. |
||
| 621 | * @param __MODE__ specifies the SPI Direction Mode. |
||
| 622 | * This parameter can be a value of @ref SPI_Direction |
||
| 623 | * @retval None |
||
| 624 | */ |
||
| 625 | #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
||
| 626 | ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ |
||
| 627 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
||
| 628 | |||
| 629 | /** @brief Checks if SPI Direction Mode parameter is 2 lines. |
||
| 630 | * @param __MODE__ specifies the SPI Direction Mode. |
||
| 631 | * @retval None |
||
| 632 | */ |
||
| 633 | #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) |
||
| 634 | |||
| 635 | /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. |
||
| 636 | * @param __MODE__ specifies the SPI Direction Mode. |
||
| 637 | * @retval None |
||
| 638 | */ |
||
| 639 | #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ |
||
| 640 | ((__MODE__) == SPI_DIRECTION_1LINE)) |
||
| 641 | |||
| 642 | /** @brief Checks if SPI Data Size parameter is in allowed range. |
||
| 643 | * @param __DATASIZE__ specifies the SPI Data Size. |
||
| 644 | * This parameter can be a value of @ref SPI_Data_Size |
||
| 645 | * @retval None |
||
| 646 | */ |
||
| 647 | #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ |
||
| 648 | ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ |
||
| 649 | ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ |
||
| 650 | ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ |
||
| 651 | ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ |
||
| 652 | ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ |
||
| 653 | ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ |
||
| 654 | ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ |
||
| 655 | ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ |
||
| 656 | ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ |
||
| 657 | ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ |
||
| 658 | ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ |
||
| 659 | ((__DATASIZE__) == SPI_DATASIZE_4BIT)) |
||
| 660 | |||
| 661 | /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. |
||
| 662 | * @param __CPOL__ specifies the SPI serial clock steady state. |
||
| 663 | * This parameter can be a value of @ref SPI_Clock_Polarity |
||
| 664 | * @retval None |
||
| 665 | */ |
||
| 666 | #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ |
||
| 667 | ((__CPOL__) == SPI_POLARITY_HIGH)) |
||
| 668 | |||
| 669 | /** @brief Checks if SPI Clock Phase parameter is in allowed range. |
||
| 670 | * @param __CPHA__ specifies the SPI Clock Phase. |
||
| 671 | * This parameter can be a value of @ref SPI_Clock_Phase |
||
| 672 | * @retval None |
||
| 673 | */ |
||
| 674 | #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ |
||
| 675 | ((__CPHA__) == SPI_PHASE_2EDGE)) |
||
| 676 | |||
| 677 | /** @brief Checks if SPI Slave Select parameter is in allowed range. |
||
| 678 | * @param __NSS__ specifies the SPI Slave Select management parameter. |
||
| 679 | * This parameter can be a value of @ref SPI_Slave_Select_management |
||
| 680 | * @retval None |
||
| 681 | */ |
||
| 682 | #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ |
||
| 683 | ((__NSS__) == SPI_NSS_HARD_INPUT) || \ |
||
| 684 | ((__NSS__) == SPI_NSS_HARD_OUTPUT)) |
||
| 685 | |||
| 686 | /** @brief Checks if SPI NSS Pulse parameter is in allowed range. |
||
| 687 | * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. |
||
| 688 | * This parameter can be a value of @ref SPI_NSSP_Mode |
||
| 689 | * @retval None |
||
| 690 | */ |
||
| 691 | #define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ |
||
| 692 | ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) |
||
| 693 | |||
| 694 | /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. |
||
| 695 | * @param __PRESCALER__ specifies the SPI Baudrate prescaler. |
||
| 696 | * This parameter can be a value of @ref SPI_BaudRate_Prescaler |
||
| 697 | * @retval None |
||
| 698 | */ |
||
| 699 | #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ |
||
| 700 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ |
||
| 701 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ |
||
| 702 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ |
||
| 703 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ |
||
| 704 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ |
||
| 705 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ |
||
| 706 | ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) |
||
| 707 | |||
| 708 | /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. |
||
| 709 | * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). |
||
| 710 | * This parameter can be a value of @ref SPI_MSB_LSB_transmission |
||
| 711 | * @retval None |
||
| 712 | */ |
||
| 713 | #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ |
||
| 714 | ((__BIT__) == SPI_FIRSTBIT_LSB)) |
||
| 715 | |||
| 716 | /** @brief Checks if SPI TI mode parameter is in allowed range. |
||
| 717 | * @param __MODE__ specifies the SPI TI mode. |
||
| 718 | * This parameter can be a value of @ref SPI_TI_mode |
||
| 719 | * @retval None |
||
| 720 | */ |
||
| 721 | #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ |
||
| 722 | ((__MODE__) == SPI_TIMODE_ENABLE)) |
||
| 723 | |||
| 724 | /** @brief Checks if SPI CRC calculation enabled state is in allowed range. |
||
| 725 | * @param __CALCULATION__ specifies the SPI CRC calculation enable state. |
||
| 726 | * This parameter can be a value of @ref SPI_CRC_Calculation |
||
| 727 | * @retval None |
||
| 728 | */ |
||
| 729 | #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ |
||
| 730 | ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) |
||
| 731 | |||
| 732 | /** @brief Checks if SPI CRC length is in allowed range. |
||
| 733 | * @param __LENGTH__ specifies the SPI CRC length. |
||
| 734 | * This parameter can be a value of @ref SPI_CRC_length |
||
| 735 | * @retval None |
||
| 736 | */ |
||
| 737 | #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ |
||
| 738 | ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ |
||
| 739 | ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) |
||
| 740 | |||
| 741 | /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. |
||
| 742 | * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. |
||
| 743 | * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 |
||
| 744 | * @retval None |
||
| 745 | */ |
||
| 746 | #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) |
||
| 747 | |||
| 748 | /** @brief Checks if DMA handle is valid. |
||
| 749 | * @param __HANDLE__ specifies a DMA Handle. |
||
| 750 | * @retval None |
||
| 751 | */ |
||
| 752 | #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) |
||
| 753 | |||
| 754 | /** @brief Checks if a data address is 16bit aligned. |
||
| 755 | * @param __DATA__ specifies a data address. |
||
| 756 | * @retval None |
||
| 757 | */ |
||
| 758 | #define IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U) |
||
| 759 | |||
| 760 | /** |
||
| 761 | * @} |
||
| 762 | */ |
||
| 763 | |||
| 764 | /* Include SPI HAL Extended module */ |
||
| 765 | #include "stm32f0xx_hal_spi_ex.h" |
||
| 766 | |||
| 767 | /* Exported functions --------------------------------------------------------*/ |
||
| 768 | /** @addtogroup SPI_Exported_Functions |
||
| 769 | * @{ |
||
| 770 | */ |
||
| 771 | |||
| 772 | /** @addtogroup SPI_Exported_Functions_Group1 |
||
| 773 | * @{ |
||
| 774 | */ |
||
| 775 | /* Initialization/de-initialization functions ********************************/ |
||
| 776 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); |
||
| 777 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); |
||
| 778 | void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); |
||
| 779 | void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); |
||
| 780 | |||
| 781 | /* Callbacks Register/UnRegister functions ***********************************/ |
||
| 782 | #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) |
||
| 783 | HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); |
||
| 784 | HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); |
||
| 785 | #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ |
||
| 786 | /** |
||
| 787 | * @} |
||
| 788 | */ |
||
| 789 | |||
| 790 | /** @addtogroup SPI_Exported_Functions_Group2 |
||
| 791 | * @{ |
||
| 792 | */ |
||
| 793 | /* I/O operation functions ***************************************************/ |
||
| 794 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||
| 795 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
||
| 796 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, |
||
| 797 | uint32_t Timeout); |
||
| 798 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||
| 799 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
||
| 800 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
||
| 801 | uint16_t Size); |
||
| 802 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
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| 803 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); |
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| 804 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, |
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| 805 | uint16_t Size); |
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| 806 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); |
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| 807 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); |
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| 808 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); |
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| 809 | /* Transfer Abort functions */ |
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| 810 | HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); |
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| 811 | HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); |
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| 812 | |||
| 813 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); |
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| 814 | void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); |
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| 815 | void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); |
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| 816 | void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); |
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| 817 | void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
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| 818 | void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
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| 819 | void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); |
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| 820 | void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); |
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| 821 | void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); |
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| 822 | /** |
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| 823 | * @} |
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| 824 | */ |
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| 825 | |||
| 826 | /** @addtogroup SPI_Exported_Functions_Group3 |
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| 827 | * @{ |
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| 828 | */ |
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| 829 | /* Peripheral State and Error functions ***************************************/ |
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| 830 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); |
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| 831 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); |
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| 832 | /** |
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| 833 | * @} |
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| 834 | */ |
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| 835 | |||
| 836 | /** |
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| 837 | * @} |
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| 838 | */ |
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| 839 | |||
| 840 | /** |
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| 841 | * @} |
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| 842 | */ |
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| 843 | |||
| 844 | /** |
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| 845 | * @} |
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| 846 | */ |
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| 847 | |||
| 848 | #ifdef __cplusplus |
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| 849 | } |
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| 850 | #endif |
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| 851 | |||
| 852 | #endif /* STM32F0xx_HAL_SPI_H */ |
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| 853 | |||
| 854 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |