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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_smbus.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of SMBUS HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F0xx_HAL_SMBUS_H |
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| 22 | #define STM32F0xx_HAL_SMBUS_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup SMBUS |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
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| 40 | /** @defgroup SMBUS_Exported_Types SMBUS Exported Types |
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| 41 | * @{ |
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| 42 | */ |
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| 43 | |||
| 44 | /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition |
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| 45 | * @brief SMBUS Configuration Structure definition |
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| 46 | * @{ |
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| 47 | */ |
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| 48 | typedef struct |
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| 49 | { |
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| 50 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
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| 51 | This parameter calculated by referring to SMBUS initialization section |
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| 52 | in Reference manual */ |
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| 53 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
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| 54 | This parameter can be a value of @ref SMBUS_Analog_Filter */ |
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| 55 | |||
| 56 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
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| 57 | This parameter can be a 7-bit or 10-bit address. */ |
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| 58 | |||
| 59 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
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| 60 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
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| 61 | |||
| 62 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
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| 63 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
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| 64 | |||
| 65 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
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| 66 | This parameter can be a 7-bit address. */ |
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| 67 | |||
| 68 | uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address |
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| 69 | if dual addressing mode is selected |
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| 70 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
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| 71 | |||
| 72 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
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| 73 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
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| 74 | |||
| 75 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
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| 76 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
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| 77 | |||
| 78 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
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| 79 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
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| 80 | |||
| 81 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
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| 82 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
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| 83 | |||
| 84 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
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| 85 | (Enable bits and different timeout values) |
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| 86 | This parameter calculated by referring to SMBUS initialization section |
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| 87 | in Reference manual */ |
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| 88 | } SMBUS_InitTypeDef; |
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| 89 | /** |
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| 90 | * @} |
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| 91 | */ |
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| 92 | |||
| 93 | /** @defgroup HAL_state_definition HAL state definition |
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| 94 | * @brief HAL State definition |
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| 95 | * @{ |
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| 96 | */ |
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| 97 | #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ |
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| 98 | #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ |
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| 99 | #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ |
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| 100 | #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ |
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| 101 | #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ |
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| 102 | #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ |
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| 103 | #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ |
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| 104 | #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ |
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| 105 | #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ |
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| 106 | #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ |
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| 107 | /** |
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| 108 | * @} |
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| 109 | */ |
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| 110 | |||
| 111 | /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition |
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| 112 | * @brief SMBUS Error Code definition |
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| 113 | * @{ |
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| 114 | */ |
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| 115 | #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ |
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| 116 | #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ |
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| 117 | #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ |
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| 118 | #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ |
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| 119 | #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ |
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| 120 | #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ |
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| 121 | #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ |
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| 122 | #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ |
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| 123 | #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ |
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| 124 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
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| 125 | #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ |
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| 126 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
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| 127 | #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ |
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| 128 | /** |
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| 129 | * @} |
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| 130 | */ |
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| 131 | |||
| 132 | /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition |
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| 133 | * @brief SMBUS handle Structure definition |
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| 134 | * @{ |
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| 135 | */ |
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| 136 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
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| 137 | typedef struct __SMBUS_HandleTypeDef |
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| 138 | #else |
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| 139 | typedef struct |
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| 140 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
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| 141 | { |
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| 142 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
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| 143 | |||
| 144 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
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| 145 | |||
| 146 | uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
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| 147 | |||
| 148 | uint16_t XferSize; /*!< SMBUS transfer size */ |
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| 149 | |||
| 150 | __IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
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| 151 | |||
| 152 | __IO uint32_t XferOptions; /*!< SMBUS transfer options */ |
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| 153 | |||
| 154 | __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ |
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| 155 | |||
| 156 | HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
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| 157 | |||
| 158 | __IO uint32_t State; /*!< SMBUS communication state */ |
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| 159 | |||
| 160 | __IO uint32_t ErrorCode; /*!< SMBUS Error code */ |
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| 161 | |||
| 162 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
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| 163 | void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 164 | /*!< SMBUS Master Tx Transfer completed callback */ |
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| 165 | void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 166 | /*!< SMBUS Master Rx Transfer completed callback */ |
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| 167 | void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 168 | /*!< SMBUS Slave Tx Transfer completed callback */ |
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| 169 | void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 170 | /*!< SMBUS Slave Rx Transfer completed callback */ |
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| 171 | void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 172 | /*!< SMBUS Listen Complete callback */ |
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| 173 | void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 174 | /*!< SMBUS Error callback */ |
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| 175 | |||
| 176 | void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
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| 177 | /*!< SMBUS Slave Address Match callback */ |
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| 178 | |||
| 179 | void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 180 | /*!< SMBUS Msp Init callback */ |
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| 181 | void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
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| 182 | /*!< SMBUS Msp DeInit callback */ |
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| 183 | |||
| 184 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
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| 185 | } SMBUS_HandleTypeDef; |
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| 186 | |||
| 187 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
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| 188 | /** |
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| 189 | * @brief HAL SMBUS Callback ID enumeration definition |
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| 190 | */ |
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| 191 | typedef enum |
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| 192 | { |
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| 193 | HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ |
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| 194 | HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ |
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| 195 | HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ |
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| 196 | HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ |
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| 197 | HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ |
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| 198 | HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ |
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| 199 | |||
| 200 | HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ |
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| 201 | HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ |
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| 202 | |||
| 203 | } HAL_SMBUS_CallbackIDTypeDef; |
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| 204 | |||
| 205 | /** |
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| 206 | * @brief HAL SMBUS Callback pointer definition |
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| 207 | */ |
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| 208 | typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); |
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| 209 | /*!< pointer to an SMBUS callback function */ |
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| 210 | typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, |
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| 211 | uint16_t AddrMatchCode); |
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| 212 | /*!< pointer to an SMBUS Address Match callback function */ |
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| 213 | |||
| 214 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
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| 215 | /** |
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| 216 | * @} |
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| 217 | */ |
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| 218 | |||
| 219 | /** |
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| 220 | * @} |
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| 221 | */ |
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| 222 | /* Exported constants --------------------------------------------------------*/ |
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| 223 | |||
| 224 | /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants |
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| 225 | * @{ |
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| 226 | */ |
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| 227 | |||
| 228 | /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter |
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| 229 | * @{ |
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| 230 | */ |
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| 231 | #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) |
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| 232 | #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF |
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| 233 | /** |
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| 234 | * @} |
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| 235 | */ |
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| 236 | |||
| 237 | /** @defgroup SMBUS_addressing_mode SMBUS addressing mode |
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| 238 | * @{ |
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| 239 | */ |
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| 240 | #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) |
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| 241 | #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) |
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| 242 | /** |
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| 243 | * @} |
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| 244 | */ |
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| 245 | |||
| 246 | /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode |
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| 247 | * @{ |
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| 248 | */ |
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| 249 | |||
| 250 | #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) |
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| 251 | #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN |
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| 252 | /** |
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| 253 | * @} |
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| 254 | */ |
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| 255 | |||
| 256 | /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks |
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| 257 | * @{ |
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| 258 | */ |
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| 259 | |||
| 260 | #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) |
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| 261 | #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) |
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| 262 | #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) |
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| 263 | #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) |
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| 264 | #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) |
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| 265 | #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) |
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| 266 | #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) |
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| 267 | #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) |
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| 268 | /** |
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| 269 | * @} |
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| 270 | */ |
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| 271 | |||
| 272 | |||
| 273 | /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode |
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| 274 | * @{ |
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| 275 | */ |
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| 276 | #define SMBUS_GENERALCALL_DISABLE (0x00000000U) |
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| 277 | #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN |
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| 278 | /** |
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| 279 | * @} |
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| 280 | */ |
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| 281 | |||
| 282 | /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode |
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| 283 | * @{ |
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| 284 | */ |
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| 285 | #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) |
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| 286 | #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
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| 287 | /** |
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| 288 | * @} |
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| 289 | */ |
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| 290 | |||
| 291 | /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode |
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| 292 | * @{ |
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| 293 | */ |
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| 294 | #define SMBUS_PEC_DISABLE (0x00000000U) |
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| 295 | #define SMBUS_PEC_ENABLE I2C_CR1_PECEN |
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| 296 | /** |
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| 297 | * @} |
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| 298 | */ |
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| 299 | |||
| 300 | /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode |
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| 301 | * @{ |
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| 302 | */ |
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| 303 | #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN |
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| 304 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) |
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| 305 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN |
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| 306 | /** |
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| 307 | * @} |
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| 308 | */ |
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| 309 | |||
| 310 | /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition |
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| 311 | * @{ |
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| 312 | */ |
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| 313 | |||
| 314 | #define SMBUS_SOFTEND_MODE (0x00000000U) |
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| 315 | #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD |
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| 316 | #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND |
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| 317 | #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE |
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| 318 | /** |
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| 319 | * @} |
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| 320 | */ |
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| 321 | |||
| 322 | /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition |
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| 323 | * @{ |
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| 324 | */ |
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| 325 | |||
| 326 | #define SMBUS_NO_STARTSTOP (0x00000000U) |
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| 327 | #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) |
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| 328 | #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) |
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| 329 | #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) |
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| 330 | /** |
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| 331 | * @} |
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| 332 | */ |
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| 333 | |||
| 334 | /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition |
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| 335 | * @{ |
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| 336 | */ |
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| 337 | |||
| 338 | /* List of XferOptions in usage of : |
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| 339 | * 1- Restart condition when direction change |
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| 340 | * 2- No Restart condition in other use cases |
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| 341 | */ |
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| 342 | #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE |
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| 343 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
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| 344 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
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| 345 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
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| 346 | #define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) |
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| 347 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
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| 348 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
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| 349 | |||
| 350 | /* List of XferOptions in usage of : |
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| 351 | * 1- Restart condition in all use cases (direction change or not) |
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| 352 | */ |
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| 353 | #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) |
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| 354 | #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) |
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| 355 | #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) |
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| 356 | #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) |
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| 357 | /** |
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| 358 | * @} |
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| 359 | */ |
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| 360 | |||
| 361 | /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition |
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| 362 | * @brief SMBUS Interrupt definition |
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| 363 | * Elements values convention: 0xXXXXXXXX |
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| 364 | * - XXXXXXXX : Interrupt control mask |
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| 365 | * @{ |
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| 366 | */ |
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| 367 | #define SMBUS_IT_ERRI I2C_CR1_ERRIE |
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| 368 | #define SMBUS_IT_TCI I2C_CR1_TCIE |
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| 369 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
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| 370 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
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| 371 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
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| 372 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
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| 373 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
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| 374 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ |
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| 375 | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
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| 376 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ |
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| 377 | SMBUS_IT_RXI) |
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| 378 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
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| 379 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
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| 380 | /** |
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| 381 | * @} |
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| 382 | */ |
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| 383 | |||
| 384 | /** @defgroup SMBUS_Flag_definition SMBUS Flag definition |
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| 385 | * @brief Flag definition |
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| 386 | * Elements values convention: 0xXXXXYYYY |
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| 387 | * - XXXXXXXX : Flag mask |
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| 388 | * @{ |
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| 389 | */ |
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| 390 | |||
| 391 | #define SMBUS_FLAG_TXE I2C_ISR_TXE |
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| 392 | #define SMBUS_FLAG_TXIS I2C_ISR_TXIS |
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| 393 | #define SMBUS_FLAG_RXNE I2C_ISR_RXNE |
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| 394 | #define SMBUS_FLAG_ADDR I2C_ISR_ADDR |
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| 395 | #define SMBUS_FLAG_AF I2C_ISR_NACKF |
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| 396 | #define SMBUS_FLAG_STOPF I2C_ISR_STOPF |
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| 397 | #define SMBUS_FLAG_TC I2C_ISR_TC |
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| 398 | #define SMBUS_FLAG_TCR I2C_ISR_TCR |
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| 399 | #define SMBUS_FLAG_BERR I2C_ISR_BERR |
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| 400 | #define SMBUS_FLAG_ARLO I2C_ISR_ARLO |
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| 401 | #define SMBUS_FLAG_OVR I2C_ISR_OVR |
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| 402 | #define SMBUS_FLAG_PECERR I2C_ISR_PECERR |
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| 403 | #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
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| 404 | #define SMBUS_FLAG_ALERT I2C_ISR_ALERT |
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| 405 | #define SMBUS_FLAG_BUSY I2C_ISR_BUSY |
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| 406 | #define SMBUS_FLAG_DIR I2C_ISR_DIR |
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| 407 | /** |
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| 408 | * @} |
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| 409 | */ |
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| 410 | |||
| 411 | /** |
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| 412 | * @} |
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| 413 | */ |
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| 414 | |||
| 415 | /* Exported macros ------------------------------------------------------------*/ |
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| 416 | /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros |
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| 417 | * @{ |
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| 418 | */ |
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| 419 | |||
| 420 | /** @brief Reset SMBUS handle state. |
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| 421 | * @param __HANDLE__ specifies the SMBUS Handle. |
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| 422 | * @retval None |
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| 423 | */ |
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| 424 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
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| 425 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
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| 426 | (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ |
||
| 427 | (__HANDLE__)->MspInitCallback = NULL; \ |
||
| 428 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
||
| 429 | } while(0) |
||
| 430 | #else |
||
| 431 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
||
| 432 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
||
| 433 | |||
| 434 | /** @brief Enable the specified SMBUS interrupts. |
||
| 435 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 436 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
||
| 437 | * This parameter can be one of the following values: |
||
| 438 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
||
| 439 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
||
| 440 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
||
| 441 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
||
| 442 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
||
| 443 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
||
| 444 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
||
| 445 | * |
||
| 446 | * @retval None |
||
| 447 | */ |
||
| 448 | #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
||
| 449 | |||
| 450 | /** @brief Disable the specified SMBUS interrupts. |
||
| 451 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 452 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
||
| 453 | * This parameter can be one of the following values: |
||
| 454 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
||
| 455 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
||
| 456 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
||
| 457 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
||
| 458 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
||
| 459 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
||
| 460 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
||
| 461 | * |
||
| 462 | * @retval None |
||
| 463 | */ |
||
| 464 | #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
||
| 465 | |||
| 466 | /** @brief Check whether the specified SMBUS interrupt source is enabled or not. |
||
| 467 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 468 | * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. |
||
| 469 | * This parameter can be one of the following values: |
||
| 470 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
||
| 471 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
||
| 472 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
||
| 473 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
||
| 474 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
||
| 475 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
||
| 476 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
||
| 477 | * |
||
| 478 | * @retval The new state of __IT__ (SET or RESET). |
||
| 479 | */ |
||
| 480 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
||
| 481 | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||
| 482 | |||
| 483 | /** @brief Check whether the specified SMBUS flag is set or not. |
||
| 484 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 485 | * @param __FLAG__ specifies the flag to check. |
||
| 486 | * This parameter can be one of the following values: |
||
| 487 | * @arg @ref SMBUS_FLAG_TXE Transmit data register empty |
||
| 488 | * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status |
||
| 489 | * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty |
||
| 490 | * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) |
||
| 491 | * @arg @ref SMBUS_FLAG_AF NACK received flag |
||
| 492 | * @arg @ref SMBUS_FLAG_STOPF STOP detection flag |
||
| 493 | * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) |
||
| 494 | * @arg @ref SMBUS_FLAG_TCR Transfer complete reload |
||
| 495 | * @arg @ref SMBUS_FLAG_BERR Bus error |
||
| 496 | * @arg @ref SMBUS_FLAG_ARLO Arbitration lost |
||
| 497 | * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun |
||
| 498 | * @arg @ref SMBUS_FLAG_PECERR PEC error in reception |
||
| 499 | * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
||
| 500 | * @arg @ref SMBUS_FLAG_ALERT SMBus alert |
||
| 501 | * @arg @ref SMBUS_FLAG_BUSY Bus busy |
||
| 502 | * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) |
||
| 503 | * |
||
| 504 | * @retval The new state of __FLAG__ (SET or RESET). |
||
| 505 | */ |
||
| 506 | #define SMBUS_FLAG_MASK (0x0001FFFFU) |
||
| 507 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ |
||
| 508 | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ |
||
| 509 | ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
||
| 510 | |||
| 511 | /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
||
| 512 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 513 | * @param __FLAG__ specifies the flag to clear. |
||
| 514 | * This parameter can be any combination of the following values: |
||
| 515 | * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) |
||
| 516 | * @arg @ref SMBUS_FLAG_AF NACK received flag |
||
| 517 | * @arg @ref SMBUS_FLAG_STOPF STOP detection flag |
||
| 518 | * @arg @ref SMBUS_FLAG_BERR Bus error |
||
| 519 | * @arg @ref SMBUS_FLAG_ARLO Arbitration lost |
||
| 520 | * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun |
||
| 521 | * @arg @ref SMBUS_FLAG_PECERR PEC error in reception |
||
| 522 | * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
||
| 523 | * @arg @ref SMBUS_FLAG_ALERT SMBus alert |
||
| 524 | * |
||
| 525 | * @retval None |
||
| 526 | */ |
||
| 527 | #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
||
| 528 | |||
| 529 | /** @brief Enable the specified SMBUS peripheral. |
||
| 530 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 531 | * @retval None |
||
| 532 | */ |
||
| 533 | #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
||
| 534 | |||
| 535 | /** @brief Disable the specified SMBUS peripheral. |
||
| 536 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 537 | * @retval None |
||
| 538 | */ |
||
| 539 | #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
||
| 540 | |||
| 541 | /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. |
||
| 542 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 543 | * @retval None |
||
| 544 | */ |
||
| 545 | #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) |
||
| 546 | |||
| 547 | /** |
||
| 548 | * @} |
||
| 549 | */ |
||
| 550 | |||
| 551 | |||
| 552 | /* Private constants ---------------------------------------------------------*/ |
||
| 553 | |||
| 554 | /* Private macros ------------------------------------------------------------*/ |
||
| 555 | /** @defgroup SMBUS_Private_Macro SMBUS Private Macros |
||
| 556 | * @{ |
||
| 557 | */ |
||
| 558 | |||
| 559 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
||
| 560 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
||
| 561 | |||
| 562 | #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
||
| 563 | |||
| 564 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
||
| 565 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
||
| 566 | |||
| 567 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
||
| 568 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
||
| 569 | |||
| 570 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
||
| 571 | ((MASK) == SMBUS_OA2_MASK01) || \ |
||
| 572 | ((MASK) == SMBUS_OA2_MASK02) || \ |
||
| 573 | ((MASK) == SMBUS_OA2_MASK03) || \ |
||
| 574 | ((MASK) == SMBUS_OA2_MASK04) || \ |
||
| 575 | ((MASK) == SMBUS_OA2_MASK05) || \ |
||
| 576 | ((MASK) == SMBUS_OA2_MASK06) || \ |
||
| 577 | ((MASK) == SMBUS_OA2_MASK07)) |
||
| 578 | |||
| 579 | #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ |
||
| 580 | ((CALL) == SMBUS_GENERALCALL_ENABLE)) |
||
| 581 | |||
| 582 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
||
| 583 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
||
| 584 | |||
| 585 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
||
| 586 | ((PEC) == SMBUS_PEC_ENABLE)) |
||
| 587 | |||
| 588 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
||
| 589 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
||
| 590 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
||
| 591 | |||
| 592 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
||
| 593 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
||
| 594 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
||
| 595 | ((MODE) == SMBUS_SENDPEC_MODE) || \ |
||
| 596 | ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ |
||
| 597 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
||
| 598 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
||
| 599 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ |
||
| 600 | SMBUS_RELOAD_MODE ))) |
||
| 601 | |||
| 602 | |||
| 603 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
||
| 604 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
||
| 605 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
||
| 606 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
||
| 607 | |||
| 608 | |||
| 609 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ |
||
| 610 | ((REQUEST) == SMBUS_FIRST_FRAME) || \ |
||
| 611 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
||
| 612 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
||
| 613 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
||
| 614 | ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ |
||
| 615 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
||
| 616 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
||
| 617 | |||
| 618 | #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ |
||
| 619 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ |
||
| 620 | ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ |
||
| 621 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) |
||
| 622 | |||
| 623 | #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ |
||
| 624 | (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ |
||
| 625 | I2C_CR1_PECEN))) |
||
| 626 | #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ |
||
| 627 | (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ |
||
| 628 | I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ |
||
| 629 | I2C_CR2_RD_WRN))) |
||
| 630 | |||
| 631 | #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ |
||
| 632 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ |
||
| 633 | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ |
||
| 634 | (~I2C_CR2_RD_WRN)) : \ |
||
| 635 | (uint32_t)((((uint32_t)(__ADDRESS__) & \ |
||
| 636 | (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ |
||
| 637 | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
||
| 638 | |||
| 639 | #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) |
||
| 640 | #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) |
||
| 641 | #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
||
| 642 | #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
||
| 643 | #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
||
| 644 | |||
| 645 | #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ |
||
| 646 | ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
||
| 647 | #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
||
| 648 | |||
| 649 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
||
| 650 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
||
| 651 | |||
| 652 | /** |
||
| 653 | * @} |
||
| 654 | */ |
||
| 655 | |||
| 656 | |||
| 657 | /* Exported functions --------------------------------------------------------*/ |
||
| 658 | /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions |
||
| 659 | * @{ |
||
| 660 | */ |
||
| 661 | |||
| 662 | /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
||
| 663 | * @{ |
||
| 664 | */ |
||
| 665 | |||
| 666 | /* Initialization and de-initialization functions ****************************/ |
||
| 667 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
||
| 668 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); |
||
| 669 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
||
| 670 | void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
||
| 671 | HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); |
||
| 672 | HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); |
||
| 673 | |||
| 674 | /* Callbacks Register/UnRegister functions ***********************************/ |
||
| 675 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
||
| 676 | HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, |
||
| 677 | HAL_SMBUS_CallbackIDTypeDef CallbackID, |
||
| 678 | pSMBUS_CallbackTypeDef pCallback); |
||
| 679 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, |
||
| 680 | HAL_SMBUS_CallbackIDTypeDef CallbackID); |
||
| 681 | |||
| 682 | HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, |
||
| 683 | pSMBUS_AddrCallbackTypeDef pCallback); |
||
| 684 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 685 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
||
| 686 | /** |
||
| 687 | * @} |
||
| 688 | */ |
||
| 689 | |||
| 690 | /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
||
| 691 | * @{ |
||
| 692 | */ |
||
| 693 | |||
| 694 | /* IO operation functions *****************************************************/ |
||
| 695 | /** @addtogroup Blocking_mode_Polling Blocking mode Polling |
||
| 696 | * @{ |
||
| 697 | */ |
||
| 698 | /******* Blocking mode: Polling */ |
||
| 699 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, |
||
| 700 | uint32_t Timeout); |
||
| 701 | /** |
||
| 702 | * @} |
||
| 703 | */ |
||
| 704 | |||
| 705 | /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt |
||
| 706 | * @{ |
||
| 707 | */ |
||
| 708 | /******* Non-Blocking mode: Interrupt */ |
||
| 709 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, |
||
| 710 | uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||
| 711 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, |
||
| 712 | uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||
| 713 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
||
| 714 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, |
||
| 715 | uint32_t XferOptions); |
||
| 716 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, |
||
| 717 | uint32_t XferOptions); |
||
| 718 | |||
| 719 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 720 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 721 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 722 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 723 | /** |
||
| 724 | * @} |
||
| 725 | */ |
||
| 726 | |||
| 727 | /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
||
| 728 | * @{ |
||
| 729 | */ |
||
| 730 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
||
| 731 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
||
| 732 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
||
| 733 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 734 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 735 | void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 736 | void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 737 | void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
||
| 738 | void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 739 | void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 740 | |||
| 741 | /** |
||
| 742 | * @} |
||
| 743 | */ |
||
| 744 | |||
| 745 | /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
||
| 746 | * @{ |
||
| 747 | */ |
||
| 748 | |||
| 749 | /* Peripheral State and Errors functions **************************************************/ |
||
| 750 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
||
| 751 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
||
| 752 | |||
| 753 | /** |
||
| 754 | * @} |
||
| 755 | */ |
||
| 756 | |||
| 757 | /** |
||
| 758 | * @} |
||
| 759 | */ |
||
| 760 | |||
| 761 | /* Private Functions ---------------------------------------------------------*/ |
||
| 762 | /** @defgroup SMBUS_Private_Functions SMBUS Private Functions |
||
| 763 | * @{ |
||
| 764 | */ |
||
| 765 | /* Private functions are defined in stm32f0xx_hal_smbus.c file */ |
||
| 766 | /** |
||
| 767 | * @} |
||
| 768 | */ |
||
| 769 | |||
| 770 | /** |
||
| 771 | * @} |
||
| 772 | */ |
||
| 773 | |||
| 774 | /** |
||
| 775 | * @} |
||
| 776 | */ |
||
| 777 | |||
| 778 | /** |
||
| 779 | * @} |
||
| 780 | */ |
||
| 781 | |||
| 782 | #ifdef __cplusplus |
||
| 783 | } |
||
| 784 | #endif |
||
| 785 | |||
| 786 | |||
| 787 | #endif /* STM32F0xx_HAL_SMBUS_H */ |
||
| 788 | |||
| 789 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |