Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
||
| 3 | * @file stm32f0xx_hal_smbus.h |
||
| 4 | * @author MCD Application Team |
||
| 5 | * @brief Header file of SMBUS HAL module. |
||
| 6 | ****************************************************************************** |
||
| 7 | * @attention |
||
| 8 | * |
||
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
||
| 10 | * All rights reserved.</center></h2> |
||
| 11 | * |
||
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
||
| 13 | * the "License"; You may not use this file except in compliance with the |
||
| 14 | * License. You may obtain a copy of the License at: |
||
| 15 | * opensource.org/licenses/BSD-3-Clause |
||
| 16 | * |
||
| 17 | ****************************************************************************** |
||
| 18 | */ |
||
| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
||
| 21 | #ifndef STM32F0xx_HAL_SMBUS_H |
||
| 22 | #define STM32F0xx_HAL_SMBUS_H |
||
| 23 | |||
| 24 | #ifdef __cplusplus |
||
| 25 | extern "C" { |
||
| 26 | #endif |
||
| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
||
| 29 | #include "stm32f0xx_hal_def.h" |
||
| 30 | |||
| 31 | /** @addtogroup STM32F0xx_HAL_Driver |
||
| 32 | * @{ |
||
| 33 | */ |
||
| 34 | |||
| 35 | /** @addtogroup SMBUS |
||
| 36 | * @{ |
||
| 37 | */ |
||
| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
||
| 40 | /** @defgroup SMBUS_Exported_Types SMBUS Exported Types |
||
| 41 | * @{ |
||
| 42 | */ |
||
| 43 | |||
| 44 | /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition |
||
| 45 | * @brief SMBUS Configuration Structure definition |
||
| 46 | * @{ |
||
| 47 | */ |
||
| 48 | typedef struct |
||
| 49 | { |
||
| 50 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
||
| 51 | This parameter calculated by referring to SMBUS initialization |
||
| 52 | section in Reference manual */ |
||
| 53 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
||
| 54 | This parameter can be a value of @ref SMBUS_Analog_Filter */ |
||
| 55 | |||
| 56 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
||
| 57 | This parameter can be a 7-bit or 10-bit address. */ |
||
| 58 | |||
| 59 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
||
| 60 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
||
| 61 | |||
| 62 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
||
| 63 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
||
| 64 | |||
| 65 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
||
| 66 | This parameter can be a 7-bit address. */ |
||
| 67 | |||
| 68 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
||
| 69 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
||
| 70 | |||
| 71 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
||
| 72 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
||
| 73 | |||
| 74 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
||
| 75 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
||
| 76 | |||
| 77 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
||
| 78 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
||
| 79 | |||
| 80 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
||
| 81 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
||
| 82 | |||
| 83 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
||
| 84 | (Enable bits and different timeout values) |
||
| 85 | This parameter calculated by referring to SMBUS initialization |
||
| 86 | section in Reference manual */ |
||
| 87 | } SMBUS_InitTypeDef; |
||
| 88 | /** |
||
| 89 | * @} |
||
| 90 | */ |
||
| 91 | |||
| 92 | /** @defgroup HAL_state_definition HAL state definition |
||
| 93 | * @brief HAL State definition |
||
| 94 | * @{ |
||
| 95 | */ |
||
| 96 | #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ |
||
| 97 | #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ |
||
| 98 | #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ |
||
| 99 | #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ |
||
| 100 | #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ |
||
| 101 | #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ |
||
| 102 | #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ |
||
| 103 | #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ |
||
| 104 | #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ |
||
| 105 | #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ |
||
| 106 | /** |
||
| 107 | * @} |
||
| 108 | */ |
||
| 109 | |||
| 110 | /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition |
||
| 111 | * @brief SMBUS Error Code definition |
||
| 112 | * @{ |
||
| 113 | */ |
||
| 114 | #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ |
||
| 115 | #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ |
||
| 116 | #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ |
||
| 117 | #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ |
||
| 118 | #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ |
||
| 119 | #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ |
||
| 120 | #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ |
||
| 121 | #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ |
||
| 122 | #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ |
||
| 123 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
||
| 124 | #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ |
||
| 125 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
||
| 126 | #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ |
||
| 127 | /** |
||
| 128 | * @} |
||
| 129 | */ |
||
| 130 | |||
| 131 | /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition |
||
| 132 | * @brief SMBUS handle Structure definition |
||
| 133 | * @{ |
||
| 134 | */ |
||
| 135 | typedef struct __SMBUS_HandleTypeDef |
||
| 136 | { |
||
| 137 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
||
| 138 | |||
| 139 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
||
| 140 | |||
| 141 | uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
||
| 142 | |||
| 143 | uint16_t XferSize; /*!< SMBUS transfer size */ |
||
| 144 | |||
| 145 | __IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
||
| 146 | |||
| 147 | __IO uint32_t XferOptions; /*!< SMBUS transfer options */ |
||
| 148 | |||
| 149 | __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ |
||
| 150 | |||
| 151 | HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
||
| 152 | |||
| 153 | __IO uint32_t State; /*!< SMBUS communication state */ |
||
| 154 | |||
| 155 | __IO uint32_t ErrorCode; /*!< SMBUS Error code */ |
||
| 156 | |||
| 157 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
||
| 158 | void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ |
||
| 159 | void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ |
||
| 160 | void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ |
||
| 161 | void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ |
||
| 162 | void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ |
||
| 163 | void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ |
||
| 164 | |||
| 165 | void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ |
||
| 166 | |||
| 167 | void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ |
||
| 168 | void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ |
||
| 169 | |||
| 170 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
||
| 171 | } SMBUS_HandleTypeDef; |
||
| 172 | |||
| 173 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
||
| 174 | /** |
||
| 175 | * @brief HAL SMBUS Callback ID enumeration definition |
||
| 176 | */ |
||
| 177 | typedef enum |
||
| 178 | { |
||
| 179 | HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ |
||
| 180 | HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ |
||
| 181 | HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ |
||
| 182 | HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ |
||
| 183 | HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ |
||
| 184 | HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ |
||
| 185 | |||
| 186 | HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ |
||
| 187 | HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ |
||
| 188 | |||
| 189 | } HAL_SMBUS_CallbackIDTypeDef; |
||
| 190 | |||
| 191 | /** |
||
| 192 | * @brief HAL SMBUS Callback pointer definition |
||
| 193 | */ |
||
| 194 | typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ |
||
| 195 | typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ |
||
| 196 | |||
| 197 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
||
| 198 | /** |
||
| 199 | * @} |
||
| 200 | */ |
||
| 201 | |||
| 202 | /** |
||
| 203 | * @} |
||
| 204 | */ |
||
| 205 | /* Exported constants --------------------------------------------------------*/ |
||
| 206 | |||
| 207 | /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants |
||
| 208 | * @{ |
||
| 209 | */ |
||
| 210 | |||
| 211 | /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter |
||
| 212 | * @{ |
||
| 213 | */ |
||
| 214 | #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) |
||
| 215 | #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF |
||
| 216 | /** |
||
| 217 | * @} |
||
| 218 | */ |
||
| 219 | |||
| 220 | /** @defgroup SMBUS_addressing_mode SMBUS addressing mode |
||
| 221 | * @{ |
||
| 222 | */ |
||
| 223 | #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) |
||
| 224 | #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) |
||
| 225 | /** |
||
| 226 | * @} |
||
| 227 | */ |
||
| 228 | |||
| 229 | /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode |
||
| 230 | * @{ |
||
| 231 | */ |
||
| 232 | |||
| 233 | #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) |
||
| 234 | #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN |
||
| 235 | /** |
||
| 236 | * @} |
||
| 237 | */ |
||
| 238 | |||
| 239 | /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks |
||
| 240 | * @{ |
||
| 241 | */ |
||
| 242 | |||
| 243 | #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) |
||
| 244 | #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) |
||
| 245 | #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) |
||
| 246 | #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) |
||
| 247 | #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) |
||
| 248 | #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) |
||
| 249 | #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) |
||
| 250 | #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) |
||
| 251 | /** |
||
| 252 | * @} |
||
| 253 | */ |
||
| 254 | |||
| 255 | |||
| 256 | /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode |
||
| 257 | * @{ |
||
| 258 | */ |
||
| 259 | #define SMBUS_GENERALCALL_DISABLE (0x00000000U) |
||
| 260 | #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN |
||
| 261 | /** |
||
| 262 | * @} |
||
| 263 | */ |
||
| 264 | |||
| 265 | /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode |
||
| 266 | * @{ |
||
| 267 | */ |
||
| 268 | #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) |
||
| 269 | #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
||
| 270 | /** |
||
| 271 | * @} |
||
| 272 | */ |
||
| 273 | |||
| 274 | /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode |
||
| 275 | * @{ |
||
| 276 | */ |
||
| 277 | #define SMBUS_PEC_DISABLE (0x00000000U) |
||
| 278 | #define SMBUS_PEC_ENABLE I2C_CR1_PECEN |
||
| 279 | /** |
||
| 280 | * @} |
||
| 281 | */ |
||
| 282 | |||
| 283 | /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode |
||
| 284 | * @{ |
||
| 285 | */ |
||
| 286 | #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN |
||
| 287 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) |
||
| 288 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN |
||
| 289 | /** |
||
| 290 | * @} |
||
| 291 | */ |
||
| 292 | |||
| 293 | /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition |
||
| 294 | * @{ |
||
| 295 | */ |
||
| 296 | |||
| 297 | #define SMBUS_SOFTEND_MODE (0x00000000U) |
||
| 298 | #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD |
||
| 299 | #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND |
||
| 300 | #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE |
||
| 301 | /** |
||
| 302 | * @} |
||
| 303 | */ |
||
| 304 | |||
| 305 | /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition |
||
| 306 | * @{ |
||
| 307 | */ |
||
| 308 | |||
| 309 | #define SMBUS_NO_STARTSTOP (0x00000000U) |
||
| 310 | #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) |
||
| 311 | #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) |
||
| 312 | #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) |
||
| 313 | /** |
||
| 314 | * @} |
||
| 315 | */ |
||
| 316 | |||
| 317 | /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition |
||
| 318 | * @{ |
||
| 319 | */ |
||
| 320 | |||
| 321 | /* List of XferOptions in usage of : |
||
| 322 | * 1- Restart condition when direction change |
||
| 323 | * 2- No Restart condition in other use cases |
||
| 324 | */ |
||
| 325 | #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE |
||
| 326 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
||
| 327 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
||
| 328 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
||
| 329 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
||
| 330 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
||
| 331 | |||
| 332 | /* List of XferOptions in usage of : |
||
| 333 | * 1- Restart condition in all use cases (direction change or not) |
||
| 334 | */ |
||
| 335 | #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) |
||
| 336 | #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) |
||
| 337 | #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) |
||
| 338 | #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) |
||
| 339 | /** |
||
| 340 | * @} |
||
| 341 | */ |
||
| 342 | |||
| 343 | /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition |
||
| 344 | * @brief SMBUS Interrupt definition |
||
| 345 | * Elements values convention: 0xXXXXXXXX |
||
| 346 | * - XXXXXXXX : Interrupt control mask |
||
| 347 | * @{ |
||
| 348 | */ |
||
| 349 | #define SMBUS_IT_ERRI I2C_CR1_ERRIE |
||
| 350 | #define SMBUS_IT_TCI I2C_CR1_TCIE |
||
| 351 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
||
| 352 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
||
| 353 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
||
| 354 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
||
| 355 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
||
| 356 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
||
| 357 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) |
||
| 358 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
||
| 359 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
||
| 360 | /** |
||
| 361 | * @} |
||
| 362 | */ |
||
| 363 | |||
| 364 | /** @defgroup SMBUS_Flag_definition SMBUS Flag definition |
||
| 365 | * @brief Flag definition |
||
| 366 | * Elements values convention: 0xXXXXYYYY |
||
| 367 | * - XXXXXXXX : Flag mask |
||
| 368 | * @{ |
||
| 369 | */ |
||
| 370 | |||
| 371 | #define SMBUS_FLAG_TXE I2C_ISR_TXE |
||
| 372 | #define SMBUS_FLAG_TXIS I2C_ISR_TXIS |
||
| 373 | #define SMBUS_FLAG_RXNE I2C_ISR_RXNE |
||
| 374 | #define SMBUS_FLAG_ADDR I2C_ISR_ADDR |
||
| 375 | #define SMBUS_FLAG_AF I2C_ISR_NACKF |
||
| 376 | #define SMBUS_FLAG_STOPF I2C_ISR_STOPF |
||
| 377 | #define SMBUS_FLAG_TC I2C_ISR_TC |
||
| 378 | #define SMBUS_FLAG_TCR I2C_ISR_TCR |
||
| 379 | #define SMBUS_FLAG_BERR I2C_ISR_BERR |
||
| 380 | #define SMBUS_FLAG_ARLO I2C_ISR_ARLO |
||
| 381 | #define SMBUS_FLAG_OVR I2C_ISR_OVR |
||
| 382 | #define SMBUS_FLAG_PECERR I2C_ISR_PECERR |
||
| 383 | #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
||
| 384 | #define SMBUS_FLAG_ALERT I2C_ISR_ALERT |
||
| 385 | #define SMBUS_FLAG_BUSY I2C_ISR_BUSY |
||
| 386 | #define SMBUS_FLAG_DIR I2C_ISR_DIR |
||
| 387 | /** |
||
| 388 | * @} |
||
| 389 | */ |
||
| 390 | |||
| 391 | /** |
||
| 392 | * @} |
||
| 393 | */ |
||
| 394 | |||
| 395 | /* Exported macros ------------------------------------------------------------*/ |
||
| 396 | /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros |
||
| 397 | * @{ |
||
| 398 | */ |
||
| 399 | |||
| 400 | /** @brief Reset SMBUS handle state. |
||
| 401 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 402 | * @retval None |
||
| 403 | */ |
||
| 404 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
||
| 405 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
||
| 406 | (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ |
||
| 407 | (__HANDLE__)->MspInitCallback = NULL; \ |
||
| 408 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
||
| 409 | } while(0) |
||
| 410 | #else |
||
| 411 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
||
| 412 | #endif |
||
| 413 | |||
| 414 | /** @brief Enable the specified SMBUS interrupts. |
||
| 415 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 416 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
||
| 417 | * This parameter can be one of the following values: |
||
| 418 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
||
| 419 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
||
| 420 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
||
| 421 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
||
| 422 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
||
| 423 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
||
| 424 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
||
| 425 | * |
||
| 426 | * @retval None |
||
| 427 | */ |
||
| 428 | #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
||
| 429 | |||
| 430 | /** @brief Disable the specified SMBUS interrupts. |
||
| 431 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 432 | * @param __INTERRUPT__ specifies the interrupt source to disable. |
||
| 433 | * This parameter can be one of the following values: |
||
| 434 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
||
| 435 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
||
| 436 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
||
| 437 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
||
| 438 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
||
| 439 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
||
| 440 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
||
| 441 | * |
||
| 442 | * @retval None |
||
| 443 | */ |
||
| 444 | #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
||
| 445 | |||
| 446 | /** @brief Check whether the specified SMBUS interrupt source is enabled or not. |
||
| 447 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 448 | * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. |
||
| 449 | * This parameter can be one of the following values: |
||
| 450 | * @arg @ref SMBUS_IT_ERRI Errors interrupt enable |
||
| 451 | * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable |
||
| 452 | * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable |
||
| 453 | * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable |
||
| 454 | * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable |
||
| 455 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
||
| 456 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
||
| 457 | * |
||
| 458 | * @retval The new state of __IT__ (SET or RESET). |
||
| 459 | */ |
||
| 460 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
||
| 461 | |||
| 462 | /** @brief Check whether the specified SMBUS flag is set or not. |
||
| 463 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 464 | * @param __FLAG__ specifies the flag to check. |
||
| 465 | * This parameter can be one of the following values: |
||
| 466 | * @arg @ref SMBUS_FLAG_TXE Transmit data register empty |
||
| 467 | * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status |
||
| 468 | * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty |
||
| 469 | * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) |
||
| 470 | * @arg @ref SMBUS_FLAG_AF NACK received flag |
||
| 471 | * @arg @ref SMBUS_FLAG_STOPF STOP detection flag |
||
| 472 | * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) |
||
| 473 | * @arg @ref SMBUS_FLAG_TCR Transfer complete reload |
||
| 474 | * @arg @ref SMBUS_FLAG_BERR Bus error |
||
| 475 | * @arg @ref SMBUS_FLAG_ARLO Arbitration lost |
||
| 476 | * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun |
||
| 477 | * @arg @ref SMBUS_FLAG_PECERR PEC error in reception |
||
| 478 | * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
||
| 479 | * @arg @ref SMBUS_FLAG_ALERT SMBus alert |
||
| 480 | * @arg @ref SMBUS_FLAG_BUSY Bus busy |
||
| 481 | * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) |
||
| 482 | * |
||
| 483 | * @retval The new state of __FLAG__ (SET or RESET). |
||
| 484 | */ |
||
| 485 | #define SMBUS_FLAG_MASK (0x0001FFFFU) |
||
| 486 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
||
| 487 | |||
| 488 | /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
||
| 489 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 490 | * @param __FLAG__ specifies the flag to clear. |
||
| 491 | * This parameter can be any combination of the following values: |
||
| 492 | * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) |
||
| 493 | * @arg @ref SMBUS_FLAG_AF NACK received flag |
||
| 494 | * @arg @ref SMBUS_FLAG_STOPF STOP detection flag |
||
| 495 | * @arg @ref SMBUS_FLAG_BERR Bus error |
||
| 496 | * @arg @ref SMBUS_FLAG_ARLO Arbitration lost |
||
| 497 | * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun |
||
| 498 | * @arg @ref SMBUS_FLAG_PECERR PEC error in reception |
||
| 499 | * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag |
||
| 500 | * @arg @ref SMBUS_FLAG_ALERT SMBus alert |
||
| 501 | * |
||
| 502 | * @retval None |
||
| 503 | */ |
||
| 504 | #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
||
| 505 | |||
| 506 | /** @brief Enable the specified SMBUS peripheral. |
||
| 507 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 508 | * @retval None |
||
| 509 | */ |
||
| 510 | #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
||
| 511 | |||
| 512 | /** @brief Disable the specified SMBUS peripheral. |
||
| 513 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 514 | * @retval None |
||
| 515 | */ |
||
| 516 | #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) |
||
| 517 | |||
| 518 | /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. |
||
| 519 | * @param __HANDLE__ specifies the SMBUS Handle. |
||
| 520 | * @retval None |
||
| 521 | */ |
||
| 522 | #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) |
||
| 523 | |||
| 524 | /** |
||
| 525 | * @} |
||
| 526 | */ |
||
| 527 | |||
| 528 | |||
| 529 | /* Private constants ---------------------------------------------------------*/ |
||
| 530 | |||
| 531 | /* Private macros ------------------------------------------------------------*/ |
||
| 532 | /** @defgroup SMBUS_Private_Macro SMBUS Private Macros |
||
| 533 | * @{ |
||
| 534 | */ |
||
| 535 | |||
| 536 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
||
| 537 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
||
| 538 | |||
| 539 | #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
||
| 540 | |||
| 541 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
||
| 542 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
||
| 543 | |||
| 544 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
||
| 545 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
||
| 546 | |||
| 547 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
||
| 548 | ((MASK) == SMBUS_OA2_MASK01) || \ |
||
| 549 | ((MASK) == SMBUS_OA2_MASK02) || \ |
||
| 550 | ((MASK) == SMBUS_OA2_MASK03) || \ |
||
| 551 | ((MASK) == SMBUS_OA2_MASK04) || \ |
||
| 552 | ((MASK) == SMBUS_OA2_MASK05) || \ |
||
| 553 | ((MASK) == SMBUS_OA2_MASK06) || \ |
||
| 554 | ((MASK) == SMBUS_OA2_MASK07)) |
||
| 555 | |||
| 556 | #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ |
||
| 557 | ((CALL) == SMBUS_GENERALCALL_ENABLE)) |
||
| 558 | |||
| 559 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
||
| 560 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
||
| 561 | |||
| 562 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
||
| 563 | ((PEC) == SMBUS_PEC_ENABLE)) |
||
| 564 | |||
| 565 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
||
| 566 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
||
| 567 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
||
| 568 | |||
| 569 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
||
| 570 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
||
| 571 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
||
| 572 | ((MODE) == SMBUS_SENDPEC_MODE) || \ |
||
| 573 | ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ |
||
| 574 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
||
| 575 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
||
| 576 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) |
||
| 577 | |||
| 578 | |||
| 579 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
||
| 580 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
||
| 581 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
||
| 582 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
||
| 583 | |||
| 584 | |||
| 585 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ |
||
| 586 | ((REQUEST) == SMBUS_FIRST_FRAME) || \ |
||
| 587 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
||
| 588 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
||
| 589 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
||
| 590 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
||
| 591 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
||
| 592 | |||
| 593 | #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ |
||
| 594 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ |
||
| 595 | ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ |
||
| 596 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) |
||
| 597 | |||
| 598 | #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) |
||
| 599 | #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
||
| 600 | |||
| 601 | #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
||
| 602 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
||
| 603 | |||
| 604 | #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) |
||
| 605 | #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) |
||
| 606 | #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
||
| 607 | #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
||
| 608 | #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
||
| 609 | |||
| 610 | #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
||
| 611 | #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
||
| 612 | |||
| 613 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
||
| 614 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
||
| 615 | |||
| 616 | /** |
||
| 617 | * @} |
||
| 618 | */ |
||
| 619 | |||
| 620 | /* Exported functions --------------------------------------------------------*/ |
||
| 621 | /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions |
||
| 622 | * @{ |
||
| 623 | */ |
||
| 624 | |||
| 625 | /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
||
| 626 | * @{ |
||
| 627 | */ |
||
| 628 | |||
| 629 | /* Initialization and de-initialization functions ****************************/ |
||
| 630 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
||
| 631 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); |
||
| 632 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
||
| 633 | void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
||
| 634 | HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); |
||
| 635 | HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); |
||
| 636 | |||
| 637 | /* Callbacks Register/UnRegister functions ***********************************/ |
||
| 638 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
||
| 639 | HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); |
||
| 640 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); |
||
| 641 | |||
| 642 | HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); |
||
| 643 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 644 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
||
| 645 | /** |
||
| 646 | * @} |
||
| 647 | */ |
||
| 648 | |||
| 649 | /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
||
| 650 | * @{ |
||
| 651 | */ |
||
| 652 | |||
| 653 | /* IO operation functions *****************************************************/ |
||
| 654 | /** @addtogroup Blocking_mode_Polling Blocking mode Polling |
||
| 655 | * @{ |
||
| 656 | */ |
||
| 657 | /******* Blocking mode: Polling */ |
||
| 658 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
||
| 659 | /** |
||
| 660 | * @} |
||
| 661 | */ |
||
| 662 | |||
| 663 | /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt |
||
| 664 | * @{ |
||
| 665 | */ |
||
| 666 | /******* Non-Blocking mode: Interrupt */ |
||
| 667 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||
| 668 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||
| 669 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
||
| 670 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||
| 671 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
||
| 672 | |||
| 673 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 674 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 675 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 676 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
||
| 677 | /** |
||
| 678 | * @} |
||
| 679 | */ |
||
| 680 | |||
| 681 | /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
||
| 682 | * @{ |
||
| 683 | */ |
||
| 684 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
||
| 685 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
||
| 686 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
||
| 687 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 688 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 689 | void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 690 | void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 691 | void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
||
| 692 | void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 693 | void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
||
| 694 | |||
| 695 | /** |
||
| 696 | * @} |
||
| 697 | */ |
||
| 698 | |||
| 699 | /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
||
| 700 | * @{ |
||
| 701 | */ |
||
| 702 | |||
| 703 | /* Peripheral State and Errors functions **************************************************/ |
||
| 704 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
||
| 705 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
||
| 706 | |||
| 707 | /** |
||
| 708 | * @} |
||
| 709 | */ |
||
| 710 | |||
| 711 | /** |
||
| 712 | * @} |
||
| 713 | */ |
||
| 714 | |||
| 715 | /* Private Functions ---------------------------------------------------------*/ |
||
| 716 | /** @defgroup SMBUS_Private_Functions SMBUS Private Functions |
||
| 717 | * @{ |
||
| 718 | */ |
||
| 719 | /* Private functions are defined in stm32f0xx_hal_smbus.c file */ |
||
| 720 | /** |
||
| 721 | * @} |
||
| 722 | */ |
||
| 723 | |||
| 724 | /** |
||
| 725 | * @} |
||
| 726 | */ |
||
| 727 | |||
| 728 | /** |
||
| 729 | * @} |
||
| 730 | */ |
||
| 731 | |||
| 732 | /** |
||
| 733 | * @} |
||
| 734 | */ |
||
| 735 | |||
| 736 | #ifdef __cplusplus |
||
| 737 | } |
||
| 738 | #endif |
||
| 739 | |||
| 740 | |||
| 741 | #endif /* STM32F0xx_HAL_SMBUS_H */ |
||
| 742 | |||
| 743 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |