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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_rcc_ex.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of RCC HAL Extension module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F0xx_HAL_RCC_EX_H |
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| 22 | #define __STM32F0xx_HAL_RCC_EX_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup RCC |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /** @addtogroup RCC_Private_Macros |
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| 40 | * @{ |
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| 41 | */ |
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| 42 | #if defined(RCC_HSI48_SUPPORT) |
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| 43 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
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| 44 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
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| 45 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
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| 46 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
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| 47 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
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| 48 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \ |
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| 49 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) |
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| 50 | |||
| 51 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
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| 52 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
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| 53 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ |
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| 54 | ((SOURCE) == RCC_SYSCLKSOURCE_HSI48)) |
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| 55 | |||
| 56 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
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| 57 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
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| 58 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \ |
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| 59 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48)) |
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| 60 | |||
| 61 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
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| 62 | ((SOURCE) == RCC_PLLSOURCE_HSI48) || \ |
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| 63 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
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| 64 | |||
| 65 | #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) |
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| 66 | |||
| 67 | #else |
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| 68 | |||
| 69 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ |
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| 70 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
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| 71 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
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| 72 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
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| 73 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ |
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| 74 | (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)) |
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| 75 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
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| 76 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
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| 77 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
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| 78 | |||
| 79 | #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
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| 80 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
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| 81 | ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) |
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| 82 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
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| 83 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
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| 84 | |||
| 85 | #endif /* RCC_HSI48_SUPPORT */ |
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| 86 | |||
| 87 | #if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) |
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| 88 | |||
| 89 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ |
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| 90 | ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ |
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| 91 | ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
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| 92 | ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ |
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| 93 | ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ |
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| 94 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ |
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| 95 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ |
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| 96 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ |
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| 97 | ((SOURCE) == RCC_MCO1SOURCE_HSI14)) |
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| 98 | |||
| 99 | #elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48) |
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| 100 | |||
| 101 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ |
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| 102 | ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ |
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| 103 | ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
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| 104 | ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ |
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| 105 | ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ |
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| 106 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ |
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| 107 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ |
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| 108 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ |
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| 109 | ((SOURCE) == RCC_MCO1SOURCE_HSI14) || \ |
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| 110 | ((SOURCE) == RCC_MCO1SOURCE_HSI48)) |
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| 111 | |||
| 112 | #elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48) |
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| 113 | |||
| 114 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ |
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| 115 | ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ |
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| 116 | ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
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| 117 | ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ |
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| 118 | ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ |
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| 119 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ |
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| 120 | ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) || \ |
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| 121 | ((SOURCE) == RCC_MCO1SOURCE_HSI14)) |
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| 122 | |||
| 123 | #endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */ |
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| 124 | |||
| 125 | /** |
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| 126 | * @} |
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| 127 | */ |
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| 128 | |||
| 129 | /** @addtogroup RCC_Exported_Constants |
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| 130 | * @{ |
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| 131 | */ |
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| 132 | #if defined(RCC_HSI48_SUPPORT) |
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| 133 | |||
| 134 | /** @addtogroup RCC_PLL_Clock_Source |
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| 135 | * @{ |
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| 136 | */ |
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| 137 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV |
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| 138 | #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV |
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| 139 | |||
| 140 | /** |
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| 141 | * @} |
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| 142 | */ |
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| 143 | |||
| 144 | /** @addtogroup RCC_Interrupt |
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| 145 | * @{ |
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| 146 | */ |
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| 147 | #define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ |
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| 148 | /** |
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| 149 | * @} |
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| 150 | */ |
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| 151 | |||
| 152 | /** @addtogroup RCC_Flag |
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| 153 | * @{ |
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| 154 | */ |
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| 155 | #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI48RDY_BitNumber)) |
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| 156 | /** |
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| 157 | * @} |
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| 158 | */ |
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| 159 | |||
| 160 | /** @addtogroup RCC_System_Clock_Source |
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| 161 | * @{ |
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| 162 | */ |
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| 163 | #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48 |
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| 164 | /** |
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| 165 | * @} |
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| 166 | */ |
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| 167 | |||
| 168 | /** @addtogroup RCC_System_Clock_Source_Status |
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| 169 | * @{ |
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| 170 | */ |
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| 171 | #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48 |
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| 172 | /** |
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| 173 | * @} |
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| 174 | */ |
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| 175 | |||
| 176 | #else |
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| 177 | /** @addtogroup RCC_PLL_Clock_Source |
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| 178 | * @{ |
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| 179 | */ |
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| 180 | |||
| 181 | #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC) |
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| 182 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV |
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| 183 | #else |
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| 184 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 |
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| 185 | #endif |
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| 186 | |||
| 187 | /** |
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| 188 | * @} |
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| 189 | */ |
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| 190 | |||
| 191 | #endif /* RCC_HSI48_SUPPORT */ |
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| 192 | |||
| 193 | /** @addtogroup RCC_MCO_Clock_Source |
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| 194 | * @{ |
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| 195 | */ |
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| 196 | |||
| 197 | #if defined(RCC_CFGR_PLLNODIV) |
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| 198 | |||
| 199 | #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV) |
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| 200 | |||
| 201 | #endif /* RCC_CFGR_PLLNODIV */ |
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| 202 | |||
| 203 | #if defined(RCC_CFGR_MCO_HSI48) |
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| 204 | |||
| 205 | #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 |
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| 206 | |||
| 207 | #endif /* SRCC_CFGR_MCO_HSI48 */ |
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| 208 | /** |
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| 209 | * @} |
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| 210 | */ |
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| 211 | |||
| 212 | /** |
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| 213 | * @} |
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| 214 | */ |
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| 215 | |||
| 216 | /** |
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| 217 | * @} |
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| 218 | */ |
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| 219 | |||
| 220 | /** @addtogroup RCCEx |
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| 221 | * @{ |
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| 222 | */ |
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| 223 | |||
| 224 | /* Private Constants -------------------------------------------------------------*/ |
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| 225 | #if defined(CRS) |
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| 226 | /** @addtogroup RCCEx_Private_Constants |
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| 227 | * @{ |
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| 228 | */ |
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| 229 | |||
| 230 | /* CRS IT Error Mask */ |
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| 231 | #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) |
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| 232 | |||
| 233 | /* CRS Flag Error Mask */ |
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| 234 | #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) |
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| 235 | |||
| 236 | /** |
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| 237 | * @} |
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| 238 | */ |
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| 239 | #endif /* CRS */ |
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| 240 | |||
| 241 | /* Private macro -------------------------------------------------------------*/ |
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| 242 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
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| 243 | * @{ |
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| 244 | */ |
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| 245 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ |
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| 246 | || defined(STM32F030xC) |
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| 247 | |||
| 248 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
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| 249 | RCC_PERIPHCLK_RTC)) |
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| 250 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || |
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| 251 | STM32F030xC */ |
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| 252 | |||
| 253 | #if defined(STM32F070x6) || defined(STM32F070xB) |
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| 254 | |||
| 255 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
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| 256 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) |
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| 257 | #endif /* STM32F070x6 || STM32F070xB */ |
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| 258 | |||
| 259 | #if defined(STM32F042x6) || defined(STM32F048xx) |
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| 260 | |||
| 261 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
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| 262 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ |
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| 263 | RCC_PERIPHCLK_USB)) |
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| 264 | #endif /* STM32F042x6 || STM32F048xx */ |
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| 265 | |||
| 266 | #if defined(STM32F051x8) || defined(STM32F058xx) |
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| 267 | |||
| 268 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \ |
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| 269 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) |
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| 270 | #endif /* STM32F051x8 || STM32F058xx */ |
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| 271 | |||
| 272 | #if defined(STM32F071xB) |
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| 273 | |||
| 274 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
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| 275 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
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| 276 | RCC_PERIPHCLK_RTC)) |
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| 277 | #endif /* STM32F071xB */ |
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| 278 | |||
| 279 | #if defined(STM32F072xB) || defined(STM32F078xx) |
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| 280 | |||
| 281 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
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| 282 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
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| 283 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB)) |
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| 284 | #endif /* STM32F072xB || STM32F078xx */ |
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| 285 | |||
| 286 | #if defined(STM32F091xC) || defined(STM32F098xx) |
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| 287 | |||
| 288 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ |
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| 289 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \ |
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| 290 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 )) |
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| 291 | #endif /* STM32F091xC || STM32F098xx */ |
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| 292 | |||
| 293 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) |
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| 294 | |||
| 295 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ |
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| 296 | ((SOURCE) == RCC_USBCLKSOURCE_PLL)) |
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| 297 | |||
| 298 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ |
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| 299 | |||
| 300 | #if defined(STM32F070x6) || defined(STM32F070xB) |
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| 301 | |||
| 302 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) || \ |
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| 303 | ((SOURCE) == RCC_USBCLKSOURCE_PLL)) |
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| 304 | |||
| 305 | #endif /* STM32F070x6 || STM32F070xB */ |
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| 306 | |||
| 307 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
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| 308 | || defined(STM32F091xC) || defined(STM32F098xx) |
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| 309 | |||
| 310 | #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ |
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| 311 | ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
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| 312 | ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ |
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| 313 | ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) |
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| 314 | |||
| 315 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
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| 316 | /* STM32F091xC || STM32F098xx */ |
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| 317 | |||
| 318 | #if defined(STM32F091xC) || defined(STM32F098xx) |
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| 319 | |||
| 320 | #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ |
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| 321 | ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
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| 322 | ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ |
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| 323 | ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) |
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| 324 | #endif /* STM32F091xC || STM32F098xx */ |
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| 325 | |||
| 326 | |||
| 327 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
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| 328 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
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| 329 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
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| 330 | || defined(STM32F091xC) || defined(STM32F098xx) |
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| 331 | |||
| 332 | #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
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| 333 | ((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
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| 334 | #endif /* STM32F042x6 || STM32F048xx || */ |
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| 335 | /* STM32F051x8 || STM32F058xx || */ |
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| 336 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
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| 337 | /* STM32F091xC || STM32F098xx */ |
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| 338 | |||
| 339 | #if defined(RCC_CFGR_MCOPRE) |
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| 340 | |||
| 341 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
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| 342 | ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ |
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| 343 | ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ |
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| 344 | ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) |
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| 345 | #else |
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| 346 | |||
| 347 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) |
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| 348 | |||
| 349 | #endif /* RCC_CFGR_MCOPRE */ |
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| 350 | |||
| 351 | #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ |
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| 352 | ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
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| 353 | ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ |
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| 354 | ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) |
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| 355 | |||
| 356 | #if defined(CRS) |
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| 357 | |||
| 358 | #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ |
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| 359 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \ |
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| 360 | ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) |
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| 361 | #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \ |
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| 362 | ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ |
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| 363 | ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ |
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| 364 | ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) |
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| 365 | #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ |
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| 366 | ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) |
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| 367 | #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU)) |
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| 368 | #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU)) |
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| 369 | #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU)) |
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| 370 | #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ |
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| 371 | ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) |
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| 372 | #endif /* CRS */ |
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| 373 | /** |
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| 374 | * @} |
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| 375 | */ |
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| 376 | |||
| 377 | /* Exported types ------------------------------------------------------------*/ |
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| 378 | |||
| 379 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
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| 380 | * @{ |
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| 381 | */ |
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| 382 | |||
| 383 | /** |
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| 384 | * @brief RCC extended clocks structure definition |
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| 385 | */ |
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| 386 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ |
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| 387 | || defined(STM32F030xC) |
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| 388 | typedef struct |
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| 389 | { |
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| 390 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 391 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 392 | |||
| 393 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 394 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 395 | |||
| 396 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 397 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 398 | |||
| 399 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 400 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 401 | |||
| 402 | }RCC_PeriphCLKInitTypeDef; |
||
| 403 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || |
||
| 404 | STM32F030xC */ |
||
| 405 | |||
| 406 | #if defined(STM32F070x6) || defined(STM32F070xB) |
||
| 407 | typedef struct |
||
| 408 | { |
||
| 409 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 410 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 411 | |||
| 412 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 413 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 414 | |||
| 415 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 416 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 417 | |||
| 418 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 419 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 420 | |||
| 421 | uint32_t UsbClockSelection; /*!< USB clock source |
||
| 422 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
||
| 423 | |||
| 424 | }RCC_PeriphCLKInitTypeDef; |
||
| 425 | #endif /* STM32F070x6 || STM32F070xB */ |
||
| 426 | |||
| 427 | #if defined(STM32F042x6) || defined(STM32F048xx) |
||
| 428 | typedef struct |
||
| 429 | { |
||
| 430 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 431 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 432 | |||
| 433 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 434 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 435 | |||
| 436 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 437 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 438 | |||
| 439 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 440 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 441 | |||
| 442 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
||
| 443 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
||
| 444 | |||
| 445 | uint32_t UsbClockSelection; /*!< USB clock source |
||
| 446 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
||
| 447 | |||
| 448 | }RCC_PeriphCLKInitTypeDef; |
||
| 449 | #endif /* STM32F042x6 || STM32F048xx */ |
||
| 450 | |||
| 451 | #if defined(STM32F051x8) || defined(STM32F058xx) |
||
| 452 | typedef struct |
||
| 453 | { |
||
| 454 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 455 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 456 | |||
| 457 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 458 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 459 | |||
| 460 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 461 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 462 | |||
| 463 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 464 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 465 | |||
| 466 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
||
| 467 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
||
| 468 | |||
| 469 | }RCC_PeriphCLKInitTypeDef; |
||
| 470 | #endif /* STM32F051x8 || STM32F058xx */ |
||
| 471 | |||
| 472 | #if defined(STM32F071xB) |
||
| 473 | typedef struct |
||
| 474 | { |
||
| 475 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 476 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 477 | |||
| 478 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 479 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 480 | |||
| 481 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 482 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 483 | |||
| 484 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
||
| 485 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
||
| 486 | |||
| 487 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 488 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 489 | |||
| 490 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
||
| 491 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
||
| 492 | |||
| 493 | }RCC_PeriphCLKInitTypeDef; |
||
| 494 | #endif /* STM32F071xB */ |
||
| 495 | |||
| 496 | #if defined(STM32F072xB) || defined(STM32F078xx) |
||
| 497 | typedef struct |
||
| 498 | { |
||
| 499 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 500 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 501 | |||
| 502 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 503 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 504 | |||
| 505 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 506 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 507 | |||
| 508 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
||
| 509 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
||
| 510 | |||
| 511 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 512 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 513 | |||
| 514 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
||
| 515 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
||
| 516 | |||
| 517 | uint32_t UsbClockSelection; /*!< USB clock source |
||
| 518 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
||
| 519 | |||
| 520 | }RCC_PeriphCLKInitTypeDef; |
||
| 521 | #endif /* STM32F072xB || STM32F078xx */ |
||
| 522 | |||
| 523 | |||
| 524 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 525 | typedef struct |
||
| 526 | { |
||
| 527 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
||
| 528 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
||
| 529 | |||
| 530 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
||
| 531 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
||
| 532 | |||
| 533 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
||
| 534 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
||
| 535 | |||
| 536 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
||
| 537 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
||
| 538 | |||
| 539 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
||
| 540 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
||
| 541 | |||
| 542 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
||
| 543 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
||
| 544 | |||
| 545 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
||
| 546 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
||
| 547 | |||
| 548 | }RCC_PeriphCLKInitTypeDef; |
||
| 549 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 550 | |||
| 551 | #if defined(CRS) |
||
| 552 | |||
| 553 | /** |
||
| 554 | * @brief RCC_CRS Init structure definition |
||
| 555 | */ |
||
| 556 | typedef struct |
||
| 557 | { |
||
| 558 | uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. |
||
| 559 | This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ |
||
| 560 | |||
| 561 | uint32_t Source; /*!< Specifies the SYNC signal source. |
||
| 562 | This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ |
||
| 563 | |||
| 564 | uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. |
||
| 565 | This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ |
||
| 566 | |||
| 567 | uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. |
||
| 568 | It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) |
||
| 569 | This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ |
||
| 570 | |||
| 571 | uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. |
||
| 572 | This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ |
||
| 573 | |||
| 574 | uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. |
||
| 575 | This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ |
||
| 576 | |||
| 577 | }RCC_CRSInitTypeDef; |
||
| 578 | |||
| 579 | /** |
||
| 580 | * @brief RCC_CRS Synchronization structure definition |
||
| 581 | */ |
||
| 582 | typedef struct |
||
| 583 | { |
||
| 584 | uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. |
||
| 585 | This parameter must be a number between 0 and 0xFFFFU */ |
||
| 586 | |||
| 587 | uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. |
||
| 588 | This parameter must be a number between 0 and 0x3FU */ |
||
| 589 | |||
| 590 | uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter |
||
| 591 | value latched in the time of the last SYNC event. |
||
| 592 | This parameter must be a number between 0 and 0xFFFFU */ |
||
| 593 | |||
| 594 | uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the |
||
| 595 | frequency error counter latched in the time of the last SYNC event. |
||
| 596 | It shows whether the actual frequency is below or above the target. |
||
| 597 | This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ |
||
| 598 | |||
| 599 | }RCC_CRSSynchroInfoTypeDef; |
||
| 600 | |||
| 601 | #endif /* CRS */ |
||
| 602 | |||
| 603 | /** |
||
| 604 | * @} |
||
| 605 | */ |
||
| 606 | |||
| 607 | /* Exported constants --------------------------------------------------------*/ |
||
| 608 | |||
| 609 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
||
| 610 | * @{ |
||
| 611 | */ |
||
| 612 | |||
| 613 | /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection |
||
| 614 | * @{ |
||
| 615 | */ |
||
| 616 | #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)\ |
||
| 617 | || defined(STM32F030xC) |
||
| 618 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 619 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 620 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 621 | |||
| 622 | #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx || |
||
| 623 | STM32F030xC */ |
||
| 624 | |||
| 625 | #if defined(STM32F070x6) || defined(STM32F070xB) |
||
| 626 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 627 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 628 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 629 | #define RCC_PERIPHCLK_USB (0x00020000U) |
||
| 630 | |||
| 631 | #endif /* STM32F070x6 || STM32F070xB */ |
||
| 632 | |||
| 633 | #if defined(STM32F042x6) || defined(STM32F048xx) |
||
| 634 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 635 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 636 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
||
| 637 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 638 | #define RCC_PERIPHCLK_USB (0x00020000U) |
||
| 639 | |||
| 640 | #endif /* STM32F042x6 || STM32F048xx */ |
||
| 641 | |||
| 642 | #if defined(STM32F051x8) || defined(STM32F058xx) |
||
| 643 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 644 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 645 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
||
| 646 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 647 | |||
| 648 | #endif /* STM32F051x8 || STM32F058xx */ |
||
| 649 | |||
| 650 | #if defined(STM32F071xB) |
||
| 651 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 652 | #define RCC_PERIPHCLK_USART2 (0x00000002U) |
||
| 653 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 654 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
||
| 655 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 656 | |||
| 657 | #endif /* STM32F071xB */ |
||
| 658 | |||
| 659 | #if defined(STM32F072xB) || defined(STM32F078xx) |
||
| 660 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 661 | #define RCC_PERIPHCLK_USART2 (0x00000002U) |
||
| 662 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 663 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
||
| 664 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 665 | #define RCC_PERIPHCLK_USB (0x00020000U) |
||
| 666 | |||
| 667 | #endif /* STM32F072xB || STM32F078xx */ |
||
| 668 | |||
| 669 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 670 | #define RCC_PERIPHCLK_USART1 (0x00000001U) |
||
| 671 | #define RCC_PERIPHCLK_USART2 (0x00000002U) |
||
| 672 | #define RCC_PERIPHCLK_I2C1 (0x00000020U) |
||
| 673 | #define RCC_PERIPHCLK_CEC (0x00000400U) |
||
| 674 | #define RCC_PERIPHCLK_RTC (0x00010000U) |
||
| 675 | #define RCC_PERIPHCLK_USART3 (0x00040000U) |
||
| 676 | |||
| 677 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 678 | |||
| 679 | /** |
||
| 680 | * @} |
||
| 681 | */ |
||
| 682 | |||
| 683 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) |
||
| 684 | |||
| 685 | /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source |
||
| 686 | * @{ |
||
| 687 | */ |
||
| 688 | #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /*!< HSI48 clock selected as USB clock source */ |
||
| 689 | #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ |
||
| 690 | |||
| 691 | /** |
||
| 692 | * @} |
||
| 693 | */ |
||
| 694 | |||
| 695 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ |
||
| 696 | |||
| 697 | #if defined(STM32F070x6) || defined(STM32F070xB) |
||
| 698 | |||
| 699 | /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source |
||
| 700 | * @{ |
||
| 701 | */ |
||
| 702 | #define RCC_USBCLKSOURCE_NONE (0x00000000U) /*!< USB clock disabled */ |
||
| 703 | #define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /*!< PLL clock (PLLCLK) selected as USB clock */ |
||
| 704 | |||
| 705 | /** |
||
| 706 | * @} |
||
| 707 | */ |
||
| 708 | |||
| 709 | #endif /* STM32F070x6 || STM32F070xB */ |
||
| 710 | |||
| 711 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 712 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 713 | |||
| 714 | /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source |
||
| 715 | * @{ |
||
| 716 | */ |
||
| 717 | #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK |
||
| 718 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK |
||
| 719 | #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE |
||
| 720 | #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI |
||
| 721 | |||
| 722 | /** |
||
| 723 | * @} |
||
| 724 | */ |
||
| 725 | |||
| 726 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 727 | /* STM32F091xC || STM32F098xx */ |
||
| 728 | |||
| 729 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 730 | |||
| 731 | /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source |
||
| 732 | * @{ |
||
| 733 | */ |
||
| 734 | #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK |
||
| 735 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK |
||
| 736 | #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE |
||
| 737 | #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI |
||
| 738 | |||
| 739 | /** |
||
| 740 | * @} |
||
| 741 | */ |
||
| 742 | |||
| 743 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 744 | |||
| 745 | |||
| 746 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 747 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 748 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 749 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 750 | |||
| 751 | /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source |
||
| 752 | * @{ |
||
| 753 | */ |
||
| 754 | #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 |
||
| 755 | #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE |
||
| 756 | |||
| 757 | /** |
||
| 758 | * @} |
||
| 759 | */ |
||
| 760 | |||
| 761 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 762 | /* STM32F051x8 || STM32F058xx || */ |
||
| 763 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 764 | /* STM32F091xC || STM32F098xx */ |
||
| 765 | |||
| 766 | /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler |
||
| 767 | * @{ |
||
| 768 | */ |
||
| 769 | |||
| 770 | #if defined(RCC_CFGR_MCOPRE) |
||
| 771 | |||
| 772 | #define RCC_MCODIV_1 (0x00000000U) |
||
| 773 | #define RCC_MCODIV_2 (0x10000000U) |
||
| 774 | #define RCC_MCODIV_4 (0x20000000U) |
||
| 775 | #define RCC_MCODIV_8 (0x30000000U) |
||
| 776 | #define RCC_MCODIV_16 (0x40000000U) |
||
| 777 | #define RCC_MCODIV_32 (0x50000000U) |
||
| 778 | #define RCC_MCODIV_64 (0x60000000U) |
||
| 779 | #define RCC_MCODIV_128 (0x70000000U) |
||
| 780 | |||
| 781 | #else |
||
| 782 | |||
| 783 | #define RCC_MCODIV_1 (0x00000000U) |
||
| 784 | |||
| 785 | #endif /* RCC_CFGR_MCOPRE */ |
||
| 786 | |||
| 787 | /** |
||
| 788 | * @} |
||
| 789 | */ |
||
| 790 | |||
| 791 | /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration |
||
| 792 | * @{ |
||
| 793 | */ |
||
| 794 | |||
| 795 | #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ |
||
| 796 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ |
||
| 797 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ |
||
| 798 | #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ |
||
| 799 | |||
| 800 | /** |
||
| 801 | * @} |
||
| 802 | */ |
||
| 803 | |||
| 804 | #if defined(CRS) |
||
| 805 | |||
| 806 | /** @defgroup RCCEx_CRS_Status RCCEx CRS Status |
||
| 807 | * @{ |
||
| 808 | */ |
||
| 809 | #define RCC_CRS_NONE (0x00000000U) |
||
| 810 | #define RCC_CRS_TIMEOUT (0x00000001U) |
||
| 811 | #define RCC_CRS_SYNCOK (0x00000002U) |
||
| 812 | #define RCC_CRS_SYNCWARN (0x00000004U) |
||
| 813 | #define RCC_CRS_SYNCERR (0x00000008U) |
||
| 814 | #define RCC_CRS_SYNCMISS (0x00000010U) |
||
| 815 | #define RCC_CRS_TRIMOVF (0x00000020U) |
||
| 816 | |||
| 817 | /** |
||
| 818 | * @} |
||
| 819 | */ |
||
| 820 | |||
| 821 | /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source |
||
| 822 | * @{ |
||
| 823 | */ |
||
| 824 | #define RCC_CRS_SYNC_SOURCE_GPIO (0x00000000U) /*!< Synchro Signal source GPIO */ |
||
| 825 | #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ |
||
| 826 | #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ |
||
| 827 | /** |
||
| 828 | * @} |
||
| 829 | */ |
||
| 830 | |||
| 831 | /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider |
||
| 832 | * @{ |
||
| 833 | */ |
||
| 834 | #define RCC_CRS_SYNC_DIV1 (0x00000000U) /*!< Synchro Signal not divided (default) */ |
||
| 835 | #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ |
||
| 836 | #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ |
||
| 837 | #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ |
||
| 838 | #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ |
||
| 839 | #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ |
||
| 840 | #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ |
||
| 841 | #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ |
||
| 842 | /** |
||
| 843 | * @} |
||
| 844 | */ |
||
| 845 | |||
| 846 | /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity |
||
| 847 | * @{ |
||
| 848 | */ |
||
| 849 | #define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /*!< Synchro Active on rising edge (default) */ |
||
| 850 | #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ |
||
| 851 | /** |
||
| 852 | * @} |
||
| 853 | */ |
||
| 854 | |||
| 855 | /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value |
||
| 856 | * @{ |
||
| 857 | */ |
||
| 858 | #define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds |
||
| 859 | to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ |
||
| 860 | /** |
||
| 861 | * @} |
||
| 862 | */ |
||
| 863 | |||
| 864 | /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value |
||
| 865 | * @{ |
||
| 866 | */ |
||
| 867 | #define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /*!< Default Frequency error limit */ |
||
| 868 | /** |
||
| 869 | * @} |
||
| 870 | */ |
||
| 871 | |||
| 872 | /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye |
||
| 873 | * @{ |
||
| 874 | */ |
||
| 875 | #define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. |
||
| 876 | The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value |
||
| 877 | corresponds to a higher output frequency */ |
||
| 878 | /** |
||
| 879 | * @} |
||
| 880 | */ |
||
| 881 | |||
| 882 | /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction |
||
| 883 | * @{ |
||
| 884 | */ |
||
| 885 | #define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ |
||
| 886 | #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ |
||
| 887 | /** |
||
| 888 | * @} |
||
| 889 | */ |
||
| 890 | |||
| 891 | /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources |
||
| 892 | * @{ |
||
| 893 | */ |
||
| 894 | #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ |
||
| 895 | #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ |
||
| 896 | #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ |
||
| 897 | #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ |
||
| 898 | #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ |
||
| 899 | #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ |
||
| 900 | #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ |
||
| 901 | |||
| 902 | /** |
||
| 903 | * @} |
||
| 904 | */ |
||
| 905 | |||
| 906 | /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags |
||
| 907 | * @{ |
||
| 908 | */ |
||
| 909 | #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ |
||
| 910 | #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ |
||
| 911 | #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ |
||
| 912 | #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ |
||
| 913 | #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ |
||
| 914 | #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ |
||
| 915 | #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ |
||
| 916 | |||
| 917 | /** |
||
| 918 | * @} |
||
| 919 | */ |
||
| 920 | |||
| 921 | #endif /* CRS */ |
||
| 922 | |||
| 923 | /** |
||
| 924 | * @} |
||
| 925 | */ |
||
| 926 | |||
| 927 | /* Exported macros ------------------------------------------------------------*/ |
||
| 928 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
||
| 929 | * @{ |
||
| 930 | */ |
||
| 931 | |||
| 932 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable |
||
| 933 | * @brief Enables or disables the AHB1 peripheral clock. |
||
| 934 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 935 | * is disabled and the application software has to enable this clock before |
||
| 936 | * using it. |
||
| 937 | * @{ |
||
| 938 | */ |
||
| 939 | #if defined(GPIOD) |
||
| 940 | |||
| 941 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
||
| 942 | __IO uint32_t tmpreg; \ |
||
| 943 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ |
||
| 944 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 945 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ |
||
| 946 | UNUSED(tmpreg); \ |
||
| 947 | } while(0U) |
||
| 948 | |||
| 949 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) |
||
| 950 | |||
| 951 | #endif /* GPIOD */ |
||
| 952 | |||
| 953 | #if defined(GPIOE) |
||
| 954 | |||
| 955 | #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ |
||
| 956 | __IO uint32_t tmpreg; \ |
||
| 957 | SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
||
| 958 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 959 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ |
||
| 960 | UNUSED(tmpreg); \ |
||
| 961 | } while(0U) |
||
| 962 | |||
| 963 | #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
||
| 964 | |||
| 965 | #endif /* GPIOE */ |
||
| 966 | |||
| 967 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 968 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 969 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 970 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 971 | |||
| 972 | #define __HAL_RCC_TSC_CLK_ENABLE() do { \ |
||
| 973 | __IO uint32_t tmpreg; \ |
||
| 974 | SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ |
||
| 975 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 976 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ |
||
| 977 | UNUSED(tmpreg); \ |
||
| 978 | } while(0U) |
||
| 979 | |||
| 980 | #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) |
||
| 981 | |||
| 982 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 983 | /* STM32F051x8 || STM32F058xx || */ |
||
| 984 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 985 | /* STM32F091xC || STM32F098xx */ |
||
| 986 | |||
| 987 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 988 | |||
| 989 | #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ |
||
| 990 | __IO uint32_t tmpreg; \ |
||
| 991 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
||
| 992 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 993 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ |
||
| 994 | UNUSED(tmpreg); \ |
||
| 995 | } while(0U) |
||
| 996 | |||
| 997 | #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
||
| 998 | |||
| 999 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 1000 | |||
| 1001 | /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
||
| 1002 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 1003 | * is disabled and the application software has to enable this clock before |
||
| 1004 | * using it. |
||
| 1005 | */ |
||
| 1006 | #if defined(STM32F030x8)\ |
||
| 1007 | || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1008 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1009 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1010 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1011 | |||
| 1012 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
||
| 1013 | __IO uint32_t tmpreg; \ |
||
| 1014 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
||
| 1015 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1016 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
||
| 1017 | UNUSED(tmpreg); \ |
||
| 1018 | } while(0U) |
||
| 1019 | |||
| 1020 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
||
| 1021 | |||
| 1022 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
||
| 1023 | /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ |
||
| 1024 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1025 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1026 | |||
| 1027 | #if defined(STM32F030x8)\ |
||
| 1028 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1029 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1030 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1031 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1032 | |||
| 1033 | #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ |
||
| 1034 | __IO uint32_t tmpreg; \ |
||
| 1035 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
||
| 1036 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1037 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ |
||
| 1038 | UNUSED(tmpreg); \ |
||
| 1039 | } while(0U) |
||
| 1040 | |||
| 1041 | #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
||
| 1042 | |||
| 1043 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
||
| 1044 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1045 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1046 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1047 | |||
| 1048 | #if defined(STM32F031x6) || defined(STM32F038xx)\ |
||
| 1049 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1050 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1051 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1052 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1053 | |||
| 1054 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
||
| 1055 | __IO uint32_t tmpreg; \ |
||
| 1056 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
||
| 1057 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1058 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
||
| 1059 | UNUSED(tmpreg); \ |
||
| 1060 | } while(0U) |
||
| 1061 | |||
| 1062 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
||
| 1063 | |||
| 1064 | #endif /* STM32F031x6 || STM32F038xx || */ |
||
| 1065 | /* STM32F042x6 || STM32F048xx || */ |
||
| 1066 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1067 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1068 | /* STM32F091xC || STM32F098xx */ |
||
| 1069 | |||
| 1070 | #if defined(STM32F030x8) \ |
||
| 1071 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1072 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1073 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1074 | |||
| 1075 | #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ |
||
| 1076 | __IO uint32_t tmpreg; \ |
||
| 1077 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
||
| 1078 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1079 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ |
||
| 1080 | UNUSED(tmpreg); \ |
||
| 1081 | } while(0U) |
||
| 1082 | #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ |
||
| 1083 | __IO uint32_t tmpreg; \ |
||
| 1084 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
||
| 1085 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1086 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ |
||
| 1087 | UNUSED(tmpreg); \ |
||
| 1088 | } while(0U) |
||
| 1089 | |||
| 1090 | #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) |
||
| 1091 | #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
||
| 1092 | |||
| 1093 | #endif /* STM32F030x8 || */ |
||
| 1094 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1095 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1096 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1097 | |||
| 1098 | #if defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1099 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1100 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1101 | |||
| 1102 | #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ |
||
| 1103 | __IO uint32_t tmpreg; \ |
||
| 1104 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
||
| 1105 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1106 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ |
||
| 1107 | UNUSED(tmpreg); \ |
||
| 1108 | } while(0U) |
||
| 1109 | |||
| 1110 | #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) |
||
| 1111 | |||
| 1112 | #endif /* STM32F051x8 || STM32F058xx || */ |
||
| 1113 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1114 | /* STM32F091xC || STM32F098xx */ |
||
| 1115 | |||
| 1116 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1117 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1118 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1119 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1120 | |||
| 1121 | #define __HAL_RCC_CEC_CLK_ENABLE() do { \ |
||
| 1122 | __IO uint32_t tmpreg; \ |
||
| 1123 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
||
| 1124 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1125 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ |
||
| 1126 | UNUSED(tmpreg); \ |
||
| 1127 | } while(0U) |
||
| 1128 | |||
| 1129 | #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
||
| 1130 | |||
| 1131 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1132 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1133 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1134 | /* STM32F091xC || STM32F098xx */ |
||
| 1135 | |||
| 1136 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1137 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1138 | |||
| 1139 | #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ |
||
| 1140 | __IO uint32_t tmpreg; \ |
||
| 1141 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
||
| 1142 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1143 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ |
||
| 1144 | UNUSED(tmpreg); \ |
||
| 1145 | } while(0U) |
||
| 1146 | #define __HAL_RCC_USART3_CLK_ENABLE() do { \ |
||
| 1147 | __IO uint32_t tmpreg; \ |
||
| 1148 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
||
| 1149 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1150 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ |
||
| 1151 | UNUSED(tmpreg); \ |
||
| 1152 | } while(0U) |
||
| 1153 | #define __HAL_RCC_USART4_CLK_ENABLE() do { \ |
||
| 1154 | __IO uint32_t tmpreg; \ |
||
| 1155 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ |
||
| 1156 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1157 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\ |
||
| 1158 | UNUSED(tmpreg); \ |
||
| 1159 | } while(0U) |
||
| 1160 | |||
| 1161 | #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
||
| 1162 | #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) |
||
| 1163 | #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN)) |
||
| 1164 | |||
| 1165 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1166 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1167 | |||
| 1168 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1169 | || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) |
||
| 1170 | |||
| 1171 | #define __HAL_RCC_USB_CLK_ENABLE() do { \ |
||
| 1172 | __IO uint32_t tmpreg; \ |
||
| 1173 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ |
||
| 1174 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1175 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ |
||
| 1176 | UNUSED(tmpreg); \ |
||
| 1177 | } while(0U) |
||
| 1178 | |||
| 1179 | #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) |
||
| 1180 | |||
| 1181 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1182 | /* STM32F072xB || STM32F078xx || STM32F070xB */ |
||
| 1183 | |||
| 1184 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ |
||
| 1185 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1186 | |||
| 1187 | #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ |
||
| 1188 | __IO uint32_t tmpreg; \ |
||
| 1189 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ |
||
| 1190 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1191 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ |
||
| 1192 | UNUSED(tmpreg); \ |
||
| 1193 | } while(0U) |
||
| 1194 | #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) |
||
| 1195 | |||
| 1196 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ |
||
| 1197 | /* STM32F091xC || STM32F098xx */ |
||
| 1198 | |||
| 1199 | #if defined(CRS) |
||
| 1200 | |||
| 1201 | #define __HAL_RCC_CRS_CLK_ENABLE() do { \ |
||
| 1202 | __IO uint32_t tmpreg; \ |
||
| 1203 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ |
||
| 1204 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1205 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\ |
||
| 1206 | UNUSED(tmpreg); \ |
||
| 1207 | } while(0U) |
||
| 1208 | |||
| 1209 | #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) |
||
| 1210 | |||
| 1211 | #endif /* CRS */ |
||
| 1212 | |||
| 1213 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1214 | |||
| 1215 | #define __HAL_RCC_USART5_CLK_ENABLE() do { \ |
||
| 1216 | __IO uint32_t tmpreg; \ |
||
| 1217 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ |
||
| 1218 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1219 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\ |
||
| 1220 | UNUSED(tmpreg); \ |
||
| 1221 | } while(0U) |
||
| 1222 | |||
| 1223 | #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN)) |
||
| 1224 | |||
| 1225 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1226 | |||
| 1227 | /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
||
| 1228 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 1229 | * is disabled and the application software has to enable this clock before |
||
| 1230 | * using it. |
||
| 1231 | */ |
||
| 1232 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1233 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1234 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1235 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1236 | |||
| 1237 | #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ |
||
| 1238 | __IO uint32_t tmpreg; \ |
||
| 1239 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
||
| 1240 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1241 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ |
||
| 1242 | UNUSED(tmpreg); \ |
||
| 1243 | } while(0U) |
||
| 1244 | |||
| 1245 | #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) |
||
| 1246 | |||
| 1247 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1248 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1249 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1250 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1251 | |||
| 1252 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1253 | |||
| 1254 | #define __HAL_RCC_USART6_CLK_ENABLE() do { \ |
||
| 1255 | __IO uint32_t tmpreg; \ |
||
| 1256 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
||
| 1257 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1258 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ |
||
| 1259 | UNUSED(tmpreg); \ |
||
| 1260 | } while(0U) |
||
| 1261 | |||
| 1262 | #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) |
||
| 1263 | |||
| 1264 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1265 | |||
| 1266 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1267 | |||
| 1268 | #define __HAL_RCC_USART7_CLK_ENABLE() do { \ |
||
| 1269 | __IO uint32_t tmpreg; \ |
||
| 1270 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ |
||
| 1271 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1272 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\ |
||
| 1273 | UNUSED(tmpreg); \ |
||
| 1274 | } while(0U) |
||
| 1275 | #define __HAL_RCC_USART8_CLK_ENABLE() do { \ |
||
| 1276 | __IO uint32_t tmpreg; \ |
||
| 1277 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ |
||
| 1278 | /* Delay after an RCC peripheral clock enabling */ \ |
||
| 1279 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\ |
||
| 1280 | UNUSED(tmpreg); \ |
||
| 1281 | } while(0U) |
||
| 1282 | |||
| 1283 | #define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN)) |
||
| 1284 | #define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN)) |
||
| 1285 | |||
| 1286 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 1287 | |||
| 1288 | /** |
||
| 1289 | * @} |
||
| 1290 | */ |
||
| 1291 | |||
| 1292 | |||
| 1293 | /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset |
||
| 1294 | * @brief Forces or releases peripheral reset. |
||
| 1295 | * @{ |
||
| 1296 | */ |
||
| 1297 | |||
| 1298 | /** @brief Force or release AHB peripheral reset. |
||
| 1299 | */ |
||
| 1300 | #if defined(GPIOD) |
||
| 1301 | |||
| 1302 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) |
||
| 1303 | |||
| 1304 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) |
||
| 1305 | |||
| 1306 | #endif /* GPIOD */ |
||
| 1307 | |||
| 1308 | #if defined(GPIOE) |
||
| 1309 | |||
| 1310 | #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
||
| 1311 | |||
| 1312 | #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
||
| 1313 | |||
| 1314 | #endif /* GPIOE */ |
||
| 1315 | |||
| 1316 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1317 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1318 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1319 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1320 | |||
| 1321 | #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) |
||
| 1322 | |||
| 1323 | #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) |
||
| 1324 | |||
| 1325 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1326 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1327 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1328 | /* STM32F091xC || STM32F098xx */ |
||
| 1329 | |||
| 1330 | /** @brief Force or release APB1 peripheral reset. |
||
| 1331 | */ |
||
| 1332 | #if defined(STM32F030x8) \ |
||
| 1333 | || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1334 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1335 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1336 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1337 | |||
| 1338 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
||
| 1339 | #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
||
| 1340 | |||
| 1341 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
||
| 1342 | #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
||
| 1343 | |||
| 1344 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1345 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1346 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1347 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1348 | |||
| 1349 | #if defined(STM32F031x6) || defined(STM32F038xx)\ |
||
| 1350 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1351 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1352 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1353 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1354 | |||
| 1355 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
||
| 1356 | |||
| 1357 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
||
| 1358 | |||
| 1359 | #endif /* STM32F031x6 || STM32F038xx || */ |
||
| 1360 | /* STM32F042x6 || STM32F048xx || */ |
||
| 1361 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1362 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1363 | /* STM32F091xC || STM32F098xx */ |
||
| 1364 | |||
| 1365 | #if defined(STM32F030x8) \ |
||
| 1366 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1367 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1368 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1369 | |||
| 1370 | #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) |
||
| 1371 | #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
||
| 1372 | |||
| 1373 | #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) |
||
| 1374 | #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
||
| 1375 | |||
| 1376 | #endif /* STM32F030x8 || */ |
||
| 1377 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1378 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1379 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1380 | |||
| 1381 | #if defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1382 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1383 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1384 | |||
| 1385 | #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) |
||
| 1386 | |||
| 1387 | #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) |
||
| 1388 | |||
| 1389 | #endif /* STM32F051x8 || STM32F058xx || */ |
||
| 1390 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1391 | /* STM32F091xC || STM32F098xx */ |
||
| 1392 | |||
| 1393 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1394 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1395 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1396 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1397 | |||
| 1398 | #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
||
| 1399 | |||
| 1400 | #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
||
| 1401 | |||
| 1402 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1403 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1404 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1405 | /* STM32F091xC || STM32F098xx */ |
||
| 1406 | |||
| 1407 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1408 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1409 | |||
| 1410 | #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
||
| 1411 | #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) |
||
| 1412 | #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) |
||
| 1413 | |||
| 1414 | #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
||
| 1415 | #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) |
||
| 1416 | #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST)) |
||
| 1417 | |||
| 1418 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1419 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1420 | |||
| 1421 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1422 | || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) |
||
| 1423 | |||
| 1424 | #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) |
||
| 1425 | |||
| 1426 | #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) |
||
| 1427 | |||
| 1428 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1429 | /* STM32F072xB || STM32F078xx || STM32F070xB */ |
||
| 1430 | |||
| 1431 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ |
||
| 1432 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1433 | |||
| 1434 | #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) |
||
| 1435 | |||
| 1436 | #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) |
||
| 1437 | |||
| 1438 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ |
||
| 1439 | /* STM32F091xC || STM32F098xx */ |
||
| 1440 | |||
| 1441 | #if defined(CRS) |
||
| 1442 | |||
| 1443 | #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) |
||
| 1444 | |||
| 1445 | #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) |
||
| 1446 | |||
| 1447 | #endif /* CRS */ |
||
| 1448 | |||
| 1449 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1450 | |||
| 1451 | #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) |
||
| 1452 | |||
| 1453 | #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST)) |
||
| 1454 | |||
| 1455 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1456 | |||
| 1457 | |||
| 1458 | /** @brief Force or release APB2 peripheral reset. |
||
| 1459 | */ |
||
| 1460 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1461 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1462 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1463 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1464 | |||
| 1465 | #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) |
||
| 1466 | |||
| 1467 | #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) |
||
| 1468 | |||
| 1469 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1470 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1471 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1472 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1473 | |||
| 1474 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1475 | |||
| 1476 | #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) |
||
| 1477 | |||
| 1478 | #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) |
||
| 1479 | |||
| 1480 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1481 | |||
| 1482 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1483 | |||
| 1484 | #define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST)) |
||
| 1485 | #define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST)) |
||
| 1486 | |||
| 1487 | #define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST)) |
||
| 1488 | #define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST)) |
||
| 1489 | |||
| 1490 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 1491 | |||
| 1492 | /** |
||
| 1493 | * @} |
||
| 1494 | */ |
||
| 1495 | |||
| 1496 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status |
||
| 1497 | * @brief Get the enable or disable status of peripheral clock. |
||
| 1498 | * @note After reset, the peripheral clock (used for registers read/write access) |
||
| 1499 | * is disabled and the application software has to enable this clock before |
||
| 1500 | * using it. |
||
| 1501 | * @{ |
||
| 1502 | */ |
||
| 1503 | /** @brief AHB Peripheral Clock Enable Disable Status |
||
| 1504 | */ |
||
| 1505 | #if defined(GPIOD) |
||
| 1506 | |||
| 1507 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) |
||
| 1508 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) |
||
| 1509 | |||
| 1510 | #endif /* GPIOD */ |
||
| 1511 | |||
| 1512 | #if defined(GPIOE) |
||
| 1513 | |||
| 1514 | #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) |
||
| 1515 | #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) |
||
| 1516 | |||
| 1517 | #endif /* GPIOE */ |
||
| 1518 | |||
| 1519 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1520 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1521 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1522 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1523 | |||
| 1524 | #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) |
||
| 1525 | #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) |
||
| 1526 | |||
| 1527 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1528 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1529 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1530 | /* STM32F091xC || STM32F098xx */ |
||
| 1531 | |||
| 1532 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1533 | |||
| 1534 | #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) |
||
| 1535 | #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) |
||
| 1536 | |||
| 1537 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 1538 | |||
| 1539 | /** @brief APB1 Peripheral Clock Enable Disable Status |
||
| 1540 | */ |
||
| 1541 | #if defined(STM32F030x8)\ |
||
| 1542 | || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1543 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1544 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1545 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1546 | |||
| 1547 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
||
| 1548 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
||
| 1549 | |||
| 1550 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
||
| 1551 | /* STM32F051x8 || STM32F058xx || STM32F070x6 || */ |
||
| 1552 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1553 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1554 | |||
| 1555 | #if defined(STM32F030x8)\ |
||
| 1556 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1557 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1558 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1559 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1560 | |||
| 1561 | #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) |
||
| 1562 | #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) |
||
| 1563 | |||
| 1564 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */ |
||
| 1565 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1566 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1567 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1568 | |||
| 1569 | #if defined(STM32F031x6) || defined(STM32F038xx)\ |
||
| 1570 | || defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1571 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1572 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1573 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1574 | |||
| 1575 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
||
| 1576 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
||
| 1577 | |||
| 1578 | #endif /* STM32F031x6 || STM32F038xx || */ |
||
| 1579 | /* STM32F042x6 || STM32F048xx || */ |
||
| 1580 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1581 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1582 | /* STM32F091xC || STM32F098xx */ |
||
| 1583 | |||
| 1584 | #if defined(STM32F030x8) \ |
||
| 1585 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1586 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1587 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1588 | |||
| 1589 | #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) |
||
| 1590 | #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) |
||
| 1591 | #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) |
||
| 1592 | #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) |
||
| 1593 | |||
| 1594 | #endif /* STM32F030x8 || */ |
||
| 1595 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1596 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1597 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1598 | |||
| 1599 | #if defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1600 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1601 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1602 | |||
| 1603 | #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) |
||
| 1604 | #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) |
||
| 1605 | |||
| 1606 | #endif /* STM32F051x8 || STM32F058xx || */ |
||
| 1607 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1608 | /* STM32F091xC || STM32F098xx */ |
||
| 1609 | |||
| 1610 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1611 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1612 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1613 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1614 | |||
| 1615 | #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) |
||
| 1616 | #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) |
||
| 1617 | |||
| 1618 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1619 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1620 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1621 | /* STM32F091xC || STM32F098xx */ |
||
| 1622 | |||
| 1623 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1624 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1625 | |||
| 1626 | #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) |
||
| 1627 | #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) |
||
| 1628 | #define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET) |
||
| 1629 | #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) |
||
| 1630 | #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) |
||
| 1631 | #define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET) |
||
| 1632 | |||
| 1633 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1634 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1635 | |||
| 1636 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1637 | || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) |
||
| 1638 | |||
| 1639 | #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) |
||
| 1640 | #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) |
||
| 1641 | |||
| 1642 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1643 | /* STM32F072xB || STM32F078xx || STM32F070xB */ |
||
| 1644 | |||
| 1645 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)\ |
||
| 1646 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1647 | |||
| 1648 | #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) |
||
| 1649 | #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) |
||
| 1650 | |||
| 1651 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */ |
||
| 1652 | /* STM32F091xC || STM32F098xx */ |
||
| 1653 | |||
| 1654 | #if defined(CRS) |
||
| 1655 | |||
| 1656 | #define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET) |
||
| 1657 | #define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET) |
||
| 1658 | |||
| 1659 | #endif /* CRS */ |
||
| 1660 | |||
| 1661 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1662 | |||
| 1663 | #define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET) |
||
| 1664 | #define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET) |
||
| 1665 | |||
| 1666 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1667 | |||
| 1668 | /** @brief APB1 Peripheral Clock Enable Disable Status |
||
| 1669 | */ |
||
| 1670 | #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6)\ |
||
| 1671 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1672 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)\ |
||
| 1673 | || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1674 | |||
| 1675 | #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) |
||
| 1676 | #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) |
||
| 1677 | |||
| 1678 | #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */ |
||
| 1679 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1680 | /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */ |
||
| 1681 | /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1682 | |||
| 1683 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
||
| 1684 | |||
| 1685 | #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) |
||
| 1686 | #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) |
||
| 1687 | |||
| 1688 | #endif /* STM32F091xC || STM32F098xx || STM32F030xC */ |
||
| 1689 | |||
| 1690 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1691 | |||
| 1692 | #define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET) |
||
| 1693 | #define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET) |
||
| 1694 | #define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET) |
||
| 1695 | #define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET) |
||
| 1696 | |||
| 1697 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 1698 | /** |
||
| 1699 | * @} |
||
| 1700 | */ |
||
| 1701 | |||
| 1702 | |||
| 1703 | /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable |
||
| 1704 | * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48). |
||
| 1705 | * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. |
||
| 1706 | * @note HSI48 can not be stopped if it is used as system clock source. In this case, |
||
| 1707 | * you have to select another source of the system clock then stop the HSI14. |
||
| 1708 | * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software |
||
| 1709 | * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be |
||
| 1710 | * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used. |
||
| 1711 | * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator |
||
| 1712 | * clock cycles. |
||
| 1713 | * @{ |
||
| 1714 | */ |
||
| 1715 | #if defined(RCC_HSI48_SUPPORT) |
||
| 1716 | |||
| 1717 | #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON) |
||
| 1718 | #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON) |
||
| 1719 | |||
| 1720 | /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state. |
||
| 1721 | * @retval The clock source can be one of the following values: |
||
| 1722 | * @arg @ref RCC_HSI48_ON HSI48 enabled |
||
| 1723 | * @arg @ref RCC_HSI48_OFF HSI48 disabled |
||
| 1724 | */ |
||
| 1725 | #define __HAL_RCC_GET_HSI48_STATE() \ |
||
| 1726 | (((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF) |
||
| 1727 | |||
| 1728 | #endif /* RCC_HSI48_SUPPORT */ |
||
| 1729 | |||
| 1730 | /** |
||
| 1731 | * @} |
||
| 1732 | */ |
||
| 1733 | |||
| 1734 | /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config |
||
| 1735 | * @{ |
||
| 1736 | */ |
||
| 1737 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1738 | || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1739 | || defined(STM32F070x6) || defined(STM32F070xB) |
||
| 1740 | |||
| 1741 | /** @brief Macro to configure the USB clock (USBCLK). |
||
| 1742 | * @param __USBCLKSOURCE__ specifies the USB clock source. |
||
| 1743 | * This parameter can be one of the following values: |
||
| 1744 | @if STM32F070xB |
||
| 1745 | @elseif STM32F070x6 |
||
| 1746 | @else |
||
| 1747 | * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock |
||
| 1748 | @endif |
||
| 1749 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock |
||
| 1750 | */ |
||
| 1751 | #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ |
||
| 1752 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__)) |
||
| 1753 | |||
| 1754 | /** @brief Macro to get the USB clock source. |
||
| 1755 | * @retval The clock source can be one of the following values: |
||
| 1756 | @if STM32F070xB |
||
| 1757 | @elseif STM32F070x6 |
||
| 1758 | @else |
||
| 1759 | * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock |
||
| 1760 | @endif |
||
| 1761 | * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock |
||
| 1762 | */ |
||
| 1763 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW))) |
||
| 1764 | |||
| 1765 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1766 | /* STM32F072xB || STM32F078xx || */ |
||
| 1767 | /* STM32F070x6 || STM32F070xB */ |
||
| 1768 | |||
| 1769 | #if defined(STM32F042x6) || defined(STM32F048xx)\ |
||
| 1770 | || defined(STM32F051x8) || defined(STM32F058xx)\ |
||
| 1771 | || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1772 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1773 | |||
| 1774 | /** @brief Macro to configure the CEC clock. |
||
| 1775 | * @param __CECCLKSOURCE__ specifies the CEC clock source. |
||
| 1776 | * This parameter can be one of the following values: |
||
| 1777 | * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock |
||
| 1778 | * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock |
||
| 1779 | */ |
||
| 1780 | #define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \ |
||
| 1781 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__)) |
||
| 1782 | |||
| 1783 | /** @brief Macro to get the HDMI CEC clock source. |
||
| 1784 | * @retval The clock source can be one of the following values: |
||
| 1785 | * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock |
||
| 1786 | * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock |
||
| 1787 | */ |
||
| 1788 | #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) |
||
| 1789 | |||
| 1790 | #endif /* STM32F042x6 || STM32F048xx || */ |
||
| 1791 | /* STM32F051x8 || STM32F058xx || */ |
||
| 1792 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
||
| 1793 | /* STM32F091xC || defined(STM32F098xx) */ |
||
| 1794 | |||
| 1795 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\ |
||
| 1796 | || defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1797 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
||
| 1798 | * @param __USART2CLKSOURCE__ specifies the USART2 clock source. |
||
| 1799 | * This parameter can be one of the following values: |
||
| 1800 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
||
| 1801 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
||
| 1802 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
||
| 1803 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
||
| 1804 | */ |
||
| 1805 | #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ |
||
| 1806 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) |
||
| 1807 | |||
| 1808 | /** @brief Macro to get the USART2 clock source. |
||
| 1809 | * @retval The clock source can be one of the following values: |
||
| 1810 | * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock |
||
| 1811 | * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock |
||
| 1812 | * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock |
||
| 1813 | * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock |
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| 1814 | */ |
||
| 1815 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) |
||
| 1816 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/ |
||
| 1817 | |||
| 1818 | #if defined(STM32F091xC) || defined(STM32F098xx) |
||
| 1819 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
||
| 1820 | * @param __USART3CLKSOURCE__ specifies the USART3 clock source. |
||
| 1821 | * This parameter can be one of the following values: |
||
| 1822 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
||
| 1823 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
||
| 1824 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
||
| 1825 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
||
| 1826 | */ |
||
| 1827 | #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ |
||
| 1828 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) |
||
| 1829 | |||
| 1830 | /** @brief Macro to get the USART3 clock source. |
||
| 1831 | * @retval The clock source can be one of the following values: |
||
| 1832 | * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock |
||
| 1833 | * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock |
||
| 1834 | * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock |
||
| 1835 | * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock |
||
| 1836 | */ |
||
| 1837 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) |
||
| 1838 | |||
| 1839 | #endif /* STM32F091xC || STM32F098xx */ |
||
| 1840 | /** |
||
| 1841 | * @} |
||
| 1842 | */ |
||
| 1843 | |||
| 1844 | /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration |
||
| 1845 | * @{ |
||
| 1846 | */ |
||
| 1847 | |||
| 1848 | /** |
||
| 1849 | * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. |
||
| 1850 | * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. |
||
| 1851 | * This parameter can be one of the following values: |
||
| 1852 | * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. |
||
| 1853 | * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. |
||
| 1854 | * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. |
||
| 1855 | * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. |
||
| 1856 | * @retval None |
||
| 1857 | */ |
||
| 1858 | #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ |
||
| 1859 | RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) |
||
| 1860 | |||
| 1861 | /** |
||
| 1862 | * @} |
||
| 1863 | */ |
||
| 1864 | |||
| 1865 | #if defined(CRS) |
||
| 1866 | |||
| 1867 | /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag |
||
| 1868 | * @{ |
||
| 1869 | */ |
||
| 1870 | /* Interrupt & Flag management */ |
||
| 1871 | |||
| 1872 | /** |
||
| 1873 | * @brief Enable the specified CRS interrupts. |
||
| 1874 | * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. |
||
| 1875 | * This parameter can be any combination of the following values: |
||
| 1876 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
||
| 1877 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
||
| 1878 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
||
| 1879 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
||
| 1880 | * @retval None |
||
| 1881 | */ |
||
| 1882 | #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) |
||
| 1883 | |||
| 1884 | /** |
||
| 1885 | * @brief Disable the specified CRS interrupts. |
||
| 1886 | * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. |
||
| 1887 | * This parameter can be any combination of the following values: |
||
| 1888 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
||
| 1889 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
||
| 1890 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
||
| 1891 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
||
| 1892 | * @retval None |
||
| 1893 | */ |
||
| 1894 | #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) |
||
| 1895 | |||
| 1896 | /** @brief Check whether the CRS interrupt has occurred or not. |
||
| 1897 | * @param __INTERRUPT__ specifies the CRS interrupt source to check. |
||
| 1898 | * This parameter can be one of the following values: |
||
| 1899 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
||
| 1900 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
||
| 1901 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
||
| 1902 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
||
| 1903 | * @retval The new state of __INTERRUPT__ (SET or RESET). |
||
| 1904 | */ |
||
| 1905 | #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) |
||
| 1906 | |||
| 1907 | /** @brief Clear the CRS interrupt pending bits |
||
| 1908 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
||
| 1909 | * This parameter can be any combination of the following values: |
||
| 1910 | * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt |
||
| 1911 | * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt |
||
| 1912 | * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt |
||
| 1913 | * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt |
||
| 1914 | * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt |
||
| 1915 | * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt |
||
| 1916 | * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt |
||
| 1917 | */ |
||
| 1918 | #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ |
||
| 1919 | if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ |
||
| 1920 | { \ |
||
| 1921 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ |
||
| 1922 | } \ |
||
| 1923 | else \ |
||
| 1924 | { \ |
||
| 1925 | WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ |
||
| 1926 | } \ |
||
| 1927 | } while(0U) |
||
| 1928 | |||
| 1929 | /** |
||
| 1930 | * @brief Check whether the specified CRS flag is set or not. |
||
| 1931 | * @param __FLAG__ specifies the flag to check. |
||
| 1932 | * This parameter can be one of the following values: |
||
| 1933 | * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK |
||
| 1934 | * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning |
||
| 1935 | * @arg @ref RCC_CRS_FLAG_ERR Error |
||
| 1936 | * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC |
||
| 1937 | * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow |
||
| 1938 | * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error |
||
| 1939 | * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed |
||
| 1940 | * @retval The new state of _FLAG_ (TRUE or FALSE). |
||
| 1941 | */ |
||
| 1942 | #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) |
||
| 1943 | |||
| 1944 | /** |
||
| 1945 | * @brief Clear the CRS specified FLAG. |
||
| 1946 | * @param __FLAG__ specifies the flag to clear. |
||
| 1947 | * This parameter can be one of the following values: |
||
| 1948 | * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK |
||
| 1949 | * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning |
||
| 1950 | * @arg @ref RCC_CRS_FLAG_ERR Error |
||
| 1951 | * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC |
||
| 1952 | * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow |
||
| 1953 | * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error |
||
| 1954 | * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed |
||
| 1955 | * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR |
||
| 1956 | * @retval None |
||
| 1957 | */ |
||
| 1958 | #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ |
||
| 1959 | if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ |
||
| 1960 | { \ |
||
| 1961 | WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ |
||
| 1962 | } \ |
||
| 1963 | else \ |
||
| 1964 | { \ |
||
| 1965 | WRITE_REG(CRS->ICR, (__FLAG__)); \ |
||
| 1966 | } \ |
||
| 1967 | } while(0U) |
||
| 1968 | |||
| 1969 | /** |
||
| 1970 | * @} |
||
| 1971 | */ |
||
| 1972 | |||
| 1973 | /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features |
||
| 1974 | * @{ |
||
| 1975 | */ |
||
| 1976 | /** |
||
| 1977 | * @brief Enable the oscillator clock for frequency error counter. |
||
| 1978 | * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. |
||
| 1979 | * @retval None |
||
| 1980 | */ |
||
| 1981 | #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) |
||
| 1982 | |||
| 1983 | /** |
||
| 1984 | * @brief Disable the oscillator clock for frequency error counter. |
||
| 1985 | * @retval None |
||
| 1986 | */ |
||
| 1987 | #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) |
||
| 1988 | |||
| 1989 | /** |
||
| 6 | mjames | 1990 | * @brief Enable the automatic hardware adjustment of TRIM bits. |
| 2 | mjames | 1991 | * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. |
| 1992 | * @retval None |
||
| 1993 | */ |
||
| 1994 | #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
||
| 1995 | |||
| 1996 | /** |
||
| 6 | mjames | 1997 | * @brief Disable the automatic hardware adjustment of TRIM bits. |
| 2 | mjames | 1998 | * @retval None |
| 1999 | */ |
||
| 2000 | #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) |
||
| 2001 | |||
| 2002 | /** |
||
| 2003 | * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies |
||
| 2004 | * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency |
||
| 2005 | * of the synchronization source after prescaling. It is then decreased by one in order to |
||
| 2006 | * reach the expected synchronization on the zero value. The formula is the following: |
||
| 2007 | * RELOAD = (fTARGET / fSYNC) -1 |
||
| 2008 | * @param __FTARGET__ Target frequency (value in Hz) |
||
| 2009 | * @param __FSYNC__ Synchronization signal frequency (value in Hz) |
||
| 2010 | * @retval None |
||
| 2011 | */ |
||
| 2012 | #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) |
||
| 2013 | |||
| 2014 | /** |
||
| 2015 | * @} |
||
| 2016 | */ |
||
| 2017 | |||
| 2018 | #endif /* CRS */ |
||
| 2019 | |||
| 2020 | /** |
||
| 2021 | * @} |
||
| 2022 | */ |
||
| 2023 | |||
| 2024 | /* Exported functions --------------------------------------------------------*/ |
||
| 2025 | /** @addtogroup RCCEx_Exported_Functions |
||
| 2026 | * @{ |
||
| 2027 | */ |
||
| 2028 | |||
| 2029 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
||
| 2030 | * @{ |
||
| 2031 | */ |
||
| 2032 | |||
| 2033 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
||
| 2034 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
||
| 2035 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
||
| 2036 | |||
| 2037 | /** |
||
| 2038 | * @} |
||
| 2039 | */ |
||
| 2040 | |||
| 2041 | #if defined(CRS) |
||
| 2042 | |||
| 2043 | /** @addtogroup RCCEx_Exported_Functions_Group3 |
||
| 2044 | * @{ |
||
| 2045 | */ |
||
| 2046 | |||
| 2047 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); |
||
| 2048 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); |
||
| 2049 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); |
||
| 2050 | uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); |
||
| 2051 | void HAL_RCCEx_CRS_IRQHandler(void); |
||
| 2052 | void HAL_RCCEx_CRS_SyncOkCallback(void); |
||
| 2053 | void HAL_RCCEx_CRS_SyncWarnCallback(void); |
||
| 2054 | void HAL_RCCEx_CRS_ExpectedSyncCallback(void); |
||
| 2055 | void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); |
||
| 2056 | |||
| 2057 | /** |
||
| 2058 | * @} |
||
| 2059 | */ |
||
| 2060 | |||
| 2061 | #endif /* CRS */ |
||
| 2062 | |||
| 2063 | /** |
||
| 2064 | * @} |
||
| 2065 | */ |
||
| 2066 | |||
| 2067 | /** |
||
| 2068 | * @} |
||
| 2069 | */ |
||
| 2070 | |||
| 2071 | /** |
||
| 2072 | * @} |
||
| 2073 | */ |
||
| 2074 | |||
| 2075 | /** |
||
| 2076 | * @} |
||
| 2077 | */ |
||
| 2078 | |||
| 2079 | #ifdef __cplusplus |
||
| 2080 | } |
||
| 2081 | #endif |
||
| 2082 | |||
| 2083 | #endif /* __STM32F0xx_HAL_RCC_EX_H */ |
||
| 2084 | |||
| 2085 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |