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2 mjames 1 
/**
2 
  ******************************************************************************
3 
  * @file    stm32f0xx_hal_rcc.h
4 
  * @author  MCD Application Team
5 
  * @brief   Header file of RCC HAL module.
6 
  ******************************************************************************
7 
  * @attention
8 
  *
9 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10 
  * All rights reserved.</center></h2>
11 
  *
12 
  * This software component is licensed by ST under BSD 3-Clause license,
13 
  * the "License"; You may not use this file except in compliance with the
14 
  * License. You may obtain a copy of the License at:
15 
  *                        opensource.org/licenses/BSD-3-Clause
16 
  *
17 
  ******************************************************************************
18 
  */
19 
 
20 
/* Define to prevent recursive inclusion -------------------------------------*/
21 
#ifndef __STM32F0xx_HAL_RCC_H
22 
#define __STM32F0xx_HAL_RCC_H
23 
 
24 
#ifdef __cplusplus
25 
 extern "C" {
26 
#endif
27 
 
28 
/* Includes ------------------------------------------------------------------*/
29 
#include "stm32f0xx_hal_def.h"
30 
 
31 
/** @addtogroup STM32F0xx_HAL_Driver
32 
  * @{
33 
  */
34 
 
35 
/** @addtogroup RCC
36 
  * @{
37 
  */
38 
 
39 
/** @addtogroup RCC_Private_Constants
40 
  * @{
41 
  */
42 
 
43 
/** @defgroup RCC_Timeout RCC Timeout
44 
  * @{
45 
  */
46 
 
47 
/* Disable Backup domain write protection state change timeout */
48 
#define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
49 
/* LSE state change timeout */
50 
#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
51 
#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
52 
#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
53 
#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
54 
#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
55 
#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
56 
#define HSI14_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1U) */
57 
#if defined(RCC_HSI48_SUPPORT)
58 
#define HSI48_TIMEOUT_VALUE        (2U)      /* 2 ms (minimum Tick + 1U) */
59 
#endif /* RCC_HSI48_SUPPORT */
60 
/**
61 
  * @}
62 
  */
63 
 
64 
/** @defgroup RCC_Register_Offset Register offsets
65 
  * @{
66 
  */
67 
#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
68 
#define RCC_CR_OFFSET             0x00
69 
#define RCC_CFGR_OFFSET           0x04
70 
#define RCC_CIR_OFFSET            0x08
71 
#define RCC_BDCR_OFFSET           0x20
72 
#define RCC_CSR_OFFSET            0x24
73 
 
74 
/**
75 
  * @}
76 
  */
77 
 
78 
 
79 
/* CR register byte 2 (Bits[23:16]) base address */
80 
#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
81 
 
82 
/* CIR register byte 1 (Bits[15:8]) base address */
83 
#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
84 
 
85 
/* CIR register byte 2 (Bits[23:16]) base address */
86 
#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
87 
 
88 
/* Defines used for Flags */
89 
#define CR_REG_INDEX                     ((uint8_t)1U)
90 
#define CR2_REG_INDEX                    ((uint8_t)2U)
91 
#define BDCR_REG_INDEX                   ((uint8_t)3U)
92 
#define CSR_REG_INDEX                    ((uint8_t)4U)
93 
 
94 
/* Bits position in  in the CFGR register */
95 
#define RCC_CFGR_PLLMUL_BITNUMBER         18U
96 
#define RCC_CFGR_HPRE_BITNUMBER           4U
97 
#define RCC_CFGR_PPRE_BITNUMBER           8U
98 
/* Flags in the CFGR2 register */
99 
#define RCC_CFGR2_PREDIV_BITNUMBER        0
100 
/* Flags in the CR register */
101 
#define RCC_CR_HSIRDY_BitNumber           1
102 
#define RCC_CR_HSERDY_BitNumber           17
103 
#define RCC_CR_PLLRDY_BitNumber           25
104 
/* Flags in the CR2 register */
105 
#define RCC_CR2_HSI14RDY_BitNumber        1
106 
#define RCC_CR2_HSI48RDY_BitNumber       16
107 
/* Flags in the BDCR register */
108 
#define RCC_BDCR_LSERDY_BitNumber         1
109 
/* Flags in the CSR register */
110 
#define RCC_CSR_LSIRDY_BitNumber          1
111 
#define RCC_CSR_V18PWRRSTF_BitNumber      23
112 
#define RCC_CSR_RMVF_BitNumber            24
113 
#define RCC_CSR_OBLRSTF_BitNumber         25
114 
#define RCC_CSR_PINRSTF_BitNumber         26
115 
#define RCC_CSR_PORRSTF_BitNumber         27
116 
#define RCC_CSR_SFTRSTF_BitNumber         28
117 
#define RCC_CSR_IWDGRSTF_BitNumber        29
118 
#define RCC_CSR_WWDGRSTF_BitNumber        30
119 
#define RCC_CSR_LPWRRSTF_BitNumber        31
120 
/* Flags in the HSITRIM register */
121 
#define RCC_CR_HSITRIM_BitNumber          3
122 
#define RCC_HSI14TRIM_BIT_NUMBER          3
123 
#define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
124 
 
125 
/**
126 
  * @}
127 
  */
128 
 
129 
/** @addtogroup RCC_Private_Macros
130 
  * @{
131 
  */
132 
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
133 
                             ((__HSE__) == RCC_HSE_BYPASS))
134 
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
135 
                             ((__LSE__) == RCC_LSE_BYPASS))
136 
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
137 
#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
138 
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
139 
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
140 
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
141 
                             ((__PLL__) == RCC_PLL_ON))
142 
#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1)  || ((__PREDIV__) == RCC_PREDIV_DIV2)   || \
143 
                                  ((__PREDIV__) == RCC_PREDIV_DIV3)  || ((__PREDIV__) == RCC_PREDIV_DIV4)   || \
144 
                                  ((__PREDIV__) == RCC_PREDIV_DIV5)  || ((__PREDIV__) == RCC_PREDIV_DIV6)   || \
145 
                                  ((__PREDIV__) == RCC_PREDIV_DIV7)  || ((__PREDIV__) == RCC_PREDIV_DIV8)   || \
146 
                                  ((__PREDIV__) == RCC_PREDIV_DIV9)  || ((__PREDIV__) == RCC_PREDIV_DIV10)  || \
147 
                                  ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12)  || \
148 
                                  ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14)  || \
149 
                                  ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))
150 
 
151 
#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3)   || \
152 
                                 ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5)   || \
153 
                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7)   || \
154 
                                 ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9)   || \
155 
                                 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11)  || \
156 
                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13)  || \
157 
                                 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15)  || \
158 
                                 ((__MUL__) == RCC_PLL_MUL16))
159 
#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
160 
                                   (((__CLK__) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
161 
                                   (((__CLK__) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1))
162 
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
163 
                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
164 
                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
165 
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
166 
                               ((__HCLK__) == RCC_SYSCLK_DIV512))
167 
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
168 
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
169 
                               ((__PCLK__) == RCC_HCLK_DIV16))
170 
#define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
171 
#define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
172 
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
173 
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
174 
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
175 
#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1)  || \
176 
                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
177 
                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
178 
                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
179 
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
180 
                                           ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
181 
 
182 
/**
183 
  * @}
184 
  */
185 
 
186 
/* Exported types ------------------------------------------------------------*/
187 
 
188 
/** @defgroup RCC_Exported_Types RCC Exported Types
189 
  * @{
190 
  */
191 
 
192 
/**
193 
  * @brief  RCC PLL configuration structure definition  
194 
  */
195 
typedef struct
196 
{
197 
  uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
198 
                              This parameter can be a value of @ref RCC_PLL_Config */
199 
 
200 
  uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
201 
                              This parameter must be a value of @ref RCC_PLL_Clock_Source */          
202 
 
203 
  uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
204 
                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
205 
 
206 
  uint32_t PREDIV;        /*!< PREDIV: Predivision factor for PLL VCO input clock
207 
                              This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
208 
 
209 
} RCC_PLLInitTypeDef;
210 
 
211 
/**
212 
  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
213 
  */
214 
typedef struct
215 
{
216 
  uint32_t OscillatorType;        /*!< The oscillators to be configured.
217 
                                       This parameter can be a value of @ref RCC_Oscillator_Type */
218 
 
219 
  uint32_t HSEState;              /*!< The new state of the HSE.
220 
                                       This parameter can be a value of @ref RCC_HSE_Config */
221 
 
222 
  uint32_t LSEState;              /*!< The new state of the LSE.
223 
                                       This parameter can be a value of @ref RCC_LSE_Config */
224 
 
225 
  uint32_t HSIState;              /*!< The new state of the HSI.
226 
                                       This parameter can be a value of @ref RCC_HSI_Config */
227 
 
228 
  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
229 
                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
230 
 
231 
  uint32_t HSI14State;             /*!< The new state of the HSI14.
232 
                                        This parameter can be a value of @ref RCC_HSI14_Config */
233 
 
234 
  uint32_t HSI14CalibrationValue;  /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
235 
                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
236 
 
237 
  uint32_t LSIState;              /*!< The new state of the LSI.
238 
                                       This parameter can be a value of @ref RCC_LSI_Config */
239 
 
240 
#if defined(RCC_HSI48_SUPPORT)
241 
  uint32_t HSI48State;            /*!< The new state of the HSI48.
242 
                                       This parameter can be a value of @ref RCC_HSI48_Config */
243 
 
244 
#endif /* RCC_HSI48_SUPPORT */
245 
  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */    
246 
 
247 
} RCC_OscInitTypeDef;
248 
 
249 
/**
250 
  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
251 
  */
252 
typedef struct
253 
{
254 
  uint32_t ClockType;             /*!< The clock to be configured.
255 
                                       This parameter can be a value of @ref RCC_System_Clock_Type */
256 
 
257 
  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
258 
                                       This parameter can be a value of @ref RCC_System_Clock_Source */
259 
 
260 
  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
261 
                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
262 
 
263 
  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
264 
                                       This parameter can be a value of @ref RCC_APB1_Clock_Source */
265 
 
266 
} RCC_ClkInitTypeDef;
267 
 
268 
/**
269 
  * @}
270 
  */
271 
 
272 
/* Exported constants --------------------------------------------------------*/
273 
/** @defgroup RCC_Exported_Constants RCC Exported Constants
274 
  * @{
275 
  */
276 
 
277 
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
278 
  * @{
279 
  */
280 
 
281 
#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */
282 
 
283 
/**
284 
  * @}
285 
  */
286 
 
287 
/** @defgroup RCC_Oscillator_Type Oscillator Type
288 
  * @{
289 
  */
290 
#define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
291 
#define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
292 
#define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
293 
#define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
294 
#define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
295 
#define RCC_OSCILLATORTYPE_HSI14           (0x00000010U)
296 
#if defined(RCC_HSI48_SUPPORT)
297 
#define RCC_OSCILLATORTYPE_HSI48           (0x00000020U)
298 
#endif /* RCC_HSI48_SUPPORT */
299 
/**
300 
  * @}
301 
  */
302 
 
303 
/** @defgroup RCC_HSE_Config HSE Config
304 
  * @{
305 
  */
306 
#define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
307 
#define RCC_HSE_ON                       (0x00000001U)                     /*!< HSE clock activation */
308 
#define RCC_HSE_BYPASS                   (0x00000005U)                     /*!< External clock source for HSE clock */
309 
/**
310 
  * @}
311 
  */
312 
 
313 
/** @defgroup RCC_LSE_Config LSE Config
314 
  * @{
315 
  */
316 
#define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
317 
#define RCC_LSE_ON                       (0x00000001U)                       /*!< LSE clock activation */
318 
#define RCC_LSE_BYPASS                   (0x00000005U)                       /*!< External clock source for LSE clock */
319 
 
320 
/**
321 
  * @}
322 
  */
323 
 
324 
/** @defgroup RCC_HSI_Config HSI Config
325 
  * @{
326 
  */
327 
#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
328 
#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
329 
 
330 
#define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
331 
 
332 
/**
333 
  * @}
334 
  */
335 
 
336 
/** @defgroup RCC_HSI14_Config RCC HSI14 Config
337 
  * @{
338 
  */
339 
#define RCC_HSI14_OFF                    (0x00000000U)
340 
#define RCC_HSI14_ON                     RCC_CR2_HSI14ON
341 
#define RCC_HSI14_ADC_CONTROL            (~RCC_CR2_HSI14DIS)
342 
 
343 
#define RCC_HSI14CALIBRATION_DEFAULT     (0x10U)   /* Default HSI14 calibration trimming value */
344 
/**
345 
  * @}
346 
  */
347 
 
348 
/** @defgroup RCC_LSI_Config LSI Config
349 
  * @{
350 
  */
351 
#define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
352 
#define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
353 
 
354 
/**
355 
  * @}
356 
  */
357 
 
358 
#if defined(RCC_HSI48_SUPPORT)
359 
/** @defgroup RCC_HSI48_Config HSI48 Config
360 
  * @{
361 
  */
362 
#define RCC_HSI48_OFF               ((uint8_t)0x00U)
363 
#define RCC_HSI48_ON                ((uint8_t)0x01U)
364 
 
365 
/**
366 
  * @}
367 
  */
368 
#endif /* RCC_HSI48_SUPPORT */
369 
 
370 
/** @defgroup RCC_PLL_Config PLL Config
371 
  * @{
372 
  */
373 
#define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
374 
#define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
375 
#define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
376 
 
377 
/**
378 
  * @}
379 
  */
380 
 
381 
/** @defgroup RCC_System_Clock_Type System Clock Type
382 
  * @{
383 
  */
384 
#define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
385 
#define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
386 
#define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
387 
 
388 
/**
389 
  * @}
390 
  */
391 
 
392 
/** @defgroup RCC_System_Clock_Source System Clock Source
393 
  * @{
394 
  */
395 
#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
396 
#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
397 
#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
398 
 
399 
/**
400 
  * @}
401 
  */
402 
 
403 
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
404 
  * @{
405 
  */
406 
#define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
407 
#define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
408 
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
409 
 
410 
/**
411 
  * @}
412 
  */
413 
 
414 
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
415 
  * @{
416 
  */
417 
#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
418 
#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
419 
#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
420 
#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
421 
#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
422 
#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
423 
#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
424 
#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
425 
#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
426 
 
427 
/**
428 
  * @}
429 
  */
430 
 
431 
/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
432 
  * @{
433 
  */
434 
#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE_DIV1  /*!< HCLK not divided */
435 
#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE_DIV2  /*!< HCLK divided by 2 */
436 
#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE_DIV4  /*!< HCLK divided by 4 */
437 
#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE_DIV8  /*!< HCLK divided by 8 */
438 
#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE_DIV16 /*!< HCLK divided by 16 */
439 
 
440 
/**
441 
  * @}
442 
  */
443 
 
444 
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
445 
  * @{
446 
  */
447 
#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)                 /*!< No clock */
448 
#define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
449 
#define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
450 
#define RCC_RTCCLKSOURCE_HSE_DIV32       RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 32 used as RTC clock */
451 
/**
452 
  * @}
453 
  */
454 
 
455 
/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
456 
  * @{
457 
  */
458 
#define RCC_PLL_MUL2                     RCC_CFGR_PLLMUL2
459 
#define RCC_PLL_MUL3                     RCC_CFGR_PLLMUL3
460 
#define RCC_PLL_MUL4                     RCC_CFGR_PLLMUL4
461 
#define RCC_PLL_MUL5                     RCC_CFGR_PLLMUL5
462 
#define RCC_PLL_MUL6                     RCC_CFGR_PLLMUL6
463 
#define RCC_PLL_MUL7                     RCC_CFGR_PLLMUL7
464 
#define RCC_PLL_MUL8                     RCC_CFGR_PLLMUL8
465 
#define RCC_PLL_MUL9                     RCC_CFGR_PLLMUL9
466 
#define RCC_PLL_MUL10                    RCC_CFGR_PLLMUL10
467 
#define RCC_PLL_MUL11                    RCC_CFGR_PLLMUL11
468 
#define RCC_PLL_MUL12                    RCC_CFGR_PLLMUL12
469 
#define RCC_PLL_MUL13                    RCC_CFGR_PLLMUL13
470 
#define RCC_PLL_MUL14                    RCC_CFGR_PLLMUL14
471 
#define RCC_PLL_MUL15                    RCC_CFGR_PLLMUL15
472 
#define RCC_PLL_MUL16                    RCC_CFGR_PLLMUL16
473 
 
474 
/**
475 
  * @}
476 
  */
477 
 
478 
/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
479 
  * @{
480 
  */
481 
 
482 
#define RCC_PREDIV_DIV1                  RCC_CFGR2_PREDIV_DIV1
483 
#define RCC_PREDIV_DIV2                  RCC_CFGR2_PREDIV_DIV2
484 
#define RCC_PREDIV_DIV3                  RCC_CFGR2_PREDIV_DIV3
485 
#define RCC_PREDIV_DIV4                  RCC_CFGR2_PREDIV_DIV4
486 
#define RCC_PREDIV_DIV5                  RCC_CFGR2_PREDIV_DIV5
487 
#define RCC_PREDIV_DIV6                  RCC_CFGR2_PREDIV_DIV6
488 
#define RCC_PREDIV_DIV7                  RCC_CFGR2_PREDIV_DIV7
489 
#define RCC_PREDIV_DIV8                  RCC_CFGR2_PREDIV_DIV8
490 
#define RCC_PREDIV_DIV9                  RCC_CFGR2_PREDIV_DIV9
491 
#define RCC_PREDIV_DIV10                 RCC_CFGR2_PREDIV_DIV10
492 
#define RCC_PREDIV_DIV11                 RCC_CFGR2_PREDIV_DIV11
493 
#define RCC_PREDIV_DIV12                 RCC_CFGR2_PREDIV_DIV12
494 
#define RCC_PREDIV_DIV13                 RCC_CFGR2_PREDIV_DIV13
495 
#define RCC_PREDIV_DIV14                 RCC_CFGR2_PREDIV_DIV14
496 
#define RCC_PREDIV_DIV15                 RCC_CFGR2_PREDIV_DIV15
497 
#define RCC_PREDIV_DIV16                 RCC_CFGR2_PREDIV_DIV16
498 
 
499 
/**
500 
  * @}
501 
  */
502 
 
503 
 
504 
/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
505 
  * @{
506 
  */
507 
#define RCC_USART1CLKSOURCE_PCLK1        RCC_CFGR3_USART1SW_PCLK
508 
#define RCC_USART1CLKSOURCE_SYSCLK       RCC_CFGR3_USART1SW_SYSCLK
509 
#define RCC_USART1CLKSOURCE_LSE          RCC_CFGR3_USART1SW_LSE
510 
#define RCC_USART1CLKSOURCE_HSI          RCC_CFGR3_USART1SW_HSI
511 
 
512 
/**
513 
  * @}
514 
  */
515 
 
516 
/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
517 
  * @{
518 
  */
519 
#define RCC_I2C1CLKSOURCE_HSI            RCC_CFGR3_I2C1SW_HSI
520 
#define RCC_I2C1CLKSOURCE_SYSCLK         RCC_CFGR3_I2C1SW_SYSCLK
521 
 
522 
/**
523 
  * @}
524 
  */
525 
/** @defgroup RCC_MCO_Index MCO Index
526 
  * @{
527 
  */
528 
#define RCC_MCO1                         (0x00000000U)
529 
#define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
530 
 
531 
/**
532 
  * @}
533 
  */
534 
 
535 
/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
536 
  * @{
537 
  */
538 
#define RCC_MCO1SOURCE_NOCLOCK            RCC_CFGR_MCO_NOCLOCK
539 
#define RCC_MCO1SOURCE_LSI                RCC_CFGR_MCO_LSI
540 
#define RCC_MCO1SOURCE_LSE                RCC_CFGR_MCO_LSE
541 
#define RCC_MCO1SOURCE_SYSCLK             RCC_CFGR_MCO_SYSCLK
542 
#define RCC_MCO1SOURCE_HSI                RCC_CFGR_MCO_HSI
543 
#define RCC_MCO1SOURCE_HSE                RCC_CFGR_MCO_HSE
544 
#define RCC_MCO1SOURCE_PLLCLK_DIV2        RCC_CFGR_MCO_PLL
545 
#define RCC_MCO1SOURCE_HSI14              RCC_CFGR_MCO_HSI14
546 
 
547 
/**
548 
  * @}
549 
  */
550 
 
551 
/** @defgroup RCC_Interrupt Interrupts
552 
  * @{
553 
  */
554 
#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
555 
#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
556 
#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
557 
#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
558 
#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
559 
#define RCC_IT_HSI14RDY                  ((uint8_t)RCC_CIR_HSI14RDYF) /*!< HSI14 Ready Interrupt flag */
560 
#if defined(RCC_CIR_HSI48RDYF)
561 
#define RCC_IT_HSI48RDY                  ((uint8_t)RCC_CIR_HSI48RDYF) /*!< HSI48 Ready Interrupt flag */
562 
#endif
563 
#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
564 
/**
565 
  * @}
566 
  */
567 
 
568 
/** @defgroup RCC_Flag Flags
569 
  *        Elements values convention: XXXYYYYYb
570 
  *           - YYYYY  : Flag position in the register
571 
  *           - XXX  : Register index
572 
  *                 - 001: CR register
573 
  *                 - 010: CR2 register
574 
  *                 - 011: BDCR register
575 
  *                 - 0100: CSR register
576 
  * @{
577 
  */
578 
/* Flags in the CR register */
579 
#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_BitNumber))
580 
#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_BitNumber))
581 
#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_BitNumber))
582 
/* Flags in the CR2 register */
583 
#define RCC_FLAG_HSI14RDY                ((uint8_t)((CR2_REG_INDEX << 5U) | RCC_CR2_HSI14RDY_BitNumber))
584 
 
585 
/* Flags in the CSR register */
586 
#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_BitNumber))
587 
#if   defined(RCC_CSR_V18PWRRSTF)
588 
#define RCC_FLAG_V18PWRRST               ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_V18PWRRSTF_BitNumber))
589 
#endif
590 
#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_BitNumber))
591 
#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_BitNumber))      /*!< PIN reset flag */
592 
#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_BitNumber))      /*!< POR/PDR reset flag */
593 
#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_BitNumber))      /*!< Software Reset flag */
594 
#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_BitNumber))     /*!< Independent Watchdog reset flag */
595 
#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_BitNumber))     /*!< Window watchdog reset flag */
596 
#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_BitNumber))     /*!< Low-Power reset flag */
597 
 
598 
/* Flags in the BDCR register */
599 
#define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_BitNumber))     /*!< External Low Speed oscillator Ready */
600 
 
601 
/**
602 
  * @}
603 
  */
604 
 
605 
/**
606 
  * @}
607 
  */
608 
 
609 
/* Exported macro ------------------------------------------------------------*/
610 
 
611 
/** @defgroup RCC_Exported_Macros RCC Exported Macros
612 
  * @{
613 
  */
614 
 
615 
/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
616 
  * @brief  Enable or disable the AHB peripheral clock.
617 
  * @note   After reset, the peripheral clock (used for registers read/write access)
618 
  *         is disabled and the application software has to enable this clock before
619 
  *         using it.
620 
  * @{  
621 
  */
622 
#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
623 
                                        __IO uint32_t tmpreg; \
624 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
625 
                                        /* Delay after an RCC peripheral clock enabling */\
626 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
627 
                                        UNUSED(tmpreg); \
628 
                                      } while(0U)
629 
#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
630 
                                        __IO uint32_t tmpreg; \
631 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
632 
                                        /* Delay after an RCC peripheral clock enabling */\
633 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
634 
                                        UNUSED(tmpreg); \
635 
                                      } while(0U)
636 
#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
637 
                                        __IO uint32_t tmpreg; \
638 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
639 
                                        /* Delay after an RCC peripheral clock enabling */\
640 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
641 
                                        UNUSED(tmpreg); \
642 
                                      } while(0U)
643 
#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
644 
                                        __IO uint32_t tmpreg; \
645 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
646 
                                        /* Delay after an RCC peripheral clock enabling */\
647 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
648 
                                        UNUSED(tmpreg); \
649 
                                      } while(0U)
650 
#define __HAL_RCC_CRC_CLK_ENABLE()   do { \
651 
                                        __IO uint32_t tmpreg; \
652 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
653 
                                        /* Delay after an RCC peripheral clock enabling */\
654 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
655 
                                        UNUSED(tmpreg); \
656 
                                      } while(0U)
657 
#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
658 
                                        __IO uint32_t tmpreg; \
659 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
660 
                                        /* Delay after an RCC peripheral clock enabling */\
661 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
662 
                                        UNUSED(tmpreg); \
663 
                                      } while(0U)
664 
#define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
665 
                                        __IO uint32_t tmpreg; \
666 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
667 
                                        /* Delay after an RCC peripheral clock enabling */\
668 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
669 
                                        UNUSED(tmpreg); \
670 
                                      } while(0U)
671 
#define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
672 
                                        __IO uint32_t tmpreg; \
673 
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
674 
                                        /* Delay after an RCC peripheral clock enabling */\
675 
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
676 
                                        UNUSED(tmpreg); \
677 
                                      } while(0U)
678 
 
679 
#define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
680 
#define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
681 
#define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
682 
#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
683 
#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
684 
#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
685 
#define __HAL_RCC_SRAM_CLK_DISABLE()         (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
686 
#define __HAL_RCC_FLITF_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
687 
/**
688 
  * @}
689 
  */
690 
 
691 
/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
692 
  * @brief  Get the enable or disable status of the AHB peripheral clock.
693 
  * @note   After reset, the peripheral clock (used for registers read/write access)
694 
  *         is disabled and the application software has to enable this clock before
695 
  *         using it.
696 
  * @{
697 
  */
698 
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()     ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
699 
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()     ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
700 
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()     ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
701 
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
702 
#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_CRCEN))   != RESET)
703 
#define __HAL_RCC_DMA1_IS_CLK_ENABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA1EN))  != RESET)
704 
#define __HAL_RCC_SRAM_IS_CLK_ENABLED()      ((RCC->AHBENR & (RCC_AHBENR_SRAMEN))  != RESET)
705 
#define __HAL_RCC_FLITF_IS_CLK_ENABLED()     ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
706 
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()    ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
707 
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()    ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
708 
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()    ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
709 
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()    ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
710 
#define __HAL_RCC_CRC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_CRCEN))   == RESET)
711 
#define __HAL_RCC_DMA1_IS_CLK_DISABLED()     ((RCC->AHBENR & (RCC_AHBENR_DMA1EN))  == RESET)
712 
#define __HAL_RCC_SRAM_IS_CLK_DISABLED()     ((RCC->AHBENR & (RCC_AHBENR_SRAMEN))  == RESET)
713 
#define __HAL_RCC_FLITF_IS_CLK_DISABLED()    ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
714 
/**
715 
  * @}
716 
  */
717 
 
718 
/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
719 
  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
720 
  * @note   After reset, the peripheral clock (used for registers read/write access)
721 
  *         is disabled and the application software has to enable this clock before
722 
  *         using it.
723 
  * @{  
724 
  */
725 
#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
726 
                                        __IO uint32_t tmpreg; \
727 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
728 
                                        /* Delay after an RCC peripheral clock enabling */\
729 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
730 
                                        UNUSED(tmpreg); \
731 
                                      } while(0U)
732 
#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
733 
                                        __IO uint32_t tmpreg; \
734 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
735 
                                        /* Delay after an RCC peripheral clock enabling */\
736 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
737 
                                        UNUSED(tmpreg); \
738 
                                      } while(0U)
739 
#define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
740 
                                        __IO uint32_t tmpreg; \
741 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
742 
                                        /* Delay after an RCC peripheral clock enabling */\
743 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
744 
                                        UNUSED(tmpreg); \
745 
                                      } while(0U)
746 
#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
747 
                                        __IO uint32_t tmpreg; \
748 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
749 
                                        /* Delay after an RCC peripheral clock enabling */\
750 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
751 
                                        UNUSED(tmpreg); \
752 
                                      } while(0U)
753 
#define __HAL_RCC_PWR_CLK_ENABLE()   do { \
754 
                                        __IO uint32_t tmpreg; \
755 
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
756 
                                        /* Delay after an RCC peripheral clock enabling */\
757 
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
758 
                                        UNUSED(tmpreg); \
759 
                                      } while(0U)
760 
 
761 
#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
762 
#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
763 
#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
764 
#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
765 
#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
766 
/**
767 
  * @}
768 
  */
769 
 
770 
/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
771 
  * @brief  Get the enable or disable status of the APB1 peripheral clock.
772 
  * @note   After reset, the peripheral clock (used for registers read/write access)
773 
  *         is disabled and the application software has to enable this clock before
774 
  *         using it.
775 
  * @{
776 
  */
777 
#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN))  != RESET)
778 
#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
779 
#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN))  != RESET)
780 
#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN))  != RESET)
781 
#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN))   != RESET)
782 
#define __HAL_RCC_TIM3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN))  == RESET)
783 
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
784 
#define __HAL_RCC_WWDG_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN))  == RESET)
785 
#define __HAL_RCC_I2C1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN))  == RESET)
786 
#define __HAL_RCC_PWR_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_PWREN))   == RESET)
787 
/**
788 
  * @}
789 
  */
790 
 
791 
 
792 
/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
793 
  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
794 
  * @note   After reset, the peripheral clock (used for registers read/write access)
795 
  *         is disabled and the application software has to enable this clock before
796 
  *         using it.
797 
  * @{  
798 
  */
799 
#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
800 
                                        __IO uint32_t tmpreg; \
801 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
802 
                                        /* Delay after an RCC peripheral clock enabling */\
803 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
804 
                                        UNUSED(tmpreg); \
805 
                                      } while(0U)
806 
#define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
807 
                                        __IO uint32_t tmpreg; \
808 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
809 
                                        /* Delay after an RCC peripheral clock enabling */\
810 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
811 
                                        UNUSED(tmpreg); \
812 
                                      } while(0U)
813 
#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
814 
                                        __IO uint32_t tmpreg; \
815 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
816 
                                        /* Delay after an RCC peripheral clock enabling */\
817 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
818 
                                        UNUSED(tmpreg); \
819 
                                      } while(0U)
820 
#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
821 
                                        __IO uint32_t tmpreg; \
822 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
823 
                                        /* Delay after an RCC peripheral clock enabling */\
824 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
825 
                                        UNUSED(tmpreg); \
826 
                                      } while(0U)
827 
#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
828 
                                        __IO uint32_t tmpreg; \
829 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
830 
                                        /* Delay after an RCC peripheral clock enabling */\
831 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
832 
                                        UNUSED(tmpreg); \
833 
                                      } while(0U)
834 
#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
835 
                                        __IO uint32_t tmpreg; \
836 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
837 
                                        /* Delay after an RCC peripheral clock enabling */\
838 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
839 
                                        UNUSED(tmpreg); \
840 
                                      } while(0U)
841 
#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
842 
                                        __IO uint32_t tmpreg; \
843 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
844 
                                        /* Delay after an RCC peripheral clock enabling */\
845 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
846 
                                        UNUSED(tmpreg); \
847 
                                      } while(0U)
848 
#define __HAL_RCC_DBGMCU_CLK_ENABLE()   do { \
849 
                                        __IO uint32_t tmpreg; \
850 
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
851 
                                        /* Delay after an RCC peripheral clock enabling */\
852 
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
853 
                                        UNUSED(tmpreg); \
854 
                                      } while(0U)
855 
 
856 
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
857 
#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
858 
#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
859 
#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
860 
#define __HAL_RCC_TIM16_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
861 
#define __HAL_RCC_TIM17_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
862 
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
863 
#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
864 
/**
865 
  * @}
866 
  */
867 
 
868 
/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
869 
  * @brief  Get the enable or disable status of the APB2 peripheral clock.
870 
  * @note   After reset, the peripheral clock (used for registers read/write access)
871 
  *         is disabled and the application software has to enable this clock before
872 
  *         using it.
873 
  * @{
874 
  */
875 
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
876 
#define __HAL_RCC_ADC1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN))   != RESET)
877 
#define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN))   != RESET)
878 
#define __HAL_RCC_SPI1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN))   != RESET)
879 
#define __HAL_RCC_TIM16_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN))  != RESET)
880 
#define __HAL_RCC_TIM17_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN))  != RESET)
881 
#define __HAL_RCC_USART1_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
882 
#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
883 
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
884 
#define __HAL_RCC_ADC1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN))   == RESET)
885 
#define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN))   == RESET)
886 
#define __HAL_RCC_SPI1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN))   == RESET)
887 
#define __HAL_RCC_TIM16_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN))  == RESET)
888 
#define __HAL_RCC_TIM17_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN))  == RESET)
889 
#define __HAL_RCC_USART1_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
890 
#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
891 
/**
892 
  * @}
893 
  */
894 
 
895 
/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
896 
  * @brief  Force or release AHB peripheral reset.
897 
  * @{  
898 
  */
899 
#define __HAL_RCC_AHB_FORCE_RESET()     (RCC->AHBRSTR = 0xFFFFFFFFU)
900 
#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
901 
#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
902 
#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
903 
#define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
904 
 
905 
#define __HAL_RCC_AHB_RELEASE_RESET()   (RCC->AHBRSTR = 0x00000000U)
906 
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
907 
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
908 
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
909 
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
910 
/**
911 
  * @}
912 
  */
913 
 
914 
/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
915 
  * @brief  Force or release APB1 peripheral reset.
916 
  * @{  
917 
  */  
918 
#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
919 
#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
920 
#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
921 
#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
922 
#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
923 
#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
924 
 
925 
#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00000000U)
926 
#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
927 
#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
928 
#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
929 
#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
930 
#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
931 
/**
932 
  * @}
933 
  */
934 
 
935 
/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
936 
  * @brief  Force or release APB2 peripheral reset.
937 
  * @{  
938 
  */    
939 
#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
940 
#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
941 
#define __HAL_RCC_ADC1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
942 
#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
943 
#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
944 
#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
945 
#define __HAL_RCC_TIM16_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
946 
#define __HAL_RCC_TIM17_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
947 
#define __HAL_RCC_DBGMCU_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
948 
 
949 
#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00000000U)
950 
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
951 
#define __HAL_RCC_ADC1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
952 
#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
953 
#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
954 
#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
955 
#define __HAL_RCC_TIM16_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
956 
#define __HAL_RCC_TIM17_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
957 
#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
958 
/**
959 
  * @}
960 
  */
961 
/** @defgroup RCC_HSI_Configuration HSI Configuration
962 
  * @{  
963 
  */
964 
 
965 
/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
966 
  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
967 
  * @note   HSI can not be stopped if it is used as system clock source. In this case,
968 
  *         you have to select another source of the system clock then stop the HSI.  
969 
  * @note   After enabling the HSI, the application software should wait on HSIRDY
970 
  *         flag to be set indicating that HSI clock is stable and can be used as
971 
  *         system clock source.  
972 
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
973 
  *         clock cycles.  
974 
  */
975 
#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)
976 
#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
977 
 
978 
/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
979 
  * @note   The calibration is used to compensate for the variations in voltage
980 
  *         and temperature that influence the frequency of the internal HSI RC.
981 
  * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
982 
  *         (default is RCC_HSICALIBRATION_DEFAULT).
983 
  *         This parameter must be a number between 0 and 0x1F.
984 
  */  
985 
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
986 
                  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
987 
 
988 
/**
989 
  * @}
990 
  */
991 
 
992 
/** @defgroup RCC_LSI_Configuration  LSI Configuration
993 
  * @{  
994 
  */
995 
 
996 
/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
997 
  * @note   After enabling the LSI, the application software should wait on
998 
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
999 
  *         be used to clock the IWDG and/or the RTC.
1000 
  */
1001 
#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
1002 
 
1003 
/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
1004 
  * @note   LSI can not be disabled if the IWDG is running.  
1005 
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
1006 
  *         clock cycles.
1007 
  */
1008 
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
1009 
 
1010 
/**
1011 
  * @}
1012 
  */
1013 
 
1014 
/** @defgroup RCC_HSE_Configuration HSE Configuration
1015 
  * @{  
1016 
  */
1017 
 
1018 
/**
1019 
  * @brief  Macro to configure the External High Speed oscillator (HSE).
1020 
  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
1021 
  *         supported by this macro. User should request a transition to HSE Off
1022 
  *         first and then HSE On or HSE Bypass.
1023 
  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
1024 
  *         software should wait on HSERDY flag to be set indicating that HSE clock
1025 
  *         is stable and can be used to clock the PLL and/or system clock.
1026 
  * @note   HSE state can not be changed if it is used directly or through the
1027 
  *         PLL as system clock. In this case, you have to select another source
1028 
  *         of the system clock then change the HSE state (ex. disable it).
1029 
  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
1030 
  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
1031 
  *         was previously enabled you have to enable it again after calling this
1032 
  *         function.
1033 
  * @param  __STATE__ specifies the new state of the HSE.
1034 
  *          This parameter can be one of the following values:
1035 
  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
1036 
  *                              6 HSE oscillator clock cycles.
1037 
  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
1038 
  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
1039 
  */
1040 
#define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
1041 
                    do{                                                     \
1042 
                      if ((__STATE__) == RCC_HSE_ON)                        \
1043 
                      {                                                     \
1044 
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
1045 
                      }                                                     \
1046 
                      else if ((__STATE__) == RCC_HSE_OFF)                  \
1047 
                      {                                                     \
1048 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
1049 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
1050 
                      }                                                     \
1051 
                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
1052 
                      {                                                     \
1053 
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
1054 
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
1055 
                      }                                                     \
1056 
                      else                                                  \
1057 
                      {                                                     \
1058 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
1059 
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
1060 
                      }                                                     \
1061 
                    }while(0U)
1062 
 
1063 
/**
1064 
  * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
1065 
  * @note   Predivision factor can not be changed if PLL is used as system clock
1066 
  *         In this case, you have to select another source of the system clock, disable the PLL and
1067 
  *         then change the HSE predivision factor.
1068 
  * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
1069 
  *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
1070 
  */
1071 
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
1072 
                  MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
1073 
 
1074 
/**
1075 
  * @}
1076 
  */
1077 
 
1078 
/** @defgroup RCC_LSE_Configuration LSE Configuration
1079 
  * @{  
1080 
  */
1081 
 
1082 
/**
1083 
  * @brief  Macro to configure the External Low Speed oscillator (LSE).
1084 
  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
1085 
  * @note   As the LSE is in the Backup domain and write access is denied to
1086 
  *         this domain after reset, you have to enable write access using
1087 
  *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
1088 
  *         (to be done once after reset).  
1089 
  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
1090 
  *         software should wait on LSERDY flag to be set indicating that LSE clock
1091 
  *         is stable and can be used to clock the RTC.
1092 
  * @param  __STATE__ specifies the new state of the LSE.
1093 
  *         This parameter can be one of the following values:
1094 
  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
1095 
  *                              6 LSE oscillator clock cycles.
1096 
  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
1097 
  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
1098 
  */
1099 
#define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
1100 
                    do{                                                     \
1101 
                      if ((__STATE__) == RCC_LSE_ON)                        \
1102 
                      {                                                     \
1103 
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
1104 
                      }                                                     \
1105 
                      else if ((__STATE__) == RCC_LSE_OFF)                  \
1106 
                      {                                                     \
1107 
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
1108 
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
1109 
                      }                                                     \
1110 
                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
1111 
                      {                                                     \
1112 
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
1113 
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
1114 
                      }                                                     \
1115 
                      else                                                  \
1116 
                      {                                                     \
1117 
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
1118 
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
1119 
                      }                                                     \
1120 
                    }while(0U)
1121 
 
1122 
/**
1123 
  * @}
1124 
  */
1125 
 
1126 
/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
1127 
  * @{  
1128 
  */
1129 
 
1130 
/** @brief  Macro to enable the Internal 14Mhz High Speed oscillator (HSI14).
1131 
  * @note   After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software
1132 
  *         should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
1133 
  *         used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used.
1134 
  *         clock cycles.
1135 
  */
1136 
#define __HAL_RCC_HSI14_ENABLE()  SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
1137 
 
1138 
/** @brief  Macro to disable the Internal 14Mhz High Speed oscillator (HSI14).
1139 
  * @note   The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
1140 
  * @note   HSI14 can not be stopped if it is used as system clock source. In this case,
1141 
  *         you have to select another source of the system clock then stop the HSI14.
1142 
  * @note   When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
1143 
  *         clock cycles.
1144 
  */
1145 
#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
1146 
 
1147 
/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
1148 
  */
1149 
#define __HAL_RCC_HSI14ADC_ENABLE()  CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
1150 
 
1151 
/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
1152 
  */
1153 
#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
1154 
 
1155 
/** @brief  Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
1156 
  * @note   The calibration is used to compensate for the variations in voltage
1157 
  *         and temperature that influence the frequency of the internal HSI14 RC.
1158 
  * @param  __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value
1159 
  *         (default is RCC_HSI14CALIBRATION_DEFAULT).
1160 
  *         This parameter must be a number between 0 and 0x1F.
1161 
  */
1162 
#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \
1163 
                  MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER)
1164 
/**
1165 
  * @}
1166 
  */
1167 
 
1168 
/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
1169 
  * @{  
1170 
  */
1171 
 
1172 
/** @brief  Macro to configure the USART1 clock (USART1CLK).
1173 
  * @param  __USART1CLKSOURCE__ specifies the USART1 clock source.
1174 
  *         This parameter can be one of the following values:
1175 
  *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1176 
  *            @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
1177 
  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
1178 
  *            @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
1179 
  */
1180 
#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
1181 
                  MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
1182 
 
1183 
/** @brief  Macro to get the USART1 clock source.
1184 
  * @retval The clock source can be one of the following values:
1185 
  *            @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
1186 
  *            @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
1187 
  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
1188 
  *            @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
1189 
  */
1190 
#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
1191 
 
1192 
/**
1193 
  * @}
1194 
  */
1195 
 
1196 
/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
1197 
  * @{  
1198 
  */
1199 
 
1200 
/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
1201 
  * @param  __I2C1CLKSOURCE__ specifies the I2C1 clock source.
1202 
  *         This parameter can be one of the following values:
1203 
  *            @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
1204 
  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
1205 
  */
1206 
#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
1207 
                  MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
1208 
 
1209 
/** @brief  Macro to get the I2C1 clock source.
1210 
  * @retval The clock source can be one of the following values:
1211 
  *            @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
1212 
  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
1213 
  */
1214 
#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
1215 
/**
1216 
  * @}
1217 
  */
1218 
 
1219 
/** @defgroup RCC_PLL_Configuration PLL Configuration
1220 
  * @{  
1221 
  */
1222 
 
1223 
/** @brief Macro to enable the main PLL.
1224 
  * @note   After enabling the main PLL, the application software should wait on
1225 
  *         PLLRDY flag to be set indicating that PLL clock is stable and can
1226 
  *         be used as system clock source.
1227 
  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
1228 
  */
1229 
#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
1230 
 
1231 
/** @brief Macro to disable the main PLL.
1232 
  * @note   The main PLL can not be disabled if it is used as system clock source
1233 
  */
1234 
#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
1235 
 
1236 
/** @brief  Macro to configure the PLL clock source, multiplication and division factors.
1237 
  * @note   This function must be used only when the main PLL is disabled.
1238 
  *  
1239 
  * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
1240 
  *          This parameter can be one of the following values:
1241 
  *            @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
1242 
  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
1243 
  * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
1244 
  *          This parameter can be one of the following values:
1245 
  *         This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
1246 
  * @param  __PREDIV__ specifies the predivider factor for PLL VCO input clock
1247 
  *         This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
1248 
  *  
1249 
  */
1250 
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
1251 
                  do { \
1252 
                    MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
1253 
                    MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
1254 
                  } while(0U)
1255 
 
1256 
 
1257 
/** @brief  Get oscillator clock selected as PLL input clock
1258 
  * @retval The clock source used for PLL entry. The returned value can be one
1259 
  *         of the following:
1260 
  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
1261 
  */
1262 
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
1263 
 
1264 
/**
1265 
  * @}
1266 
  */
1267 
 
1268 
/** @defgroup RCC_Get_Clock_source Get Clock source
1269 
  * @{  
1270 
  */
1271 
 
1272 
/**
1273 
  * @brief  Macro to configure the system clock source.
1274 
  * @param  __SYSCLKSOURCE__ specifies the system clock source.
1275 
  *          This parameter can be one of the following values:
1276 
  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
1277 
  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
1278 
  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
1279 
  */
1280 
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
1281 
                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
1282 
 
1283 
/** @brief  Macro to get the clock source used as system clock.
1284 
  * @retval The clock source used as system clock. The returned value can be one
1285 
  *         of the following:
1286 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
1287 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
1288 
  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
1289 
  */
1290 
#define __HAL_RCC_GET_SYSCLK_SOURCE()         ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
1291 
 
1292 
/**
1293 
  * @}
1294 
  */
1295 
 
1296 
/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
1297 
  * @{  
1298 
  */
1299 
 
1300 
#if defined(RCC_CFGR_MCOPRE)
1301 
/** @brief  Macro to configure the MCO clock.
1302 
  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
1303 
  *          This parameter can be one of the following values:
1304 
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
1305 
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System Clock selected as MCO clock
1306 
  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI oscillator clock selected as MCO clock
1307 
  *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
1308 
  *            @arg @ref RCC_MCO1SOURCE_LSI          LSI selected as MCO clock
1309 
  *            @arg @ref RCC_MCO1SOURCE_LSE          LSE selected as MCO clock
1310 
  *            @arg @ref RCC_MCO1SOURCE_HSI14        HSI14 selected as MCO clock
1311 
  @if STM32F042x6
1312 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1313 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1314 
  @elseif STM32F048xx
1315 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1316 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1317 
  @elseif STM32F071xB
1318 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1319 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1320 
  @elseif STM32F072xB
1321 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1322 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1323 
  @elseif STM32F078xx
1324 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1325 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1326 
  @elseif STM32F091xC
1327 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1328 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1329 
  @elseif STM32F098xx
1330 
  *            @arg @ref RCC_MCO1SOURCE_HSI48       HSI48 selected as MCO clock
1331 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1332 
  @elseif STM32F030x6
1333 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1334 
  @elseif STM32F030xC
1335 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1336 
  @elseif STM32F031x6
1337 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1338 
  @elseif STM32F038xx
1339 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1340 
  @elseif STM32F070x6
1341 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1342 
  @elseif STM32F070xB
1343 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK      PLLCLK selected as MCO clock
1344 
  @endif
1345 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2  PLLCLK Divided by 2 selected as MCO clock
1346 
  * @param  __MCODIV__ specifies the MCO clock prescaler.
1347 
  *          This parameter can be one of the following values:
1348 
  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
1349 
  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
1350 
  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
1351 
  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
1352 
  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
1353 
  *            @arg @ref RCC_MCODIV_32  MCO clock source is divided by 32
1354 
  *            @arg @ref RCC_MCODIV_64  MCO clock source is divided by 64
1355 
  *            @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
1356 
  */
1357 
#else
1358 
/** @brief  Macro to configure the MCO clock.
1359 
  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
1360 
  *         This parameter can be one of the following values:
1361 
  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
1362 
  *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System Clock selected as MCO clock
1363 
  *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
1364 
  *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
1365 
  *            @arg @ref RCC_MCO1SOURCE_LSI         LSI selected as MCO clock
1366 
  *            @arg @ref RCC_MCO1SOURCE_LSE         LSE selected as MCO clock
1367 
  *            @arg @ref RCC_MCO1SOURCE_HSI14       HSI14 selected as MCO clock
1368 
  *            @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
1369 
  * @param  __MCODIV__ specifies the MCO clock prescaler.
1370 
  *         This parameter can be one of the following values:
1371 
  *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
1372 
  */
1373 
#endif
1374 
#if   defined(RCC_CFGR_MCOPRE)
1375 
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1376 
                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1377 
#else
1378 
 
1379 
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1380 
                 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
1381 
 
1382 
#endif
1383 
 
1384 
/**
1385 
  * @}
1386 
  */
1387 
 
1388 
  /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
1389 
  * @{  
1390 
  */
1391 
 
1392 
/** @brief Macro to configure the RTC clock (RTCCLK).
1393 
  * @note   As the RTC clock configuration bits are in the Backup domain and write
1394 
  *         access is denied to this domain after reset, you have to enable write
1395 
  *         access using the Power Backup Access macro before to configure
1396 
  *         the RTC clock source (to be done once after reset).    
1397 
  * @note   Once the RTC clock is configured it cannot be changed unless the  
1398 
  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
1399 
  *         a Power On Reset (POR).
1400 
  *
1401 
  * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
1402 
  *          This parameter can be one of the following values:
1403 
  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1404 
  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1405 
  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1406 
  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
1407 
  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
1408 
  *         work in STOP and STANDBY modes, and can be used as wakeup source.
1409 
  *         However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
1410 
  *         the RTC cannot be used in STOP and STANDBY modes.
1411 
  * @note   The system must always be configured so as to get a PCLK frequency greater than or
1412 
  *             equal to the RTCCLK frequency for a proper operation of the RTC.
1413 
  */
1414 
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
1415 
 
1416 
/** @brief Macro to get the RTC clock source.
1417 
  * @retval The clock source can be one of the following values:
1418 
  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1419 
  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1420 
  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1421 
  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
1422 
  */
1423 
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1424 
 
1425 
/** @brief Macro to enable the the RTC clock.
1426 
  * @note   These macros must be used only after the RTC clock source was selected.
1427 
  */
1428 
#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
1429 
 
1430 
/** @brief Macro to disable the the RTC clock.
1431 
  * @note  These macros must be used only after the RTC clock source was selected.
1432 
  */
1433 
#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
1434 
 
1435 
/** @brief  Macro to force the Backup domain reset.
1436 
  * @note   This function resets the RTC peripheral (including the backup registers)
1437 
  *         and the RTC clock source selection in RCC_BDCR register.
1438 
  */
1439 
#define __HAL_RCC_BACKUPRESET_FORCE()  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
1440 
 
1441 
/** @brief  Macros to release the Backup domain reset.
1442 
  */
1443 
#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
1444 
 
1445 
/**
1446 
  * @}
1447 
  */
1448 
 
1449 
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1450 
  * @brief macros to manage the specified RCC Flags and interrupts.
1451 
  * @{
1452 
  */
1453 
 
1454 
/** @brief Enable RCC interrupt.
1455 
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1456 
  *          This parameter can be any combination of the following values:
1457 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1458 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
1459 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1460 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
1461 
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1462 
  *            @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
1463 
  @if STM32F042x6
1464 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1465 
  @elseif STM32F048xx
1466 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1467 
  @elseif STM32F071xB
1468 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1469 
  @elseif STM32F072xB
1470 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1471 
  @elseif STM32F078xx
1472 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1473 
  @elseif STM32F091xC
1474 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1475 
  @elseif STM32F098xx
1476 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1477 
  @endif
1478 
  */
1479 
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1480 
 
1481 
/** @brief Disable RCC interrupt.
1482 
  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1483 
  *          This parameter can be any combination of the following values:
1484 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1485 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
1486 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1487 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
1488 
  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1489 
  *            @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
1490 
  @if STM32F042x6
1491 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1492 
  @elseif STM32F048xx
1493 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1494 
  @elseif STM32F071xB
1495 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1496 
  @elseif STM32F072xB
1497 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1498 
  @elseif STM32F078xx
1499 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1500 
  @elseif STM32F091xC
1501 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1502 
  @elseif STM32F098xx
1503 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1504 
  @endif
1505 
  */
1506 
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1507 
 
1508 
/** @brief Clear the RCC's interrupt pending bits.
1509 
  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
1510 
  *          This parameter can be any combination of the following values:
1511 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1512 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1513 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1514 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1515 
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1516 
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
1517 
  *            @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
1518 
  @if STM32F042x6
1519 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1520 
  @elseif STM32F048xx
1521 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1522 
  @elseif STM32F071xB
1523 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1524 
  @elseif STM32F072xB
1525 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1526 
  @elseif STM32F078xx
1527 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1528 
  @elseif STM32F091xC
1529 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1530 
  @elseif STM32F098xx
1531 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1532 
  @endif
1533 
  */
1534 
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1535 
 
1536 
/** @brief Check the RCC's interrupt has occurred or not.
1537 
  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
1538 
  *          This parameter can be one of the following values:
1539 
  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1540 
  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1541 
  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1542 
  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1543 
  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1544 
  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
1545 
  *            @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable
1546 
  @if STM32F042x6
1547 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1548 
  @elseif STM32F048xx
1549 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1550 
  @elseif STM32F071xB
1551 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1552 
  @elseif STM32F072xB
1553 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1554 
  @elseif STM32F078xx
1555 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1556 
  @elseif STM32F091xC
1557 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1558 
  @elseif STM32F098xx
1559 
  *            @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
1560 
  @endif
1561 
  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1562 
  */
1563 
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1564 
 
1565 
/** @brief Set RMVF bit to clear the reset flags.
1566 
  *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1567 
  *         RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1568 
  */
1569 
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1570 
 
1571 
/** @brief  Check RCC flag is set or not.
1572 
  * @param  __FLAG__ specifies the flag to check.
1573 
  *          This parameter can be one of the following values:
1574 
  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
1575 
  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
1576 
  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
1577 
  *            @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready
1578 
  @if STM32F038xx
1579 
  *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1580 
  @elseif STM32F042x6
1581 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1582 
  @elseif STM32F048xx
1583 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1584 
  *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1585 
  @elseif STM32F058xx
1586 
  *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1587 
  @elseif STM32F071xB
1588 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1589 
  @elseif STM32F072xB
1590 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1591 
  @elseif STM32F078xx
1592 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1593 
  *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1594 
  @elseif STM32F091xC
1595 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1596 
  @elseif STM32F098xx
1597 
  *            @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
1598 
  *            @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
1599 
  @endif
1600 
  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
1601 
  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
1602 
  *            @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
1603 
  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
1604 
  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
1605 
  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
1606 
  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
1607 
  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
1608 
  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
1609 
  * @retval The new state of __FLAG__ (TRUE or FALSE).
1610 
  */
1611 
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :      \
1612 
                                       (((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 :    \
1613 
                                       (((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
1614 
                                       RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1615 
 
1616 
/**
1617 
  * @}
1618 
  */
1619 
 
1620 
/**
1621 
  * @}
1622 
  */
1623 
 
1624 
/* Include RCC HAL Extension module */
1625 
#include "stm32f0xx_hal_rcc_ex.h"
1626 
 
1627 
/* Exported functions --------------------------------------------------------*/
1628 
/** @addtogroup RCC_Exported_Functions
1629 
  * @{
1630 
  */
1631 
 
1632 
/** @addtogroup RCC_Exported_Functions_Group1
1633 
  * @{
1634 
  */
1635 
 
1636 
/* Initialization and de-initialization functions  ******************************/
1637 
HAL_StatusTypeDef HAL_RCC_DeInit(void);
1638 
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1639 
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
1640 
 
1641 
/**
1642 
  * @}
1643 
  */
1644 
 
1645 
/** @addtogroup RCC_Exported_Functions_Group2
1646 
  * @{
1647 
  */
1648 
 
1649 
/* Peripheral Control functions  ************************************************/
1650 
void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1651 
void              HAL_RCC_EnableCSS(void);
1652 
/* CSS NMI IRQ handler */
1653 
void              HAL_RCC_NMI_IRQHandler(void);
1654 
/* User Callbacks in non blocking mode (IT mode) */
1655 
void              HAL_RCC_CSSCallback(void);
1656 
void              HAL_RCC_DisableCSS(void);
1657 
uint32_t          HAL_RCC_GetSysClockFreq(void);
1658 
uint32_t          HAL_RCC_GetHCLKFreq(void);
1659 
uint32_t          HAL_RCC_GetPCLK1Freq(void);
1660 
void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
1661 
void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
1662 
 
1663 
/**
1664 
  * @}
1665 
  */
1666 
 
1667 
/**
1668 
  * @}
1669 
  */
1670 
 
1671 
/**
1672 
  * @}
1673 
  */
1674 
 
1675 
/**
1676 
  * @}
1677 
  */
1678 
 
1679 
#ifdef __cplusplus
1680 
}
1681 
#endif
1682 
 
1683 
#endif /* __STM32F0xx_HAL_RCC_H */
1684 
 
1685 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1686