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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_dma.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file of DMA HAL module. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef __STM32F0xx_HAL_DMA_H |
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| 22 | #define __STM32F0xx_HAL_DMA_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup DMA |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
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| 40 | |||
| 41 | /** @defgroup DMA_Exported_Types DMA Exported Types |
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| 42 | * @{ |
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| 43 | */ |
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| 44 | |||
| 45 | /** |
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| 46 | * @brief DMA Configuration Structure definition |
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| 47 | */ |
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| 48 | typedef struct |
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| 49 | { |
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| 50 | uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, |
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| 51 | from memory to memory or from peripheral to memory. |
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| 52 | This parameter can be a value of @ref DMA_Data_transfer_direction */ |
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| 53 | |||
| 54 | uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. |
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| 55 | This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ |
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| 56 | |||
| 57 | uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. |
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| 58 | This parameter can be a value of @ref DMA_Memory_incremented_mode */ |
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| 59 | |||
| 60 | uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. |
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| 61 | This parameter can be a value of @ref DMA_Peripheral_data_size */ |
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| 62 | |||
| 63 | uint32_t MemDataAlignment; /*!< Specifies the Memory data width. |
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| 64 | This parameter can be a value of @ref DMA_Memory_data_size */ |
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| 65 | |||
| 66 | uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. |
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| 67 | This parameter can be a value of @ref DMA_mode |
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| 68 | @note The circular buffer mode cannot be used if the memory-to-memory |
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| 69 | data transfer is configured on the selected Channel */ |
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| 70 | |||
| 71 | uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. |
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| 72 | This parameter can be a value of @ref DMA_Priority_level */ |
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| 73 | } DMA_InitTypeDef; |
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| 74 | |||
| 75 | /** |
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| 76 | * @brief HAL DMA State structures definition |
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| 77 | */ |
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| 78 | typedef enum |
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| 79 | { |
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| 80 | HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ |
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| 81 | HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ |
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| 82 | HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ |
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| 83 | HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ |
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| 84 | }HAL_DMA_StateTypeDef; |
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| 85 | |||
| 86 | /** |
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| 87 | * @brief HAL DMA Error Code structure definition |
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| 88 | */ |
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| 89 | typedef enum |
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| 90 | { |
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| 91 | HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ |
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| 92 | HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ |
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| 93 | }HAL_DMA_LevelCompleteTypeDef; |
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| 94 | |||
| 95 | /** |
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| 96 | * @brief HAL DMA Callback ID structure definition |
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| 97 | */ |
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| 98 | typedef enum |
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| 99 | { |
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| 100 | HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ |
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| 101 | HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ |
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| 102 | HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ |
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| 103 | HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ |
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| 104 | HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ |
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| 105 | |||
| 106 | }HAL_DMA_CallbackIDTypeDef; |
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| 107 | |||
| 108 | /** |
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| 109 | * @brief DMA handle Structure definition |
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| 110 | */ |
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| 111 | typedef struct __DMA_HandleTypeDef |
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| 112 | { |
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| 113 | DMA_Channel_TypeDef *Instance; /*!< Register base address */ |
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| 114 | |||
| 115 | DMA_InitTypeDef Init; /*!< DMA communication parameters */ |
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| 116 | |||
| 117 | HAL_LockTypeDef Lock; /*!< DMA locking object */ |
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| 118 | |||
| 119 | __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ |
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| 120 | |||
| 121 | void *Parent; /*!< Parent object state */ |
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| 122 | |||
| 123 | void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ |
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| 124 | |||
| 125 | void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ |
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| 126 | |||
| 127 | void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ |
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| 128 | |||
| 129 | void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ |
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| 130 | |||
| 131 | __IO uint32_t ErrorCode; /*!< DMA Error code */ |
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| 132 | |||
| 133 | DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ |
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| 134 | |||
| 135 | uint32_t ChannelIndex; /*!< DMA Channel Index */ |
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| 136 | } DMA_HandleTypeDef; |
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| 137 | |||
| 138 | /** |
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| 139 | * @} |
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| 140 | */ |
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| 141 | |||
| 142 | /* Exported constants --------------------------------------------------------*/ |
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| 143 | |||
| 144 | /** @defgroup DMA_Exported_Constants DMA Exported Constants |
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| 145 | * @{ |
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| 146 | */ |
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| 147 | |||
| 148 | /** @defgroup DMA_Error_Code DMA Error Code |
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| 149 | * @{ |
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| 150 | */ |
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| 151 | #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ |
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| 152 | #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ |
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| 153 | #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ |
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| 154 | #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ |
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| 155 | #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ |
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| 156 | /** |
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| 157 | * @} |
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| 158 | */ |
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| 159 | |||
| 160 | /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction |
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| 161 | * @{ |
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| 162 | */ |
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| 163 | #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ |
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| 164 | #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ |
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| 165 | #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */ |
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| 166 | |||
| 167 | /** |
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| 168 | * @} |
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| 169 | */ |
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| 170 | |||
| 171 | /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode |
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| 172 | * @{ |
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| 173 | */ |
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| 174 | #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ |
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| 175 | #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ |
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| 176 | /** |
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| 177 | * @} |
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| 178 | */ |
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| 179 | |||
| 180 | /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode |
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| 181 | * @{ |
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| 182 | */ |
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| 183 | #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ |
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| 184 | #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ |
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| 185 | /** |
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| 186 | * @} |
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| 187 | */ |
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| 188 | |||
| 189 | /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size |
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| 190 | * @{ |
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| 191 | */ |
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| 192 | #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ |
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| 193 | #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ |
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| 194 | #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ |
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| 195 | /** |
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| 196 | * @} |
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| 197 | */ |
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| 198 | |||
| 199 | /** @defgroup DMA_Memory_data_size DMA Memory data size |
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| 200 | * @{ |
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| 201 | */ |
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| 202 | #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ |
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| 203 | #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ |
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| 204 | #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ |
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| 205 | /** |
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| 206 | * @} |
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| 207 | */ |
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| 208 | |||
| 209 | /** @defgroup DMA_mode DMA mode |
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| 210 | * @{ |
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| 211 | */ |
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| 212 | #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ |
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| 213 | #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ |
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| 214 | /** |
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| 215 | * @} |
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| 216 | */ |
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| 217 | |||
| 218 | /** @defgroup DMA_Priority_level DMA Priority level |
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| 219 | * @{ |
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| 220 | */ |
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| 221 | #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ |
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| 222 | #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ |
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| 223 | #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ |
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| 224 | #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ |
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| 225 | /** |
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| 226 | * @} |
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| 227 | */ |
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| 228 | |||
| 229 | |||
| 230 | /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions |
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| 231 | * @{ |
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| 232 | */ |
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| 233 | #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
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| 234 | #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
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| 235 | #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
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| 236 | /** |
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| 237 | * @} |
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| 238 | */ |
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| 239 | |||
| 240 | /** @defgroup DMA_flag_definitions DMA flag definitions |
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| 241 | * @{ |
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| 242 | */ |
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| 243 | |||
| 244 | #define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */ |
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| 245 | #define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */ |
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| 246 | #define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */ |
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| 247 | #define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */ |
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| 248 | #define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */ |
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| 249 | #define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */ |
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| 250 | #define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */ |
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| 251 | #define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */ |
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| 252 | #define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */ |
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| 253 | #define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */ |
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| 254 | #define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */ |
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| 255 | #define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */ |
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| 256 | #define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */ |
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| 257 | #define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */ |
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| 258 | #define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */ |
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| 259 | #define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */ |
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| 260 | #define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */ |
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| 261 | #define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */ |
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| 262 | #define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */ |
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| 263 | #define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */ |
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| 264 | #define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */ |
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| 265 | #define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */ |
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| 266 | #define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */ |
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| 267 | #define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */ |
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| 268 | #define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */ |
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| 269 | #define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */ |
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| 270 | #define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */ |
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| 271 | #define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */ |
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| 272 | |||
| 273 | /** |
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| 274 | * @} |
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| 275 | */ |
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| 276 | |||
| 277 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
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| 278 | /** @defgroup HAL_DMA_remapping HAL DMA remapping |
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| 279 | * Elements values convention: 0xYYYYYYYY |
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| 280 | * - YYYYYYYY : Position in the SYSCFG register CFGR1 |
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| 281 | * @{ |
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| 282 | */ |
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| 283 | #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap |
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| 284 | 0: No remap (ADC DMA requests mapped on DMA channel 1 |
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| 285 | 1: Remap (ADC DMA requests mapped on DMA channel 2 */ |
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| 286 | #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap |
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| 287 | 0: No remap (USART1_TX DMA request mapped on DMA channel 2 |
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| 288 | 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ |
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| 289 | #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap |
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| 290 | 0: No remap (USART1_RX DMA request mapped on DMA channel 3 |
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| 291 | 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ |
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| 292 | #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap |
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| 293 | 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) |
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| 294 | 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ |
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| 295 | #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap |
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| 296 | 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 |
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| 297 | 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ |
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| 298 | #if defined (STM32F070xB) |
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| 299 | #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only. |
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| 300 | 0: Disabled, need to remap before use |
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| 301 | 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ |
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| 302 | |||
| 303 | #endif |
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| 304 | |||
| 305 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) |
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| 306 | #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only |
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| 307 | 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) |
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| 308 | 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ |
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| 309 | #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only |
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| 310 | 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) |
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| 311 | 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ |
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| 312 | #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. |
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| 313 | 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) |
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| 314 | 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ |
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| 315 | #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. |
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| 316 | 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) |
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| 317 | 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ |
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| 318 | #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. |
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| 319 | 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) |
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| 320 | 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ |
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| 321 | #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. |
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| 322 | 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) |
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| 323 | 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ |
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| 324 | #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. |
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| 325 | 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) |
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| 326 | 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ |
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| 327 | #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. |
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| 328 | 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) |
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| 329 | 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ |
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| 330 | #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. |
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| 331 | 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) |
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| 332 | 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ |
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| 333 | #endif |
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| 334 | |||
| 335 | /** |
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| 336 | * @} |
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| 337 | */ |
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| 338 | |||
| 339 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
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| 340 | /** |
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| 341 | * @} |
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| 342 | */ |
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| 343 | |||
| 344 | /* Exported macro ------------------------------------------------------------*/ |
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| 345 | /** @defgroup DMA_Exported_Macros DMA Exported Macros |
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| 346 | * @{ |
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| 347 | */ |
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| 348 | |||
| 349 | /** @brief Reset DMA handle state |
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| 350 | * @param __HANDLE__ DMA handle. |
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| 351 | * @retval None |
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| 352 | */ |
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| 353 | #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
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| 354 | |||
| 355 | /** |
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| 356 | * @brief Enable the specified DMA Channel. |
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| 357 | * @param __HANDLE__ DMA handle |
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| 358 | * @retval None |
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| 359 | */ |
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| 360 | #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
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| 361 | |||
| 362 | /** |
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| 363 | * @brief Disable the specified DMA Channel. |
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| 364 | * @param __HANDLE__ DMA handle |
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| 365 | * @retval None |
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| 366 | */ |
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| 367 | #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
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| 368 | |||
| 369 | |||
| 370 | /* Interrupt & Flag management */ |
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| 371 | |||
| 372 | /** |
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| 373 | * @brief Enables the specified DMA Channel interrupts. |
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| 374 | * @param __HANDLE__ DMA handle |
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| 375 | * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. |
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| 376 | * This parameter can be any combination of the following values: |
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| 377 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
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| 378 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
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| 379 | * @arg DMA_IT_TE: Transfer error interrupt mask |
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| 380 | * @retval None |
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| 381 | */ |
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| 382 | #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
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| 383 | |||
| 384 | /** |
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| 385 | * @brief Disables the specified DMA Channel interrupts. |
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| 386 | * @param __HANDLE__ DMA handle |
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| 387 | * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. |
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| 388 | * This parameter can be any combination of the following values: |
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| 389 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
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| 390 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
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| 391 | * @arg DMA_IT_TE: Transfer error interrupt mask |
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| 392 | * @retval None |
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| 393 | */ |
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| 394 | #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
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| 395 | |||
| 396 | /** |
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| 397 | * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. |
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| 398 | * @param __HANDLE__ DMA handle |
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| 399 | * @param __INTERRUPT__ specifies the DMA interrupt source to check. |
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| 400 | * This parameter can be one of the following values: |
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| 401 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
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| 402 | * @arg DMA_IT_HT: Half transfer complete interrupt mask |
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| 403 | * @arg DMA_IT_TE: Transfer error interrupt mask |
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| 404 | * @retval The state of DMA_IT (SET or RESET). |
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| 405 | */ |
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| 406 | #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
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| 407 | |||
| 408 | /** |
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| 409 | * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. |
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| 410 | * @param __HANDLE__ DMA handle |
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| 411 | * |
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| 412 | * @retval The number of remaining data units in the current DMA Channel transfer. |
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| 413 | */ |
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| 414 | #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
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| 415 | |||
| 416 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
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| 417 | /** @brief DMA remapping enable/disable macros |
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| 418 | * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping |
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| 419 | */ |
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| 420 | #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ |
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| 421 | SYSCFG->CFGR1 |= (__DMA_REMAP__); \ |
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| 422 | }while(0) |
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| 423 | #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ |
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| 424 | SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ |
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| 425 | }while(0) |
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| 426 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
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| 427 | |||
| 428 | /** |
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| 429 | * @} |
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| 430 | */ |
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| 431 | |||
| 432 | /* Include DMA HAL Extension module */ |
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| 433 | #include "stm32f0xx_hal_dma_ex.h" |
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| 434 | |||
| 435 | /* Exported functions --------------------------------------------------------*/ |
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| 436 | /** @addtogroup DMA_Exported_Functions |
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| 437 | * @{ |
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| 438 | */ |
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| 439 | |||
| 440 | /** @addtogroup DMA_Exported_Functions_Group1 |
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| 441 | * @{ |
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| 442 | */ |
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| 443 | /* Initialization and de-initialization functions *****************************/ |
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| 444 | HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); |
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| 445 | HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); |
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| 446 | /** |
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| 447 | * @} |
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| 448 | */ |
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| 449 | |||
| 450 | /** @addtogroup DMA_Exported_Functions_Group2 |
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| 451 | * @{ |
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| 452 | */ |
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| 453 | /* Input and Output operation functions *****************************************************/ |
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| 454 | HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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| 455 | HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); |
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| 456 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); |
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| 457 | HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); |
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| 458 | HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); |
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| 459 | void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); |
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| 460 | HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); |
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| 461 | HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); |
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| 462 | |||
| 463 | /** |
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| 464 | * @} |
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| 465 | */ |
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| 466 | |||
| 467 | /** @addtogroup DMA_Exported_Functions_Group3 |
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| 468 | * @{ |
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| 469 | */ |
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| 470 | /* Peripheral State and Error functions ***************************************/ |
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| 471 | HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); |
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| 472 | uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); |
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| 473 | /** |
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| 474 | * @} |
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| 475 | */ |
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| 476 | |||
| 477 | /** |
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| 478 | * @} |
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| 479 | */ |
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| 480 | |||
| 481 | /** @addtogroup DMA_Private_Macros |
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| 482 | * @{ |
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| 483 | */ |
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| 484 | #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ |
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| 485 | ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ |
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| 486 | ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) |
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| 487 | #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ |
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| 488 | ((STATE) == DMA_PINC_DISABLE)) |
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| 489 | |||
| 490 | #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ |
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| 491 | ((STATE) == DMA_MINC_DISABLE)) |
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| 492 | |||
| 493 | #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ |
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| 494 | ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ |
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| 495 | ((SIZE) == DMA_PDATAALIGN_WORD)) |
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| 496 | |||
| 497 | #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ |
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| 498 | ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ |
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| 499 | ((SIZE) == DMA_MDATAALIGN_WORD )) |
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| 500 | |||
| 501 | #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ |
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| 502 | ((MODE) == DMA_CIRCULAR)) |
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| 503 | #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ |
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| 504 | ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ |
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| 505 | ((PRIORITY) == DMA_PRIORITY_HIGH) || \ |
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| 506 | ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) |
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| 507 | #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) |
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| 508 | |||
| 509 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
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| 510 | |||
| 511 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) |
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| 512 | #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ |
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| 513 | ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ |
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| 514 | ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ |
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| 515 | ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ |
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| 516 | ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \ |
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| 517 | ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \ |
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| 518 | ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \ |
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| 519 | ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \ |
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| 520 | ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \ |
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| 521 | ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ |
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| 522 | ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \ |
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| 523 | ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \ |
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| 524 | ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \ |
||
| 525 | ((RMP) == DMA_REMAP_TIM3_DMA_CH6)) |
||
| 526 | #elif defined (STM32F070xB) |
||
| 527 | #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \ |
||
| 528 | ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ |
||
| 529 | ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ |
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| 530 | ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ |
||
| 531 | ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ |
||
| 532 | ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) |
||
| 533 | #else |
||
| 534 | #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \ |
||
| 535 | ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \ |
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| 536 | ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \ |
||
| 537 | ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \ |
||
| 538 | ((RMP) == DMA_REMAP_TIM17_DMA_CH2)) |
||
| 539 | #endif |
||
| 540 | |||
| 541 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
||
| 542 | |||
| 543 | |||
| 544 | /** |
||
| 545 | * @} |
||
| 546 | */ |
||
| 547 | |||
| 548 | /** |
||
| 549 | * @} |
||
| 550 | */ |
||
| 551 | |||
| 552 | /** |
||
| 553 | * @} |
||
| 554 | */ |
||
| 555 | |||
| 556 | #ifdef __cplusplus |
||
| 557 | } |
||
| 558 | #endif |
||
| 559 | |||
| 560 | #endif /* __STM32F0xx_HAL_DMA_H */ |
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| 561 | |||
| 562 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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| 563 |