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| Rev | Author | Line No. | Line |
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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32f0xx_hal_adc.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @brief Header file containing functions prototypes of ADC HAL library. |
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| 6 | ****************************************************************************** |
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| 7 | * @attention |
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| 8 | * |
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| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
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| 10 | * All rights reserved.</center></h2> |
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| 11 | * |
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| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
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| 13 | * the "License"; You may not use this file except in compliance with the |
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| 14 | * License. You may obtain a copy of the License at: |
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| 15 | * opensource.org/licenses/BSD-3-Clause |
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| 16 | * |
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| 17 | ****************************************************************************** |
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| 18 | */ |
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| 19 | |||
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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| 21 | #ifndef STM32F0xx_HAL_ADC_H |
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| 22 | #define STM32F0xx_HAL_ADC_H |
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| 23 | |||
| 24 | #ifdef __cplusplus |
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| 25 | extern "C" { |
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| 26 | #endif |
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| 27 | |||
| 28 | /* Includes ------------------------------------------------------------------*/ |
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| 29 | #include "stm32f0xx_hal_def.h" |
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| 30 | |||
| 31 | /** @addtogroup STM32F0xx_HAL_Driver |
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| 32 | * @{ |
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| 33 | */ |
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| 34 | |||
| 35 | /** @addtogroup ADC |
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| 36 | * @{ |
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| 37 | */ |
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| 38 | |||
| 39 | /* Exported types ------------------------------------------------------------*/ |
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| 40 | /** @defgroup ADC_Exported_Types ADC Exported Types |
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| 41 | * @{ |
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| 42 | */ |
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| 43 | |||
| 44 | /** |
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| 45 | * @brief Structure definition of ADC initialization and regular group |
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| 46 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
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| 47 | * ADC state can be either: |
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| 48 | * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') |
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| 49 | * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. |
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| 50 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
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| 51 | * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
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| 52 | */ |
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| 53 | typedef struct |
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| 54 | { |
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| 55 | uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. |
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| 56 | This parameter can be a value of @ref ADC_ClockPrescaler |
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| 57 | Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. |
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| 58 | Note: This parameter can be modified only if the ADC is disabled */ |
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| 59 | uint32_t Resolution; /*!< Configures the ADC resolution. |
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| 60 | This parameter can be a value of @ref ADC_Resolution */ |
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| 61 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
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| 62 | This parameter can be a value of @ref ADC_Data_align */ |
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| 63 | uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. |
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| 64 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
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| 65 | Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): |
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| 66 | If only 1 channel is set: Conversion is performed in single mode. |
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| 67 | If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
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| 68 | Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). |
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| 69 | This parameter can be a value of @ref ADC_Scan_mode */ |
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| 70 | uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. |
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| 71 | This parameter can be a value of @ref ADC_EOCSelection. */ |
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| 72 | FunctionalState LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous |
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| 73 | conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). |
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| 74 | This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. |
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| 75 | This parameter can be set to ENABLE or DISABLE. |
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| 76 | Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. |
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| 77 | Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed |
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| 78 | and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ |
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| 79 | FunctionalState LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). |
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| 80 | This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). |
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| 81 | This parameter can be set to ENABLE or DISABLE. |
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| 82 | Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ |
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| 83 | FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
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| 84 | after the selected trigger occurred (software start or external trigger). |
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| 85 | This parameter can be set to ENABLE or DISABLE. */ |
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| 86 | FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
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| 87 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
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| 88 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
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| 89 | This parameter can be set to ENABLE or DISABLE |
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| 90 | Note: Number of discontinuous ranks increment is fixed to one-by-one. */ |
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| 91 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
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| 92 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
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| 93 | This parameter can be a value of @ref ADC_External_trigger_source_Regular */ |
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| 94 | uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. |
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| 95 | If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. |
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| 96 | This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
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| 97 | FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) |
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| 98 | or in Continuous mode (DMA transfer unlimited, whatever number of conversions). |
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| 99 | Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. |
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| 100 | This parameter can be set to ENABLE or DISABLE. */ |
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| 101 | uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten |
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| 102 | This parameter has an effect on regular group only, including in DMA mode. |
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| 103 | This parameter can be a value of @ref ADC_Overrun */ |
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| 104 | uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. |
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| 105 | Unit: ADC clock cycles |
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| 106 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). |
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| 107 | Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. |
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| 108 | This parameter can be a value of @ref ADC_sampling_times |
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| 109 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
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| 110 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
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| 111 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ |
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| 112 | }ADC_InitTypeDef; |
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| 113 | |||
| 114 | /** |
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| 115 | * @brief Structure definition of ADC channel for regular group |
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| 116 | * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
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| 117 | * ADC state can be either: |
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| 118 | * - For all parameters: ADC disabled or enabled without conversion on going on regular group. |
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| 119 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
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| 120 | * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
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| 121 | */ |
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| 122 | typedef struct |
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| 123 | { |
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| 124 | uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
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| 125 | This parameter can be a value of @ref ADC_channels |
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| 126 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
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| 127 | uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. |
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| 128 | On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. |
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| 129 | Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. |
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| 130 | This parameter can be a value of @ref ADC_rank */ |
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| 131 | uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
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| 132 | Unit: ADC clock cycles |
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| 133 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). |
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| 134 | This parameter can be a value of @ref ADC_sampling_times |
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| 135 | Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. |
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| 136 | Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. |
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| 137 | If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. |
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| 138 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
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| 139 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
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| 140 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ |
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| 141 | }ADC_ChannelConfTypeDef; |
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| 142 | |||
| 143 | /** |
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| 144 | * @brief Structure definition of ADC analog watchdog |
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| 145 | * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. |
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| 146 | * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. |
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| 147 | */ |
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| 148 | typedef struct |
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| 149 | { |
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| 150 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. |
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| 151 | This parameter can be a value of @ref ADC_analog_watchdog_mode. */ |
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| 152 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
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| 153 | This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. |
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| 154 | This parameter can be a value of @ref ADC_channels. */ |
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| 155 | FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
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| 156 | This parameter can be set to ENABLE or DISABLE */ |
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| 157 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
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| 158 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
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| 159 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
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| 160 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
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| 161 | }ADC_AnalogWDGConfTypeDef; |
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| 162 | |||
| 163 | /** |
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| 164 | * @brief HAL ADC state machine: ADC states definition (bitfields) |
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| 165 | * @note ADC state machine is managed by bitfields, state must be compared |
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| 166 | * with bit by bit. |
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| 167 | * For example: |
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| 168 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " |
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| 169 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " |
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| 170 | */ |
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| 171 | /* States of ADC global scope */ |
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| 172 | #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ |
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| 173 | #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ |
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| 174 | #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ |
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| 175 | #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ |
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| 176 | |||
| 177 | /* States of ADC errors */ |
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| 178 | #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ |
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| 179 | #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ |
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| 180 | #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ |
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| 181 | |||
| 182 | /* States of ADC group regular */ |
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| 183 | #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, |
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| 184 | external trigger, low power auto power-on, multimode ADC master control) */ |
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| 185 | #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ |
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| 186 | #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ |
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| 187 | #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ |
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| 188 | |||
| 189 | /* States of ADC group injected */ |
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| 190 | #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
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| 191 | external trigger, low power auto power-on, multimode ADC master control) */ |
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| 192 | #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ |
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| 193 | #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ |
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| 194 | |||
| 195 | /* States of ADC analog watchdogs */ |
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| 196 | #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ |
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| 197 | #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ |
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| 198 | #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ |
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| 199 | |||
| 200 | /* States of ADC multi-mode */ |
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| 201 | #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ |
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| 202 | |||
| 203 | |||
| 204 | /** |
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| 205 | * @brief ADC handle Structure definition |
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| 206 | */ |
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| 207 | typedef struct __ADC_HandleTypeDef |
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| 208 | { |
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| 209 | ADC_TypeDef *Instance; /*!< Register base address */ |
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| 210 | |||
| 211 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
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| 212 | |||
| 213 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
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| 214 | |||
| 215 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
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| 216 | |||
| 217 | __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ |
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| 218 | |||
| 219 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
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| 220 | |||
| 221 | |||
| 222 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
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| 223 | void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ |
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| 224 | void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ |
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| 225 | void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ |
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| 226 | void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ |
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| 227 | void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ |
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| 228 | void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ |
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| 229 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
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| 230 | }ADC_HandleTypeDef; |
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| 231 | |||
| 232 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
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| 233 | /** |
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| 234 | * @brief HAL ADC Callback ID enumeration definition |
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| 235 | */ |
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| 236 | typedef enum |
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| 237 | { |
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| 238 | HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ |
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| 239 | HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ |
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| 240 | HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ |
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| 241 | HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ |
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| 242 | HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ |
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| 243 | HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ |
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| 244 | HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ |
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| 245 | } HAL_ADC_CallbackIDTypeDef; |
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| 246 | |||
| 247 | /** |
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| 248 | * @brief HAL ADC Callback pointer definition |
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| 249 | */ |
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| 250 | typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ |
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| 251 | |||
| 252 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
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| 253 | |||
| 254 | /** |
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| 255 | * @} |
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| 256 | */ |
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| 257 | |||
| 258 | |||
| 259 | |||
| 260 | /* Exported constants --------------------------------------------------------*/ |
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| 261 | |||
| 262 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
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| 263 | * @{ |
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| 264 | */ |
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| 265 | |||
| 266 | /** @defgroup ADC_Error_Code ADC Error Code |
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| 267 | * @{ |
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| 268 | */ |
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| 269 | #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ |
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| 270 | #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, |
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| 271 | enable/disable, erroneous state */ |
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| 272 | #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ |
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| 273 | #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ |
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| 274 | |||
| 275 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
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| 276 | #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ |
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| 277 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
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| 278 | |||
| 279 | /** |
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| 280 | * @} |
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| 281 | */ |
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| 282 | |||
| 283 | /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler |
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| 284 | * @{ |
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| 285 | */ |
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| 286 | #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ |
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| 287 | |||
| 288 | #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ |
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| 289 | #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ |
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| 290 | |||
| 291 | /** |
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| 292 | * @} |
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| 293 | */ |
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| 294 | |||
| 295 | /** @defgroup ADC_Resolution ADC Resolution |
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| 296 | * @{ |
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| 297 | */ |
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| 298 | #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ |
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| 299 | #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ |
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| 300 | #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ |
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| 301 | #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ |
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| 302 | /** |
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| 303 | * @} |
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| 304 | */ |
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| 305 | |||
| 306 | /** @defgroup ADC_Data_align ADC Data_align |
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| 307 | * @{ |
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| 308 | */ |
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| 309 | #define ADC_DATAALIGN_RIGHT (0x00000000U) |
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| 310 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) |
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| 311 | /** |
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| 312 | * @} |
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| 313 | */ |
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| 314 | |||
| 315 | /** @defgroup ADC_Scan_mode ADC Scan mode |
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| 316 | * @{ |
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| 317 | */ |
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| 318 | /* Note: Scan mode values must be compatible with other STM32 devices having */ |
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| 319 | /* a configurable sequencer. */ |
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| 320 | /* Scan direction setting values are defined by taking in account */ |
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| 321 | /* already defined values for other STM32 devices: */ |
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| 322 | /* ADC_SCAN_DISABLE (0x00000000U) */ |
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| 323 | /* ADC_SCAN_ENABLE (0x00000001U) */ |
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| 324 | /* Scan direction forward is considered as default setting equivalent */ |
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| 325 | /* to scan enable. */ |
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| 326 | /* Scan direction backward is considered as additional setting. */ |
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| 327 | /* In case of migration from another STM32 device, the user will be */ |
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| 328 | /* warned of change of setting choices with assert check. */ |
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| 329 | #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ |
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| 330 | #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ |
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| 331 | |||
| 332 | #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ |
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| 333 | |||
| 334 | /** |
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| 335 | * @} |
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| 336 | */ |
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| 337 | |||
| 338 | /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular |
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| 339 | * @{ |
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| 340 | */ |
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| 341 | #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) |
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| 342 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) |
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| 343 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) |
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| 344 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) |
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| 345 | /** |
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| 346 | * @} |
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| 347 | */ |
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| 348 | |||
| 349 | /** @defgroup ADC_EOCSelection ADC EOCSelection |
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| 350 | * @{ |
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| 351 | */ |
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| 352 | #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) |
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| 353 | #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) |
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| 354 | /** |
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| 355 | * @} |
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| 356 | */ |
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| 357 | |||
| 358 | /** @defgroup ADC_Overrun ADC Overrun |
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| 359 | * @{ |
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| 360 | */ |
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| 361 | #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) |
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| 362 | #define ADC_OVR_DATA_PRESERVED (0x00000001U) |
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| 363 | /** |
||
| 364 | * @} |
||
| 365 | */ |
||
| 366 | |||
| 367 | /** @defgroup ADC_rank ADC rank |
||
| 368 | * @{ |
||
| 369 | */ |
||
| 370 | #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ |
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| 371 | #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ |
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| 372 | /** |
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| 373 | * @} |
||
| 374 | */ |
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| 375 | |||
| 376 | /** @defgroup ADC_sampling_times ADC sampling times |
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| 377 | * @{ |
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| 378 | */ |
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| 379 | /* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ |
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| 380 | /* to distinguish this parameter versus reset value 0x00000000, */ |
||
| 381 | /* in the context of management of parameters "SamplingTimeCommon" */ |
||
| 382 | /* and "SamplingTime" (obsolete)). */ |
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| 383 | #define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */ |
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| 384 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ |
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| 385 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ |
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| 386 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ |
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| 387 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ |
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| 388 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ |
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| 389 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ |
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| 390 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ |
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| 391 | /** |
||
| 392 | * @} |
||
| 393 | */ |
||
| 394 | |||
| 395 | /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode |
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| 396 | * @{ |
||
| 397 | */ |
||
| 398 | #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) |
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| 399 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) |
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| 400 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) |
||
| 401 | /** |
||
| 402 | * @} |
||
| 403 | */ |
||
| 404 | |||
| 405 | /** @defgroup ADC_Event_type ADC Event type |
||
| 406 | * @{ |
||
| 407 | */ |
||
| 408 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ |
||
| 409 | #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ |
||
| 410 | /** |
||
| 411 | * @} |
||
| 412 | */ |
||
| 413 | |||
| 414 | /** @defgroup ADC_interrupts_definition ADC interrupts definition |
||
| 415 | * @{ |
||
| 416 | */ |
||
| 417 | #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ |
||
| 418 | #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ |
||
| 419 | #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ |
||
| 420 | #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
||
| 421 | #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ |
||
| 422 | #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ |
||
| 423 | /** |
||
| 424 | * @} |
||
| 425 | */ |
||
| 426 | |||
| 427 | /** @defgroup ADC_flags_definition ADC flags definition |
||
| 428 | * @{ |
||
| 429 | */ |
||
| 430 | #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ |
||
| 431 | #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ |
||
| 432 | #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ |
||
| 433 | #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ |
||
| 434 | #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ |
||
| 435 | #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ |
||
| 436 | /** |
||
| 437 | * @} |
||
| 438 | */ |
||
| 439 | |||
| 440 | /** |
||
| 441 | * @} |
||
| 442 | */ |
||
| 443 | |||
| 444 | |||
| 445 | /* Private constants ---------------------------------------------------------*/ |
||
| 446 | |||
| 447 | /** @addtogroup ADC_Private_Constants ADC Private Constants |
||
| 448 | * @{ |
||
| 449 | */ |
||
| 450 | |||
| 451 | /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular |
||
| 452 | * @{ |
||
| 453 | */ |
||
| 454 | |||
| 455 | /* List of external triggers of regular group for ADC1: */ |
||
| 456 | /* (used internally by HAL driver. To not use into HAL structure parameters) */ |
||
| 457 | #define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U) |
||
| 458 | #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) |
||
| 459 | #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) |
||
| 460 | #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) |
||
| 461 | #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) |
||
| 462 | /** |
||
| 463 | * @} |
||
| 464 | */ |
||
| 465 | |||
| 466 | /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ |
||
| 467 | #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) |
||
| 468 | |||
| 469 | /** |
||
| 470 | * @} |
||
| 471 | */ |
||
| 472 | |||
| 473 | |||
| 474 | /* Exported macro ------------------------------------------------------------*/ |
||
| 475 | |||
| 476 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
||
| 477 | * @{ |
||
| 478 | */ |
||
| 479 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
||
| 480 | /* final user. */ |
||
| 481 | |||
| 482 | /** |
||
| 483 | * @brief Enable the ADC peripheral |
||
| 484 | * @param __HANDLE__ ADC handle |
||
| 485 | * @retval None |
||
| 486 | */ |
||
| 487 | #define __HAL_ADC_ENABLE(__HANDLE__) \ |
||
| 488 | ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) |
||
| 489 | |||
| 490 | /** |
||
| 491 | * @brief Disable the ADC peripheral |
||
| 492 | * @param __HANDLE__ ADC handle |
||
| 493 | * @retval None |
||
| 494 | */ |
||
| 495 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
||
| 496 | do{ \ |
||
| 497 | (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ |
||
| 498 | __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ |
||
| 499 | } while(0) |
||
| 500 | |||
| 501 | /** |
||
| 502 | * @brief Enable the ADC end of conversion interrupt. |
||
| 503 | * @param __HANDLE__ ADC handle |
||
| 504 | * @param __INTERRUPT__ ADC Interrupt |
||
| 505 | * This parameter can be any combination of the following values: |
||
| 506 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
||
| 507 | * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source |
||
| 508 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
||
| 509 | * @arg ADC_IT_OVR: ADC overrun interrupt source |
||
| 510 | * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source |
||
| 511 | * @arg ADC_IT_RDY: ADC Ready interrupt source |
||
| 512 | * @retval None |
||
| 513 | */ |
||
| 514 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
||
| 515 | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
||
| 516 | |||
| 517 | /** |
||
| 518 | * @brief Disable the ADC end of conversion interrupt. |
||
| 519 | * @param __HANDLE__ ADC handle |
||
| 520 | * @param __INTERRUPT__ ADC Interrupt |
||
| 521 | * This parameter can be any combination of the following values: |
||
| 522 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
||
| 523 | * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source |
||
| 524 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
||
| 525 | * @arg ADC_IT_OVR: ADC overrun interrupt source |
||
| 526 | * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source |
||
| 527 | * @arg ADC_IT_RDY: ADC Ready interrupt source |
||
| 528 | * @retval None |
||
| 529 | */ |
||
| 530 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
||
| 531 | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
||
| 532 | |||
| 533 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
||
| 534 | * @param __HANDLE__ ADC handle |
||
| 535 | * @param __INTERRUPT__ ADC interrupt source to check |
||
| 536 | * This parameter can be any combination of the following values: |
||
| 537 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
||
| 538 | * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source |
||
| 539 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
||
| 540 | * @arg ADC_IT_OVR: ADC overrun interrupt source |
||
| 541 | * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source |
||
| 542 | * @arg ADC_IT_RDY: ADC Ready interrupt source |
||
| 543 | * @retval State ofinterruption (SET or RESET) |
||
| 544 | */ |
||
| 545 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
||
| 546 | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) |
||
| 547 | |||
| 548 | /** |
||
| 549 | * @brief Get the selected ADC's flag status. |
||
| 550 | * @param __HANDLE__ ADC handle |
||
| 551 | * @param __FLAG__ ADC flag |
||
| 552 | * This parameter can be any combination of the following values: |
||
| 553 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
||
| 554 | * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag |
||
| 555 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
||
| 556 | * @arg ADC_FLAG_OVR: ADC overrun flag |
||
| 557 | * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag |
||
| 558 | * @arg ADC_FLAG_RDY: ADC Ready flag |
||
| 559 | * @retval None |
||
| 560 | */ |
||
| 561 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ |
||
| 562 | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) |
||
| 563 | |||
| 564 | /** |
||
| 565 | * @brief Clear the ADC's pending flags |
||
| 566 | * @param __HANDLE__ ADC handle |
||
| 567 | * @param __FLAG__ ADC flag |
||
| 568 | * This parameter can be any combination of the following values: |
||
| 569 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
||
| 570 | * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag |
||
| 571 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
||
| 572 | * @arg ADC_FLAG_OVR: ADC overrun flag |
||
| 573 | * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag |
||
| 574 | * @arg ADC_FLAG_RDY: ADC Ready flag |
||
| 575 | * @retval None |
||
| 576 | */ |
||
| 577 | /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ |
||
| 578 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
||
| 579 | (((__HANDLE__)->Instance->ISR) = (__FLAG__)) |
||
| 580 | |||
| 581 | /** @brief Reset ADC handle state |
||
| 582 | * @param __HANDLE__ ADC handle |
||
| 583 | * @retval None |
||
| 584 | */ |
||
| 585 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 586 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
||
| 587 | do{ \ |
||
| 588 | (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ |
||
| 589 | (__HANDLE__)->MspInitCallback = NULL; \ |
||
| 590 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
||
| 591 | } while(0) |
||
| 592 | #else |
||
| 593 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
||
| 594 | ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
||
| 595 | #endif |
||
| 596 | |||
| 597 | /** |
||
| 598 | * @} |
||
| 599 | */ |
||
| 600 | |||
| 601 | |||
| 602 | /* Private macro -------------------------------------------------------------*/ |
||
| 603 | |||
| 604 | /** @defgroup ADC_Private_Macros ADC Private Macros |
||
| 605 | * @{ |
||
| 606 | */ |
||
| 607 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
||
| 608 | /* code of final user. */ |
||
| 609 | |||
| 610 | |||
| 611 | /** |
||
| 612 | * @brief Verification of hardware constraints before ADC can be enabled |
||
| 613 | * @param __HANDLE__ ADC handle |
||
| 614 | * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) |
||
| 615 | */ |
||
| 616 | #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ |
||
| 617 | (( ( ((__HANDLE__)->Instance->CR) & \ |
||
| 618 | (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ |
||
| 619 | ) == RESET \ |
||
| 620 | ) ? SET : RESET) |
||
| 621 | |||
| 622 | /** |
||
| 623 | * @brief Verification of hardware constraints before ADC can be disabled |
||
| 624 | * @param __HANDLE__ ADC handle |
||
| 625 | * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) |
||
| 626 | */ |
||
| 627 | #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ |
||
| 628 | (( ( ((__HANDLE__)->Instance->CR) & \ |
||
| 629 | (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ |
||
| 630 | ) ? SET : RESET) |
||
| 631 | |||
| 632 | /** |
||
| 633 | * @brief Verification of ADC state: enabled or disabled |
||
| 634 | * @param __HANDLE__ ADC handle |
||
| 635 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
||
| 636 | */ |
||
| 637 | /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
||
| 638 | /* performed automatically by hardware and flag ADC_FLAG_RDY is not */ |
||
| 639 | /* set. */ |
||
| 640 | #define ADC_IS_ENABLE(__HANDLE__) \ |
||
| 641 | (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ |
||
| 642 | (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ |
||
| 643 | ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ |
||
| 644 | ) ? SET : RESET) |
||
| 645 | |||
| 646 | /** |
||
| 647 | * @brief Test if conversion trigger of regular group is software start |
||
| 648 | * or external trigger. |
||
| 649 | * @param __HANDLE__ ADC handle |
||
| 650 | * @retval SET (software start) or RESET (external trigger) |
||
| 651 | */ |
||
| 652 | #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
||
| 653 | (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) |
||
| 654 | |||
| 655 | /** |
||
| 656 | * @brief Check if no conversion on going on regular group |
||
| 657 | * @param __HANDLE__ ADC handle |
||
| 658 | * @retval SET (conversion is on going) or RESET (no conversion is on going) |
||
| 659 | */ |
||
| 660 | #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ |
||
| 661 | (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ |
||
| 662 | ) ? RESET : SET) |
||
| 663 | |||
| 664 | /** |
||
| 665 | * @brief Returns resolution bits in CFGR1 register: RES[1:0]. |
||
| 666 | * Returned value is among parameters to @ref ADC_Resolution. |
||
| 667 | * @param __HANDLE__ ADC handle |
||
| 668 | * @retval None |
||
| 669 | */ |
||
| 670 | #define ADC_GET_RESOLUTION(__HANDLE__) \ |
||
| 671 | (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) |
||
| 672 | |||
| 673 | /** |
||
| 674 | * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. |
||
| 675 | * Returned value is among parameters to @ref ADC_Resolution. |
||
| 676 | * @param __HANDLE__ ADC handle |
||
| 677 | * @retval None |
||
| 678 | */ |
||
| 679 | #define ADC_GET_SAMPLINGTIME(__HANDLE__) \ |
||
| 680 | (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) |
||
| 681 | |||
| 682 | /** |
||
| 683 | * @brief Simultaneously clears and sets specific bits of the handle State |
||
| 684 | * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
||
| 685 | * the first parameter is the ADC handle State, the second parameter is the |
||
| 686 | * bit field to clear, the third and last parameter is the bit field to set. |
||
| 687 | * @retval None |
||
| 688 | */ |
||
| 689 | #define ADC_STATE_CLR_SET MODIFY_REG |
||
| 690 | |||
| 691 | /** |
||
| 692 | * @brief Clear ADC error code (set it to error code: "no error") |
||
| 693 | * @param __HANDLE__ ADC handle |
||
| 694 | * @retval None |
||
| 695 | */ |
||
| 696 | #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
||
| 697 | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
||
| 698 | |||
| 699 | |||
| 700 | /** |
||
| 701 | * @brief Configure the channel number into channel selection register |
||
| 702 | * @param _CHANNEL_ ADC Channel |
||
| 703 | * @retval None |
||
| 704 | */ |
||
| 705 | /* This function converts ADC channels from numbers (see defgroup ADC_channels) |
||
| 706 | to bitfields, to get the equivalence of CMSIS channels: |
||
| 707 | ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) |
||
| 708 | ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) |
||
| 709 | ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) |
||
| 710 | ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) |
||
| 711 | ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) |
||
| 712 | ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) |
||
| 713 | ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) |
||
| 714 | ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) |
||
| 715 | ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) |
||
| 716 | ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) |
||
| 717 | ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) |
||
| 718 | ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) |
||
| 719 | ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) |
||
| 720 | ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) |
||
| 721 | ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) |
||
| 722 | ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) |
||
| 723 | ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) |
||
| 724 | ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) |
||
| 725 | ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) |
||
| 726 | */ |
||
| 727 | #define ADC_CHSELR_CHANNEL(_CHANNEL_) \ |
||
| 728 | ( 1U << (_CHANNEL_)) |
||
| 729 | |||
| 730 | /** |
||
| 731 | * @brief Set the ADC's sample time |
||
| 732 | * @param _SAMPLETIME_ Sample time parameter. |
||
| 733 | * @retval None |
||
| 734 | */ |
||
| 735 | /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ |
||
| 736 | /* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ |
||
| 737 | /* distinguish this parameter versus reset value 0x00000000, */ |
||
| 738 | /* in the context of management of parameters "SamplingTimeCommon" */ |
||
| 739 | /* and "SamplingTime" (obsolete)). */ |
||
| 740 | #define ADC_SMPR_SET(_SAMPLETIME_) \ |
||
| 741 | ((_SAMPLETIME_) & (ADC_SMPR_SMP)) |
||
| 742 | |||
| 743 | /** |
||
| 744 | * @brief Set the Analog Watchdog 1 channel. |
||
| 745 | * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. |
||
| 746 | * @retval None |
||
| 747 | */ |
||
| 748 | #define ADC_CFGR_AWDCH(_CHANNEL_) \ |
||
| 749 | ((_CHANNEL_) << 26U) |
||
| 750 | |||
| 751 | /** |
||
| 752 | * @brief Enable ADC discontinuous conversion mode for regular group |
||
| 753 | * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. |
||
| 754 | * @retval None |
||
| 755 | */ |
||
| 756 | #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ |
||
| 757 | ((_REG_DISCONTINUOUS_MODE_) << 16U) |
||
| 758 | |||
| 759 | /** |
||
| 760 | * @brief Enable the ADC auto off mode. |
||
| 761 | * @param _AUTOOFF_ Auto off bit enable or disable. |
||
| 762 | * @retval None |
||
| 763 | */ |
||
| 764 | #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ |
||
| 765 | ((_AUTOOFF_) << 15U) |
||
| 766 | |||
| 767 | /** |
||
| 768 | * @brief Enable the ADC auto delay mode. |
||
| 769 | * @param _AUTOWAIT_ Auto delay bit enable or disable. |
||
| 770 | * @retval None |
||
| 771 | */ |
||
| 772 | #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ |
||
| 773 | ((_AUTOWAIT_) << 14U) |
||
| 774 | |||
| 775 | /** |
||
| 776 | * @brief Enable ADC continuous conversion mode. |
||
| 777 | * @param _CONTINUOUS_MODE_ Continuous mode. |
||
| 778 | * @retval None |
||
| 779 | */ |
||
| 780 | #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ |
||
| 781 | ((_CONTINUOUS_MODE_) << 13U) |
||
| 782 | |||
| 783 | /** |
||
| 784 | * @brief Enable ADC overrun mode. |
||
| 785 | * @param _OVERRUN_MODE_ Overrun mode. |
||
| 786 | * @retval Overun bit setting to be programmed into CFGR register |
||
| 787 | */ |
||
| 788 | /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ |
||
| 789 | /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ |
||
| 790 | /* as the default case to be compliant with other STM32 devices. */ |
||
| 791 | #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ |
||
| 792 | ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ |
||
| 793 | )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ |
||
| 794 | ) |
||
| 795 | |||
| 796 | /** |
||
| 797 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
||
| 798 | * @param _SCAN_MODE_ Scan conversion mode. |
||
| 799 | * @retval None |
||
| 800 | */ |
||
| 801 | /* Note: Scan mode set using this macro (instead of parameter direct set) */ |
||
| 802 | /* due to different modes on other STM32 devices: to avoid any */ |
||
| 803 | /* unwanted setting, the exact parameter corresponding to the device */ |
||
| 804 | /* must be passed to this macro. */ |
||
| 805 | #define ADC_SCANDIR(_SCAN_MODE_) \ |
||
| 806 | ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ |
||
| 807 | )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ |
||
| 808 | ) |
||
| 809 | |||
| 810 | /** |
||
| 811 | * @brief Enable the ADC DMA continuous request. |
||
| 812 | * @param _DMACONTREQ_MODE_ DMA continuous request mode. |
||
| 813 | * @retval None |
||
| 814 | */ |
||
| 815 | #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ |
||
| 816 | ((_DMACONTREQ_MODE_) << 1U) |
||
| 817 | |||
| 818 | /** |
||
| 819 | * @brief Configure the analog watchdog high threshold into register TR. |
||
| 820 | * @param _Threshold_ Threshold value |
||
| 821 | * @retval None |
||
| 822 | */ |
||
| 823 | #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ |
||
| 824 | ((_Threshold_) << 16U) |
||
| 825 | |||
| 826 | /** |
||
| 827 | * @brief Shift the AWD threshold in function of the selected ADC resolution. |
||
| 828 | * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. |
||
| 829 | * If resolution 12 bits, no shift. |
||
| 830 | * If resolution 10 bits, shift of 2 ranks on the left. |
||
| 831 | * If resolution 8 bits, shift of 4 ranks on the left. |
||
| 832 | * If resolution 6 bits, shift of 6 ranks on the left. |
||
| 833 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
||
| 834 | * @param __HANDLE__ ADC handle |
||
| 835 | * @param _Threshold_ Value to be shifted |
||
| 836 | * @retval None |
||
| 837 | */ |
||
| 838 | #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ |
||
| 839 | ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2)) |
||
| 840 | |||
| 841 | |||
| 842 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ |
||
| 843 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
||
| 844 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) |
||
| 845 | |||
| 846 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ |
||
| 847 | ((RESOLUTION) == ADC_RESOLUTION_10B) || \ |
||
| 848 | ((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
||
| 849 | ((RESOLUTION) == ADC_RESOLUTION_6B) ) |
||
| 850 | |||
| 851 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
||
| 852 | ((ALIGN) == ADC_DATAALIGN_LEFT) ) |
||
| 853 | |||
| 854 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ |
||
| 855 | ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) |
||
| 856 | |||
| 857 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
||
| 858 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
||
| 859 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
||
| 860 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) |
||
| 861 | |||
| 862 | #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ |
||
| 863 | ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) |
||
| 864 | |||
| 865 | #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ |
||
| 866 | ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) |
||
| 867 | |||
| 868 | #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ |
||
| 869 | ((WATCHDOG) == ADC_RANK_NONE) ) |
||
| 870 | |||
| 871 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ |
||
| 872 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ |
||
| 873 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ |
||
| 874 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ |
||
| 875 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ |
||
| 876 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ |
||
| 877 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ |
||
| 878 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) |
||
| 879 | |||
| 880 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ |
||
| 881 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
||
| 882 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) |
||
| 883 | |||
| 884 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ |
||
| 885 | ((EVENT) == ADC_OVR_EVENT) ) |
||
| 886 | |||
| 887 | /** @defgroup ADC_range_verification ADC range verification |
||
| 888 | * in function of ADC resolution selected (12, 10, 8 or 6 bits) |
||
| 889 | * @{ |
||
| 890 | */ |
||
| 891 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
||
| 892 | ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ |
||
| 893 | (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ |
||
| 894 | (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ |
||
| 895 | (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) |
||
| 896 | /** |
||
| 897 | * @} |
||
| 898 | */ |
||
| 899 | |||
| 900 | /** @defgroup ADC_regular_rank_verification ADC regular rank verification |
||
| 901 | * @{ |
||
| 902 | */ |
||
| 903 | #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U))) |
||
| 904 | /** |
||
| 905 | * @} |
||
| 906 | */ |
||
| 907 | |||
| 908 | /** |
||
| 909 | * @} |
||
| 910 | */ |
||
| 911 | |||
| 912 | /* Include ADC HAL Extension module */ |
||
| 913 | #include "stm32f0xx_hal_adc_ex.h" |
||
| 914 | |||
| 915 | /* Exported functions --------------------------------------------------------*/ |
||
| 916 | /** @addtogroup ADC_Exported_Functions |
||
| 917 | * @{ |
||
| 918 | */ |
||
| 919 | |||
| 920 | /** @addtogroup ADC_Exported_Functions_Group1 |
||
| 921 | * @{ |
||
| 922 | */ |
||
| 923 | |||
| 924 | |||
| 925 | /* Initialization and de-initialization functions **********************************/ |
||
| 926 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
||
| 927 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
||
| 928 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
||
| 929 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
||
| 930 | |||
| 931 | #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
||
| 932 | /* Callbacks Register/UnRegister functions ***********************************/ |
||
| 933 | HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); |
||
| 934 | HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); |
||
| 935 | #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
||
| 936 | |||
| 937 | /** |
||
| 938 | * @} |
||
| 939 | */ |
||
| 940 | |||
| 941 | /* IO operation functions *****************************************************/ |
||
| 942 | |||
| 943 | /** @addtogroup ADC_Exported_Functions_Group2 |
||
| 944 | * @{ |
||
| 945 | */ |
||
| 946 | |||
| 947 | |||
| 948 | /* Blocking mode: Polling */ |
||
| 949 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
||
| 950 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
||
| 951 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
||
| 952 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
||
| 953 | |||
| 954 | /* Non-blocking mode: Interruption */ |
||
| 955 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
||
| 956 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
||
| 957 | |||
| 958 | /* Non-blocking mode: DMA */ |
||
| 959 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
||
| 960 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
||
| 961 | |||
| 962 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
||
| 963 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
||
| 964 | |||
| 965 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
||
| 966 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
||
| 967 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
||
| 968 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
||
| 969 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
||
| 970 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
||
| 971 | /** |
||
| 972 | * @} |
||
| 973 | */ |
||
| 974 | |||
| 975 | |||
| 976 | /* Peripheral Control functions ***********************************************/ |
||
| 977 | /** @addtogroup ADC_Exported_Functions_Group3 |
||
| 978 | * @{ |
||
| 979 | */ |
||
| 980 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
||
| 981 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
||
| 982 | /** |
||
| 983 | * @} |
||
| 984 | */ |
||
| 985 | |||
| 986 | |||
| 987 | /* Peripheral State functions *************************************************/ |
||
| 988 | /** @addtogroup ADC_Exported_Functions_Group4 |
||
| 989 | * @{ |
||
| 990 | */ |
||
| 991 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
||
| 992 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
||
| 993 | /** |
||
| 994 | * @} |
||
| 995 | */ |
||
| 996 | |||
| 997 | |||
| 998 | /** |
||
| 999 | * @} |
||
| 1000 | */ |
||
| 1001 | |||
| 1002 | |||
| 1003 | /** |
||
| 1004 | * @} |
||
| 1005 | */ |
||
| 1006 | |||
| 1007 | /** |
||
| 1008 | * @} |
||
| 1009 | */ |
||
| 1010 | |||
| 1011 | #ifdef __cplusplus |
||
| 1012 | } |
||
| 1013 | #endif |
||
| 1014 | |||
| 1015 | |||
| 1016 | #endif /* STM32F0xx_HAL_ADC_H */ |
||
| 1017 | |||
| 1018 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
||
| 1019 |