Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /* |
| 2 | * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. |
||
| 3 | * |
||
| 4 | * SPDX-License-Identifier: Apache-2.0 |
||
| 5 | * |
||
| 6 | * Licensed under the Apache License, Version 2.0 (the License); you may |
||
| 7 | * not use this file except in compliance with the License. |
||
| 8 | * You may obtain a copy of the License at |
||
| 9 | * |
||
| 10 | * www.apache.org/licenses/LICENSE-2.0 |
||
| 11 | * |
||
| 12 | * Unless required by applicable law or agreed to in writing, software |
||
| 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
||
| 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
||
| 15 | * See the License for the specific language governing permissions and |
||
| 16 | * limitations under the License. |
||
| 17 | */ |
||
| 18 | |||
| 19 | /* ---------------------------------------------------------------------- |
||
| 20 | * Project: CMSIS NN Library |
||
| 21 | * Title: arm_q7_to_q15_reordered_no_shift.c |
||
| 22 | * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift |
||
| 23 | * |
||
| 24 | * $Date: 17. January 2018 |
||
| 25 | * $Revision: V.1.0.0 |
||
| 26 | * |
||
| 27 | * Target Processor: Cortex-M cores |
||
| 28 | * |
||
| 29 | * -------------------------------------------------------------------- */ |
||
| 30 | |||
| 31 | #include "arm_nnsupportfunctions.h" |
||
| 32 | |||
| 33 | /** |
||
| 34 | * @ingroup groupSupport |
||
| 35 | */ |
||
| 36 | |||
| 37 | /** |
||
| 38 | * @addtogroup nndata_convert |
||
| 39 | * @{ |
||
| 40 | */ |
||
| 41 | |||
| 42 | /** |
||
| 43 | * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift |
||
| 44 | * @param[in] *pSrc points to the Q7 input vector |
||
| 45 | * @param[out] *pDst points to the Q15 output vector |
||
| 46 | * @param[in] blockSize length of the input vector |
||
| 47 | * @return none. |
||
| 48 | * |
||
| 49 | * @details |
||
| 50 | * |
||
| 51 | * This function does the q7 to q15 expansion with re-ordering |
||
| 52 | * |
||
| 53 | * <pre> |
||
| 54 | * | A1 | A2 | A3 | A4 | |
||
| 55 | * |
||
| 56 | * 0 7 8 15 16 23 24 31 |
||
| 57 | * </pre> |
||
| 58 | * |
||
| 59 | * is converted into: |
||
| 60 | * |
||
| 61 | * <pre> |
||
| 62 | * | A1 | A3 | and | A2 | A4 | |
||
| 63 | * |
||
| 64 | * 0 15 16 31 0 15 16 31 |
||
| 65 | * </pre> |
||
| 66 | * |
||
| 67 | * |
||
| 68 | * This looks strange but is natural considering how sign-extension is done at |
||
| 69 | * assembly level. |
||
| 70 | * |
||
| 71 | * The expansion of other other oprand will follow the same rule so that the end |
||
| 72 | * results are the same. |
||
| 73 | * |
||
| 74 | * The tail (i.e., last (N % 4) elements) will still be in original order. |
||
| 75 | * |
||
| 76 | */ |
||
| 77 | |||
| 78 | void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) |
||
| 79 | { |
||
| 80 | const q7_t *pIn = pSrc; /* Src pointer */ |
||
| 81 | uint32_t blkCnt; /* loop counter */ |
||
| 82 | |||
| 83 | #ifndef ARM_MATH_CM0_FAMILY |
||
| 84 | q31_t in; |
||
| 85 | q31_t in1, in2; |
||
| 86 | |||
| 87 | /* Run the below code for Cortex-M4 and Cortex-M3 */ |
||
| 88 | |||
| 89 | /*loop Unrolling */ |
||
| 90 | blkCnt = blockSize >> 2u; |
||
| 91 | |||
| 92 | /* First part of the processing with loop unrolling. Compute 4 outputs at a time. |
||
| 93 | ** a second loop below computes the remaining 1 to 3 samples. */ |
||
| 94 | while (blkCnt > 0u) |
||
| 95 | { |
||
| 96 | /* C = (q15_t) A << 8 */ |
||
| 97 | /* convert from q7 to q15 and then store the results in the destination buffer */ |
||
| 98 | in = *__SIMD32(pIn)++; |
||
| 99 | |||
| 100 | /* rotatate in by 8 and extend two q7_t values to q15_t values */ |
||
| 101 | in1 = __SXTB16(__ROR(in, 8)); |
||
| 102 | |||
| 103 | /* extend remainig two q7_t values to q15_t values */ |
||
| 104 | in2 = __SXTB16(in); |
||
| 105 | |||
| 106 | #ifndef ARM_MATH_BIG_ENDIAN |
||
| 107 | *__SIMD32(pDst)++ = in2; |
||
| 108 | *__SIMD32(pDst)++ = in1; |
||
| 109 | #else |
||
| 110 | *__SIMD32(pDst)++ = in1; |
||
| 111 | *__SIMD32(pDst)++ = in2; |
||
| 112 | #endif |
||
| 113 | |||
| 114 | /* Decrement the loop counter */ |
||
| 115 | blkCnt--; |
||
| 116 | } |
||
| 117 | |||
| 118 | /* If the blockSize is not a multiple of 4, compute any remaining output samples here. |
||
| 119 | ** No loop unrolling is used. */ |
||
| 120 | blkCnt = blockSize % 0x4u; |
||
| 121 | |||
| 122 | #else |
||
| 123 | |||
| 124 | /* Run the below code for Cortex-M0 */ |
||
| 125 | |||
| 126 | /* Loop over blockSize number of values */ |
||
| 127 | blkCnt = blockSize; |
||
| 128 | |||
| 129 | #endif /* #ifndef ARM_MATH_CM0_FAMILY */ |
||
| 130 | |||
| 131 | while (blkCnt > 0u) |
||
| 132 | { |
||
| 133 | /* C = (q15_t) A << 8 */ |
||
| 134 | /* convert from q7 to q15 and then store the results in the destination buffer */ |
||
| 135 | *pDst++ = (q15_t) * pIn++; |
||
| 136 | |||
| 137 | /* Decrement the loop counter */ |
||
| 138 | blkCnt--; |
||
| 139 | } |
||
| 140 | |||
| 141 | } |
||
| 142 | |||
| 143 | /** |
||
| 144 | * @} end of q7_to_x group |
||
| 145 | */ |