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| 2 | mjames | 1 | /**************************************************************************//** |
| 2 | * @file core_sc000.h |
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| 3 | * @brief CMSIS SC000 Core Peripheral Access Layer Header File |
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| 4 | * @version V4.10 |
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| 5 | * @date 18. March 2015 |
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| 6 | * |
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| 7 | * @note |
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| 8 | * |
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| 9 | ******************************************************************************/ |
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| 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
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| 11 | |||
| 12 | All rights reserved. |
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| 13 | Redistribution and use in source and binary forms, with or without |
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| 14 | modification, are permitted provided that the following conditions are met: |
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| 15 | - Redistributions of source code must retain the above copyright |
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| 16 | notice, this list of conditions and the following disclaimer. |
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| 17 | - Redistributions in binary form must reproduce the above copyright |
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| 18 | notice, this list of conditions and the following disclaimer in the |
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| 19 | documentation and/or other materials provided with the distribution. |
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| 20 | - Neither the name of ARM nor the names of its contributors may be used |
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| 21 | to endorse or promote products derived from this software without |
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| 22 | specific prior written permission. |
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| 23 | * |
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| 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
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| 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 34 | POSSIBILITY OF SUCH DAMAGE. |
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| 35 | ---------------------------------------------------------------------------*/ |
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| 36 | |||
| 37 | |||
| 38 | #if defined ( __ICCARM__ ) |
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| 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
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| 40 | #endif |
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| 41 | |||
| 42 | #ifndef __CORE_SC000_H_GENERIC |
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| 43 | #define __CORE_SC000_H_GENERIC |
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| 44 | |||
| 45 | #ifdef __cplusplus |
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| 46 | extern "C" { |
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| 47 | #endif |
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| 48 | |||
| 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
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| 50 | CMSIS violates the following MISRA-C:2004 rules: |
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| 51 | |||
| 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
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| 53 | Function definitions in header files are used to allow 'inlining'. |
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| 54 | |||
| 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
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| 56 | Unions are used for effective representation of core registers. |
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| 57 | |||
| 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
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| 59 | Function-like macros are used to allow more efficient code. |
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| 60 | */ |
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| 61 | |||
| 62 | |||
| 63 | /******************************************************************************* |
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| 64 | * CMSIS definitions |
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| 65 | ******************************************************************************/ |
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| 66 | /** \ingroup SC000 |
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| 67 | @{ |
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| 68 | */ |
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| 69 | |||
| 70 | /* CMSIS SC000 definitions */ |
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| 71 | #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
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| 72 | #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
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| 73 | #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ |
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| 74 | __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
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| 75 | |||
| 76 | #define __CORTEX_SC (000) /*!< Cortex secure core */ |
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| 77 | |||
| 78 | |||
| 79 | #if defined ( __CC_ARM ) |
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| 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
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| 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
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| 82 | #define __STATIC_INLINE static __inline |
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| 83 | |||
| 84 | #elif defined ( __GNUC__ ) |
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| 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
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| 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
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| 87 | #define __STATIC_INLINE static inline |
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| 88 | |||
| 89 | #elif defined ( __ICCARM__ ) |
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| 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
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| 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
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| 92 | #define __STATIC_INLINE static inline |
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| 93 | |||
| 94 | #elif defined ( __TMS470__ ) |
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| 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
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| 96 | #define __STATIC_INLINE static inline |
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| 97 | |||
| 98 | #elif defined ( __TASKING__ ) |
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| 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
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| 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
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| 101 | #define __STATIC_INLINE static inline |
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| 102 | |||
| 103 | #elif defined ( __CSMC__ ) |
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| 104 | #define __packed |
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| 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
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| 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
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| 107 | #define __STATIC_INLINE static inline |
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| 108 | |||
| 109 | #endif |
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| 110 | |||
| 111 | /** __FPU_USED indicates whether an FPU is used or not. |
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| 112 | This core does not support an FPU at all |
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| 113 | */ |
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| 114 | #define __FPU_USED 0 |
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| 115 | |||
| 116 | #if defined ( __CC_ARM ) |
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| 117 | #if defined __TARGET_FPU_VFP |
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| 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 119 | #endif |
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| 120 | |||
| 121 | #elif defined ( __GNUC__ ) |
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| 122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
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| 123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 124 | #endif |
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| 125 | |||
| 126 | #elif defined ( __ICCARM__ ) |
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| 127 | #if defined __ARMVFP__ |
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| 128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 129 | #endif |
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| 130 | |||
| 131 | #elif defined ( __TMS470__ ) |
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| 132 | #if defined __TI__VFP_SUPPORT____ |
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| 133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 134 | #endif |
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| 135 | |||
| 136 | #elif defined ( __TASKING__ ) |
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| 137 | #if defined __FPU_VFP__ |
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| 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 139 | #endif |
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| 140 | |||
| 141 | #elif defined ( __CSMC__ ) /* Cosmic */ |
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| 142 | #if ( __CSMC__ & 0x400) // FPU present for parser |
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| 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 144 | #endif |
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| 145 | #endif |
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| 146 | |||
| 147 | #include <stdint.h> /* standard types definitions */ |
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| 148 | #include <core_cmInstr.h> /* Core Instruction Access */ |
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| 149 | #include <core_cmFunc.h> /* Core Function Access */ |
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| 150 | |||
| 151 | #ifdef __cplusplus |
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| 152 | } |
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| 153 | #endif |
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| 154 | |||
| 155 | #endif /* __CORE_SC000_H_GENERIC */ |
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| 156 | |||
| 157 | #ifndef __CMSIS_GENERIC |
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| 158 | |||
| 159 | #ifndef __CORE_SC000_H_DEPENDANT |
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| 160 | #define __CORE_SC000_H_DEPENDANT |
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| 161 | |||
| 162 | #ifdef __cplusplus |
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| 163 | extern "C" { |
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| 164 | #endif |
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| 165 | |||
| 166 | /* check device defines and use defaults */ |
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| 167 | #if defined __CHECK_DEVICE_DEFINES |
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| 168 | #ifndef __SC000_REV |
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| 169 | #define __SC000_REV 0x0000 |
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| 170 | #warning "__SC000_REV not defined in device header file; using default!" |
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| 171 | #endif |
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| 172 | |||
| 173 | #ifndef __MPU_PRESENT |
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| 174 | #define __MPU_PRESENT 0 |
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| 175 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
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| 176 | #endif |
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| 177 | |||
| 178 | #ifndef __NVIC_PRIO_BITS |
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| 179 | #define __NVIC_PRIO_BITS 2 |
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| 180 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
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| 181 | #endif |
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| 182 | |||
| 183 | #ifndef __Vendor_SysTickConfig |
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| 184 | #define __Vendor_SysTickConfig 0 |
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| 185 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
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| 186 | #endif |
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| 187 | #endif |
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| 188 | |||
| 189 | /* IO definitions (access restrictions to peripheral registers) */ |
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| 190 | /** |
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| 191 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
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| 192 | |||
| 193 | <strong>IO Type Qualifiers</strong> are used |
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| 194 | \li to specify the access to peripheral variables. |
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| 195 | \li for automatic generation of peripheral register debug information. |
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| 196 | */ |
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| 197 | #ifdef __cplusplus |
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| 198 | #define __I volatile /*!< Defines 'read only' permissions */ |
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| 199 | #else |
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| 200 | #define __I volatile const /*!< Defines 'read only' permissions */ |
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| 201 | #endif |
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| 202 | #define __O volatile /*!< Defines 'write only' permissions */ |
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| 203 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
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| 204 | |||
| 205 | /*@} end of group SC000 */ |
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| 206 | |||
| 207 | |||
| 208 | |||
| 209 | /******************************************************************************* |
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| 210 | * Register Abstraction |
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| 211 | Core Register contain: |
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| 212 | - Core Register |
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| 213 | - Core NVIC Register |
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| 214 | - Core SCB Register |
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| 215 | - Core SysTick Register |
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| 216 | - Core MPU Register |
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| 217 | ******************************************************************************/ |
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| 218 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
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| 219 | \brief Type definitions and defines for Cortex-M processor based devices. |
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| 220 | */ |
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| 221 | |||
| 222 | /** \ingroup CMSIS_core_register |
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| 223 | \defgroup CMSIS_CORE Status and Control Registers |
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| 224 | \brief Core Register type definitions. |
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| 225 | @{ |
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| 226 | */ |
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| 227 | |||
| 228 | /** \brief Union type to access the Application Program Status Register (APSR). |
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| 229 | */ |
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| 230 | typedef union |
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| 231 | { |
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| 232 | struct |
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| 233 | { |
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| 234 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
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| 235 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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| 236 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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| 237 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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| 238 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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| 239 | } b; /*!< Structure used for bit access */ |
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| 240 | uint32_t w; /*!< Type used for word access */ |
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| 241 | } APSR_Type; |
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| 242 | |||
| 243 | /* APSR Register Definitions */ |
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| 244 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
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| 245 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
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| 246 | |||
| 247 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
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| 248 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
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| 249 | |||
| 250 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
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| 251 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
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| 252 | |||
| 253 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
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| 254 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
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| 255 | |||
| 256 | |||
| 257 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
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| 258 | */ |
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| 259 | typedef union |
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| 260 | { |
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| 261 | struct |
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| 262 | { |
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| 263 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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| 264 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
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| 265 | } b; /*!< Structure used for bit access */ |
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| 266 | uint32_t w; /*!< Type used for word access */ |
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| 267 | } IPSR_Type; |
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| 268 | |||
| 269 | /* IPSR Register Definitions */ |
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| 270 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
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| 271 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
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| 272 | |||
| 273 | |||
| 274 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
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| 275 | */ |
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| 276 | typedef union |
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| 277 | { |
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| 278 | struct |
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| 279 | { |
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| 280 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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| 281 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
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| 282 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
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| 283 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
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| 284 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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| 285 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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| 286 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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| 287 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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| 288 | } b; /*!< Structure used for bit access */ |
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| 289 | uint32_t w; /*!< Type used for word access */ |
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| 290 | } xPSR_Type; |
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| 291 | |||
| 292 | /* xPSR Register Definitions */ |
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| 293 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
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| 294 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
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| 295 | |||
| 296 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
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| 297 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
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| 298 | |||
| 299 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
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| 300 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
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| 301 | |||
| 302 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
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| 303 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
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| 304 | |||
| 305 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
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| 306 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
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| 307 | |||
| 308 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
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| 309 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
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| 310 | |||
| 311 | |||
| 312 | /** \brief Union type to access the Control Registers (CONTROL). |
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| 313 | */ |
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| 314 | typedef union |
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| 315 | { |
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| 316 | struct |
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| 317 | { |
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| 318 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
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| 319 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
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| 320 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
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| 321 | } b; /*!< Structure used for bit access */ |
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| 322 | uint32_t w; /*!< Type used for word access */ |
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| 323 | } CONTROL_Type; |
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| 324 | |||
| 325 | /* CONTROL Register Definitions */ |
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| 326 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
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| 327 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
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| 328 | |||
| 329 | /*@} end of group CMSIS_CORE */ |
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| 330 | |||
| 331 | |||
| 332 | /** \ingroup CMSIS_core_register |
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| 333 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
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| 334 | \brief Type definitions for the NVIC Registers |
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| 335 | @{ |
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| 336 | */ |
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| 337 | |||
| 338 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
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| 339 | */ |
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| 340 | typedef struct |
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| 341 | { |
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| 342 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
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| 343 | uint32_t RESERVED0[31]; |
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| 344 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
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| 345 | uint32_t RSERVED1[31]; |
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| 346 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
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| 347 | uint32_t RESERVED2[31]; |
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| 348 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
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| 349 | uint32_t RESERVED3[31]; |
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| 350 | uint32_t RESERVED4[64]; |
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| 351 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
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| 352 | } NVIC_Type; |
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| 353 | |||
| 354 | /*@} end of group CMSIS_NVIC */ |
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| 355 | |||
| 356 | |||
| 357 | /** \ingroup CMSIS_core_register |
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| 358 | \defgroup CMSIS_SCB System Control Block (SCB) |
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| 359 | \brief Type definitions for the System Control Block Registers |
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| 360 | @{ |
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| 361 | */ |
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| 362 | |||
| 363 | /** \brief Structure type to access the System Control Block (SCB). |
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| 364 | */ |
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| 365 | typedef struct |
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| 366 | { |
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| 367 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
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| 368 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
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| 369 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
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| 370 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
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| 371 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
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| 372 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
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| 373 | uint32_t RESERVED0[1]; |
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| 374 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
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| 375 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
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| 376 | uint32_t RESERVED1[154]; |
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| 377 | __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ |
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| 378 | } SCB_Type; |
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| 379 | |||
| 380 | /* SCB CPUID Register Definitions */ |
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| 381 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
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| 382 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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| 383 | |||
| 384 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
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| 385 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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| 386 | |||
| 387 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
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| 388 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
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| 389 | |||
| 390 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
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| 391 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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| 392 | |||
| 393 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
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| 394 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
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| 395 | |||
| 396 | /* SCB Interrupt Control State Register Definitions */ |
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| 397 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
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| 398 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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| 399 | |||
| 400 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
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| 401 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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| 402 | |||
| 403 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
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| 404 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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| 405 | |||
| 406 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
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| 407 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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| 408 | |||
| 409 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
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| 410 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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| 411 | |||
| 412 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
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| 413 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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| 414 | |||
| 415 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
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| 416 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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| 417 | |||
| 418 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
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| 419 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
||
| 420 | |||
| 421 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
||
| 422 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||
| 423 | |||
| 424 | /* SCB Interrupt Control State Register Definitions */ |
||
| 425 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
||
| 426 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
||
| 427 | |||
| 428 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
||
| 429 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
||
| 430 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||
| 431 | |||
| 432 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||
| 433 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||
| 434 | |||
| 435 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
||
| 436 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||
| 437 | |||
| 438 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
||
| 439 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||
| 440 | |||
| 441 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||
| 442 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||
| 443 | |||
| 444 | /* SCB System Control Register Definitions */ |
||
| 445 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
||
| 446 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||
| 447 | |||
| 448 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
||
| 449 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||
| 450 | |||
| 451 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
||
| 452 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||
| 453 | |||
| 454 | /* SCB Configuration Control Register Definitions */ |
||
| 455 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
||
| 456 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||
| 457 | |||
| 458 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
||
| 459 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||
| 460 | |||
| 461 | /* SCB System Handler Control and State Register Definitions */ |
||
| 462 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
||
| 463 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||
| 464 | |||
| 465 | /*@} end of group CMSIS_SCB */ |
||
| 466 | |||
| 467 | |||
| 468 | /** \ingroup CMSIS_core_register |
||
| 469 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
||
| 470 | \brief Type definitions for the System Control and ID Register not in the SCB |
||
| 471 | @{ |
||
| 472 | */ |
||
| 473 | |||
| 474 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
||
| 475 | */ |
||
| 476 | typedef struct |
||
| 477 | { |
||
| 478 | uint32_t RESERVED0[2]; |
||
| 479 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
||
| 480 | } SCnSCB_Type; |
||
| 481 | |||
| 482 | /* Auxiliary Control Register Definitions */ |
||
| 483 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
||
| 484 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
||
| 485 | |||
| 486 | /*@} end of group CMSIS_SCnotSCB */ |
||
| 487 | |||
| 488 | |||
| 489 | /** \ingroup CMSIS_core_register |
||
| 490 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||
| 491 | \brief Type definitions for the System Timer Registers. |
||
| 492 | @{ |
||
| 493 | */ |
||
| 494 | |||
| 495 | /** \brief Structure type to access the System Timer (SysTick). |
||
| 496 | */ |
||
| 497 | typedef struct |
||
| 498 | { |
||
| 499 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||
| 500 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||
| 501 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||
| 502 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||
| 503 | } SysTick_Type; |
||
| 504 | |||
| 505 | /* SysTick Control / Status Register Definitions */ |
||
| 506 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
||
| 507 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||
| 508 | |||
| 509 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
||
| 510 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||
| 511 | |||
| 512 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
||
| 513 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||
| 514 | |||
| 515 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
||
| 516 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||
| 517 | |||
| 518 | /* SysTick Reload Register Definitions */ |
||
| 519 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
||
| 520 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||
| 521 | |||
| 522 | /* SysTick Current Register Definitions */ |
||
| 523 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
||
| 524 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||
| 525 | |||
| 526 | /* SysTick Calibration Register Definitions */ |
||
| 527 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
||
| 528 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||
| 529 | |||
| 530 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
||
| 531 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||
| 532 | |||
| 533 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
||
| 534 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||
| 535 | |||
| 536 | /*@} end of group CMSIS_SysTick */ |
||
| 537 | |||
| 538 | #if (__MPU_PRESENT == 1) |
||
| 539 | /** \ingroup CMSIS_core_register |
||
| 540 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||
| 541 | \brief Type definitions for the Memory Protection Unit (MPU) |
||
| 542 | @{ |
||
| 543 | */ |
||
| 544 | |||
| 545 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
||
| 546 | */ |
||
| 547 | typedef struct |
||
| 548 | { |
||
| 549 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||
| 550 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||
| 551 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||
| 552 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
||
| 553 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
||
| 554 | } MPU_Type; |
||
| 555 | |||
| 556 | /* MPU Type Register */ |
||
| 557 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
||
| 558 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||
| 559 | |||
| 560 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
||
| 561 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||
| 562 | |||
| 563 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
||
| 564 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
||
| 565 | |||
| 566 | /* MPU Control Register */ |
||
| 567 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
||
| 568 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||
| 569 | |||
| 570 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
||
| 571 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||
| 572 | |||
| 573 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
||
| 574 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
||
| 575 | |||
| 576 | /* MPU Region Number Register */ |
||
| 577 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
||
| 578 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
||
| 579 | |||
| 580 | /* MPU Region Base Address Register */ |
||
| 581 | #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ |
||
| 582 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||
| 583 | |||
| 584 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
||
| 585 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||
| 586 | |||
| 587 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
||
| 588 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
||
| 589 | |||
| 590 | /* MPU Region Attribute and Size Register */ |
||
| 591 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
||
| 592 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
||
| 593 | |||
| 594 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
||
| 595 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
||
| 596 | |||
| 597 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
||
| 598 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
||
| 599 | |||
| 600 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
||
| 601 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
||
| 602 | |||
| 603 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
||
| 604 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
||
| 605 | |||
| 606 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
||
| 607 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
||
| 608 | |||
| 609 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
||
| 610 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
||
| 611 | |||
| 612 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
||
| 613 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||
| 614 | |||
| 615 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
||
| 616 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||
| 617 | |||
| 618 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
||
| 619 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
||
| 620 | |||
| 621 | /*@} end of group CMSIS_MPU */ |
||
| 622 | #endif |
||
| 623 | |||
| 624 | |||
| 625 | /** \ingroup CMSIS_core_register |
||
| 626 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||
| 627 | \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) |
||
| 628 | are only accessible over DAP and not via processor. Therefore |
||
| 629 | they are not covered by the Cortex-M0 header file. |
||
| 630 | @{ |
||
| 631 | */ |
||
| 632 | /*@} end of group CMSIS_CoreDebug */ |
||
| 633 | |||
| 634 | |||
| 635 | /** \ingroup CMSIS_core_register |
||
| 636 | \defgroup CMSIS_core_base Core Definitions |
||
| 637 | \brief Definitions for base addresses, unions, and structures. |
||
| 638 | @{ |
||
| 639 | */ |
||
| 640 | |||
| 641 | /* Memory mapping of SC000 Hardware */ |
||
| 642 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||
| 643 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||
| 644 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||
| 645 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||
| 646 | |||
| 647 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
||
| 648 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||
| 649 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||
| 650 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||
| 651 | |||
| 652 | #if (__MPU_PRESENT == 1) |
||
| 653 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
||
| 654 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
||
| 655 | #endif |
||
| 656 | |||
| 657 | /*@} */ |
||
| 658 | |||
| 659 | |||
| 660 | |||
| 661 | /******************************************************************************* |
||
| 662 | * Hardware Abstraction Layer |
||
| 663 | Core Function Interface contains: |
||
| 664 | - Core NVIC Functions |
||
| 665 | - Core SysTick Functions |
||
| 666 | - Core Register Access Functions |
||
| 667 | ******************************************************************************/ |
||
| 668 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||
| 669 | */ |
||
| 670 | |||
| 671 | |||
| 672 | |||
| 673 | /* ########################## NVIC functions #################################### */ |
||
| 674 | /** \ingroup CMSIS_Core_FunctionInterface |
||
| 675 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||
| 676 | \brief Functions that manage interrupts and exceptions via the NVIC. |
||
| 677 | @{ |
||
| 678 | */ |
||
| 679 | |||
| 680 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
||
| 681 | /* The following MACROS handle generation of the register offset and byte masks */ |
||
| 682 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||
| 683 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||
| 684 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||
| 685 | |||
| 686 | |||
| 687 | /** \brief Enable External Interrupt |
||
| 688 | |||
| 689 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
||
| 690 | |||
| 691 | \param [in] IRQn External interrupt number. Value cannot be negative. |
||
| 692 | */ |
||
| 693 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||
| 694 | { |
||
| 695 | NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||
| 696 | } |
||
| 697 | |||
| 698 | |||
| 699 | /** \brief Disable External Interrupt |
||
| 700 | |||
| 701 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
||
| 702 | |||
| 703 | \param [in] IRQn External interrupt number. Value cannot be negative. |
||
| 704 | */ |
||
| 705 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||
| 706 | { |
||
| 707 | NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||
| 708 | } |
||
| 709 | |||
| 710 | |||
| 711 | /** \brief Get Pending Interrupt |
||
| 712 | |||
| 713 | The function reads the pending register in the NVIC and returns the pending bit |
||
| 714 | for the specified interrupt. |
||
| 715 | |||
| 716 | \param [in] IRQn Interrupt number. |
||
| 717 | |||
| 718 | \return 0 Interrupt status is not pending. |
||
| 719 | \return 1 Interrupt status is pending. |
||
| 720 | */ |
||
| 721 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||
| 722 | { |
||
| 723 | return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||
| 724 | } |
||
| 725 | |||
| 726 | |||
| 727 | /** \brief Set Pending Interrupt |
||
| 728 | |||
| 729 | The function sets the pending bit of an external interrupt. |
||
| 730 | |||
| 731 | \param [in] IRQn Interrupt number. Value cannot be negative. |
||
| 732 | */ |
||
| 733 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||
| 734 | { |
||
| 735 | NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||
| 736 | } |
||
| 737 | |||
| 738 | |||
| 739 | /** \brief Clear Pending Interrupt |
||
| 740 | |||
| 741 | The function clears the pending bit of an external interrupt. |
||
| 742 | |||
| 743 | \param [in] IRQn External interrupt number. Value cannot be negative. |
||
| 744 | */ |
||
| 745 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||
| 746 | { |
||
| 747 | NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
||
| 748 | } |
||
| 749 | |||
| 750 | |||
| 751 | /** \brief Set Interrupt Priority |
||
| 752 | |||
| 753 | The function sets the priority of an interrupt. |
||
| 754 | |||
| 755 | \note The priority cannot be set for every core interrupt. |
||
| 756 | |||
| 757 | \param [in] IRQn Interrupt number. |
||
| 758 | \param [in] priority Priority to set. |
||
| 759 | */ |
||
| 760 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||
| 761 | { |
||
| 762 | if((int32_t)(IRQn) < 0) { |
||
| 763 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||
| 764 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||
| 765 | } |
||
| 766 | else { |
||
| 767 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||
| 768 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||
| 769 | } |
||
| 770 | } |
||
| 771 | |||
| 772 | |||
| 773 | /** \brief Get Interrupt Priority |
||
| 774 | |||
| 775 | The function reads the priority of an interrupt. The interrupt |
||
| 776 | number can be positive to specify an external (device specific) |
||
| 777 | interrupt, or negative to specify an internal (core) interrupt. |
||
| 778 | |||
| 779 | |||
| 780 | \param [in] IRQn Interrupt number. |
||
| 781 | \return Interrupt Priority. Value is aligned automatically to the implemented |
||
| 782 | priority bits of the microcontroller. |
||
| 783 | */ |
||
| 784 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
||
| 785 | { |
||
| 786 | |||
| 787 | if((int32_t)(IRQn) < 0) { |
||
| 788 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
||
| 789 | } |
||
| 790 | else { |
||
| 791 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
||
| 792 | } |
||
| 793 | } |
||
| 794 | |||
| 795 | |||
| 796 | /** \brief System Reset |
||
| 797 | |||
| 798 | The function initiates a system reset request to reset the MCU. |
||
| 799 | */ |
||
| 800 | __STATIC_INLINE void NVIC_SystemReset(void) |
||
| 801 | { |
||
| 802 | __DSB(); /* Ensure all outstanding memory accesses included |
||
| 803 | buffered write are completed before reset */ |
||
| 804 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||
| 805 | SCB_AIRCR_SYSRESETREQ_Msk); |
||
| 806 | __DSB(); /* Ensure completion of memory access */ |
||
| 807 | while(1) { __NOP(); } /* wait until reset */ |
||
| 808 | } |
||
| 809 | |||
| 810 | /*@} end of CMSIS_Core_NVICFunctions */ |
||
| 811 | |||
| 812 | |||
| 813 | |||
| 814 | /* ################################## SysTick function ############################################ */ |
||
| 815 | /** \ingroup CMSIS_Core_FunctionInterface |
||
| 816 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||
| 817 | \brief Functions that configure the System. |
||
| 818 | @{ |
||
| 819 | */ |
||
| 820 | |||
| 821 | #if (__Vendor_SysTickConfig == 0) |
||
| 822 | |||
| 823 | /** \brief System Tick Configuration |
||
| 824 | |||
| 825 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||
| 826 | Counter is in free running mode to generate periodic interrupts. |
||
| 827 | |||
| 828 | \param [in] ticks Number of ticks between two interrupts. |
||
| 829 | |||
| 830 | \return 0 Function succeeded. |
||
| 831 | \return 1 Function failed. |
||
| 832 | |||
| 833 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||
| 834 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||
| 835 | must contain a vendor-specific implementation of this function. |
||
| 836 | |||
| 837 | */ |
||
| 838 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||
| 839 | { |
||
| 840 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ |
||
| 841 | |||
| 842 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||
| 843 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||
| 844 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||
| 845 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||
| 846 | SysTick_CTRL_TICKINT_Msk | |
||
| 847 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||
| 848 | return (0UL); /* Function successful */ |
||
| 849 | } |
||
| 850 | |||
| 851 | #endif |
||
| 852 | |||
| 853 | /*@} end of CMSIS_Core_SysTickFunctions */ |
||
| 854 | |||
| 855 | |||
| 856 | |||
| 857 | |||
| 858 | #ifdef __cplusplus |
||
| 859 | } |
||
| 860 | #endif |
||
| 861 | |||
| 862 | #endif /* __CORE_SC000_H_DEPENDANT */ |
||
| 863 | |||
| 864 | #endif /* __CMSIS_GENERIC */ |