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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /**************************************************************************//** |
| 2 | * @file core_cm0plus.h |
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| 3 | * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
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| 4 | * @version V5.0.6 |
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| 5 | * @date 28. May 2018 |
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| 6 | ******************************************************************************/ |
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| 7 | /* |
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| 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
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| 9 | * |
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| 10 | * SPDX-License-Identifier: Apache-2.0 |
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| 11 | * |
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| 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
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| 13 | * not use this file except in compliance with the License. |
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| 14 | * You may obtain a copy of the License at |
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| 15 | * |
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| 16 | * www.apache.org/licenses/LICENSE-2.0 |
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| 17 | * |
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| 18 | * Unless required by applicable law or agreed to in writing, software |
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| 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
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| 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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| 21 | * See the License for the specific language governing permissions and |
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| 22 | * limitations under the License. |
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| 23 | */ |
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| 24 | |||
| 25 | #if defined ( __ICCARM__ ) |
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| 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
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| 27 | #elif defined (__clang__) |
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| 28 | #pragma clang system_header /* treat file as system include file */ |
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| 29 | #endif |
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| 30 | |||
| 31 | #ifndef __CORE_CM0PLUS_H_GENERIC |
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| 32 | #define __CORE_CM0PLUS_H_GENERIC |
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| 33 | |||
| 34 | #include <stdint.h> |
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| 35 | |||
| 36 | #ifdef __cplusplus |
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| 37 | extern "C" { |
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| 38 | #endif |
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| 39 | |||
| 40 | /** |
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| 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
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| 42 | CMSIS violates the following MISRA-C:2004 rules: |
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| 43 | |||
| 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
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| 45 | Function definitions in header files are used to allow 'inlining'. |
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| 46 | |||
| 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
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| 48 | Unions are used for effective representation of core registers. |
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| 49 | |||
| 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
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| 51 | Function-like macros are used to allow more efficient code. |
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| 52 | */ |
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| 53 | |||
| 54 | |||
| 55 | /******************************************************************************* |
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| 56 | * CMSIS definitions |
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| 57 | ******************************************************************************/ |
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| 58 | /** |
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| 59 | \ingroup Cortex-M0+ |
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| 60 | @{ |
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| 61 | */ |
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| 62 | |||
| 63 | #include "cmsis_version.h" |
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| 64 | |||
| 65 | /* CMSIS CM0+ definitions */ |
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| 66 | #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
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| 67 | #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
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| 68 | #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ |
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| 69 | __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
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| 70 | |||
| 71 | #define __CORTEX_M (0U) /*!< Cortex-M Core */ |
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| 72 | |||
| 73 | /** __FPU_USED indicates whether an FPU is used or not. |
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| 74 | This core does not support an FPU at all |
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| 75 | */ |
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| 76 | #define __FPU_USED 0U |
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| 77 | |||
| 78 | #if defined ( __CC_ARM ) |
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| 79 | #if defined __TARGET_FPU_VFP |
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| 80 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 81 | #endif |
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| 82 | |||
| 83 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
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| 84 | #if defined __ARM_PCS_VFP |
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| 85 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 86 | #endif |
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| 87 | |||
| 88 | #elif defined ( __GNUC__ ) |
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| 89 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
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| 90 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 91 | #endif |
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| 92 | |||
| 93 | #elif defined ( __ICCARM__ ) |
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| 94 | #if defined __ARMVFP__ |
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| 95 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 96 | #endif |
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| 97 | |||
| 98 | #elif defined ( __TI_ARM__ ) |
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| 99 | #if defined __TI_VFP_SUPPORT__ |
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| 100 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 101 | #endif |
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| 102 | |||
| 103 | #elif defined ( __TASKING__ ) |
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| 104 | #if defined __FPU_VFP__ |
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| 105 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 106 | #endif |
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| 107 | |||
| 108 | #elif defined ( __CSMC__ ) |
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| 109 | #if ( __CSMC__ & 0x400U) |
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| 110 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
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| 111 | #endif |
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| 112 | |||
| 113 | #endif |
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| 114 | |||
| 115 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
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| 116 | |||
| 117 | |||
| 118 | #ifdef __cplusplus |
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| 119 | } |
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| 120 | #endif |
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| 121 | |||
| 122 | #endif /* __CORE_CM0PLUS_H_GENERIC */ |
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| 123 | |||
| 124 | #ifndef __CMSIS_GENERIC |
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| 125 | |||
| 126 | #ifndef __CORE_CM0PLUS_H_DEPENDANT |
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| 127 | #define __CORE_CM0PLUS_H_DEPENDANT |
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| 128 | |||
| 129 | #ifdef __cplusplus |
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| 130 | extern "C" { |
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| 131 | #endif |
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| 132 | |||
| 133 | /* check device defines and use defaults */ |
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| 134 | #if defined __CHECK_DEVICE_DEFINES |
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| 135 | #ifndef __CM0PLUS_REV |
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| 136 | #define __CM0PLUS_REV 0x0000U |
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| 137 | #warning "__CM0PLUS_REV not defined in device header file; using default!" |
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| 138 | #endif |
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| 139 | |||
| 140 | #ifndef __MPU_PRESENT |
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| 141 | #define __MPU_PRESENT 0U |
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| 142 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
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| 143 | #endif |
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| 144 | |||
| 145 | #ifndef __VTOR_PRESENT |
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| 146 | #define __VTOR_PRESENT 0U |
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| 147 | #warning "__VTOR_PRESENT not defined in device header file; using default!" |
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| 148 | #endif |
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| 149 | |||
| 150 | #ifndef __NVIC_PRIO_BITS |
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| 151 | #define __NVIC_PRIO_BITS 2U |
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| 152 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
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| 153 | #endif |
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| 154 | |||
| 155 | #ifndef __Vendor_SysTickConfig |
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| 156 | #define __Vendor_SysTickConfig 0U |
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| 157 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
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| 158 | #endif |
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| 159 | #endif |
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| 160 | |||
| 161 | /* IO definitions (access restrictions to peripheral registers) */ |
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| 162 | /** |
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| 163 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
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| 164 | |||
| 165 | <strong>IO Type Qualifiers</strong> are used |
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| 166 | \li to specify the access to peripheral variables. |
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| 167 | \li for automatic generation of peripheral register debug information. |
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| 168 | */ |
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| 169 | #ifdef __cplusplus |
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| 170 | #define __I volatile /*!< Defines 'read only' permissions */ |
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| 171 | #else |
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| 172 | #define __I volatile const /*!< Defines 'read only' permissions */ |
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| 173 | #endif |
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| 174 | #define __O volatile /*!< Defines 'write only' permissions */ |
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| 175 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
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| 176 | |||
| 177 | /* following defines should be used for structure members */ |
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| 178 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
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| 179 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
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| 180 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
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| 181 | |||
| 182 | /*@} end of group Cortex-M0+ */ |
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| 183 | |||
| 184 | |||
| 185 | |||
| 186 | /******************************************************************************* |
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| 187 | * Register Abstraction |
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| 188 | Core Register contain: |
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| 189 | - Core Register |
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| 190 | - Core NVIC Register |
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| 191 | - Core SCB Register |
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| 192 | - Core SysTick Register |
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| 193 | - Core MPU Register |
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| 194 | ******************************************************************************/ |
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| 195 | /** |
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| 196 | \defgroup CMSIS_core_register Defines and Type Definitions |
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| 197 | \brief Type definitions and defines for Cortex-M processor based devices. |
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| 198 | */ |
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| 199 | |||
| 200 | /** |
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| 201 | \ingroup CMSIS_core_register |
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| 202 | \defgroup CMSIS_CORE Status and Control Registers |
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| 203 | \brief Core Register type definitions. |
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| 204 | @{ |
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| 205 | */ |
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| 206 | |||
| 207 | /** |
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| 208 | \brief Union type to access the Application Program Status Register (APSR). |
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| 209 | */ |
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| 210 | typedef union |
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| 211 | { |
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| 212 | struct |
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| 213 | { |
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| 214 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
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| 215 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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| 216 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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| 217 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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| 218 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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| 219 | } b; /*!< Structure used for bit access */ |
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| 220 | uint32_t w; /*!< Type used for word access */ |
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| 221 | } APSR_Type; |
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| 222 | |||
| 223 | /* APSR Register Definitions */ |
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| 224 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
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| 225 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
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| 226 | |||
| 227 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
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| 228 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
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| 229 | |||
| 230 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
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| 231 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
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| 232 | |||
| 233 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
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| 234 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
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| 235 | |||
| 236 | |||
| 237 | /** |
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| 238 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
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| 239 | */ |
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| 240 | typedef union |
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| 241 | { |
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| 242 | struct |
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| 243 | { |
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| 244 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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| 245 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
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| 246 | } b; /*!< Structure used for bit access */ |
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| 247 | uint32_t w; /*!< Type used for word access */ |
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| 248 | } IPSR_Type; |
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| 249 | |||
| 250 | /* IPSR Register Definitions */ |
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| 251 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
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| 252 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
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| 253 | |||
| 254 | |||
| 255 | /** |
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| 256 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
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| 257 | */ |
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| 258 | typedef union |
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| 259 | { |
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| 260 | struct |
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| 261 | { |
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| 262 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
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| 263 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
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| 264 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
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| 265 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
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| 266 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
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| 267 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
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| 268 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
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| 269 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
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| 270 | } b; /*!< Structure used for bit access */ |
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| 271 | uint32_t w; /*!< Type used for word access */ |
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| 272 | } xPSR_Type; |
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| 273 | |||
| 274 | /* xPSR Register Definitions */ |
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| 275 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
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| 276 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
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| 277 | |||
| 278 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
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| 279 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
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| 280 | |||
| 281 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
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| 282 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
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| 283 | |||
| 284 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
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| 285 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
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| 286 | |||
| 287 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
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| 288 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
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| 289 | |||
| 290 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
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| 291 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
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| 292 | |||
| 293 | |||
| 294 | /** |
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| 295 | \brief Union type to access the Control Registers (CONTROL). |
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| 296 | */ |
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| 297 | typedef union |
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| 298 | { |
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| 299 | struct |
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| 300 | { |
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| 301 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
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| 302 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
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| 303 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
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| 304 | } b; /*!< Structure used for bit access */ |
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| 305 | uint32_t w; /*!< Type used for word access */ |
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| 306 | } CONTROL_Type; |
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| 307 | |||
| 308 | /* CONTROL Register Definitions */ |
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| 309 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
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| 310 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
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| 311 | |||
| 312 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
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| 313 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
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| 314 | |||
| 315 | /*@} end of group CMSIS_CORE */ |
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| 316 | |||
| 317 | |||
| 318 | /** |
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| 319 | \ingroup CMSIS_core_register |
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| 320 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
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| 321 | \brief Type definitions for the NVIC Registers |
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| 322 | @{ |
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| 323 | */ |
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| 324 | |||
| 325 | /** |
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| 326 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
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| 327 | */ |
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| 328 | typedef struct |
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| 329 | { |
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| 330 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
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| 331 | uint32_t RESERVED0[31U]; |
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| 332 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
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| 333 | uint32_t RSERVED1[31U]; |
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| 334 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
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| 335 | uint32_t RESERVED2[31U]; |
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| 336 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
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| 337 | uint32_t RESERVED3[31U]; |
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| 338 | uint32_t RESERVED4[64U]; |
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| 339 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
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| 340 | } NVIC_Type; |
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| 341 | |||
| 342 | /*@} end of group CMSIS_NVIC */ |
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| 343 | |||
| 344 | |||
| 345 | /** |
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| 346 | \ingroup CMSIS_core_register |
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| 347 | \defgroup CMSIS_SCB System Control Block (SCB) |
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| 348 | \brief Type definitions for the System Control Block Registers |
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| 349 | @{ |
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| 350 | */ |
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| 351 | |||
| 352 | /** |
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| 353 | \brief Structure type to access the System Control Block (SCB). |
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| 354 | */ |
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| 355 | typedef struct |
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| 356 | { |
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| 357 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
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| 358 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
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| 359 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
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| 360 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
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| 361 | #else |
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| 362 | uint32_t RESERVED0; |
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| 363 | #endif |
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| 364 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
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| 365 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
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| 366 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
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| 367 | uint32_t RESERVED1; |
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| 368 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
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| 369 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
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| 370 | } SCB_Type; |
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| 371 | |||
| 372 | /* SCB CPUID Register Definitions */ |
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| 373 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
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| 374 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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| 375 | |||
| 376 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
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| 377 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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| 378 | |||
| 379 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
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| 380 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
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| 381 | |||
| 382 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
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| 383 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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| 384 | |||
| 385 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
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| 386 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
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| 387 | |||
| 388 | /* SCB Interrupt Control State Register Definitions */ |
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| 389 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
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| 390 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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| 391 | |||
| 392 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
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| 393 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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| 394 | |||
| 395 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
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| 396 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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| 397 | |||
| 398 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
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| 399 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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| 400 | |||
| 401 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
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| 402 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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| 403 | |||
| 404 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
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| 405 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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| 406 | |||
| 407 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
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| 408 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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| 409 | |||
| 410 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
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| 411 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
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| 412 | |||
| 413 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
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| 414 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
||
| 415 | |||
| 416 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
||
| 417 | /* SCB Interrupt Control State Register Definitions */ |
||
| 418 | #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ |
||
| 419 | #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
||
| 420 | #endif |
||
| 421 | |||
| 422 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
||
| 423 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
||
| 424 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
||
| 425 | |||
| 426 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
||
| 427 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
||
| 428 | |||
| 429 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
||
| 430 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
||
| 431 | |||
| 432 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
||
| 433 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
||
| 434 | |||
| 435 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
||
| 436 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
||
| 437 | |||
| 438 | /* SCB System Control Register Definitions */ |
||
| 439 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
||
| 440 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
||
| 441 | |||
| 442 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
||
| 443 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
||
| 444 | |||
| 445 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
||
| 446 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
||
| 447 | |||
| 448 | /* SCB Configuration Control Register Definitions */ |
||
| 449 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
||
| 450 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
||
| 451 | |||
| 452 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
||
| 453 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
||
| 454 | |||
| 455 | /* SCB System Handler Control and State Register Definitions */ |
||
| 456 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
||
| 457 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
||
| 458 | |||
| 459 | /*@} end of group CMSIS_SCB */ |
||
| 460 | |||
| 461 | |||
| 462 | /** |
||
| 463 | \ingroup CMSIS_core_register |
||
| 464 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
||
| 465 | \brief Type definitions for the System Timer Registers. |
||
| 466 | @{ |
||
| 467 | */ |
||
| 468 | |||
| 469 | /** |
||
| 470 | \brief Structure type to access the System Timer (SysTick). |
||
| 471 | */ |
||
| 472 | typedef struct |
||
| 473 | { |
||
| 474 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
||
| 475 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
||
| 476 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
||
| 477 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
||
| 478 | } SysTick_Type; |
||
| 479 | |||
| 480 | /* SysTick Control / Status Register Definitions */ |
||
| 481 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
||
| 482 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||
| 483 | |||
| 484 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
||
| 485 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||
| 486 | |||
| 487 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
||
| 488 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||
| 489 | |||
| 490 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
||
| 491 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
||
| 492 | |||
| 493 | /* SysTick Reload Register Definitions */ |
||
| 494 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
||
| 495 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
||
| 496 | |||
| 497 | /* SysTick Current Register Definitions */ |
||
| 498 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
||
| 499 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
||
| 500 | |||
| 501 | /* SysTick Calibration Register Definitions */ |
||
| 502 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
||
| 503 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||
| 504 | |||
| 505 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
||
| 506 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||
| 507 | |||
| 508 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
||
| 509 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
||
| 510 | |||
| 511 | /*@} end of group CMSIS_SysTick */ |
||
| 512 | |||
| 513 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
||
| 514 | /** |
||
| 515 | \ingroup CMSIS_core_register |
||
| 516 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
||
| 517 | \brief Type definitions for the Memory Protection Unit (MPU) |
||
| 518 | @{ |
||
| 519 | */ |
||
| 520 | |||
| 521 | /** |
||
| 522 | \brief Structure type to access the Memory Protection Unit (MPU). |
||
| 523 | */ |
||
| 524 | typedef struct |
||
| 525 | { |
||
| 526 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
||
| 527 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
||
| 528 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
||
| 529 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
||
| 530 | __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
||
| 531 | } MPU_Type; |
||
| 532 | |||
| 533 | #define MPU_TYPE_RALIASES 1U |
||
| 534 | |||
| 535 | /* MPU Type Register Definitions */ |
||
| 536 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
||
| 537 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||
| 538 | |||
| 539 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
||
| 540 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||
| 541 | |||
| 542 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
||
| 543 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
||
| 544 | |||
| 545 | /* MPU Control Register Definitions */ |
||
| 546 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
||
| 547 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||
| 548 | |||
| 549 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
||
| 550 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||
| 551 | |||
| 552 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
||
| 553 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
||
| 554 | |||
| 555 | /* MPU Region Number Register Definitions */ |
||
| 556 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
||
| 557 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
||
| 558 | |||
| 559 | /* MPU Region Base Address Register Definitions */ |
||
| 560 | #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
||
| 561 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||
| 562 | |||
| 563 | #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
||
| 564 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||
| 565 | |||
| 566 | #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
||
| 567 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
||
| 568 | |||
| 569 | /* MPU Region Attribute and Size Register Definitions */ |
||
| 570 | #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
||
| 571 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
||
| 572 | |||
| 573 | #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
||
| 574 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
||
| 575 | |||
| 576 | #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
||
| 577 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
||
| 578 | |||
| 579 | #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
||
| 580 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
||
| 581 | |||
| 582 | #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
||
| 583 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
||
| 584 | |||
| 585 | #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
||
| 586 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
||
| 587 | |||
| 588 | #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
||
| 589 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
||
| 590 | |||
| 591 | #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
||
| 592 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||
| 593 | |||
| 594 | #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
||
| 595 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||
| 596 | |||
| 597 | #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
||
| 598 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
||
| 599 | |||
| 600 | /*@} end of group CMSIS_MPU */ |
||
| 601 | #endif |
||
| 602 | |||
| 603 | |||
| 604 | /** |
||
| 605 | \ingroup CMSIS_core_register |
||
| 606 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
||
| 607 | \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
||
| 608 | Therefore they are not covered by the Cortex-M0+ header file. |
||
| 609 | @{ |
||
| 610 | */ |
||
| 611 | /*@} end of group CMSIS_CoreDebug */ |
||
| 612 | |||
| 613 | |||
| 614 | /** |
||
| 615 | \ingroup CMSIS_core_register |
||
| 616 | \defgroup CMSIS_core_bitfield Core register bit field macros |
||
| 617 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
||
| 618 | @{ |
||
| 619 | */ |
||
| 620 | |||
| 621 | /** |
||
| 622 | \brief Mask and shift a bit field value for use in a register bit range. |
||
| 623 | \param[in] field Name of the register bit field. |
||
| 624 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
||
| 625 | \return Masked and shifted value. |
||
| 626 | */ |
||
| 627 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
||
| 628 | |||
| 629 | /** |
||
| 630 | \brief Mask and shift a register value to extract a bit filed value. |
||
| 631 | \param[in] field Name of the register bit field. |
||
| 632 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
||
| 633 | \return Masked and shifted bit field value. |
||
| 634 | */ |
||
| 635 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
||
| 636 | |||
| 637 | /*@} end of group CMSIS_core_bitfield */ |
||
| 638 | |||
| 639 | |||
| 640 | /** |
||
| 641 | \ingroup CMSIS_core_register |
||
| 642 | \defgroup CMSIS_core_base Core Definitions |
||
| 643 | \brief Definitions for base addresses, unions, and structures. |
||
| 644 | @{ |
||
| 645 | */ |
||
| 646 | |||
| 647 | /* Memory mapping of Core Hardware */ |
||
| 648 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
||
| 649 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
||
| 650 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
||
| 651 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
||
| 652 | |||
| 653 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
||
| 654 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
||
| 655 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
||
| 656 | |||
| 657 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
||
| 658 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
||
| 659 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
||
| 660 | #endif |
||
| 661 | |||
| 662 | /*@} */ |
||
| 663 | |||
| 664 | |||
| 665 | |||
| 666 | /******************************************************************************* |
||
| 667 | * Hardware Abstraction Layer |
||
| 668 | Core Function Interface contains: |
||
| 669 | - Core NVIC Functions |
||
| 670 | - Core SysTick Functions |
||
| 671 | - Core Register Access Functions |
||
| 672 | ******************************************************************************/ |
||
| 673 | /** |
||
| 674 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
||
| 675 | */ |
||
| 676 | |||
| 677 | |||
| 678 | |||
| 679 | /* ########################## NVIC functions #################################### */ |
||
| 680 | /** |
||
| 681 | \ingroup CMSIS_Core_FunctionInterface |
||
| 682 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
||
| 683 | \brief Functions that manage interrupts and exceptions via the NVIC. |
||
| 684 | @{ |
||
| 685 | */ |
||
| 686 | |||
| 687 | #ifdef CMSIS_NVIC_VIRTUAL |
||
| 688 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||
| 689 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
||
| 690 | #endif |
||
| 691 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
||
| 692 | #else |
||
| 693 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
||
| 694 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
||
| 695 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
||
| 696 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
||
| 697 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
||
| 698 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
||
| 699 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
||
| 700 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
||
| 701 | /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ |
||
| 702 | #define NVIC_SetPriority __NVIC_SetPriority |
||
| 703 | #define NVIC_GetPriority __NVIC_GetPriority |
||
| 704 | #define NVIC_SystemReset __NVIC_SystemReset |
||
| 705 | #endif /* CMSIS_NVIC_VIRTUAL */ |
||
| 706 | |||
| 707 | #ifdef CMSIS_VECTAB_VIRTUAL |
||
| 708 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||
| 709 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
||
| 710 | #endif |
||
| 711 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
||
| 712 | #else |
||
| 713 | #define NVIC_SetVector __NVIC_SetVector |
||
| 714 | #define NVIC_GetVector __NVIC_GetVector |
||
| 715 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
||
| 716 | |||
| 717 | #define NVIC_USER_IRQ_OFFSET 16 |
||
| 718 | |||
| 719 | |||
| 720 | /* The following EXC_RETURN values are saved the LR on exception entry */ |
||
| 721 | #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
||
| 722 | #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
||
| 723 | #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
||
| 724 | |||
| 725 | |||
| 726 | /* Interrupt Priorities are WORD accessible only under Armv6-M */ |
||
| 727 | /* The following MACROS handle generation of the register offset and byte masks */ |
||
| 728 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
||
| 729 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
||
| 730 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
||
| 731 | |||
| 732 | #define __NVIC_SetPriorityGrouping(X) (void)(X) |
||
| 733 | #define __NVIC_GetPriorityGrouping() (0U) |
||
| 734 | |||
| 735 | /** |
||
| 736 | \brief Enable Interrupt |
||
| 737 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
||
| 738 | \param [in] IRQn Device specific interrupt number. |
||
| 739 | \note IRQn must not be negative. |
||
| 740 | */ |
||
| 741 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
||
| 742 | { |
||
| 743 | if ((int32_t)(IRQn) >= 0) |
||
| 744 | { |
||
| 745 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 746 | } |
||
| 747 | } |
||
| 748 | |||
| 749 | |||
| 750 | /** |
||
| 751 | \brief Get Interrupt Enable status |
||
| 752 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
||
| 753 | \param [in] IRQn Device specific interrupt number. |
||
| 754 | \return 0 Interrupt is not enabled. |
||
| 755 | \return 1 Interrupt is enabled. |
||
| 756 | \note IRQn must not be negative. |
||
| 757 | */ |
||
| 758 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
||
| 759 | { |
||
| 760 | if ((int32_t)(IRQn) >= 0) |
||
| 761 | { |
||
| 762 | return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||
| 763 | } |
||
| 764 | else |
||
| 765 | { |
||
| 766 | return(0U); |
||
| 767 | } |
||
| 768 | } |
||
| 769 | |||
| 770 | |||
| 771 | /** |
||
| 772 | \brief Disable Interrupt |
||
| 773 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
||
| 774 | \param [in] IRQn Device specific interrupt number. |
||
| 775 | \note IRQn must not be negative. |
||
| 776 | */ |
||
| 777 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
||
| 778 | { |
||
| 779 | if ((int32_t)(IRQn) >= 0) |
||
| 780 | { |
||
| 781 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 782 | __DSB(); |
||
| 783 | __ISB(); |
||
| 784 | } |
||
| 785 | } |
||
| 786 | |||
| 787 | |||
| 788 | /** |
||
| 789 | \brief Get Pending Interrupt |
||
| 790 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
||
| 791 | \param [in] IRQn Device specific interrupt number. |
||
| 792 | \return 0 Interrupt status is not pending. |
||
| 793 | \return 1 Interrupt status is pending. |
||
| 794 | \note IRQn must not be negative. |
||
| 795 | */ |
||
| 796 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
||
| 797 | { |
||
| 798 | if ((int32_t)(IRQn) >= 0) |
||
| 799 | { |
||
| 800 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
||
| 801 | } |
||
| 802 | else |
||
| 803 | { |
||
| 804 | return(0U); |
||
| 805 | } |
||
| 806 | } |
||
| 807 | |||
| 808 | |||
| 809 | /** |
||
| 810 | \brief Set Pending Interrupt |
||
| 811 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
||
| 812 | \param [in] IRQn Device specific interrupt number. |
||
| 813 | \note IRQn must not be negative. |
||
| 814 | */ |
||
| 815 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||
| 816 | { |
||
| 817 | if ((int32_t)(IRQn) >= 0) |
||
| 818 | { |
||
| 819 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 820 | } |
||
| 821 | } |
||
| 822 | |||
| 823 | |||
| 824 | /** |
||
| 825 | \brief Clear Pending Interrupt |
||
| 826 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
||
| 827 | \param [in] IRQn Device specific interrupt number. |
||
| 828 | \note IRQn must not be negative. |
||
| 829 | */ |
||
| 830 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||
| 831 | { |
||
| 832 | if ((int32_t)(IRQn) >= 0) |
||
| 833 | { |
||
| 834 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
||
| 835 | } |
||
| 836 | } |
||
| 837 | |||
| 838 | |||
| 839 | /** |
||
| 840 | \brief Set Interrupt Priority |
||
| 841 | \details Sets the priority of a device specific interrupt or a processor exception. |
||
| 842 | The interrupt number can be positive to specify a device specific interrupt, |
||
| 843 | or negative to specify a processor exception. |
||
| 844 | \param [in] IRQn Interrupt number. |
||
| 845 | \param [in] priority Priority to set. |
||
| 846 | \note The priority cannot be set for every processor exception. |
||
| 847 | */ |
||
| 848 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||
| 849 | { |
||
| 850 | if ((int32_t)(IRQn) >= 0) |
||
| 851 | { |
||
| 852 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||
| 853 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||
| 854 | } |
||
| 855 | else |
||
| 856 | { |
||
| 857 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
||
| 858 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
||
| 859 | } |
||
| 860 | } |
||
| 861 | |||
| 862 | |||
| 863 | /** |
||
| 864 | \brief Get Interrupt Priority |
||
| 865 | \details Reads the priority of a device specific interrupt or a processor exception. |
||
| 866 | The interrupt number can be positive to specify a device specific interrupt, |
||
| 867 | or negative to specify a processor exception. |
||
| 868 | \param [in] IRQn Interrupt number. |
||
| 869 | \return Interrupt Priority. |
||
| 870 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
||
| 871 | */ |
||
| 872 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
||
| 873 | { |
||
| 874 | |||
| 875 | if ((int32_t)(IRQn) >= 0) |
||
| 876 | { |
||
| 877 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||
| 878 | } |
||
| 879 | else |
||
| 880 | { |
||
| 881 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
||
| 882 | } |
||
| 883 | } |
||
| 884 | |||
| 885 | |||
| 886 | /** |
||
| 887 | \brief Encode Priority |
||
| 888 | \details Encodes the priority for an interrupt with the given priority group, |
||
| 889 | preemptive priority value, and subpriority value. |
||
| 890 | In case of a conflict between priority grouping and available |
||
| 891 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
||
| 892 | \param [in] PriorityGroup Used priority group. |
||
| 893 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
||
| 894 | \param [in] SubPriority Subpriority value (starting from 0). |
||
| 895 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
||
| 896 | */ |
||
| 897 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
||
| 898 | { |
||
| 899 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||
| 900 | uint32_t PreemptPriorityBits; |
||
| 901 | uint32_t SubPriorityBits; |
||
| 902 | |||
| 903 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||
| 904 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||
| 905 | |||
| 906 | return ( |
||
| 907 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
||
| 908 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
||
| 909 | ); |
||
| 910 | } |
||
| 911 | |||
| 912 | |||
| 913 | /** |
||
| 914 | \brief Decode Priority |
||
| 915 | \details Decodes an interrupt priority value with a given priority group to |
||
| 916 | preemptive priority value and subpriority value. |
||
| 917 | In case of a conflict between priority grouping and available |
||
| 918 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
||
| 919 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
||
| 920 | \param [in] PriorityGroup Used priority group. |
||
| 921 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
||
| 922 | \param [out] pSubPriority Subpriority value (starting from 0). |
||
| 923 | */ |
||
| 924 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
||
| 925 | { |
||
| 926 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
||
| 927 | uint32_t PreemptPriorityBits; |
||
| 928 | uint32_t SubPriorityBits; |
||
| 929 | |||
| 930 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
||
| 931 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
||
| 932 | |||
| 933 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
||
| 934 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
||
| 935 | } |
||
| 936 | |||
| 937 | |||
| 938 | /** |
||
| 939 | \brief Set Interrupt Vector |
||
| 940 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
||
| 941 | The interrupt number can be positive to specify a device specific interrupt, |
||
| 942 | or negative to specify a processor exception. |
||
| 943 | VTOR must been relocated to SRAM before. |
||
| 944 | If VTOR is not present address 0 must be mapped to SRAM. |
||
| 945 | \param [in] IRQn Interrupt number |
||
| 946 | \param [in] vector Address of interrupt handler function |
||
| 947 | */ |
||
| 948 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
||
| 949 | { |
||
| 950 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
||
| 951 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
||
| 952 | #else |
||
| 953 | uint32_t *vectors = (uint32_t *)0x0U; |
||
| 954 | #endif |
||
| 955 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
||
| 956 | } |
||
| 957 | |||
| 958 | |||
| 959 | /** |
||
| 960 | \brief Get Interrupt Vector |
||
| 961 | \details Reads an interrupt vector from interrupt vector table. |
||
| 962 | The interrupt number can be positive to specify a device specific interrupt, |
||
| 963 | or negative to specify a processor exception. |
||
| 964 | \param [in] IRQn Interrupt number. |
||
| 965 | \return Address of interrupt handler function |
||
| 966 | */ |
||
| 967 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
||
| 968 | { |
||
| 969 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
||
| 970 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
||
| 971 | #else |
||
| 972 | uint32_t *vectors = (uint32_t *)0x0U; |
||
| 973 | #endif |
||
| 974 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
||
| 975 | |||
| 976 | } |
||
| 977 | |||
| 978 | |||
| 979 | /** |
||
| 980 | \brief System Reset |
||
| 981 | \details Initiates a system reset request to reset the MCU. |
||
| 982 | */ |
||
| 983 | __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
||
| 984 | { |
||
| 985 | __DSB(); /* Ensure all outstanding memory accesses included |
||
| 986 | buffered write are completed before reset */ |
||
| 987 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
||
| 988 | SCB_AIRCR_SYSRESETREQ_Msk); |
||
| 989 | __DSB(); /* Ensure completion of memory access */ |
||
| 990 | |||
| 991 | for(;;) /* wait until reset */ |
||
| 992 | { |
||
| 993 | __NOP(); |
||
| 994 | } |
||
| 995 | } |
||
| 996 | |||
| 997 | /*@} end of CMSIS_Core_NVICFunctions */ |
||
| 998 | |||
| 999 | /* ########################## MPU functions #################################### */ |
||
| 1000 | |||
| 1001 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
||
| 1002 | |||
| 1003 | #include "mpu_armv7.h" |
||
| 1004 | |||
| 1005 | #endif |
||
| 1006 | |||
| 1007 | /* ########################## FPU functions #################################### */ |
||
| 1008 | /** |
||
| 1009 | \ingroup CMSIS_Core_FunctionInterface |
||
| 1010 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
||
| 1011 | \brief Function that provides FPU type. |
||
| 1012 | @{ |
||
| 1013 | */ |
||
| 1014 | |||
| 1015 | /** |
||
| 1016 | \brief get FPU type |
||
| 1017 | \details returns the FPU type |
||
| 1018 | \returns |
||
| 1019 | - \b 0: No FPU |
||
| 1020 | - \b 1: Single precision FPU |
||
| 1021 | - \b 2: Double + Single precision FPU |
||
| 1022 | */ |
||
| 1023 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
||
| 1024 | { |
||
| 1025 | return 0U; /* No FPU */ |
||
| 1026 | } |
||
| 1027 | |||
| 1028 | |||
| 1029 | /*@} end of CMSIS_Core_FpuFunctions */ |
||
| 1030 | |||
| 1031 | |||
| 1032 | |||
| 1033 | /* ################################## SysTick function ############################################ */ |
||
| 1034 | /** |
||
| 1035 | \ingroup CMSIS_Core_FunctionInterface |
||
| 1036 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
||
| 1037 | \brief Functions that configure the System. |
||
| 1038 | @{ |
||
| 1039 | */ |
||
| 1040 | |||
| 1041 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
||
| 1042 | |||
| 1043 | /** |
||
| 1044 | \brief System Tick Configuration |
||
| 1045 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
||
| 1046 | Counter is in free running mode to generate periodic interrupts. |
||
| 1047 | \param [in] ticks Number of ticks between two interrupts. |
||
| 1048 | \return 0 Function succeeded. |
||
| 1049 | \return 1 Function failed. |
||
| 1050 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
||
| 1051 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
||
| 1052 | must contain a vendor-specific implementation of this function. |
||
| 1053 | */ |
||
| 1054 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
||
| 1055 | { |
||
| 1056 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
||
| 1057 | { |
||
| 1058 | return (1UL); /* Reload value impossible */ |
||
| 1059 | } |
||
| 1060 | |||
| 1061 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
||
| 1062 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
||
| 1063 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
||
| 1064 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||
| 1065 | SysTick_CTRL_TICKINT_Msk | |
||
| 1066 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
||
| 1067 | return (0UL); /* Function successful */ |
||
| 1068 | } |
||
| 1069 | |||
| 1070 | #endif |
||
| 1071 | |||
| 1072 | /*@} end of CMSIS_Core_SysTickFunctions */ |
||
| 1073 | |||
| 1074 | |||
| 1075 | |||
| 1076 | |||
| 1077 | #ifdef __cplusplus |
||
| 1078 | } |
||
| 1079 | #endif |
||
| 1080 | |||
| 1081 | #endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
||
| 1082 | |||
| 1083 | #endif /* __CMSIS_GENERIC */ |