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| 2 | mjames | 1 | /** |
| 2 | ****************************************************************************** |
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| 3 | * @file stm32l162xd.h |
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| 4 | * @author MCD Application Team |
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| 5 | * @version V2.2.0 |
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| 6 | * @date 01-July-2016 |
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| 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
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| 8 | * This file contains all the peripheral register's definitions, bits |
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| 9 | * definitions and memory mapping for STM32L1xx devices. |
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| 10 | * |
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| 11 | * This file contains: |
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| 12 | * - Data structures and the address mapping for all peripherals |
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| 13 | * - Peripheral's registers declarations and bits definition |
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| 14 | * - Macros to access peripheral’s registers hardware |
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| 15 | * |
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| 16 | ****************************************************************************** |
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| 17 | * @attention |
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| 18 | * |
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| 19 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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| 20 | * |
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| 21 | * Redistribution and use in source and binary forms, with or without modification, |
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| 22 | * are permitted provided that the following conditions are met: |
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| 23 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 24 | * this list of conditions and the following disclaimer. |
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| 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 26 | * this list of conditions and the following disclaimer in the documentation |
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| 27 | * and/or other materials provided with the distribution. |
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| 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 29 | * may be used to endorse or promote products derived from this software |
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| 30 | * without specific prior written permission. |
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| 31 | * |
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| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 42 | * |
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| 43 | ****************************************************************************** |
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| 44 | */ |
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| 45 | |||
| 46 | /** @addtogroup CMSIS |
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| 47 | * @{ |
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| 48 | */ |
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| 49 | |||
| 50 | /** @addtogroup stm32l162xd |
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| 51 | * @{ |
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| 52 | */ |
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| 53 | |||
| 54 | #ifndef __STM32L162xD_H |
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| 55 | #define __STM32L162xD_H |
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| 56 | |||
| 57 | #ifdef __cplusplus |
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| 58 | extern "C" { |
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| 59 | #endif |
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| 60 | |||
| 61 | |||
| 62 | /** @addtogroup Configuration_section_for_CMSIS |
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| 63 | * @{ |
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| 64 | */ |
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| 65 | /** |
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| 66 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
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| 67 | */ |
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| 68 | #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ |
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| 69 | #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ |
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| 70 | #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ |
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| 71 | #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
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| 72 | |||
| 73 | /** |
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| 74 | * @} |
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| 75 | */ |
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| 76 | |||
| 77 | /** @addtogroup Peripheral_interrupt_number_definition |
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| 78 | * @{ |
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| 79 | */ |
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| 80 | |||
| 81 | /** |
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| 82 | * @brief STM32L1xx Interrupt Number Definition, according to the selected device |
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| 83 | * in @ref Library_configuration_section |
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| 84 | */ |
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| 85 | |||
| 86 | /*!< Interrupt Number Definition */ |
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| 87 | typedef enum |
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| 88 | { |
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| 89 | /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ |
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| 90 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
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| 91 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ |
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| 92 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
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| 93 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
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| 94 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
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| 95 | SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
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| 96 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
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| 97 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
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| 98 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
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| 99 | |||
| 100 | /****** STM32L specific Interrupt Numbers ***********************************************************/ |
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| 101 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
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| 102 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
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| 103 | TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
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| 104 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ |
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| 105 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
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| 106 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
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| 107 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
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| 108 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
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| 109 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
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| 110 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
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| 111 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
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| 112 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
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| 113 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
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| 114 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
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| 115 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
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| 116 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
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| 117 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
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| 118 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
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| 119 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
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| 120 | USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ |
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| 121 | USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ |
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| 122 | DAC_IRQn = 21, /*!< DAC Interrupt */ |
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| 123 | COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ |
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| 124 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
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| 125 | LCD_IRQn = 24, /*!< LCD Interrupt */ |
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| 126 | TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ |
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| 127 | TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ |
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| 128 | TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ |
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| 129 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
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| 130 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
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| 131 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
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| 132 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
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| 133 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
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| 134 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
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| 135 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
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| 136 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
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| 137 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
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| 138 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
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| 139 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
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| 140 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
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| 141 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
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| 142 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
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| 143 | USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ |
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| 144 | TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ |
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| 145 | TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ |
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| 146 | SDIO_IRQn = 45, /*!< SDIO global Interrupt */ |
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| 147 | TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ |
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| 148 | SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ |
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| 149 | UART4_IRQn = 48, /*!< UART4 global Interrupt */ |
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| 150 | UART5_IRQn = 49, /*!< UART5 global Interrupt */ |
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| 151 | DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ |
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| 152 | DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ |
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| 153 | DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ |
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| 154 | DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ |
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| 155 | DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ |
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| 156 | AES_IRQn = 55, /*!< AES global Interrupt */ |
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| 157 | COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ |
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| 158 | } IRQn_Type; |
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| 159 | |||
| 160 | /** |
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| 161 | * @} |
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| 162 | */ |
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| 163 | |||
| 164 | #include "core_cm3.h" |
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| 165 | #include "system_stm32l1xx.h" |
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| 166 | #include <stdint.h> |
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| 167 | |||
| 168 | /** @addtogroup Peripheral_registers_structures |
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| 169 | * @{ |
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| 170 | */ |
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| 171 | |||
| 172 | /** |
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| 173 | * @brief Analog to Digital Converter |
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| 174 | */ |
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| 175 | |||
| 176 | typedef struct |
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| 177 | { |
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| 178 | __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ |
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| 179 | __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ |
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| 180 | __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ |
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| 181 | __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ |
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| 182 | __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ |
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| 183 | __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ |
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| 184 | __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ |
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| 185 | __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ |
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| 186 | __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ |
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| 187 | __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ |
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| 188 | __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ |
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| 189 | __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ |
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| 190 | __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ |
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| 191 | __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ |
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| 192 | __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ |
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| 193 | __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ |
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| 194 | __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ |
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| 195 | __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ |
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| 196 | __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ |
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| 197 | __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ |
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| 198 | __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ |
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| 199 | __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ |
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| 200 | __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ |
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| 201 | __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ |
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| 202 | } ADC_TypeDef; |
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| 203 | |||
| 204 | typedef struct |
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| 205 | { |
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| 206 | __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ |
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| 207 | __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ |
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| 208 | } ADC_Common_TypeDef; |
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| 209 | |||
| 210 | /** |
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| 211 | * @brief AES hardware accelerator |
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| 212 | */ |
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| 213 | |||
| 214 | typedef struct |
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| 215 | { |
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| 216 | __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ |
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| 217 | __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ |
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| 218 | __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ |
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| 219 | __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ |
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| 220 | __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ |
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| 221 | __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ |
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| 222 | __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ |
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| 223 | __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ |
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| 224 | __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ |
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| 225 | __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ |
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| 226 | __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ |
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| 227 | __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ |
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| 228 | } AES_TypeDef; |
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| 229 | |||
| 230 | /** |
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| 231 | * @brief Comparator |
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| 232 | */ |
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| 233 | |||
| 234 | typedef struct |
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| 235 | { |
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| 236 | __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ |
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| 237 | } COMP_TypeDef; |
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| 238 | |||
| 239 | typedef struct |
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| 240 | { |
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| 241 | __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ |
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| 242 | } COMP_Common_TypeDef; |
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| 243 | |||
| 244 | /** |
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| 245 | * @brief CRC calculation unit |
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| 246 | */ |
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| 247 | |||
| 248 | typedef struct |
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| 249 | { |
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| 250 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
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| 251 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
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| 252 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
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| 253 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
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| 254 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
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| 255 | } CRC_TypeDef; |
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| 256 | |||
| 257 | /** |
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| 258 | * @brief Digital to Analog Converter |
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| 259 | */ |
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| 260 | |||
| 261 | typedef struct |
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| 262 | { |
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| 263 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
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| 264 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
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| 265 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
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| 266 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
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| 267 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
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| 268 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
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| 269 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
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| 270 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
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| 271 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
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| 272 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
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| 273 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
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| 274 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
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| 275 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
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| 276 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
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| 277 | } DAC_TypeDef; |
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| 278 | |||
| 279 | /** |
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| 280 | * @brief Debug MCU |
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| 281 | */ |
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| 282 | |||
| 283 | typedef struct |
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| 284 | { |
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| 285 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
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| 286 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
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| 287 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
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| 288 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
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| 289 | }DBGMCU_TypeDef; |
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| 290 | |||
| 291 | /** |
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| 292 | * @brief DMA Controller |
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| 293 | */ |
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| 294 | |||
| 295 | typedef struct |
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| 296 | { |
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| 297 | __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
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| 298 | __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
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| 299 | __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
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| 300 | __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
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| 301 | } DMA_Channel_TypeDef; |
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| 302 | |||
| 303 | typedef struct |
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| 304 | { |
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| 305 | __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
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| 306 | __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
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| 307 | } DMA_TypeDef; |
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| 308 | |||
| 309 | /** |
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| 310 | * @brief External Interrupt/Event Controller |
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| 311 | */ |
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| 312 | |||
| 313 | typedef struct |
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| 314 | { |
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| 315 | __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ |
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| 316 | __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ |
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| 317 | __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ |
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| 318 | __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ |
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| 319 | __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ |
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| 320 | __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ |
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| 321 | } EXTI_TypeDef; |
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| 322 | |||
| 323 | /** |
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| 324 | * @brief FLASH Registers |
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| 325 | */ |
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| 326 | typedef struct |
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| 327 | { |
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| 328 | __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ |
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| 329 | __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ |
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| 330 | __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ |
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| 331 | __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ |
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| 332 | __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ |
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| 333 | __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ |
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| 334 | __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ |
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| 335 | __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ |
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| 336 | __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */ |
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| 337 | uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */ |
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| 338 | __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */ |
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| 339 | __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */ |
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| 340 | } FLASH_TypeDef; |
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| 341 | |||
| 342 | /** |
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| 343 | * @brief Option Bytes Registers |
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| 344 | */ |
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| 345 | typedef struct |
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| 346 | { |
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| 347 | __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ |
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| 348 | __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ |
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| 349 | __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ |
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| 350 | __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ |
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| 351 | __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ |
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| 352 | __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ |
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| 353 | __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ |
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| 354 | __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ |
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| 355 | } OB_TypeDef; |
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| 356 | |||
| 357 | /** |
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| 358 | * @brief Operational Amplifier (OPAMP) |
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| 359 | */ |
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| 360 | typedef struct |
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| 361 | { |
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| 362 | __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ |
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| 363 | __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ |
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| 364 | __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ |
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| 365 | } OPAMP_TypeDef; |
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| 366 | |||
| 367 | typedef struct |
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| 368 | { |
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| 369 | __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ |
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| 370 | __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ |
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| 371 | } OPAMP_Common_TypeDef; |
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| 372 | |||
| 373 | /** |
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| 374 | * @brief Flexible Static Memory Controller |
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| 375 | */ |
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| 376 | |||
| 377 | typedef struct |
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| 378 | { |
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| 379 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
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| 380 | } FSMC_Bank1_TypeDef; |
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| 381 | |||
| 382 | /** |
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| 383 | * @brief Flexible Static Memory Controller Bank1E |
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| 384 | */ |
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| 385 | |||
| 386 | typedef struct |
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| 387 | { |
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| 388 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
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| 389 | } FSMC_Bank1E_TypeDef; |
||
| 390 | |||
| 391 | /** |
||
| 392 | * @brief General Purpose IO |
||
| 393 | */ |
||
| 394 | |||
| 395 | typedef struct |
||
| 396 | { |
||
| 397 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
||
| 398 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
||
| 399 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
||
| 400 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
||
| 401 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
||
| 402 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
||
| 403 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ |
||
| 404 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
||
| 405 | __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ |
||
| 406 | __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ |
||
| 407 | } GPIO_TypeDef; |
||
| 408 | |||
| 409 | /** |
||
| 410 | * @brief SysTem Configuration |
||
| 411 | */ |
||
| 412 | |||
| 413 | typedef struct |
||
| 414 | { |
||
| 415 | __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
||
| 416 | __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ |
||
| 417 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
||
| 418 | } SYSCFG_TypeDef; |
||
| 419 | |||
| 420 | /** |
||
| 421 | * @brief Inter-integrated Circuit Interface |
||
| 422 | */ |
||
| 423 | |||
| 424 | typedef struct |
||
| 425 | { |
||
| 426 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
||
| 427 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
||
| 428 | __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ |
||
| 429 | __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ |
||
| 430 | __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ |
||
| 431 | __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ |
||
| 432 | __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ |
||
| 433 | __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ |
||
| 434 | __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ |
||
| 435 | } I2C_TypeDef; |
||
| 436 | |||
| 437 | /** |
||
| 438 | * @brief Independent WATCHDOG |
||
| 439 | */ |
||
| 440 | |||
| 441 | typedef struct |
||
| 442 | { |
||
| 443 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
||
| 444 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
||
| 445 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
||
| 446 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
||
| 447 | } IWDG_TypeDef; |
||
| 448 | |||
| 449 | /** |
||
| 450 | * @brief LCD |
||
| 451 | */ |
||
| 452 | |||
| 453 | typedef struct |
||
| 454 | { |
||
| 455 | __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ |
||
| 456 | __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ |
||
| 457 | __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ |
||
| 458 | __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ |
||
| 459 | uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ |
||
| 460 | __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ |
||
| 461 | } LCD_TypeDef; |
||
| 462 | |||
| 463 | /** |
||
| 464 | * @brief Power Control |
||
| 465 | */ |
||
| 466 | |||
| 467 | typedef struct |
||
| 468 | { |
||
| 469 | __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
||
| 470 | __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
||
| 471 | } PWR_TypeDef; |
||
| 472 | |||
| 473 | /** |
||
| 474 | * @brief Reset and Clock Control |
||
| 475 | */ |
||
| 476 | |||
| 477 | typedef struct |
||
| 478 | { |
||
| 479 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
||
| 480 | __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ |
||
| 481 | __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ |
||
| 482 | __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ |
||
| 483 | __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ |
||
| 484 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ |
||
| 485 | __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ |
||
| 486 | __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ |
||
| 487 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ |
||
| 488 | __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ |
||
| 489 | __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ |
||
| 490 | __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ |
||
| 491 | __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ |
||
| 492 | __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ |
||
| 493 | } RCC_TypeDef; |
||
| 494 | |||
| 495 | /** |
||
| 496 | * @brief Routing Interface |
||
| 497 | */ |
||
| 498 | |||
| 499 | typedef struct |
||
| 500 | { |
||
| 501 | __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ |
||
| 502 | __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ |
||
| 503 | __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ |
||
| 504 | __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ |
||
| 505 | __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ |
||
| 506 | __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ |
||
| 507 | __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ |
||
| 508 | __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ |
||
| 509 | __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ |
||
| 510 | __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ |
||
| 511 | __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ |
||
| 512 | __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ |
||
| 513 | __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ |
||
| 514 | __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ |
||
| 515 | __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ |
||
| 516 | __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ |
||
| 517 | __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ |
||
| 518 | __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ |
||
| 519 | __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ |
||
| 520 | __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ |
||
| 521 | __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ |
||
| 522 | __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ |
||
| 523 | } RI_TypeDef; |
||
| 524 | |||
| 525 | /** |
||
| 526 | * @brief Real-Time Clock |
||
| 527 | */ |
||
| 528 | typedef struct |
||
| 529 | { |
||
| 530 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
||
| 531 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
||
| 532 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
||
| 533 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
||
| 534 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
||
| 535 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
||
| 536 | __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ |
||
| 537 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
||
| 538 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
||
| 539 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
||
| 540 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
||
| 541 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
||
| 542 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
||
| 543 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
||
| 544 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
||
| 545 | __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ |
||
| 546 | __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
||
| 547 | __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
||
| 548 | __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
||
| 549 | uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
||
| 550 | __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
||
| 551 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
||
| 552 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
||
| 553 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
||
| 554 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
||
| 555 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
||
| 556 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
||
| 557 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
||
| 558 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
||
| 559 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
||
| 560 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
||
| 561 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
||
| 562 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
||
| 563 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
||
| 564 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
||
| 565 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
||
| 566 | __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
||
| 567 | __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
||
| 568 | __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
||
| 569 | __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
||
| 570 | __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ |
||
| 571 | __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ |
||
| 572 | __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ |
||
| 573 | __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ |
||
| 574 | __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ |
||
| 575 | __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ |
||
| 576 | __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ |
||
| 577 | __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ |
||
| 578 | __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ |
||
| 579 | __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ |
||
| 580 | __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ |
||
| 581 | __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ |
||
| 582 | } RTC_TypeDef; |
||
| 583 | |||
| 584 | /** |
||
| 585 | * @brief SD host Interface |
||
| 586 | */ |
||
| 587 | |||
| 588 | typedef struct |
||
| 589 | { |
||
| 590 | __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ |
||
| 591 | __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ |
||
| 592 | __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ |
||
| 593 | __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ |
||
| 594 | __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ |
||
| 595 | __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ |
||
| 596 | __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ |
||
| 597 | __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ |
||
| 598 | __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ |
||
| 599 | __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ |
||
| 600 | __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ |
||
| 601 | __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ |
||
| 602 | __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ |
||
| 603 | __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ |
||
| 604 | __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ |
||
| 605 | __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ |
||
| 606 | uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
||
| 607 | __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ |
||
| 608 | uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
||
| 609 | __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ |
||
| 610 | } SDIO_TypeDef; |
||
| 611 | |||
| 612 | /** |
||
| 613 | * @brief Serial Peripheral Interface |
||
| 614 | */ |
||
| 615 | |||
| 616 | typedef struct |
||
| 617 | { |
||
| 618 | __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ |
||
| 619 | __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
||
| 620 | __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
||
| 621 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
||
| 622 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
||
| 623 | __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ |
||
| 624 | __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ |
||
| 625 | __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
||
| 626 | __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
||
| 627 | } SPI_TypeDef; |
||
| 628 | |||
| 629 | /** |
||
| 630 | * @brief TIM |
||
| 631 | */ |
||
| 632 | typedef struct |
||
| 633 | { |
||
| 634 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
||
| 635 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
||
| 636 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
||
| 637 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
||
| 638 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
||
| 639 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
||
| 640 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
||
| 641 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
||
| 642 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
||
| 643 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
||
| 644 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
||
| 645 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
||
| 646 | uint32_t RESERVED12; /*!< Reserved, 0x30 */ |
||
| 647 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
||
| 648 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
||
| 649 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
||
| 650 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
||
| 651 | uint32_t RESERVED17; /*!< Reserved, 0x44 */ |
||
| 652 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
||
| 653 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
||
| 654 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
||
| 655 | } TIM_TypeDef; |
||
| 656 | /** |
||
| 657 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
||
| 658 | */ |
||
| 659 | |||
| 660 | typedef struct |
||
| 661 | { |
||
| 662 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
||
| 663 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
||
| 664 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
||
| 665 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
||
| 666 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
||
| 667 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
||
| 668 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
||
| 669 | } USART_TypeDef; |
||
| 670 | |||
| 671 | /** |
||
| 672 | * @brief Universal Serial Bus Full Speed Device |
||
| 673 | */ |
||
| 674 | |||
| 675 | typedef struct |
||
| 676 | { |
||
| 677 | __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ |
||
| 678 | __IO uint16_t RESERVED0; /*!< Reserved */ |
||
| 679 | __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ |
||
| 680 | __IO uint16_t RESERVED1; /*!< Reserved */ |
||
| 681 | __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ |
||
| 682 | __IO uint16_t RESERVED2; /*!< Reserved */ |
||
| 683 | __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ |
||
| 684 | __IO uint16_t RESERVED3; /*!< Reserved */ |
||
| 685 | __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ |
||
| 686 | __IO uint16_t RESERVED4; /*!< Reserved */ |
||
| 687 | __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ |
||
| 688 | __IO uint16_t RESERVED5; /*!< Reserved */ |
||
| 689 | __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ |
||
| 690 | __IO uint16_t RESERVED6; /*!< Reserved */ |
||
| 691 | __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ |
||
| 692 | __IO uint16_t RESERVED7[17]; /*!< Reserved */ |
||
| 693 | __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ |
||
| 694 | __IO uint16_t RESERVED8; /*!< Reserved */ |
||
| 695 | __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ |
||
| 696 | __IO uint16_t RESERVED9; /*!< Reserved */ |
||
| 697 | __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ |
||
| 698 | __IO uint16_t RESERVEDA; /*!< Reserved */ |
||
| 699 | __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ |
||
| 700 | __IO uint16_t RESERVEDB; /*!< Reserved */ |
||
| 701 | __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ |
||
| 702 | __IO uint16_t RESERVEDC; /*!< Reserved */ |
||
| 703 | } USB_TypeDef; |
||
| 704 | |||
| 705 | /** |
||
| 706 | * @brief Window WATCHDOG |
||
| 707 | */ |
||
| 708 | typedef struct |
||
| 709 | { |
||
| 710 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
||
| 711 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
||
| 712 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
||
| 713 | } WWDG_TypeDef; |
||
| 714 | |||
| 715 | /** |
||
| 716 | * @brief Universal Serial Bus Full Speed Device |
||
| 717 | */ |
||
| 718 | /** |
||
| 719 | * @} |
||
| 720 | */ |
||
| 721 | |||
| 722 | /** @addtogroup Peripheral_memory_map |
||
| 723 | * @{ |
||
| 724 | */ |
||
| 725 | |||
| 726 | #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ |
||
| 727 | #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ |
||
| 728 | #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ |
||
| 729 | #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ |
||
| 730 | #define FSMC_BASE ((uint32_t)0x60000000U) /*!< FSMC base address */ |
||
| 731 | #define FSMC_R_BASE ((uint32_t)0xA0000000U) /*!< FSMC registers base address */ |
||
| 732 | #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ |
||
| 733 | #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ |
||
| 734 | #define FLASH_BANK2_BASE ((uint32_t)0x08030000U) /*!< FLASH BANK2 base address in the alias region */ |
||
| 735 | #define FLASH_BANK1_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK1 address */ |
||
| 736 | #define FLASH_BANK2_END ((uint32_t)0x0805FFFFU) /*!< Program end FLASH BANK2 address */ |
||
| 737 | #define FLASH_EEPROM_END ((uint32_t)0x08082FFFU) /*!< FLASH EEPROM end address (12KB) */ |
||
| 738 | |||
| 739 | /*!< Peripheral memory map */ |
||
| 740 | #define APB1PERIPH_BASE PERIPH_BASE |
||
| 741 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) |
||
| 742 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) |
||
| 743 | |||
| 744 | /*!< APB1 peripherals */ |
||
| 745 | #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) |
||
| 746 | #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) |
||
| 747 | #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) |
||
| 748 | #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U) |
||
| 749 | #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) |
||
| 750 | #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) |
||
| 751 | #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U) |
||
| 752 | #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) |
||
| 753 | #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) |
||
| 754 | #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) |
||
| 755 | #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) |
||
| 756 | #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) |
||
| 757 | #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) |
||
| 758 | #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) |
||
| 759 | #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) |
||
| 760 | #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) |
||
| 761 | #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) |
||
| 762 | #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) |
||
| 763 | |||
| 764 | /* USB device FS */ |
||
| 765 | #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ |
||
| 766 | #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ |
||
| 767 | |||
| 768 | /* USB device FS SRAM */ |
||
| 769 | #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) |
||
| 770 | #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) |
||
| 771 | #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) |
||
| 772 | #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) |
||
| 773 | #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU) |
||
| 774 | |||
| 775 | /*!< APB2 peripherals */ |
||
| 776 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) |
||
| 777 | #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) |
||
| 778 | #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) |
||
| 779 | #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) |
||
| 780 | #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) |
||
| 781 | #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) |
||
| 782 | #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) |
||
| 783 | #define SDIO_BASE (APB2PERIPH_BASE + 0x00002C00U) |
||
| 784 | #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) |
||
| 785 | #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) |
||
| 786 | |||
| 787 | /*!< AHB peripherals */ |
||
| 788 | #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) |
||
| 789 | #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) |
||
| 790 | #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) |
||
| 791 | #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) |
||
| 792 | #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) |
||
| 793 | #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) |
||
| 794 | #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U) |
||
| 795 | #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U) |
||
| 796 | #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) |
||
| 797 | #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) |
||
| 798 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ |
||
| 799 | #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ |
||
| 800 | #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ |
||
| 801 | #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ |
||
| 802 | #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) |
||
| 803 | #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) |
||
| 804 | #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) |
||
| 805 | #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) |
||
| 806 | #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) |
||
| 807 | #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) |
||
| 808 | #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) |
||
| 809 | #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) |
||
| 810 | #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) |
||
| 811 | #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U) |
||
| 812 | #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU) |
||
| 813 | #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U) |
||
| 814 | #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U) |
||
| 815 | #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U) |
||
| 816 | #define AES_BASE ((uint32_t)0x50060000U) |
||
| 817 | #define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */ |
||
| 818 | #define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */ |
||
| 819 | #define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */ |
||
| 820 | #define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */ |
||
| 821 | #define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */ |
||
| 822 | #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000U) /*!< FSMC Bank1 registers base address */ |
||
| 823 | #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104U) /*!< FSMC Bank1E registers base address */ |
||
| 824 | #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ |
||
| 825 | |||
| 826 | /** |
||
| 827 | * @} |
||
| 828 | */ |
||
| 829 | |||
| 830 | /** @addtogroup Peripheral_declaration |
||
| 831 | * @{ |
||
| 832 | */ |
||
| 833 | |||
| 834 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
||
| 835 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
||
| 836 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
||
| 837 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
||
| 838 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
||
| 839 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
||
| 840 | #define LCD ((LCD_TypeDef *) LCD_BASE) |
||
| 841 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
||
| 842 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
||
| 843 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
||
| 844 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
||
| 845 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
||
| 846 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
||
| 847 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
||
| 848 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
||
| 849 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
||
| 850 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
||
| 851 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
||
| 852 | /* USB device FS */ |
||
| 853 | #define USB ((USB_TypeDef *) USB_BASE) |
||
| 854 | /* USB device FS SRAM */ |
||
| 855 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
||
| 856 | |||
| 857 | #define DAC1 ((DAC_TypeDef *) DAC_BASE) |
||
| 858 | /* Legacy define */ |
||
| 859 | #define DAC DAC1 |
||
| 860 | |||
| 861 | #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ |
||
| 862 | #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ |
||
| 863 | #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ |
||
| 864 | #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ |
||
| 865 | |||
| 866 | #define RI ((RI_TypeDef *) RI_BASE) |
||
| 867 | |||
| 868 | #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
||
| 869 | #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) |
||
| 870 | #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) |
||
| 871 | #define OPAMP3 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U)) |
||
| 872 | #define OPAMP123_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) |
||
| 873 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
||
| 874 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
||
| 875 | #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
||
| 876 | #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
||
| 877 | #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
||
| 878 | |||
| 879 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
||
| 880 | #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) |
||
| 881 | /* Legacy defines */ |
||
| 882 | #define ADC ADC1_COMMON |
||
| 883 | |||
| 884 | #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
||
| 885 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
||
| 886 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
||
| 887 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
||
| 888 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
||
| 889 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
||
| 890 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
||
| 891 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
||
| 892 | #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
||
| 893 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
||
| 894 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
||
| 895 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
||
| 896 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
||
| 897 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
||
| 898 | #define OB ((OB_TypeDef *) OB_BASE) |
||
| 899 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
||
| 900 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
||
| 901 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
||
| 902 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
||
| 903 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
||
| 904 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
||
| 905 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
||
| 906 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
||
| 907 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
||
| 908 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
||
| 909 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
||
| 910 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
||
| 911 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
||
| 912 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
||
| 913 | #define AES ((AES_TypeDef *) AES_BASE) |
||
| 914 | #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE) |
||
| 915 | #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE) |
||
| 916 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
||
| 917 | |||
| 918 | /** |
||
| 919 | * @} |
||
| 920 | */ |
||
| 921 | |||
| 922 | /** @addtogroup Exported_constants |
||
| 923 | * @{ |
||
| 924 | */ |
||
| 925 | |||
| 926 | /** @addtogroup Peripheral_Registers_Bits_Definition |
||
| 927 | * @{ |
||
| 928 | */ |
||
| 929 | |||
| 930 | /******************************************************************************/ |
||
| 931 | /* Peripheral Registers Bits Definition */ |
||
| 932 | /******************************************************************************/ |
||
| 933 | /******************************************************************************/ |
||
| 934 | /* */ |
||
| 935 | /* Analog to Digital Converter (ADC) */ |
||
| 936 | /* */ |
||
| 937 | /******************************************************************************/ |
||
| 938 | |||
| 939 | /******************** Bit definition for ADC_SR register ********************/ |
||
| 940 | #define ADC_SR_AWD_Pos (0U) |
||
| 941 | #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
||
| 942 | #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ |
||
| 943 | #define ADC_SR_EOCS_Pos (1U) |
||
| 944 | #define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ |
||
| 945 | #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ |
||
| 946 | #define ADC_SR_JEOS_Pos (2U) |
||
| 947 | #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ |
||
| 948 | #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
||
| 949 | #define ADC_SR_JSTRT_Pos (3U) |
||
| 950 | #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
||
| 951 | #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ |
||
| 952 | #define ADC_SR_STRT_Pos (4U) |
||
| 953 | #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
||
| 954 | #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ |
||
| 955 | #define ADC_SR_OVR_Pos (5U) |
||
| 956 | #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ |
||
| 957 | #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ |
||
| 958 | #define ADC_SR_ADONS_Pos (6U) |
||
| 959 | #define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ |
||
| 960 | #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ |
||
| 961 | #define ADC_SR_RCNR_Pos (8U) |
||
| 962 | #define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ |
||
| 963 | #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ |
||
| 964 | #define ADC_SR_JCNR_Pos (9U) |
||
| 965 | #define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ |
||
| 966 | #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ |
||
| 967 | |||
| 968 | /* Legacy defines */ |
||
| 969 | #define ADC_SR_EOC (ADC_SR_EOCS) |
||
| 970 | #define ADC_SR_JEOC (ADC_SR_JEOS) |
||
| 971 | |||
| 972 | /******************* Bit definition for ADC_CR1 register ********************/ |
||
| 973 | #define ADC_CR1_AWDCH_Pos (0U) |
||
| 974 | #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
||
| 975 | #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
||
| 976 | #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
||
| 977 | #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
||
| 978 | #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
||
| 979 | #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
||
| 980 | #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
||
| 981 | |||
| 982 | #define ADC_CR1_EOCSIE_Pos (5U) |
||
| 983 | #define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ |
||
| 984 | #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ |
||
| 985 | #define ADC_CR1_AWDIE_Pos (6U) |
||
| 986 | #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
||
| 987 | #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ |
||
| 988 | #define ADC_CR1_JEOSIE_Pos (7U) |
||
| 989 | #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ |
||
| 990 | #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
||
| 991 | #define ADC_CR1_SCAN_Pos (8U) |
||
| 992 | #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
||
| 993 | #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ |
||
| 994 | #define ADC_CR1_AWDSGL_Pos (9U) |
||
| 995 | #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
||
| 996 | #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
||
| 997 | #define ADC_CR1_JAUTO_Pos (10U) |
||
| 998 | #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
||
| 999 | #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
||
| 1000 | #define ADC_CR1_DISCEN_Pos (11U) |
||
| 1001 | #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
||
| 1002 | #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
||
| 1003 | #define ADC_CR1_JDISCEN_Pos (12U) |
||
| 1004 | #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
||
| 1005 | #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
||
| 1006 | |||
| 1007 | #define ADC_CR1_DISCNUM_Pos (13U) |
||
| 1008 | #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
||
| 1009 | #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
||
| 1010 | #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
||
| 1011 | #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
||
| 1012 | #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
||
| 1013 | |||
| 1014 | #define ADC_CR1_PDD_Pos (16U) |
||
| 1015 | #define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ |
||
| 1016 | #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ |
||
| 1017 | #define ADC_CR1_PDI_Pos (17U) |
||
| 1018 | #define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ |
||
| 1019 | #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ |
||
| 1020 | |||
| 1021 | #define ADC_CR1_JAWDEN_Pos (22U) |
||
| 1022 | #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
||
| 1023 | #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
||
| 1024 | #define ADC_CR1_AWDEN_Pos (23U) |
||
| 1025 | #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
||
| 1026 | #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
||
| 1027 | |||
| 1028 | #define ADC_CR1_RES_Pos (24U) |
||
| 1029 | #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ |
||
| 1030 | #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ |
||
| 1031 | #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ |
||
| 1032 | #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ |
||
| 1033 | |||
| 1034 | #define ADC_CR1_OVRIE_Pos (26U) |
||
| 1035 | #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ |
||
| 1036 | #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ |
||
| 1037 | |||
| 1038 | /* Legacy defines */ |
||
| 1039 | #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) |
||
| 1040 | #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) |
||
| 1041 | |||
| 1042 | /******************* Bit definition for ADC_CR2 register ********************/ |
||
| 1043 | #define ADC_CR2_ADON_Pos (0U) |
||
| 1044 | #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
||
| 1045 | #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ |
||
| 1046 | #define ADC_CR2_CONT_Pos (1U) |
||
| 1047 | #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
||
| 1048 | #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
||
| 1049 | #define ADC_CR2_CFG_Pos (2U) |
||
| 1050 | #define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /*!< 0x00000004 */ |
||
| 1051 | #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */ |
||
| 1052 | |||
| 1053 | #define ADC_CR2_DELS_Pos (4U) |
||
| 1054 | #define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ |
||
| 1055 | #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ |
||
| 1056 | #define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ |
||
| 1057 | #define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ |
||
| 1058 | #define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ |
||
| 1059 | |||
| 1060 | #define ADC_CR2_DMA_Pos (8U) |
||
| 1061 | #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
||
| 1062 | #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ |
||
| 1063 | #define ADC_CR2_DDS_Pos (9U) |
||
| 1064 | #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ |
||
| 1065 | #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ |
||
| 1066 | #define ADC_CR2_EOCS_Pos (10U) |
||
| 1067 | #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ |
||
| 1068 | #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ |
||
| 1069 | #define ADC_CR2_ALIGN_Pos (11U) |
||
| 1070 | #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
||
| 1071 | #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ |
||
| 1072 | |||
| 1073 | #define ADC_CR2_JEXTSEL_Pos (16U) |
||
| 1074 | #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ |
||
| 1075 | #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
||
| 1076 | #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ |
||
| 1077 | #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ |
||
| 1078 | #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ |
||
| 1079 | #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ |
||
| 1080 | |||
| 1081 | #define ADC_CR2_JEXTEN_Pos (20U) |
||
| 1082 | #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ |
||
| 1083 | #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ |
||
| 1084 | #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ |
||
| 1085 | #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ |
||
| 1086 | |||
| 1087 | #define ADC_CR2_JSWSTART_Pos (22U) |
||
| 1088 | #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ |
||
| 1089 | #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ |
||
| 1090 | |||
| 1091 | #define ADC_CR2_EXTSEL_Pos (24U) |
||
| 1092 | #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ |
||
| 1093 | #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
||
| 1094 | #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ |
||
| 1095 | #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ |
||
| 1096 | #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ |
||
| 1097 | #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ |
||
| 1098 | |||
| 1099 | #define ADC_CR2_EXTEN_Pos (28U) |
||
| 1100 | #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ |
||
| 1101 | #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ |
||
| 1102 | #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ |
||
| 1103 | #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ |
||
| 1104 | |||
| 1105 | #define ADC_CR2_SWSTART_Pos (30U) |
||
| 1106 | #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ |
||
| 1107 | #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ |
||
| 1108 | |||
| 1109 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
||
| 1110 | #define ADC_SMPR1_SMP20_Pos (0U) |
||
| 1111 | #define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ |
||
| 1112 | #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ |
||
| 1113 | #define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ |
||
| 1114 | #define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ |
||
| 1115 | #define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ |
||
| 1116 | |||
| 1117 | #define ADC_SMPR1_SMP21_Pos (3U) |
||
| 1118 | #define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ |
||
| 1119 | #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ |
||
| 1120 | #define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ |
||
| 1121 | #define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ |
||
| 1122 | #define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ |
||
| 1123 | |||
| 1124 | #define ADC_SMPR1_SMP22_Pos (6U) |
||
| 1125 | #define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ |
||
| 1126 | #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ |
||
| 1127 | #define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ |
||
| 1128 | #define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ |
||
| 1129 | #define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ |
||
| 1130 | |||
| 1131 | #define ADC_SMPR1_SMP23_Pos (9U) |
||
| 1132 | #define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ |
||
| 1133 | #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ |
||
| 1134 | #define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ |
||
| 1135 | #define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ |
||
| 1136 | #define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ |
||
| 1137 | |||
| 1138 | #define ADC_SMPR1_SMP24_Pos (12U) |
||
| 1139 | #define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ |
||
| 1140 | #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ |
||
| 1141 | #define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ |
||
| 1142 | #define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ |
||
| 1143 | #define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ |
||
| 1144 | |||
| 1145 | #define ADC_SMPR1_SMP25_Pos (15U) |
||
| 1146 | #define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ |
||
| 1147 | #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ |
||
| 1148 | #define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ |
||
| 1149 | #define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ |
||
| 1150 | #define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ |
||
| 1151 | |||
| 1152 | #define ADC_SMPR1_SMP26_Pos (18U) |
||
| 1153 | #define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ |
||
| 1154 | #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ |
||
| 1155 | #define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ |
||
| 1156 | #define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ |
||
| 1157 | #define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ |
||
| 1158 | |||
| 1159 | #define ADC_SMPR1_SMP27_Pos (21U) |
||
| 1160 | #define ADC_SMPR1_SMP27_Msk (0x7U << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */ |
||
| 1161 | #define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */ |
||
| 1162 | #define ADC_SMPR1_SMP27_0 (0x1U << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */ |
||
| 1163 | #define ADC_SMPR1_SMP27_1 (0x2U << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */ |
||
| 1164 | #define ADC_SMPR1_SMP27_2 (0x4U << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */ |
||
| 1165 | |||
| 1166 | #define ADC_SMPR1_SMP28_Pos (24U) |
||
| 1167 | #define ADC_SMPR1_SMP28_Msk (0x7U << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */ |
||
| 1168 | #define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */ |
||
| 1169 | #define ADC_SMPR1_SMP28_0 (0x1U << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */ |
||
| 1170 | #define ADC_SMPR1_SMP28_1 (0x2U << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */ |
||
| 1171 | #define ADC_SMPR1_SMP28_2 (0x4U << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */ |
||
| 1172 | |||
| 1173 | #define ADC_SMPR1_SMP29_Pos (27U) |
||
| 1174 | #define ADC_SMPR1_SMP29_Msk (0x7U << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */ |
||
| 1175 | #define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */ |
||
| 1176 | #define ADC_SMPR1_SMP29_0 (0x1U << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */ |
||
| 1177 | #define ADC_SMPR1_SMP29_1 (0x2U << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */ |
||
| 1178 | #define ADC_SMPR1_SMP29_2 (0x4U << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */ |
||
| 1179 | |||
| 1180 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
||
| 1181 | #define ADC_SMPR2_SMP10_Pos (0U) |
||
| 1182 | #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ |
||
| 1183 | #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
||
| 1184 | #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ |
||
| 1185 | #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ |
||
| 1186 | #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ |
||
| 1187 | |||
| 1188 | #define ADC_SMPR2_SMP11_Pos (3U) |
||
| 1189 | #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ |
||
| 1190 | #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
||
| 1191 | #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ |
||
| 1192 | #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ |
||
| 1193 | #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ |
||
| 1194 | |||
| 1195 | #define ADC_SMPR2_SMP12_Pos (6U) |
||
| 1196 | #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ |
||
| 1197 | #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
||
| 1198 | #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ |
||
| 1199 | #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ |
||
| 1200 | #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ |
||
| 1201 | |||
| 1202 | #define ADC_SMPR2_SMP13_Pos (9U) |
||
| 1203 | #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ |
||
| 1204 | #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
||
| 1205 | #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ |
||
| 1206 | #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ |
||
| 1207 | #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ |
||
| 1208 | |||
| 1209 | #define ADC_SMPR2_SMP14_Pos (12U) |
||
| 1210 | #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ |
||
| 1211 | #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
||
| 1212 | #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ |
||
| 1213 | #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ |
||
| 1214 | #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ |
||
| 1215 | |||
| 1216 | #define ADC_SMPR2_SMP15_Pos (15U) |
||
| 1217 | #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ |
||
| 1218 | #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ |
||
| 1219 | #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ |
||
| 1220 | #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ |
||
| 1221 | #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ |
||
| 1222 | |||
| 1223 | #define ADC_SMPR2_SMP16_Pos (18U) |
||
| 1224 | #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ |
||
| 1225 | #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
||
| 1226 | #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ |
||
| 1227 | #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ |
||
| 1228 | #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ |
||
| 1229 | |||
| 1230 | #define ADC_SMPR2_SMP17_Pos (21U) |
||
| 1231 | #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ |
||
| 1232 | #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
||
| 1233 | #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ |
||
| 1234 | #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ |
||
| 1235 | #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ |
||
| 1236 | |||
| 1237 | #define ADC_SMPR2_SMP18_Pos (24U) |
||
| 1238 | #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ |
||
| 1239 | #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ |
||
| 1240 | #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ |
||
| 1241 | #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ |
||
| 1242 | #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ |
||
| 1243 | |||
| 1244 | #define ADC_SMPR2_SMP19_Pos (27U) |
||
| 1245 | #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ |
||
| 1246 | #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ |
||
| 1247 | #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ |
||
| 1248 | #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ |
||
| 1249 | #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ |
||
| 1250 | |||
| 1251 | /****************** Bit definition for ADC_SMPR3 register *******************/ |
||
| 1252 | #define ADC_SMPR3_SMP0_Pos (0U) |
||
| 1253 | #define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ |
||
| 1254 | #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
||
| 1255 | #define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ |
||
| 1256 | #define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ |
||
| 1257 | #define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ |
||
| 1258 | |||
| 1259 | #define ADC_SMPR3_SMP1_Pos (3U) |
||
| 1260 | #define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ |
||
| 1261 | #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
||
| 1262 | #define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ |
||
| 1263 | #define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ |
||
| 1264 | #define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ |
||
| 1265 | |||
| 1266 | #define ADC_SMPR3_SMP2_Pos (6U) |
||
| 1267 | #define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ |
||
| 1268 | #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
||
| 1269 | #define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ |
||
| 1270 | #define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ |
||
| 1271 | #define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ |
||
| 1272 | |||
| 1273 | #define ADC_SMPR3_SMP3_Pos (9U) |
||
| 1274 | #define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ |
||
| 1275 | #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
||
| 1276 | #define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ |
||
| 1277 | #define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ |
||
| 1278 | #define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ |
||
| 1279 | |||
| 1280 | #define ADC_SMPR3_SMP4_Pos (12U) |
||
| 1281 | #define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ |
||
| 1282 | #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
||
| 1283 | #define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ |
||
| 1284 | #define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ |
||
| 1285 | #define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ |
||
| 1286 | |||
| 1287 | #define ADC_SMPR3_SMP5_Pos (15U) |
||
| 1288 | #define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ |
||
| 1289 | #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
||
| 1290 | #define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ |
||
| 1291 | #define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ |
||
| 1292 | #define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ |
||
| 1293 | |||
| 1294 | #define ADC_SMPR3_SMP6_Pos (18U) |
||
| 1295 | #define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ |
||
| 1296 | #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
||
| 1297 | #define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ |
||
| 1298 | #define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ |
||
| 1299 | #define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ |
||
| 1300 | |||
| 1301 | #define ADC_SMPR3_SMP7_Pos (21U) |
||
| 1302 | #define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ |
||
| 1303 | #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
||
| 1304 | #define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ |
||
| 1305 | #define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ |
||
| 1306 | #define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ |
||
| 1307 | |||
| 1308 | #define ADC_SMPR3_SMP8_Pos (24U) |
||
| 1309 | #define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ |
||
| 1310 | #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
||
| 1311 | #define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ |
||
| 1312 | #define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ |
||
| 1313 | #define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ |
||
| 1314 | |||
| 1315 | #define ADC_SMPR3_SMP9_Pos (27U) |
||
| 1316 | #define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ |
||
| 1317 | #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
||
| 1318 | #define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ |
||
| 1319 | #define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ |
||
| 1320 | #define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ |
||
| 1321 | |||
| 1322 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
||
| 1323 | #define ADC_JOFR1_JOFFSET1_Pos (0U) |
||
| 1324 | #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
||
| 1325 | #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ |
||
| 1326 | |||
| 1327 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
||
| 1328 | #define ADC_JOFR2_JOFFSET2_Pos (0U) |
||
| 1329 | #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
||
| 1330 | #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ |
||
| 1331 | |||
| 1332 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
||
| 1333 | #define ADC_JOFR3_JOFFSET3_Pos (0U) |
||
| 1334 | #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
||
| 1335 | #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ |
||
| 1336 | |||
| 1337 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
||
| 1338 | #define ADC_JOFR4_JOFFSET4_Pos (0U) |
||
| 1339 | #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
||
| 1340 | #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ |
||
| 1341 | |||
| 1342 | /******************* Bit definition for ADC_HTR register ********************/ |
||
| 1343 | #define ADC_HTR_HT_Pos (0U) |
||
| 1344 | #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
||
| 1345 | #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ |
||
| 1346 | |||
| 1347 | /******************* Bit definition for ADC_LTR register ********************/ |
||
| 1348 | #define ADC_LTR_LT_Pos (0U) |
||
| 1349 | #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
||
| 1350 | #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ |
||
| 1351 | |||
| 1352 | /******************* Bit definition for ADC_SQR1 register *******************/ |
||
| 1353 | #define ADC_SQR1_L_Pos (20U) |
||
| 1354 | #define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ |
||
| 1355 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
||
| 1356 | #define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
||
| 1357 | #define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
||
| 1358 | #define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
||
| 1359 | #define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
||
| 1360 | #define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */ |
||
| 1361 | |||
| 1362 | #define ADC_SQR1_SQ28_Pos (15U) |
||
| 1363 | #define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */ |
||
| 1364 | #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */ |
||
| 1365 | #define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */ |
||
| 1366 | #define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */ |
||
| 1367 | #define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */ |
||
| 1368 | #define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */ |
||
| 1369 | #define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */ |
||
| 1370 | |||
| 1371 | #define ADC_SQR1_SQ27_Pos (10U) |
||
| 1372 | #define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ |
||
| 1373 | #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ |
||
| 1374 | #define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ |
||
| 1375 | #define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ |
||
| 1376 | #define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ |
||
| 1377 | #define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ |
||
| 1378 | #define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ |
||
| 1379 | |||
| 1380 | #define ADC_SQR1_SQ26_Pos (5U) |
||
| 1381 | #define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ |
||
| 1382 | #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ |
||
| 1383 | #define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ |
||
| 1384 | #define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ |
||
| 1385 | #define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ |
||
| 1386 | #define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ |
||
| 1387 | #define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ |
||
| 1388 | |||
| 1389 | #define ADC_SQR1_SQ25_Pos (0U) |
||
| 1390 | #define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ |
||
| 1391 | #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ |
||
| 1392 | #define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ |
||
| 1393 | #define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ |
||
| 1394 | #define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ |
||
| 1395 | #define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ |
||
| 1396 | #define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ |
||
| 1397 | |||
| 1398 | /******************* Bit definition for ADC_SQR2 register *******************/ |
||
| 1399 | #define ADC_SQR2_SQ19_Pos (0U) |
||
| 1400 | #define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ |
||
| 1401 | #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ |
||
| 1402 | #define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ |
||
| 1403 | #define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ |
||
| 1404 | #define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ |
||
| 1405 | #define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ |
||
| 1406 | #define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ |
||
| 1407 | |||
| 1408 | #define ADC_SQR2_SQ20_Pos (5U) |
||
| 1409 | #define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ |
||
| 1410 | #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ |
||
| 1411 | #define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ |
||
| 1412 | #define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ |
||
| 1413 | #define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ |
||
| 1414 | #define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ |
||
| 1415 | #define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ |
||
| 1416 | |||
| 1417 | #define ADC_SQR2_SQ21_Pos (10U) |
||
| 1418 | #define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ |
||
| 1419 | #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ |
||
| 1420 | #define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ |
||
| 1421 | #define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ |
||
| 1422 | #define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ |
||
| 1423 | #define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ |
||
| 1424 | #define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ |
||
| 1425 | |||
| 1426 | #define ADC_SQR2_SQ22_Pos (15U) |
||
| 1427 | #define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ |
||
| 1428 | #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ |
||
| 1429 | #define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ |
||
| 1430 | #define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ |
||
| 1431 | #define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ |
||
| 1432 | #define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ |
||
| 1433 | #define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ |
||
| 1434 | |||
| 1435 | #define ADC_SQR2_SQ23_Pos (20U) |
||
| 1436 | #define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ |
||
| 1437 | #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ |
||
| 1438 | #define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ |
||
| 1439 | #define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ |
||
| 1440 | #define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ |
||
| 1441 | #define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ |
||
| 1442 | #define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ |
||
| 1443 | |||
| 1444 | #define ADC_SQR2_SQ24_Pos (25U) |
||
| 1445 | #define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ |
||
| 1446 | #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ |
||
| 1447 | #define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ |
||
| 1448 | #define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ |
||
| 1449 | #define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ |
||
| 1450 | #define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ |
||
| 1451 | #define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ |
||
| 1452 | |||
| 1453 | /******************* Bit definition for ADC_SQR3 register *******************/ |
||
| 1454 | #define ADC_SQR3_SQ13_Pos (0U) |
||
| 1455 | #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ |
||
| 1456 | #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
||
| 1457 | #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ |
||
| 1458 | #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ |
||
| 1459 | #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ |
||
| 1460 | #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ |
||
| 1461 | #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ |
||
| 1462 | |||
| 1463 | #define ADC_SQR3_SQ14_Pos (5U) |
||
| 1464 | #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ |
||
| 1465 | #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
||
| 1466 | #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ |
||
| 1467 | #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ |
||
| 1468 | #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ |
||
| 1469 | #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ |
||
| 1470 | #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ |
||
| 1471 | |||
| 1472 | #define ADC_SQR3_SQ15_Pos (10U) |
||
| 1473 | #define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ |
||
| 1474 | #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
||
| 1475 | #define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ |
||
| 1476 | #define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ |
||
| 1477 | #define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ |
||
| 1478 | #define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ |
||
| 1479 | #define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ |
||
| 1480 | |||
| 1481 | #define ADC_SQR3_SQ16_Pos (15U) |
||
| 1482 | #define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ |
||
| 1483 | #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
||
| 1484 | #define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ |
||
| 1485 | #define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ |
||
| 1486 | #define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ |
||
| 1487 | #define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ |
||
| 1488 | #define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ |
||
| 1489 | |||
| 1490 | #define ADC_SQR3_SQ17_Pos (20U) |
||
| 1491 | #define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ |
||
| 1492 | #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ |
||
| 1493 | #define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ |
||
| 1494 | #define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ |
||
| 1495 | #define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ |
||
| 1496 | #define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ |
||
| 1497 | #define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ |
||
| 1498 | |||
| 1499 | #define ADC_SQR3_SQ18_Pos (25U) |
||
| 1500 | #define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ |
||
| 1501 | #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ |
||
| 1502 | #define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ |
||
| 1503 | #define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ |
||
| 1504 | #define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ |
||
| 1505 | #define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ |
||
| 1506 | #define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ |
||
| 1507 | |||
| 1508 | /******************* Bit definition for ADC_SQR4 register *******************/ |
||
| 1509 | #define ADC_SQR4_SQ7_Pos (0U) |
||
| 1510 | #define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ |
||
| 1511 | #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
||
| 1512 | #define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ |
||
| 1513 | #define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ |
||
| 1514 | #define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ |
||
| 1515 | #define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ |
||
| 1516 | #define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ |
||
| 1517 | |||
| 1518 | #define ADC_SQR4_SQ8_Pos (5U) |
||
| 1519 | #define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ |
||
| 1520 | #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
||
| 1521 | #define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ |
||
| 1522 | #define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ |
||
| 1523 | #define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ |
||
| 1524 | #define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ |
||
| 1525 | #define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ |
||
| 1526 | |||
| 1527 | #define ADC_SQR4_SQ9_Pos (10U) |
||
| 1528 | #define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ |
||
| 1529 | #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
||
| 1530 | #define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ |
||
| 1531 | #define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ |
||
| 1532 | #define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ |
||
| 1533 | #define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ |
||
| 1534 | #define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ |
||
| 1535 | |||
| 1536 | #define ADC_SQR4_SQ10_Pos (15U) |
||
| 1537 | #define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ |
||
| 1538 | #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
||
| 1539 | #define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ |
||
| 1540 | #define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ |
||
| 1541 | #define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ |
||
| 1542 | #define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ |
||
| 1543 | #define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ |
||
| 1544 | |||
| 1545 | #define ADC_SQR4_SQ11_Pos (20U) |
||
| 1546 | #define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ |
||
| 1547 | #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ |
||
| 1548 | #define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ |
||
| 1549 | #define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ |
||
| 1550 | #define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ |
||
| 1551 | #define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ |
||
| 1552 | #define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ |
||
| 1553 | |||
| 1554 | #define ADC_SQR4_SQ12_Pos (25U) |
||
| 1555 | #define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ |
||
| 1556 | #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
||
| 1557 | #define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ |
||
| 1558 | #define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ |
||
| 1559 | #define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ |
||
| 1560 | #define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ |
||
| 1561 | #define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ |
||
| 1562 | |||
| 1563 | /******************* Bit definition for ADC_SQR5 register *******************/ |
||
| 1564 | #define ADC_SQR5_SQ1_Pos (0U) |
||
| 1565 | #define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ |
||
| 1566 | #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
||
| 1567 | #define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ |
||
| 1568 | #define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ |
||
| 1569 | #define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ |
||
| 1570 | #define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ |
||
| 1571 | #define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ |
||
| 1572 | |||
| 1573 | #define ADC_SQR5_SQ2_Pos (5U) |
||
| 1574 | #define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ |
||
| 1575 | #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
||
| 1576 | #define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ |
||
| 1577 | #define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ |
||
| 1578 | #define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ |
||
| 1579 | #define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ |
||
| 1580 | #define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ |
||
| 1581 | |||
| 1582 | #define ADC_SQR5_SQ3_Pos (10U) |
||
| 1583 | #define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ |
||
| 1584 | #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
||
| 1585 | #define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ |
||
| 1586 | #define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ |
||
| 1587 | #define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ |
||
| 1588 | #define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ |
||
| 1589 | #define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ |
||
| 1590 | |||
| 1591 | #define ADC_SQR5_SQ4_Pos (15U) |
||
| 1592 | #define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ |
||
| 1593 | #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
||
| 1594 | #define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ |
||
| 1595 | #define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ |
||
| 1596 | #define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ |
||
| 1597 | #define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ |
||
| 1598 | #define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ |
||
| 1599 | |||
| 1600 | #define ADC_SQR5_SQ5_Pos (20U) |
||
| 1601 | #define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ |
||
| 1602 | #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
||
| 1603 | #define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ |
||
| 1604 | #define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ |
||
| 1605 | #define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ |
||
| 1606 | #define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ |
||
| 1607 | #define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ |
||
| 1608 | |||
| 1609 | #define ADC_SQR5_SQ6_Pos (25U) |
||
| 1610 | #define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ |
||
| 1611 | #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
||
| 1612 | #define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ |
||
| 1613 | #define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ |
||
| 1614 | #define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ |
||
| 1615 | #define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ |
||
| 1616 | #define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ |
||
| 1617 | |||
| 1618 | |||
| 1619 | /******************* Bit definition for ADC_JSQR register *******************/ |
||
| 1620 | #define ADC_JSQR_JSQ1_Pos (0U) |
||
| 1621 | #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
||
| 1622 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
||
| 1623 | #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
||
| 1624 | #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
||
| 1625 | #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
||
| 1626 | #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
||
| 1627 | #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
||
| 1628 | |||
| 1629 | #define ADC_JSQR_JSQ2_Pos (5U) |
||
| 1630 | #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
||
| 1631 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
||
| 1632 | #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
||
| 1633 | #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
||
| 1634 | #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
||
| 1635 | #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
||
| 1636 | #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
||
| 1637 | |||
| 1638 | #define ADC_JSQR_JSQ3_Pos (10U) |
||
| 1639 | #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
||
| 1640 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
||
| 1641 | #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
||
| 1642 | #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
||
| 1643 | #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
||
| 1644 | #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
||
| 1645 | #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
||
| 1646 | |||
| 1647 | #define ADC_JSQR_JSQ4_Pos (15U) |
||
| 1648 | #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
||
| 1649 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
||
| 1650 | #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
||
| 1651 | #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
||
| 1652 | #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
||
| 1653 | #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
||
| 1654 | #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
||
| 1655 | |||
| 1656 | #define ADC_JSQR_JL_Pos (20U) |
||
| 1657 | #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
||
| 1658 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
||
| 1659 | #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
||
| 1660 | #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
||
| 1661 | |||
| 1662 | /******************* Bit definition for ADC_JDR1 register *******************/ |
||
| 1663 | #define ADC_JDR1_JDATA_Pos (0U) |
||
| 1664 | #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 1665 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
||
| 1666 | |||
| 1667 | /******************* Bit definition for ADC_JDR2 register *******************/ |
||
| 1668 | #define ADC_JDR2_JDATA_Pos (0U) |
||
| 1669 | #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 1670 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
||
| 1671 | |||
| 1672 | /******************* Bit definition for ADC_JDR3 register *******************/ |
||
| 1673 | #define ADC_JDR3_JDATA_Pos (0U) |
||
| 1674 | #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 1675 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
||
| 1676 | |||
| 1677 | /******************* Bit definition for ADC_JDR4 register *******************/ |
||
| 1678 | #define ADC_JDR4_JDATA_Pos (0U) |
||
| 1679 | #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
||
| 1680 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
||
| 1681 | |||
| 1682 | /******************** Bit definition for ADC_DR register ********************/ |
||
| 1683 | #define ADC_DR_DATA_Pos (0U) |
||
| 1684 | #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
||
| 1685 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
||
| 1686 | |||
| 1687 | /****************** Bit definition for ADC_SMPR0 register *******************/ |
||
| 1688 | #define ADC_SMPR0_SMP30_Pos (0U) |
||
| 1689 | #define ADC_SMPR0_SMP30_Msk (0x7U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */ |
||
| 1690 | #define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */ |
||
| 1691 | #define ADC_SMPR0_SMP30_0 (0x1U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */ |
||
| 1692 | #define ADC_SMPR0_SMP30_1 (0x2U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */ |
||
| 1693 | #define ADC_SMPR0_SMP30_2 (0x4U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */ |
||
| 1694 | |||
| 1695 | #define ADC_SMPR0_SMP31_Pos (3U) |
||
| 1696 | #define ADC_SMPR0_SMP31_Msk (0x7U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */ |
||
| 1697 | #define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */ |
||
| 1698 | #define ADC_SMPR0_SMP31_0 (0x1U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */ |
||
| 1699 | #define ADC_SMPR0_SMP31_1 (0x2U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */ |
||
| 1700 | #define ADC_SMPR0_SMP31_2 (0x4U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */ |
||
| 1701 | |||
| 1702 | /******************* Bit definition for ADC_CSR register ********************/ |
||
| 1703 | #define ADC_CSR_AWD1_Pos (0U) |
||
| 1704 | #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ |
||
| 1705 | #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ |
||
| 1706 | #define ADC_CSR_EOCS1_Pos (1U) |
||
| 1707 | #define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ |
||
| 1708 | #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ |
||
| 1709 | #define ADC_CSR_JEOS1_Pos (2U) |
||
| 1710 | #define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ |
||
| 1711 | #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ |
||
| 1712 | #define ADC_CSR_JSTRT1_Pos (3U) |
||
| 1713 | #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ |
||
| 1714 | #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ |
||
| 1715 | #define ADC_CSR_STRT1_Pos (4U) |
||
| 1716 | #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ |
||
| 1717 | #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ |
||
| 1718 | #define ADC_CSR_OVR1_Pos (5U) |
||
| 1719 | #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ |
||
| 1720 | #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ |
||
| 1721 | #define ADC_CSR_ADONS1_Pos (6U) |
||
| 1722 | #define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ |
||
| 1723 | #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ |
||
| 1724 | |||
| 1725 | /* Legacy defines */ |
||
| 1726 | #define ADC_CSR_EOC1 (ADC_CSR_EOCS1) |
||
| 1727 | #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) |
||
| 1728 | |||
| 1729 | /******************* Bit definition for ADC_CCR register ********************/ |
||
| 1730 | #define ADC_CCR_ADCPRE_Pos (16U) |
||
| 1731 | #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ |
||
| 1732 | #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ |
||
| 1733 | #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ |
||
| 1734 | #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ |
||
| 1735 | #define ADC_CCR_TSVREFE_Pos (23U) |
||
| 1736 | #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ |
||
| 1737 | #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ |
||
| 1738 | |||
| 1739 | /******************************************************************************/ |
||
| 1740 | /* */ |
||
| 1741 | /* Advanced Encryption Standard (AES) */ |
||
| 1742 | /* */ |
||
| 1743 | /******************************************************************************/ |
||
| 1744 | /******************* Bit definition for AES_CR register *********************/ |
||
| 1745 | #define AES_CR_EN_Pos (0U) |
||
| 1746 | #define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */ |
||
| 1747 | #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ |
||
| 1748 | #define AES_CR_DATATYPE_Pos (1U) |
||
| 1749 | #define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ |
||
| 1750 | #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ |
||
| 1751 | #define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ |
||
| 1752 | #define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ |
||
| 1753 | |||
| 1754 | #define AES_CR_MODE_Pos (3U) |
||
| 1755 | #define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */ |
||
| 1756 | #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ |
||
| 1757 | #define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ |
||
| 1758 | #define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ |
||
| 1759 | |||
| 1760 | #define AES_CR_CHMOD_Pos (5U) |
||
| 1761 | #define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) /*!< 0x00000060 */ |
||
| 1762 | #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ |
||
| 1763 | #define AES_CR_CHMOD_0 (0x1U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ |
||
| 1764 | #define AES_CR_CHMOD_1 (0x2U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ |
||
| 1765 | |||
| 1766 | #define AES_CR_CCFC_Pos (7U) |
||
| 1767 | #define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */ |
||
| 1768 | #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ |
||
| 1769 | #define AES_CR_ERRC_Pos (8U) |
||
| 1770 | #define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */ |
||
| 1771 | #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ |
||
| 1772 | #define AES_CR_CCIE_Pos (9U) |
||
| 1773 | #define AES_CR_CCIE_Msk (0x1U << AES_CR_CCIE_Pos) /*!< 0x00000200 */ |
||
| 1774 | #define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */ |
||
| 1775 | #define AES_CR_ERRIE_Pos (10U) |
||
| 1776 | #define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ |
||
| 1777 | #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
||
| 1778 | #define AES_CR_DMAINEN_Pos (11U) |
||
| 1779 | #define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ |
||
| 1780 | #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */ |
||
| 1781 | #define AES_CR_DMAOUTEN_Pos (12U) |
||
| 1782 | #define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ |
||
| 1783 | #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */ |
||
| 1784 | |||
| 1785 | /******************* Bit definition for AES_SR register *********************/ |
||
| 1786 | #define AES_SR_CCF_Pos (0U) |
||
| 1787 | #define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */ |
||
| 1788 | #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ |
||
| 1789 | #define AES_SR_RDERR_Pos (1U) |
||
| 1790 | #define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */ |
||
| 1791 | #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ |
||
| 1792 | #define AES_SR_WRERR_Pos (2U) |
||
| 1793 | #define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */ |
||
| 1794 | #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ |
||
| 1795 | |||
| 1796 | /******************* Bit definition for AES_DINR register *******************/ |
||
| 1797 | #define AES_DINR_Pos (0U) |
||
| 1798 | #define AES_DINR_Msk (0xFFFFU << AES_DINR_Pos) /*!< 0x0000FFFF */ |
||
| 1799 | #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ |
||
| 1800 | |||
| 1801 | /******************* Bit definition for AES_DOUTR register ******************/ |
||
| 1802 | #define AES_DOUTR_Pos (0U) |
||
| 1803 | #define AES_DOUTR_Msk (0xFFFFU << AES_DOUTR_Pos) /*!< 0x0000FFFF */ |
||
| 1804 | #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ |
||
| 1805 | |||
| 1806 | /******************* Bit definition for AES_KEYR0 register ******************/ |
||
| 1807 | #define AES_KEYR0_Pos (0U) |
||
| 1808 | #define AES_KEYR0_Msk (0xFFFFU << AES_KEYR0_Pos) /*!< 0x0000FFFF */ |
||
| 1809 | #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ |
||
| 1810 | |||
| 1811 | /******************* Bit definition for AES_KEYR1 register ******************/ |
||
| 1812 | #define AES_KEYR1_Pos (0U) |
||
| 1813 | #define AES_KEYR1_Msk (0xFFFFU << AES_KEYR1_Pos) /*!< 0x0000FFFF */ |
||
| 1814 | #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ |
||
| 1815 | |||
| 1816 | /******************* Bit definition for AES_KEYR2 register ******************/ |
||
| 1817 | #define AES_KEYR2_Pos (0U) |
||
| 1818 | #define AES_KEYR2_Msk (0xFFFFU << AES_KEYR2_Pos) /*!< 0x0000FFFF */ |
||
| 1819 | #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ |
||
| 1820 | |||
| 1821 | /******************* Bit definition for AES_KEYR3 register ******************/ |
||
| 1822 | #define AES_KEYR3_Pos (0U) |
||
| 1823 | #define AES_KEYR3_Msk (0xFFFFU << AES_KEYR3_Pos) /*!< 0x0000FFFF */ |
||
| 1824 | #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ |
||
| 1825 | |||
| 1826 | /******************* Bit definition for AES_IVR0 register *******************/ |
||
| 1827 | #define AES_IVR0_Pos (0U) |
||
| 1828 | #define AES_IVR0_Msk (0xFFFFU << AES_IVR0_Pos) /*!< 0x0000FFFF */ |
||
| 1829 | #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ |
||
| 1830 | |||
| 1831 | /******************* Bit definition for AES_IVR1 register *******************/ |
||
| 1832 | #define AES_IVR1_Pos (0U) |
||
| 1833 | #define AES_IVR1_Msk (0xFFFFU << AES_IVR1_Pos) /*!< 0x0000FFFF */ |
||
| 1834 | #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ |
||
| 1835 | |||
| 1836 | /******************* Bit definition for AES_IVR2 register *******************/ |
||
| 1837 | #define AES_IVR2_Pos (0U) |
||
| 1838 | #define AES_IVR2_Msk (0xFFFFU << AES_IVR2_Pos) /*!< 0x0000FFFF */ |
||
| 1839 | #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ |
||
| 1840 | |||
| 1841 | /******************* Bit definition for AES_IVR3 register *******************/ |
||
| 1842 | #define AES_IVR3_Pos (0U) |
||
| 1843 | #define AES_IVR3_Msk (0xFFFFU << AES_IVR3_Pos) /*!< 0x0000FFFF */ |
||
| 1844 | #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ |
||
| 1845 | |||
| 1846 | /******************************************************************************/ |
||
| 1847 | /* */ |
||
| 1848 | /* Analog Comparators (COMP) */ |
||
| 1849 | /* */ |
||
| 1850 | /******************************************************************************/ |
||
| 1851 | |||
| 1852 | /****************** Bit definition for COMP_CSR register ********************/ |
||
| 1853 | #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ |
||
| 1854 | #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ |
||
| 1855 | #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ |
||
| 1856 | #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ |
||
| 1857 | #define COMP_CSR_CMP1EN_Pos (4U) |
||
| 1858 | #define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ |
||
| 1859 | #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ |
||
| 1860 | #define COMP_CSR_CMP1OUT_Pos (7U) |
||
| 1861 | #define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ |
||
| 1862 | #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ |
||
| 1863 | #define COMP_CSR_SPEED_Pos (12U) |
||
| 1864 | #define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ |
||
| 1865 | #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ |
||
| 1866 | #define COMP_CSR_CMP2OUT_Pos (13U) |
||
| 1867 | #define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ |
||
| 1868 | #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ |
||
| 1869 | |||
| 1870 | #define COMP_CSR_WNDWE_Pos (17U) |
||
| 1871 | #define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ |
||
| 1872 | #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ |
||
| 1873 | |||
| 1874 | #define COMP_CSR_INSEL_Pos (18U) |
||
| 1875 | #define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ |
||
| 1876 | #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ |
||
| 1877 | #define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ |
||
| 1878 | #define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ |
||
| 1879 | #define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ |
||
| 1880 | #define COMP_CSR_OUTSEL_Pos (21U) |
||
| 1881 | #define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ |
||
| 1882 | #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ |
||
| 1883 | #define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ |
||
| 1884 | #define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ |
||
| 1885 | #define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ |
||
| 1886 | |||
| 1887 | /* Bits present in COMP register but not related to comparator */ |
||
| 1888 | /* (or partially related to comparator, in addition to other peripherals) */ |
||
| 1889 | #define COMP_CSR_SW1_Pos (5U) |
||
| 1890 | #define COMP_CSR_SW1_Msk (0x1U << COMP_CSR_SW1_Pos) /*!< 0x00000020 */ |
||
| 1891 | #define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */ |
||
| 1892 | #define COMP_CSR_VREFOUTEN_Pos (16U) |
||
| 1893 | #define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ |
||
| 1894 | #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ |
||
| 1895 | |||
| 1896 | #define COMP_CSR_FCH3_Pos (26U) |
||
| 1897 | #define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */ |
||
| 1898 | #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */ |
||
| 1899 | #define COMP_CSR_FCH8_Pos (27U) |
||
| 1900 | #define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */ |
||
| 1901 | #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */ |
||
| 1902 | #define COMP_CSR_RCH13_Pos (28U) |
||
| 1903 | #define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */ |
||
| 1904 | #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */ |
||
| 1905 | |||
| 1906 | #define COMP_CSR_CAIE_Pos (29U) |
||
| 1907 | #define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */ |
||
| 1908 | #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */ |
||
| 1909 | #define COMP_CSR_CAIF_Pos (30U) |
||
| 1910 | #define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */ |
||
| 1911 | #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */ |
||
| 1912 | #define COMP_CSR_TSUSP_Pos (31U) |
||
| 1913 | #define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */ |
||
| 1914 | #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */ |
||
| 1915 | |||
| 1916 | /******************************************************************************/ |
||
| 1917 | /* */ |
||
| 1918 | /* Operational Amplifier (OPAMP) */ |
||
| 1919 | /* */ |
||
| 1920 | /******************************************************************************/ |
||
| 1921 | /******************* Bit definition for OPAMP_CSR register ******************/ |
||
| 1922 | #define OPAMP_CSR_OPA1PD_Pos (0U) |
||
| 1923 | #define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */ |
||
| 1924 | #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */ |
||
| 1925 | #define OPAMP_CSR_S3SEL1_Pos (1U) |
||
| 1926 | #define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */ |
||
| 1927 | #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */ |
||
| 1928 | #define OPAMP_CSR_S4SEL1_Pos (2U) |
||
| 1929 | #define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */ |
||
| 1930 | #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */ |
||
| 1931 | #define OPAMP_CSR_S5SEL1_Pos (3U) |
||
| 1932 | #define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */ |
||
| 1933 | #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */ |
||
| 1934 | #define OPAMP_CSR_S6SEL1_Pos (4U) |
||
| 1935 | #define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */ |
||
| 1936 | #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */ |
||
| 1937 | #define OPAMP_CSR_OPA1CAL_L_Pos (5U) |
||
| 1938 | #define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */ |
||
| 1939 | #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */ |
||
| 1940 | #define OPAMP_CSR_OPA1CAL_H_Pos (6U) |
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| 1941 | #define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */ |
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| 1942 | #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */ |
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| 1943 | #define OPAMP_CSR_OPA1LPM_Pos (7U) |
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| 1944 | #define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */ |
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| 1945 | #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */ |
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| 1946 | #define OPAMP_CSR_OPA2PD_Pos (8U) |
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| 1947 | #define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */ |
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| 1948 | #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */ |
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| 1949 | #define OPAMP_CSR_S3SEL2_Pos (9U) |
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| 1950 | #define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */ |
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| 1951 | #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */ |
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| 1952 | #define OPAMP_CSR_S4SEL2_Pos (10U) |
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| 1953 | #define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */ |
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| 1954 | #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */ |
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| 1955 | #define OPAMP_CSR_S5SEL2_Pos (11U) |
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| 1956 | #define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */ |
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| 1957 | #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */ |
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| 1958 | #define OPAMP_CSR_S6SEL2_Pos (12U) |
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| 1959 | #define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */ |
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| 1960 | #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */ |
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| 1961 | #define OPAMP_CSR_OPA2CAL_L_Pos (13U) |
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| 1962 | #define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */ |
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| 1963 | #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */ |
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| 1964 | #define OPAMP_CSR_OPA2CAL_H_Pos (14U) |
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| 1965 | #define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */ |
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| 1966 | #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */ |
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| 1967 | #define OPAMP_CSR_OPA2LPM_Pos (15U) |
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| 1968 | #define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */ |
||
| 1969 | #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */ |
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| 1970 | #define OPAMP_CSR_OPA3PD_Pos (16U) |
||
| 1971 | #define OPAMP_CSR_OPA3PD_Msk (0x1U << OPAMP_CSR_OPA3PD_Pos) /*!< 0x00010000 */ |
||
| 1972 | #define OPAMP_CSR_OPA3PD OPAMP_CSR_OPA3PD_Msk /*!< OPAMP3 disable */ |
||
| 1973 | #define OPAMP_CSR_S3SEL3_Pos (17U) |
||
| 1974 | #define OPAMP_CSR_S3SEL3_Msk (0x1U << OPAMP_CSR_S3SEL3_Pos) /*!< 0x00020000 */ |
||
| 1975 | #define OPAMP_CSR_S3SEL3 OPAMP_CSR_S3SEL3_Msk /*!< Switch 3 for OPAMP3 Enable */ |
||
| 1976 | #define OPAMP_CSR_S4SEL3_Pos (18U) |
||
| 1977 | #define OPAMP_CSR_S4SEL3_Msk (0x1U << OPAMP_CSR_S4SEL3_Pos) /*!< 0x00040000 */ |
||
| 1978 | #define OPAMP_CSR_S4SEL3 OPAMP_CSR_S4SEL3_Msk /*!< Switch 4 for OPAMP3 Enable */ |
||
| 1979 | #define OPAMP_CSR_S5SEL3_Pos (19U) |
||
| 1980 | #define OPAMP_CSR_S5SEL3_Msk (0x1U << OPAMP_CSR_S5SEL3_Pos) /*!< 0x00080000 */ |
||
| 1981 | #define OPAMP_CSR_S5SEL3 OPAMP_CSR_S5SEL3_Msk /*!< Switch 5 for OPAMP3 Enable */ |
||
| 1982 | #define OPAMP_CSR_S6SEL3_Pos (20U) |
||
| 1983 | #define OPAMP_CSR_S6SEL3_Msk (0x1U << OPAMP_CSR_S6SEL3_Pos) /*!< 0x00100000 */ |
||
| 1984 | #define OPAMP_CSR_S6SEL3 OPAMP_CSR_S6SEL3_Msk /*!< Switch 6 for OPAMP3 Enable */ |
||
| 1985 | #define OPAMP_CSR_OPA3CAL_L_Pos (21U) |
||
| 1986 | #define OPAMP_CSR_OPA3CAL_L_Msk (0x1U << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */ |
||
| 1987 | #define OPAMP_CSR_OPA3CAL_L OPAMP_CSR_OPA3CAL_L_Msk /*!< OPAMP3 Offset calibration for P differential pair */ |
||
| 1988 | #define OPAMP_CSR_OPA3CAL_H_Pos (22U) |
||
| 1989 | #define OPAMP_CSR_OPA3CAL_H_Msk (0x1U << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */ |
||
| 1990 | #define OPAMP_CSR_OPA3CAL_H OPAMP_CSR_OPA3CAL_H_Msk /*!< OPAMP3 Offset calibration for N differential pair */ |
||
| 1991 | #define OPAMP_CSR_OPA3LPM_Pos (23U) |
||
| 1992 | #define OPAMP_CSR_OPA3LPM_Msk (0x1U << OPAMP_CSR_OPA3LPM_Pos) /*!< 0x00800000 */ |
||
| 1993 | #define OPAMP_CSR_OPA3LPM OPAMP_CSR_OPA3LPM_Msk /*!< OPAMP3 Low power enable */ |
||
| 1994 | #define OPAMP_CSR_ANAWSEL1_Pos (24U) |
||
| 1995 | #define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */ |
||
| 1996 | #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */ |
||
| 1997 | #define OPAMP_CSR_ANAWSEL2_Pos (25U) |
||
| 1998 | #define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */ |
||
| 1999 | #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */ |
||
| 2000 | #define OPAMP_CSR_ANAWSEL3_Pos (26U) |
||
| 2001 | #define OPAMP_CSR_ANAWSEL3_Msk (0x1U << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */ |
||
| 2002 | #define OPAMP_CSR_ANAWSEL3 OPAMP_CSR_ANAWSEL3_Msk /*!< Switch ANA Enable for OPAMP3 */ |
||
| 2003 | #define OPAMP_CSR_S7SEL2_Pos (27U) |
||
| 2004 | #define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */ |
||
| 2005 | #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */ |
||
| 2006 | #define OPAMP_CSR_AOP_RANGE_Pos (28U) |
||
| 2007 | #define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */ |
||
| 2008 | #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ |
||
| 2009 | #define OPAMP_CSR_OPA1CALOUT_Pos (29U) |
||
| 2010 | #define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */ |
||
| 2011 | #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */ |
||
| 2012 | #define OPAMP_CSR_OPA2CALOUT_Pos (30U) |
||
| 2013 | #define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */ |
||
| 2014 | #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */ |
||
| 2015 | #define OPAMP_CSR_OPA3CALOUT_Pos (31U) |
||
| 2016 | #define OPAMP_CSR_OPA3CALOUT_Msk (0x1U << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */ |
||
| 2017 | #define OPAMP_CSR_OPA3CALOUT OPAMP_CSR_OPA3CALOUT_Msk /*!< OPAMP3 calibration output */ |
||
| 2018 | |||
| 2019 | /******************* Bit definition for OPAMP_OTR register ******************/ |
||
| 2020 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U) |
||
| 2021 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */ |
||
| 2022 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ |
||
| 2023 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U) |
||
| 2024 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */ |
||
| 2025 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ |
||
| 2026 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U) |
||
| 2027 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */ |
||
| 2028 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ |
||
| 2029 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U) |
||
| 2030 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */ |
||
| 2031 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ |
||
| 2032 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U) |
||
| 2033 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */ |
||
| 2034 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */ |
||
| 2035 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U) |
||
| 2036 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */ |
||
| 2037 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */ |
||
| 2038 | #define OPAMP_OTR_OT_USER_Pos (31U) |
||
| 2039 | #define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */ |
||
| 2040 | #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */ |
||
| 2041 | |||
| 2042 | /******************* Bit definition for OPAMP_LPOTR register ****************/ |
||
| 2043 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U) |
||
| 2044 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */ |
||
| 2045 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ |
||
| 2046 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U) |
||
| 2047 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */ |
||
| 2048 | #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ |
||
| 2049 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U) |
||
| 2050 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */ |
||
| 2051 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ |
||
| 2052 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U) |
||
| 2053 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */ |
||
| 2054 | #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ |
||
| 2055 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U) |
||
| 2056 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */ |
||
| 2057 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */ |
||
| 2058 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U) |
||
| 2059 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */ |
||
| 2060 | #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */ |
||
| 2061 | |||
| 2062 | /******************************************************************************/ |
||
| 2063 | /* */ |
||
| 2064 | /* CRC calculation unit (CRC) */ |
||
| 2065 | /* */ |
||
| 2066 | /******************************************************************************/ |
||
| 2067 | |||
| 2068 | /******************* Bit definition for CRC_DR register *********************/ |
||
| 2069 | #define CRC_DR_DR_Pos (0U) |
||
| 2070 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
||
| 2071 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
||
| 2072 | |||
| 2073 | /******************* Bit definition for CRC_IDR register ********************/ |
||
| 2074 | #define CRC_IDR_IDR_Pos (0U) |
||
| 2075 | #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
||
| 2076 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
||
| 2077 | |||
| 2078 | /******************** Bit definition for CRC_CR register ********************/ |
||
| 2079 | #define CRC_CR_RESET_Pos (0U) |
||
| 2080 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
||
| 2081 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
||
| 2082 | |||
| 2083 | /******************************************************************************/ |
||
| 2084 | /* */ |
||
| 2085 | /* Digital to Analog Converter (DAC) */ |
||
| 2086 | /* */ |
||
| 2087 | /******************************************************************************/ |
||
| 2088 | |||
| 2089 | /******************** Bit definition for DAC_CR register ********************/ |
||
| 2090 | #define DAC_CR_EN1_Pos (0U) |
||
| 2091 | #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
||
| 2092 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ |
||
| 2093 | #define DAC_CR_BOFF1_Pos (1U) |
||
| 2094 | #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ |
||
| 2095 | #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ |
||
| 2096 | #define DAC_CR_TEN1_Pos (2U) |
||
| 2097 | #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ |
||
| 2098 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ |
||
| 2099 | |||
| 2100 | #define DAC_CR_TSEL1_Pos (3U) |
||
| 2101 | #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ |
||
| 2102 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
||
| 2103 | #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
||
| 2104 | #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
||
| 2105 | #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
||
| 2106 | |||
| 2107 | #define DAC_CR_WAVE1_Pos (6U) |
||
| 2108 | #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
||
| 2109 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
||
| 2110 | #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
||
| 2111 | #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
||
| 2112 | |||
| 2113 | #define DAC_CR_MAMP1_Pos (8U) |
||
| 2114 | #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
||
| 2115 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
||
| 2116 | #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
||
| 2117 | #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
||
| 2118 | #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
||
| 2119 | #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
||
| 2120 | |||
| 2121 | #define DAC_CR_DMAEN1_Pos (12U) |
||
| 2122 | #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
||
| 2123 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ |
||
| 2124 | #define DAC_CR_DMAUDRIE1_Pos (13U) |
||
| 2125 | #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ |
||
| 2126 | #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */ |
||
| 2127 | #define DAC_CR_EN2_Pos (16U) |
||
| 2128 | #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
||
| 2129 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ |
||
| 2130 | #define DAC_CR_BOFF2_Pos (17U) |
||
| 2131 | #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ |
||
| 2132 | #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ |
||
| 2133 | #define DAC_CR_TEN2_Pos (18U) |
||
| 2134 | #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ |
||
| 2135 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ |
||
| 2136 | |||
| 2137 | #define DAC_CR_TSEL2_Pos (19U) |
||
| 2138 | #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ |
||
| 2139 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
||
| 2140 | #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
||
| 2141 | #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
||
| 2142 | #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
||
| 2143 | |||
| 2144 | #define DAC_CR_WAVE2_Pos (22U) |
||
| 2145 | #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
||
| 2146 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
||
| 2147 | #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
||
| 2148 | #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
||
| 2149 | |||
| 2150 | #define DAC_CR_MAMP2_Pos (24U) |
||
| 2151 | #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
||
| 2152 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
||
| 2153 | #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
||
| 2154 | #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
||
| 2155 | #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
||
| 2156 | #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
||
| 2157 | |||
| 2158 | #define DAC_CR_DMAEN2_Pos (28U) |
||
| 2159 | #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
||
| 2160 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ |
||
| 2161 | #define DAC_CR_DMAUDRIE2_Pos (29U) |
||
| 2162 | #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ |
||
| 2163 | #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */ |
||
| 2164 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
||
| 2165 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
||
| 2166 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
||
| 2167 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ |
||
| 2168 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
||
| 2169 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
||
| 2170 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ |
||
| 2171 | |||
| 2172 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
||
| 2173 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
||
| 2174 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
||
| 2175 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ |
||
| 2176 | |||
| 2177 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
||
| 2178 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
||
| 2179 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
||
| 2180 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ |
||
| 2181 | |||
| 2182 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
||
| 2183 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
||
| 2184 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
||
| 2185 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ |
||
| 2186 | |||
| 2187 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
||
| 2188 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
||
| 2189 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
||
| 2190 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ |
||
| 2191 | |||
| 2192 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
||
| 2193 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
||
| 2194 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
||
| 2195 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ |
||
| 2196 | |||
| 2197 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
||
| 2198 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
||
| 2199 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
||
| 2200 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ |
||
| 2201 | |||
| 2202 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
||
| 2203 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
||
| 2204 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
||
| 2205 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ |
||
| 2206 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
||
| 2207 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
||
| 2208 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ |
||
| 2209 | |||
| 2210 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
||
| 2211 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
||
| 2212 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
||
| 2213 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ |
||
| 2214 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
||
| 2215 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
||
| 2216 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ |
||
| 2217 | |||
| 2218 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
||
| 2219 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
||
| 2220 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
||
| 2221 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ |
||
| 2222 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
||
| 2223 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
||
| 2224 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ |
||
| 2225 | |||
| 2226 | /******************* Bit definition for DAC_DOR1 register *******************/ |
||
| 2227 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
||
| 2228 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
||
| 2229 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ |
||
| 2230 | |||
| 2231 | /******************* Bit definition for DAC_DOR2 register *******************/ |
||
| 2232 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
||
| 2233 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
||
| 2234 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ |
||
| 2235 | |||
| 2236 | /******************** Bit definition for DAC_SR register ********************/ |
||
| 2237 | #define DAC_SR_DMAUDR1_Pos (13U) |
||
| 2238 | #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ |
||
| 2239 | #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ |
||
| 2240 | #define DAC_SR_DMAUDR2_Pos (29U) |
||
| 2241 | #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ |
||
| 2242 | #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ |
||
| 2243 | |||
| 2244 | /******************************************************************************/ |
||
| 2245 | /* */ |
||
| 2246 | /* Debug MCU (DBGMCU) */ |
||
| 2247 | /* */ |
||
| 2248 | /******************************************************************************/ |
||
| 2249 | |||
| 2250 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
||
| 2251 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
||
| 2252 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
||
| 2253 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
||
| 2254 | |||
| 2255 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
||
| 2256 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
||
| 2257 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
||
| 2258 | #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
||
| 2259 | #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
||
| 2260 | #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
||
| 2261 | #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
||
| 2262 | #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
||
| 2263 | #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
||
| 2264 | #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
||
| 2265 | #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
||
| 2266 | #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
||
| 2267 | #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
||
| 2268 | #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
||
| 2269 | #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
||
| 2270 | #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
||
| 2271 | #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
||
| 2272 | #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
||
| 2273 | #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
||
| 2274 | |||
| 2275 | /****************** Bit definition for DBGMCU_CR register *******************/ |
||
| 2276 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
||
| 2277 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
||
| 2278 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ |
||
| 2279 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
||
| 2280 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
||
| 2281 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
||
| 2282 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
||
| 2283 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
||
| 2284 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
||
| 2285 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
||
| 2286 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
||
| 2287 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ |
||
| 2288 | |||
| 2289 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
||
| 2290 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
||
| 2291 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
||
| 2292 | #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
||
| 2293 | #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
||
| 2294 | |||
| 2295 | /****************** Bit definition for DBGMCU_APB1_FZ register **************/ |
||
| 2296 | |||
| 2297 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) |
||
| 2298 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ |
||
| 2299 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
||
| 2300 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) |
||
| 2301 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ |
||
| 2302 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ |
||
| 2303 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) |
||
| 2304 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ |
||
| 2305 | #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ |
||
| 2306 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) |
||
| 2307 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ |
||
| 2308 | #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ |
||
| 2309 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) |
||
| 2310 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ |
||
| 2311 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ |
||
| 2312 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) |
||
| 2313 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ |
||
| 2314 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ |
||
| 2315 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) |
||
| 2316 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ |
||
| 2317 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */ |
||
| 2318 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) |
||
| 2319 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ |
||
| 2320 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
||
| 2321 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) |
||
| 2322 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ |
||
| 2323 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
||
| 2324 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) |
||
| 2325 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ |
||
| 2326 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 2327 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) |
||
| 2328 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ |
||
| 2329 | #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
||
| 2330 | |||
| 2331 | /****************** Bit definition for DBGMCU_APB2_FZ register **************/ |
||
| 2332 | |||
| 2333 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U) |
||
| 2334 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */ |
||
| 2335 | #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */ |
||
| 2336 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U) |
||
| 2337 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */ |
||
| 2338 | #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */ |
||
| 2339 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U) |
||
| 2340 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */ |
||
| 2341 | #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */ |
||
| 2342 | |||
| 2343 | /******************************************************************************/ |
||
| 2344 | /* */ |
||
| 2345 | /* DMA Controller (DMA) */ |
||
| 2346 | /* */ |
||
| 2347 | /******************************************************************************/ |
||
| 2348 | |||
| 2349 | /******************* Bit definition for DMA_ISR register ********************/ |
||
| 2350 | #define DMA_ISR_GIF1_Pos (0U) |
||
| 2351 | #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
||
| 2352 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
||
| 2353 | #define DMA_ISR_TCIF1_Pos (1U) |
||
| 2354 | #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
||
| 2355 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
||
| 2356 | #define DMA_ISR_HTIF1_Pos (2U) |
||
| 2357 | #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
||
| 2358 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
||
| 2359 | #define DMA_ISR_TEIF1_Pos (3U) |
||
| 2360 | #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
||
| 2361 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
||
| 2362 | #define DMA_ISR_GIF2_Pos (4U) |
||
| 2363 | #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
||
| 2364 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
||
| 2365 | #define DMA_ISR_TCIF2_Pos (5U) |
||
| 2366 | #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
||
| 2367 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
||
| 2368 | #define DMA_ISR_HTIF2_Pos (6U) |
||
| 2369 | #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
||
| 2370 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
||
| 2371 | #define DMA_ISR_TEIF2_Pos (7U) |
||
| 2372 | #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
||
| 2373 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
||
| 2374 | #define DMA_ISR_GIF3_Pos (8U) |
||
| 2375 | #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
||
| 2376 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
||
| 2377 | #define DMA_ISR_TCIF3_Pos (9U) |
||
| 2378 | #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
||
| 2379 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
||
| 2380 | #define DMA_ISR_HTIF3_Pos (10U) |
||
| 2381 | #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
||
| 2382 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
||
| 2383 | #define DMA_ISR_TEIF3_Pos (11U) |
||
| 2384 | #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
||
| 2385 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
||
| 2386 | #define DMA_ISR_GIF4_Pos (12U) |
||
| 2387 | #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
||
| 2388 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
||
| 2389 | #define DMA_ISR_TCIF4_Pos (13U) |
||
| 2390 | #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
||
| 2391 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
||
| 2392 | #define DMA_ISR_HTIF4_Pos (14U) |
||
| 2393 | #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
||
| 2394 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
||
| 2395 | #define DMA_ISR_TEIF4_Pos (15U) |
||
| 2396 | #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
||
| 2397 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
||
| 2398 | #define DMA_ISR_GIF5_Pos (16U) |
||
| 2399 | #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
||
| 2400 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
||
| 2401 | #define DMA_ISR_TCIF5_Pos (17U) |
||
| 2402 | #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
||
| 2403 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
||
| 2404 | #define DMA_ISR_HTIF5_Pos (18U) |
||
| 2405 | #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
||
| 2406 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
||
| 2407 | #define DMA_ISR_TEIF5_Pos (19U) |
||
| 2408 | #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
||
| 2409 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
||
| 2410 | #define DMA_ISR_GIF6_Pos (20U) |
||
| 2411 | #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
||
| 2412 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
||
| 2413 | #define DMA_ISR_TCIF6_Pos (21U) |
||
| 2414 | #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
||
| 2415 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
||
| 2416 | #define DMA_ISR_HTIF6_Pos (22U) |
||
| 2417 | #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
||
| 2418 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
||
| 2419 | #define DMA_ISR_TEIF6_Pos (23U) |
||
| 2420 | #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
||
| 2421 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
||
| 2422 | #define DMA_ISR_GIF7_Pos (24U) |
||
| 2423 | #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
||
| 2424 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
||
| 2425 | #define DMA_ISR_TCIF7_Pos (25U) |
||
| 2426 | #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
||
| 2427 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
||
| 2428 | #define DMA_ISR_HTIF7_Pos (26U) |
||
| 2429 | #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
||
| 2430 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
||
| 2431 | #define DMA_ISR_TEIF7_Pos (27U) |
||
| 2432 | #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
||
| 2433 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
||
| 2434 | |||
| 2435 | /******************* Bit definition for DMA_IFCR register *******************/ |
||
| 2436 | #define DMA_IFCR_CGIF1_Pos (0U) |
||
| 2437 | #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
||
| 2438 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
||
| 2439 | #define DMA_IFCR_CTCIF1_Pos (1U) |
||
| 2440 | #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
||
| 2441 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
||
| 2442 | #define DMA_IFCR_CHTIF1_Pos (2U) |
||
| 2443 | #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
||
| 2444 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
||
| 2445 | #define DMA_IFCR_CTEIF1_Pos (3U) |
||
| 2446 | #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
||
| 2447 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
||
| 2448 | #define DMA_IFCR_CGIF2_Pos (4U) |
||
| 2449 | #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
||
| 2450 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
||
| 2451 | #define DMA_IFCR_CTCIF2_Pos (5U) |
||
| 2452 | #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
||
| 2453 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
||
| 2454 | #define DMA_IFCR_CHTIF2_Pos (6U) |
||
| 2455 | #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
||
| 2456 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
||
| 2457 | #define DMA_IFCR_CTEIF2_Pos (7U) |
||
| 2458 | #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
||
| 2459 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
||
| 2460 | #define DMA_IFCR_CGIF3_Pos (8U) |
||
| 2461 | #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
||
| 2462 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
||
| 2463 | #define DMA_IFCR_CTCIF3_Pos (9U) |
||
| 2464 | #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
||
| 2465 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
||
| 2466 | #define DMA_IFCR_CHTIF3_Pos (10U) |
||
| 2467 | #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
||
| 2468 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
||
| 2469 | #define DMA_IFCR_CTEIF3_Pos (11U) |
||
| 2470 | #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
||
| 2471 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
||
| 2472 | #define DMA_IFCR_CGIF4_Pos (12U) |
||
| 2473 | #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
||
| 2474 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
||
| 2475 | #define DMA_IFCR_CTCIF4_Pos (13U) |
||
| 2476 | #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
||
| 2477 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
||
| 2478 | #define DMA_IFCR_CHTIF4_Pos (14U) |
||
| 2479 | #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
||
| 2480 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
||
| 2481 | #define DMA_IFCR_CTEIF4_Pos (15U) |
||
| 2482 | #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
||
| 2483 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
||
| 2484 | #define DMA_IFCR_CGIF5_Pos (16U) |
||
| 2485 | #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
||
| 2486 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
||
| 2487 | #define DMA_IFCR_CTCIF5_Pos (17U) |
||
| 2488 | #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
||
| 2489 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
||
| 2490 | #define DMA_IFCR_CHTIF5_Pos (18U) |
||
| 2491 | #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
||
| 2492 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
||
| 2493 | #define DMA_IFCR_CTEIF5_Pos (19U) |
||
| 2494 | #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
||
| 2495 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
||
| 2496 | #define DMA_IFCR_CGIF6_Pos (20U) |
||
| 2497 | #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
||
| 2498 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
||
| 2499 | #define DMA_IFCR_CTCIF6_Pos (21U) |
||
| 2500 | #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
||
| 2501 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
||
| 2502 | #define DMA_IFCR_CHTIF6_Pos (22U) |
||
| 2503 | #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
||
| 2504 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
||
| 2505 | #define DMA_IFCR_CTEIF6_Pos (23U) |
||
| 2506 | #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
||
| 2507 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
||
| 2508 | #define DMA_IFCR_CGIF7_Pos (24U) |
||
| 2509 | #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
||
| 2510 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
||
| 2511 | #define DMA_IFCR_CTCIF7_Pos (25U) |
||
| 2512 | #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
||
| 2513 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
||
| 2514 | #define DMA_IFCR_CHTIF7_Pos (26U) |
||
| 2515 | #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
||
| 2516 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
||
| 2517 | #define DMA_IFCR_CTEIF7_Pos (27U) |
||
| 2518 | #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
||
| 2519 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
||
| 2520 | |||
| 2521 | /******************* Bit definition for DMA_CCR register *******************/ |
||
| 2522 | #define DMA_CCR_EN_Pos (0U) |
||
| 2523 | #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
||
| 2524 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/ |
||
| 2525 | #define DMA_CCR_TCIE_Pos (1U) |
||
| 2526 | #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
||
| 2527 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
||
| 2528 | #define DMA_CCR_HTIE_Pos (2U) |
||
| 2529 | #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
||
| 2530 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
||
| 2531 | #define DMA_CCR_TEIE_Pos (3U) |
||
| 2532 | #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
||
| 2533 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
||
| 2534 | #define DMA_CCR_DIR_Pos (4U) |
||
| 2535 | #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
||
| 2536 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
||
| 2537 | #define DMA_CCR_CIRC_Pos (5U) |
||
| 2538 | #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
||
| 2539 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
||
| 2540 | #define DMA_CCR_PINC_Pos (6U) |
||
| 2541 | #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
||
| 2542 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
||
| 2543 | #define DMA_CCR_MINC_Pos (7U) |
||
| 2544 | #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
||
| 2545 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
||
| 2546 | |||
| 2547 | #define DMA_CCR_PSIZE_Pos (8U) |
||
| 2548 | #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
||
| 2549 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
||
| 2550 | #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
||
| 2551 | #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
||
| 2552 | |||
| 2553 | #define DMA_CCR_MSIZE_Pos (10U) |
||
| 2554 | #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
||
| 2555 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
||
| 2556 | #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
||
| 2557 | #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
||
| 2558 | |||
| 2559 | #define DMA_CCR_PL_Pos (12U) |
||
| 2560 | #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
||
| 2561 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ |
||
| 2562 | #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
||
| 2563 | #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
||
| 2564 | |||
| 2565 | #define DMA_CCR_MEM2MEM_Pos (14U) |
||
| 2566 | #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
||
| 2567 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
||
| 2568 | |||
| 2569 | /****************** Bit definition generic for DMA_CNDTR register *******************/ |
||
| 2570 | #define DMA_CNDTR_NDT_Pos (0U) |
||
| 2571 | #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2572 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2573 | |||
| 2574 | /****************** Bit definition for DMA_CNDTR1 register ******************/ |
||
| 2575 | #define DMA_CNDTR1_NDT_Pos (0U) |
||
| 2576 | #define DMA_CNDTR1_NDT_Msk (0xFFFFU << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2577 | #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2578 | |||
| 2579 | /****************** Bit definition for DMA_CNDTR2 register ******************/ |
||
| 2580 | #define DMA_CNDTR2_NDT_Pos (0U) |
||
| 2581 | #define DMA_CNDTR2_NDT_Msk (0xFFFFU << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2582 | #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2583 | |||
| 2584 | /****************** Bit definition for DMA_CNDTR3 register ******************/ |
||
| 2585 | #define DMA_CNDTR3_NDT_Pos (0U) |
||
| 2586 | #define DMA_CNDTR3_NDT_Msk (0xFFFFU << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2587 | #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2588 | |||
| 2589 | /****************** Bit definition for DMA_CNDTR4 register ******************/ |
||
| 2590 | #define DMA_CNDTR4_NDT_Pos (0U) |
||
| 2591 | #define DMA_CNDTR4_NDT_Msk (0xFFFFU << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2592 | #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2593 | |||
| 2594 | /****************** Bit definition for DMA_CNDTR5 register ******************/ |
||
| 2595 | #define DMA_CNDTR5_NDT_Pos (0U) |
||
| 2596 | #define DMA_CNDTR5_NDT_Msk (0xFFFFU << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2597 | #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2598 | |||
| 2599 | /****************** Bit definition for DMA_CNDTR6 register ******************/ |
||
| 2600 | #define DMA_CNDTR6_NDT_Pos (0U) |
||
| 2601 | #define DMA_CNDTR6_NDT_Msk (0xFFFFU << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2602 | #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2603 | |||
| 2604 | /****************** Bit definition for DMA_CNDTR7 register ******************/ |
||
| 2605 | #define DMA_CNDTR7_NDT_Pos (0U) |
||
| 2606 | #define DMA_CNDTR7_NDT_Msk (0xFFFFU << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */ |
||
| 2607 | #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */ |
||
| 2608 | |||
| 2609 | /****************** Bit definition generic for DMA_CPAR register ********************/ |
||
| 2610 | #define DMA_CPAR_PA_Pos (0U) |
||
| 2611 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2612 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
||
| 2613 | |||
| 2614 | /****************** Bit definition for DMA_CPAR1 register *******************/ |
||
| 2615 | #define DMA_CPAR1_PA_Pos (0U) |
||
| 2616 | #define DMA_CPAR1_PA_Msk (0xFFFFFFFFU << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2617 | #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */ |
||
| 2618 | |||
| 2619 | /****************** Bit definition for DMA_CPAR2 register *******************/ |
||
| 2620 | #define DMA_CPAR2_PA_Pos (0U) |
||
| 2621 | #define DMA_CPAR2_PA_Msk (0xFFFFFFFFU << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2622 | #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */ |
||
| 2623 | |||
| 2624 | /****************** Bit definition for DMA_CPAR3 register *******************/ |
||
| 2625 | #define DMA_CPAR3_PA_Pos (0U) |
||
| 2626 | #define DMA_CPAR3_PA_Msk (0xFFFFFFFFU << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2627 | #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */ |
||
| 2628 | |||
| 2629 | |||
| 2630 | /****************** Bit definition for DMA_CPAR4 register *******************/ |
||
| 2631 | #define DMA_CPAR4_PA_Pos (0U) |
||
| 2632 | #define DMA_CPAR4_PA_Msk (0xFFFFFFFFU << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2633 | #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */ |
||
| 2634 | |||
| 2635 | /****************** Bit definition for DMA_CPAR5 register *******************/ |
||
| 2636 | #define DMA_CPAR5_PA_Pos (0U) |
||
| 2637 | #define DMA_CPAR5_PA_Msk (0xFFFFFFFFU << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2638 | #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */ |
||
| 2639 | |||
| 2640 | /****************** Bit definition for DMA_CPAR6 register *******************/ |
||
| 2641 | #define DMA_CPAR6_PA_Pos (0U) |
||
| 2642 | #define DMA_CPAR6_PA_Msk (0xFFFFFFFFU << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2643 | #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */ |
||
| 2644 | |||
| 2645 | |||
| 2646 | /****************** Bit definition for DMA_CPAR7 register *******************/ |
||
| 2647 | #define DMA_CPAR7_PA_Pos (0U) |
||
| 2648 | #define DMA_CPAR7_PA_Msk (0xFFFFFFFFU << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2649 | #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */ |
||
| 2650 | |||
| 2651 | /****************** Bit definition generic for DMA_CMAR register ********************/ |
||
| 2652 | #define DMA_CMAR_MA_Pos (0U) |
||
| 2653 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2654 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
||
| 2655 | |||
| 2656 | /****************** Bit definition for DMA_CMAR1 register *******************/ |
||
| 2657 | #define DMA_CMAR1_MA_Pos (0U) |
||
| 2658 | #define DMA_CMAR1_MA_Msk (0xFFFFFFFFU << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2659 | #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */ |
||
| 2660 | |||
| 2661 | /****************** Bit definition for DMA_CMAR2 register *******************/ |
||
| 2662 | #define DMA_CMAR2_MA_Pos (0U) |
||
| 2663 | #define DMA_CMAR2_MA_Msk (0xFFFFFFFFU << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2664 | #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */ |
||
| 2665 | |||
| 2666 | /****************** Bit definition for DMA_CMAR3 register *******************/ |
||
| 2667 | #define DMA_CMAR3_MA_Pos (0U) |
||
| 2668 | #define DMA_CMAR3_MA_Msk (0xFFFFFFFFU << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2669 | #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */ |
||
| 2670 | |||
| 2671 | |||
| 2672 | /****************** Bit definition for DMA_CMAR4 register *******************/ |
||
| 2673 | #define DMA_CMAR4_MA_Pos (0U) |
||
| 2674 | #define DMA_CMAR4_MA_Msk (0xFFFFFFFFU << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2675 | #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */ |
||
| 2676 | |||
| 2677 | /****************** Bit definition for DMA_CMAR5 register *******************/ |
||
| 2678 | #define DMA_CMAR5_MA_Pos (0U) |
||
| 2679 | #define DMA_CMAR5_MA_Msk (0xFFFFFFFFU << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2680 | #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */ |
||
| 2681 | |||
| 2682 | /****************** Bit definition for DMA_CMAR6 register *******************/ |
||
| 2683 | #define DMA_CMAR6_MA_Pos (0U) |
||
| 2684 | #define DMA_CMAR6_MA_Msk (0xFFFFFFFFU << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2685 | #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */ |
||
| 2686 | |||
| 2687 | /****************** Bit definition for DMA_CMAR7 register *******************/ |
||
| 2688 | #define DMA_CMAR7_MA_Pos (0U) |
||
| 2689 | #define DMA_CMAR7_MA_Msk (0xFFFFFFFFU << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */ |
||
| 2690 | #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */ |
||
| 2691 | |||
| 2692 | /******************************************************************************/ |
||
| 2693 | /* */ |
||
| 2694 | /* External Interrupt/Event Controller (EXTI) */ |
||
| 2695 | /* */ |
||
| 2696 | /******************************************************************************/ |
||
| 2697 | |||
| 2698 | /******************* Bit definition for EXTI_IMR register *******************/ |
||
| 2699 | #define EXTI_IMR_MR0_Pos (0U) |
||
| 2700 | #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
||
| 2701 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
||
| 2702 | #define EXTI_IMR_MR1_Pos (1U) |
||
| 2703 | #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
||
| 2704 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
||
| 2705 | #define EXTI_IMR_MR2_Pos (2U) |
||
| 2706 | #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
||
| 2707 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
||
| 2708 | #define EXTI_IMR_MR3_Pos (3U) |
||
| 2709 | #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
||
| 2710 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
||
| 2711 | #define EXTI_IMR_MR4_Pos (4U) |
||
| 2712 | #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
||
| 2713 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
||
| 2714 | #define EXTI_IMR_MR5_Pos (5U) |
||
| 2715 | #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
||
| 2716 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
||
| 2717 | #define EXTI_IMR_MR6_Pos (6U) |
||
| 2718 | #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
||
| 2719 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
||
| 2720 | #define EXTI_IMR_MR7_Pos (7U) |
||
| 2721 | #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
||
| 2722 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
||
| 2723 | #define EXTI_IMR_MR8_Pos (8U) |
||
| 2724 | #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
||
| 2725 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
||
| 2726 | #define EXTI_IMR_MR9_Pos (9U) |
||
| 2727 | #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
||
| 2728 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
||
| 2729 | #define EXTI_IMR_MR10_Pos (10U) |
||
| 2730 | #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
||
| 2731 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
||
| 2732 | #define EXTI_IMR_MR11_Pos (11U) |
||
| 2733 | #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
||
| 2734 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
||
| 2735 | #define EXTI_IMR_MR12_Pos (12U) |
||
| 2736 | #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
||
| 2737 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
||
| 2738 | #define EXTI_IMR_MR13_Pos (13U) |
||
| 2739 | #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
||
| 2740 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
||
| 2741 | #define EXTI_IMR_MR14_Pos (14U) |
||
| 2742 | #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
||
| 2743 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
||
| 2744 | #define EXTI_IMR_MR15_Pos (15U) |
||
| 2745 | #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
||
| 2746 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
||
| 2747 | #define EXTI_IMR_MR16_Pos (16U) |
||
| 2748 | #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
||
| 2749 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
||
| 2750 | #define EXTI_IMR_MR17_Pos (17U) |
||
| 2751 | #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
||
| 2752 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
||
| 2753 | #define EXTI_IMR_MR18_Pos (18U) |
||
| 2754 | #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
||
| 2755 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
||
| 2756 | #define EXTI_IMR_MR19_Pos (19U) |
||
| 2757 | #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
||
| 2758 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
||
| 2759 | #define EXTI_IMR_MR20_Pos (20U) |
||
| 2760 | #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ |
||
| 2761 | #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ |
||
| 2762 | #define EXTI_IMR_MR21_Pos (21U) |
||
| 2763 | #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ |
||
| 2764 | #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ |
||
| 2765 | #define EXTI_IMR_MR22_Pos (22U) |
||
| 2766 | #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ |
||
| 2767 | #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ |
||
| 2768 | #define EXTI_IMR_MR23_Pos (23U) |
||
| 2769 | #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ |
||
| 2770 | #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ |
||
| 2771 | |||
| 2772 | /* References Defines */ |
||
| 2773 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
||
| 2774 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
||
| 2775 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
||
| 2776 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
||
| 2777 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
||
| 2778 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
||
| 2779 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
||
| 2780 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
||
| 2781 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
||
| 2782 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
||
| 2783 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
||
| 2784 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
||
| 2785 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
||
| 2786 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
||
| 2787 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
||
| 2788 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
||
| 2789 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
||
| 2790 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
||
| 2791 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
||
| 2792 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
||
| 2793 | #define EXTI_IMR_IM20 EXTI_IMR_MR20 |
||
| 2794 | #define EXTI_IMR_IM21 EXTI_IMR_MR21 |
||
| 2795 | #define EXTI_IMR_IM22 EXTI_IMR_MR22 |
||
| 2796 | /* Category 3, 4 & 5 */ |
||
| 2797 | #define EXTI_IMR_IM23 EXTI_IMR_MR23 |
||
| 2798 | #define EXTI_IMR_IM_Pos (0U) |
||
| 2799 | #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */ |
||
| 2800 | #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ |
||
| 2801 | |||
| 2802 | /******************* Bit definition for EXTI_EMR register *******************/ |
||
| 2803 | #define EXTI_EMR_MR0_Pos (0U) |
||
| 2804 | #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
||
| 2805 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
||
| 2806 | #define EXTI_EMR_MR1_Pos (1U) |
||
| 2807 | #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
||
| 2808 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
||
| 2809 | #define EXTI_EMR_MR2_Pos (2U) |
||
| 2810 | #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
||
| 2811 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
||
| 2812 | #define EXTI_EMR_MR3_Pos (3U) |
||
| 2813 | #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
||
| 2814 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
||
| 2815 | #define EXTI_EMR_MR4_Pos (4U) |
||
| 2816 | #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
||
| 2817 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
||
| 2818 | #define EXTI_EMR_MR5_Pos (5U) |
||
| 2819 | #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
||
| 2820 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
||
| 2821 | #define EXTI_EMR_MR6_Pos (6U) |
||
| 2822 | #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
||
| 2823 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
||
| 2824 | #define EXTI_EMR_MR7_Pos (7U) |
||
| 2825 | #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
||
| 2826 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
||
| 2827 | #define EXTI_EMR_MR8_Pos (8U) |
||
| 2828 | #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
||
| 2829 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
||
| 2830 | #define EXTI_EMR_MR9_Pos (9U) |
||
| 2831 | #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
||
| 2832 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
||
| 2833 | #define EXTI_EMR_MR10_Pos (10U) |
||
| 2834 | #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
||
| 2835 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
||
| 2836 | #define EXTI_EMR_MR11_Pos (11U) |
||
| 2837 | #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
||
| 2838 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
||
| 2839 | #define EXTI_EMR_MR12_Pos (12U) |
||
| 2840 | #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
||
| 2841 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
||
| 2842 | #define EXTI_EMR_MR13_Pos (13U) |
||
| 2843 | #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
||
| 2844 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
||
| 2845 | #define EXTI_EMR_MR14_Pos (14U) |
||
| 2846 | #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
||
| 2847 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
||
| 2848 | #define EXTI_EMR_MR15_Pos (15U) |
||
| 2849 | #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
||
| 2850 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
||
| 2851 | #define EXTI_EMR_MR16_Pos (16U) |
||
| 2852 | #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
||
| 2853 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
||
| 2854 | #define EXTI_EMR_MR17_Pos (17U) |
||
| 2855 | #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
||
| 2856 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
||
| 2857 | #define EXTI_EMR_MR18_Pos (18U) |
||
| 2858 | #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
||
| 2859 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
||
| 2860 | #define EXTI_EMR_MR19_Pos (19U) |
||
| 2861 | #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
||
| 2862 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
||
| 2863 | #define EXTI_EMR_MR20_Pos (20U) |
||
| 2864 | #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ |
||
| 2865 | #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ |
||
| 2866 | #define EXTI_EMR_MR21_Pos (21U) |
||
| 2867 | #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ |
||
| 2868 | #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ |
||
| 2869 | #define EXTI_EMR_MR22_Pos (22U) |
||
| 2870 | #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ |
||
| 2871 | #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ |
||
| 2872 | #define EXTI_EMR_MR23_Pos (23U) |
||
| 2873 | #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ |
||
| 2874 | #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ |
||
| 2875 | |||
| 2876 | /* References Defines */ |
||
| 2877 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
||
| 2878 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
||
| 2879 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
||
| 2880 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
||
| 2881 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
||
| 2882 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
||
| 2883 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
||
| 2884 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
||
| 2885 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
||
| 2886 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
||
| 2887 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
||
| 2888 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
||
| 2889 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
||
| 2890 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
||
| 2891 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
||
| 2892 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
||
| 2893 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
||
| 2894 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
||
| 2895 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
||
| 2896 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
||
| 2897 | #define EXTI_EMR_EM20 EXTI_EMR_MR20 |
||
| 2898 | #define EXTI_EMR_EM21 EXTI_EMR_MR21 |
||
| 2899 | #define EXTI_EMR_EM22 EXTI_EMR_MR22 |
||
| 2900 | #define EXTI_EMR_EM23 EXTI_EMR_MR23 |
||
| 2901 | |||
| 2902 | /****************** Bit definition for EXTI_RTSR register *******************/ |
||
| 2903 | #define EXTI_RTSR_TR0_Pos (0U) |
||
| 2904 | #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
||
| 2905 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
||
| 2906 | #define EXTI_RTSR_TR1_Pos (1U) |
||
| 2907 | #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
||
| 2908 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
||
| 2909 | #define EXTI_RTSR_TR2_Pos (2U) |
||
| 2910 | #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
||
| 2911 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
||
| 2912 | #define EXTI_RTSR_TR3_Pos (3U) |
||
| 2913 | #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
||
| 2914 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
||
| 2915 | #define EXTI_RTSR_TR4_Pos (4U) |
||
| 2916 | #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
||
| 2917 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
||
| 2918 | #define EXTI_RTSR_TR5_Pos (5U) |
||
| 2919 | #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
||
| 2920 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
||
| 2921 | #define EXTI_RTSR_TR6_Pos (6U) |
||
| 2922 | #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
||
| 2923 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
||
| 2924 | #define EXTI_RTSR_TR7_Pos (7U) |
||
| 2925 | #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
||
| 2926 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
||
| 2927 | #define EXTI_RTSR_TR8_Pos (8U) |
||
| 2928 | #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
||
| 2929 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
||
| 2930 | #define EXTI_RTSR_TR9_Pos (9U) |
||
| 2931 | #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
||
| 2932 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
||
| 2933 | #define EXTI_RTSR_TR10_Pos (10U) |
||
| 2934 | #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
||
| 2935 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
||
| 2936 | #define EXTI_RTSR_TR11_Pos (11U) |
||
| 2937 | #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
||
| 2938 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
||
| 2939 | #define EXTI_RTSR_TR12_Pos (12U) |
||
| 2940 | #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
||
| 2941 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
||
| 2942 | #define EXTI_RTSR_TR13_Pos (13U) |
||
| 2943 | #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
||
| 2944 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
||
| 2945 | #define EXTI_RTSR_TR14_Pos (14U) |
||
| 2946 | #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
||
| 2947 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
||
| 2948 | #define EXTI_RTSR_TR15_Pos (15U) |
||
| 2949 | #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
||
| 2950 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
||
| 2951 | #define EXTI_RTSR_TR16_Pos (16U) |
||
| 2952 | #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
||
| 2953 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
||
| 2954 | #define EXTI_RTSR_TR17_Pos (17U) |
||
| 2955 | #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
||
| 2956 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
||
| 2957 | #define EXTI_RTSR_TR18_Pos (18U) |
||
| 2958 | #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
||
| 2959 | #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
||
| 2960 | #define EXTI_RTSR_TR19_Pos (19U) |
||
| 2961 | #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
||
| 2962 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
||
| 2963 | #define EXTI_RTSR_TR20_Pos (20U) |
||
| 2964 | #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ |
||
| 2965 | #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ |
||
| 2966 | #define EXTI_RTSR_TR21_Pos (21U) |
||
| 2967 | #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ |
||
| 2968 | #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
||
| 2969 | #define EXTI_RTSR_TR22_Pos (22U) |
||
| 2970 | #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ |
||
| 2971 | #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
||
| 2972 | #define EXTI_RTSR_TR23_Pos (23U) |
||
| 2973 | #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */ |
||
| 2974 | #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */ |
||
| 2975 | |||
| 2976 | /* References Defines */ |
||
| 2977 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
||
| 2978 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
||
| 2979 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
||
| 2980 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
||
| 2981 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
||
| 2982 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
||
| 2983 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
||
| 2984 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
||
| 2985 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
||
| 2986 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
||
| 2987 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
||
| 2988 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
||
| 2989 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
||
| 2990 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
||
| 2991 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
||
| 2992 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
||
| 2993 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
||
| 2994 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
||
| 2995 | #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 |
||
| 2996 | #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 |
||
| 2997 | #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 |
||
| 2998 | #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 |
||
| 2999 | #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 |
||
| 3000 | #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 |
||
| 3001 | |||
| 3002 | /****************** Bit definition for EXTI_FTSR register *******************/ |
||
| 3003 | #define EXTI_FTSR_TR0_Pos (0U) |
||
| 3004 | #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
||
| 3005 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
||
| 3006 | #define EXTI_FTSR_TR1_Pos (1U) |
||
| 3007 | #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
||
| 3008 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
||
| 3009 | #define EXTI_FTSR_TR2_Pos (2U) |
||
| 3010 | #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
||
| 3011 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
||
| 3012 | #define EXTI_FTSR_TR3_Pos (3U) |
||
| 3013 | #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
||
| 3014 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
||
| 3015 | #define EXTI_FTSR_TR4_Pos (4U) |
||
| 3016 | #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
||
| 3017 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
||
| 3018 | #define EXTI_FTSR_TR5_Pos (5U) |
||
| 3019 | #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
||
| 3020 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
||
| 3021 | #define EXTI_FTSR_TR6_Pos (6U) |
||
| 3022 | #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
||
| 3023 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
||
| 3024 | #define EXTI_FTSR_TR7_Pos (7U) |
||
| 3025 | #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
||
| 3026 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
||
| 3027 | #define EXTI_FTSR_TR8_Pos (8U) |
||
| 3028 | #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
||
| 3029 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
||
| 3030 | #define EXTI_FTSR_TR9_Pos (9U) |
||
| 3031 | #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
||
| 3032 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
||
| 3033 | #define EXTI_FTSR_TR10_Pos (10U) |
||
| 3034 | #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
||
| 3035 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
||
| 3036 | #define EXTI_FTSR_TR11_Pos (11U) |
||
| 3037 | #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
||
| 3038 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
||
| 3039 | #define EXTI_FTSR_TR12_Pos (12U) |
||
| 3040 | #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
||
| 3041 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
||
| 3042 | #define EXTI_FTSR_TR13_Pos (13U) |
||
| 3043 | #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
||
| 3044 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
||
| 3045 | #define EXTI_FTSR_TR14_Pos (14U) |
||
| 3046 | #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
||
| 3047 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
||
| 3048 | #define EXTI_FTSR_TR15_Pos (15U) |
||
| 3049 | #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
||
| 3050 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
||
| 3051 | #define EXTI_FTSR_TR16_Pos (16U) |
||
| 3052 | #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
||
| 3053 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
||
| 3054 | #define EXTI_FTSR_TR17_Pos (17U) |
||
| 3055 | #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
||
| 3056 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
||
| 3057 | #define EXTI_FTSR_TR18_Pos (18U) |
||
| 3058 | #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
||
| 3059 | #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
||
| 3060 | #define EXTI_FTSR_TR19_Pos (19U) |
||
| 3061 | #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
||
| 3062 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
||
| 3063 | #define EXTI_FTSR_TR20_Pos (20U) |
||
| 3064 | #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ |
||
| 3065 | #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ |
||
| 3066 | #define EXTI_FTSR_TR21_Pos (21U) |
||
| 3067 | #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ |
||
| 3068 | #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
||
| 3069 | #define EXTI_FTSR_TR22_Pos (22U) |
||
| 3070 | #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ |
||
| 3071 | #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
||
| 3072 | #define EXTI_FTSR_TR23_Pos (23U) |
||
| 3073 | #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */ |
||
| 3074 | #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */ |
||
| 3075 | |||
| 3076 | /* References Defines */ |
||
| 3077 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
||
| 3078 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
||
| 3079 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
||
| 3080 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
||
| 3081 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
||
| 3082 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
||
| 3083 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
||
| 3084 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
||
| 3085 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
||
| 3086 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
||
| 3087 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
||
| 3088 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
||
| 3089 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
||
| 3090 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
||
| 3091 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
||
| 3092 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
||
| 3093 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
||
| 3094 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
||
| 3095 | #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 |
||
| 3096 | #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 |
||
| 3097 | #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 |
||
| 3098 | #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 |
||
| 3099 | #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 |
||
| 3100 | #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 |
||
| 3101 | |||
| 3102 | /****************** Bit definition for EXTI_SWIER register ******************/ |
||
| 3103 | #define EXTI_SWIER_SWIER0_Pos (0U) |
||
| 3104 | #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
||
| 3105 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
||
| 3106 | #define EXTI_SWIER_SWIER1_Pos (1U) |
||
| 3107 | #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
||
| 3108 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
||
| 3109 | #define EXTI_SWIER_SWIER2_Pos (2U) |
||
| 3110 | #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
||
| 3111 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
||
| 3112 | #define EXTI_SWIER_SWIER3_Pos (3U) |
||
| 3113 | #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
||
| 3114 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
||
| 3115 | #define EXTI_SWIER_SWIER4_Pos (4U) |
||
| 3116 | #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
||
| 3117 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
||
| 3118 | #define EXTI_SWIER_SWIER5_Pos (5U) |
||
| 3119 | #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
||
| 3120 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
||
| 3121 | #define EXTI_SWIER_SWIER6_Pos (6U) |
||
| 3122 | #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
||
| 3123 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
||
| 3124 | #define EXTI_SWIER_SWIER7_Pos (7U) |
||
| 3125 | #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
||
| 3126 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
||
| 3127 | #define EXTI_SWIER_SWIER8_Pos (8U) |
||
| 3128 | #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
||
| 3129 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
||
| 3130 | #define EXTI_SWIER_SWIER9_Pos (9U) |
||
| 3131 | #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
||
| 3132 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
||
| 3133 | #define EXTI_SWIER_SWIER10_Pos (10U) |
||
| 3134 | #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
||
| 3135 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
||
| 3136 | #define EXTI_SWIER_SWIER11_Pos (11U) |
||
| 3137 | #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
||
| 3138 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
||
| 3139 | #define EXTI_SWIER_SWIER12_Pos (12U) |
||
| 3140 | #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
||
| 3141 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
||
| 3142 | #define EXTI_SWIER_SWIER13_Pos (13U) |
||
| 3143 | #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
||
| 3144 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
||
| 3145 | #define EXTI_SWIER_SWIER14_Pos (14U) |
||
| 3146 | #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
||
| 3147 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
||
| 3148 | #define EXTI_SWIER_SWIER15_Pos (15U) |
||
| 3149 | #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
||
| 3150 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
||
| 3151 | #define EXTI_SWIER_SWIER16_Pos (16U) |
||
| 3152 | #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
||
| 3153 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
||
| 3154 | #define EXTI_SWIER_SWIER17_Pos (17U) |
||
| 3155 | #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
||
| 3156 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
||
| 3157 | #define EXTI_SWIER_SWIER18_Pos (18U) |
||
| 3158 | #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
||
| 3159 | #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
||
| 3160 | #define EXTI_SWIER_SWIER19_Pos (19U) |
||
| 3161 | #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
||
| 3162 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
||
| 3163 | #define EXTI_SWIER_SWIER20_Pos (20U) |
||
| 3164 | #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ |
||
| 3165 | #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ |
||
| 3166 | #define EXTI_SWIER_SWIER21_Pos (21U) |
||
| 3167 | #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ |
||
| 3168 | #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ |
||
| 3169 | #define EXTI_SWIER_SWIER22_Pos (22U) |
||
| 3170 | #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ |
||
| 3171 | #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ |
||
| 3172 | #define EXTI_SWIER_SWIER23_Pos (23U) |
||
| 3173 | #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */ |
||
| 3174 | #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */ |
||
| 3175 | |||
| 3176 | /* References Defines */ |
||
| 3177 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
||
| 3178 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
||
| 3179 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
||
| 3180 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
||
| 3181 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
||
| 3182 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
||
| 3183 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
||
| 3184 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
||
| 3185 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
||
| 3186 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
||
| 3187 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
||
| 3188 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
||
| 3189 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
||
| 3190 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
||
| 3191 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
||
| 3192 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
||
| 3193 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
||
| 3194 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
||
| 3195 | #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 |
||
| 3196 | #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 |
||
| 3197 | #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 |
||
| 3198 | #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 |
||
| 3199 | #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 |
||
| 3200 | #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 |
||
| 3201 | |||
| 3202 | /******************* Bit definition for EXTI_PR register ********************/ |
||
| 3203 | #define EXTI_PR_PR0_Pos (0U) |
||
| 3204 | #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
||
| 3205 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
||
| 3206 | #define EXTI_PR_PR1_Pos (1U) |
||
| 3207 | #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
||
| 3208 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
||
| 3209 | #define EXTI_PR_PR2_Pos (2U) |
||
| 3210 | #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
||
| 3211 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
||
| 3212 | #define EXTI_PR_PR3_Pos (3U) |
||
| 3213 | #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
||
| 3214 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
||
| 3215 | #define EXTI_PR_PR4_Pos (4U) |
||
| 3216 | #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
||
| 3217 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
||
| 3218 | #define EXTI_PR_PR5_Pos (5U) |
||
| 3219 | #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
||
| 3220 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
||
| 3221 | #define EXTI_PR_PR6_Pos (6U) |
||
| 3222 | #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
||
| 3223 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
||
| 3224 | #define EXTI_PR_PR7_Pos (7U) |
||
| 3225 | #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
||
| 3226 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
||
| 3227 | #define EXTI_PR_PR8_Pos (8U) |
||
| 3228 | #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
||
| 3229 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
||
| 3230 | #define EXTI_PR_PR9_Pos (9U) |
||
| 3231 | #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
||
| 3232 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
||
| 3233 | #define EXTI_PR_PR10_Pos (10U) |
||
| 3234 | #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
||
| 3235 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
||
| 3236 | #define EXTI_PR_PR11_Pos (11U) |
||
| 3237 | #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
||
| 3238 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
||
| 3239 | #define EXTI_PR_PR12_Pos (12U) |
||
| 3240 | #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
||
| 3241 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
||
| 3242 | #define EXTI_PR_PR13_Pos (13U) |
||
| 3243 | #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
||
| 3244 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
||
| 3245 | #define EXTI_PR_PR14_Pos (14U) |
||
| 3246 | #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
||
| 3247 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
||
| 3248 | #define EXTI_PR_PR15_Pos (15U) |
||
| 3249 | #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
||
| 3250 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
||
| 3251 | #define EXTI_PR_PR16_Pos (16U) |
||
| 3252 | #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
||
| 3253 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
||
| 3254 | #define EXTI_PR_PR17_Pos (17U) |
||
| 3255 | #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
||
| 3256 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
||
| 3257 | #define EXTI_PR_PR18_Pos (18U) |
||
| 3258 | #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
||
| 3259 | #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
||
| 3260 | #define EXTI_PR_PR19_Pos (19U) |
||
| 3261 | #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
||
| 3262 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
||
| 3263 | #define EXTI_PR_PR20_Pos (20U) |
||
| 3264 | #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ |
||
| 3265 | #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ |
||
| 3266 | #define EXTI_PR_PR21_Pos (21U) |
||
| 3267 | #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ |
||
| 3268 | #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ |
||
| 3269 | #define EXTI_PR_PR22_Pos (22U) |
||
| 3270 | #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ |
||
| 3271 | #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ |
||
| 3272 | #define EXTI_PR_PR23_Pos (23U) |
||
| 3273 | #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */ |
||
| 3274 | #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */ |
||
| 3275 | |||
| 3276 | /* References Defines */ |
||
| 3277 | #define EXTI_PR_PIF0 EXTI_PR_PR0 |
||
| 3278 | #define EXTI_PR_PIF1 EXTI_PR_PR1 |
||
| 3279 | #define EXTI_PR_PIF2 EXTI_PR_PR2 |
||
| 3280 | #define EXTI_PR_PIF3 EXTI_PR_PR3 |
||
| 3281 | #define EXTI_PR_PIF4 EXTI_PR_PR4 |
||
| 3282 | #define EXTI_PR_PIF5 EXTI_PR_PR5 |
||
| 3283 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
||
| 3284 | #define EXTI_PR_PIF7 EXTI_PR_PR7 |
||
| 3285 | #define EXTI_PR_PIF8 EXTI_PR_PR8 |
||
| 3286 | #define EXTI_PR_PIF9 EXTI_PR_PR9 |
||
| 3287 | #define EXTI_PR_PIF10 EXTI_PR_PR10 |
||
| 3288 | #define EXTI_PR_PIF11 EXTI_PR_PR11 |
||
| 3289 | #define EXTI_PR_PIF12 EXTI_PR_PR12 |
||
| 3290 | #define EXTI_PR_PIF13 EXTI_PR_PR13 |
||
| 3291 | #define EXTI_PR_PIF14 EXTI_PR_PR14 |
||
| 3292 | #define EXTI_PR_PIF15 EXTI_PR_PR15 |
||
| 3293 | #define EXTI_PR_PIF16 EXTI_PR_PR16 |
||
| 3294 | #define EXTI_PR_PIF17 EXTI_PR_PR17 |
||
| 3295 | #define EXTI_PR_PIF18 EXTI_PR_PR18 |
||
| 3296 | #define EXTI_PR_PIF19 EXTI_PR_PR19 |
||
| 3297 | #define EXTI_PR_PIF20 EXTI_PR_PR20 |
||
| 3298 | #define EXTI_PR_PIF21 EXTI_PR_PR21 |
||
| 3299 | #define EXTI_PR_PIF22 EXTI_PR_PR22 |
||
| 3300 | #define EXTI_PR_PIF23 EXTI_PR_PR23 |
||
| 3301 | |||
| 3302 | /******************************************************************************/ |
||
| 3303 | /* */ |
||
| 3304 | /* FLASH, DATA EEPROM and Option Bytes Registers */ |
||
| 3305 | /* (FLASH, DATA_EEPROM, OB) */ |
||
| 3306 | /* */ |
||
| 3307 | /******************************************************************************/ |
||
| 3308 | |||
| 3309 | /******************* Bit definition for FLASH_ACR register ******************/ |
||
| 3310 | #define FLASH_ACR_LATENCY_Pos (0U) |
||
| 3311 | #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
||
| 3312 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ |
||
| 3313 | #define FLASH_ACR_PRFTEN_Pos (1U) |
||
| 3314 | #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ |
||
| 3315 | #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ |
||
| 3316 | #define FLASH_ACR_ACC64_Pos (2U) |
||
| 3317 | #define FLASH_ACR_ACC64_Msk (0x1U << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */ |
||
| 3318 | #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */ |
||
| 3319 | #define FLASH_ACR_SLEEP_PD_Pos (3U) |
||
| 3320 | #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ |
||
| 3321 | #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ |
||
| 3322 | #define FLASH_ACR_RUN_PD_Pos (4U) |
||
| 3323 | #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ |
||
| 3324 | #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ |
||
| 3325 | |||
| 3326 | /******************* Bit definition for FLASH_PECR register ******************/ |
||
| 3327 | #define FLASH_PECR_PELOCK_Pos (0U) |
||
| 3328 | #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ |
||
| 3329 | #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ |
||
| 3330 | #define FLASH_PECR_PRGLOCK_Pos (1U) |
||
| 3331 | #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ |
||
| 3332 | #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ |
||
| 3333 | #define FLASH_PECR_OPTLOCK_Pos (2U) |
||
| 3334 | #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ |
||
| 3335 | #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ |
||
| 3336 | #define FLASH_PECR_PROG_Pos (3U) |
||
| 3337 | #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ |
||
| 3338 | #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ |
||
| 3339 | #define FLASH_PECR_DATA_Pos (4U) |
||
| 3340 | #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ |
||
| 3341 | #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ |
||
| 3342 | #define FLASH_PECR_FTDW_Pos (8U) |
||
| 3343 | #define FLASH_PECR_FTDW_Msk (0x1U << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */ |
||
| 3344 | #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ |
||
| 3345 | #define FLASH_PECR_ERASE_Pos (9U) |
||
| 3346 | #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ |
||
| 3347 | #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ |
||
| 3348 | #define FLASH_PECR_FPRG_Pos (10U) |
||
| 3349 | #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ |
||
| 3350 | #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ |
||
| 3351 | #define FLASH_PECR_PARALLBANK_Pos (15U) |
||
| 3352 | #define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ |
||
| 3353 | #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ |
||
| 3354 | #define FLASH_PECR_EOPIE_Pos (16U) |
||
| 3355 | #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ |
||
| 3356 | #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ |
||
| 3357 | #define FLASH_PECR_ERRIE_Pos (17U) |
||
| 3358 | #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ |
||
| 3359 | #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ |
||
| 3360 | #define FLASH_PECR_OBL_LAUNCH_Pos (18U) |
||
| 3361 | #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ |
||
| 3362 | #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ |
||
| 3363 | |||
| 3364 | /****************** Bit definition for FLASH_PDKEYR register ******************/ |
||
| 3365 | #define FLASH_PDKEYR_PDKEYR_Pos (0U) |
||
| 3366 | #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ |
||
| 3367 | #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ |
||
| 3368 | |||
| 3369 | /****************** Bit definition for FLASH_PEKEYR register ******************/ |
||
| 3370 | #define FLASH_PEKEYR_PEKEYR_Pos (0U) |
||
| 3371 | #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ |
||
| 3372 | #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ |
||
| 3373 | |||
| 3374 | /****************** Bit definition for FLASH_PRGKEYR register ******************/ |
||
| 3375 | #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) |
||
| 3376 | #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ |
||
| 3377 | #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ |
||
| 3378 | |||
| 3379 | /****************** Bit definition for FLASH_OPTKEYR register ******************/ |
||
| 3380 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
||
| 3381 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
||
| 3382 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ |
||
| 3383 | |||
| 3384 | /****************** Bit definition for FLASH_SR register *******************/ |
||
| 3385 | #define FLASH_SR_BSY_Pos (0U) |
||
| 3386 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
||
| 3387 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
||
| 3388 | #define FLASH_SR_EOP_Pos (1U) |
||
| 3389 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ |
||
| 3390 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ |
||
| 3391 | #define FLASH_SR_ENDHV_Pos (2U) |
||
| 3392 | #define FLASH_SR_ENDHV_Msk (0x1U << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */ |
||
| 3393 | #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */ |
||
| 3394 | #define FLASH_SR_READY_Pos (3U) |
||
| 3395 | #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ |
||
| 3396 | #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ |
||
| 3397 | |||
| 3398 | #define FLASH_SR_WRPERR_Pos (8U) |
||
| 3399 | #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ |
||
| 3400 | #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */ |
||
| 3401 | #define FLASH_SR_PGAERR_Pos (9U) |
||
| 3402 | #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ |
||
| 3403 | #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ |
||
| 3404 | #define FLASH_SR_SIZERR_Pos (10U) |
||
| 3405 | #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ |
||
| 3406 | #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ |
||
| 3407 | #define FLASH_SR_OPTVERR_Pos (11U) |
||
| 3408 | #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ |
||
| 3409 | #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ |
||
| 3410 | #define FLASH_SR_OPTVERRUSR_Pos (12U) |
||
| 3411 | #define FLASH_SR_OPTVERRUSR_Msk (0x1U << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */ |
||
| 3412 | #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */ |
||
| 3413 | |||
| 3414 | /****************** Bit definition for FLASH_OBR register *******************/ |
||
| 3415 | #define FLASH_OBR_RDPRT_Pos (0U) |
||
| 3416 | #define FLASH_OBR_RDPRT_Msk (0xFFU << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */ |
||
| 3417 | #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */ |
||
| 3418 | #define FLASH_OBR_BOR_LEV_Pos (16U) |
||
| 3419 | #define FLASH_OBR_BOR_LEV_Msk (0xFU << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */ |
||
| 3420 | #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ |
||
| 3421 | #define FLASH_OBR_USER_Pos (20U) |
||
| 3422 | #define FLASH_OBR_USER_Msk (0xFU << FLASH_OBR_USER_Pos) /*!< 0x00F00000 */ |
||
| 3423 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
||
| 3424 | #define FLASH_OBR_IWDG_SW_Pos (20U) |
||
| 3425 | #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */ |
||
| 3426 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */ |
||
| 3427 | #define FLASH_OBR_nRST_STOP_Pos (21U) |
||
| 3428 | #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */ |
||
| 3429 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
||
| 3430 | #define FLASH_OBR_nRST_STDBY_Pos (22U) |
||
| 3431 | #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */ |
||
| 3432 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
||
| 3433 | #define FLASH_OBR_nRST_BFB2_Pos (23U) |
||
| 3434 | #define FLASH_OBR_nRST_BFB2_Msk (0x1U << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */ |
||
| 3435 | #define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /*!< BFB2 */ |
||
| 3436 | |||
| 3437 | /****************** Bit definition for FLASH_WRPR register ******************/ |
||
| 3438 | #define FLASH_WRPR1_WRP_Pos (0U) |
||
| 3439 | #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */ |
||
| 3440 | #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */ |
||
| 3441 | #define FLASH_WRPR2_WRP_Pos (0U) |
||
| 3442 | #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */ |
||
| 3443 | #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */ |
||
| 3444 | #define FLASH_WRPR3_WRP_Pos (0U) |
||
| 3445 | #define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */ |
||
| 3446 | #define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /*!< Write Protect sectors 64 to 95 */ |
||
| 3447 | |||
| 3448 | /******************************************************************************/ |
||
| 3449 | /* */ |
||
| 3450 | /* Flexible Static Memory Controller */ |
||
| 3451 | /* */ |
||
| 3452 | /******************************************************************************/ |
||
| 3453 | /****************** Bit definition for FSMC_BCRx register (x=1..4) *******************/ |
||
| 3454 | #define FSMC_BCRx_MBKEN_Pos (0U) |
||
| 3455 | #define FSMC_BCRx_MBKEN_Msk (0x1U << FSMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */ |
||
| 3456 | #define FSMC_BCRx_MBKEN FSMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */ |
||
| 3457 | #define FSMC_BCRx_MUXEN_Pos (1U) |
||
| 3458 | #define FSMC_BCRx_MUXEN_Msk (0x1U << FSMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */ |
||
| 3459 | #define FSMC_BCRx_MUXEN FSMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */ |
||
| 3460 | |||
| 3461 | #define FSMC_BCRx_MTYP_Pos (2U) |
||
| 3462 | #define FSMC_BCRx_MTYP_Msk (0x3U << FSMC_BCRx_MTYP_Pos) /*!< 0x0000000C */ |
||
| 3463 | #define FSMC_BCRx_MTYP FSMC_BCRx_MTYP_Msk /*!< MTYP[1:0] bits (Memory type) */ |
||
| 3464 | #define FSMC_BCRx_MTYP_0 (0x1U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000004 */ |
||
| 3465 | #define FSMC_BCRx_MTYP_1 (0x2U << FSMC_BCRx_MTYP_Pos) /*!< 0x00000008 */ |
||
| 3466 | |||
| 3467 | #define FSMC_BCRx_MWID_Pos (4U) |
||
| 3468 | #define FSMC_BCRx_MWID_Msk (0x3U << FSMC_BCRx_MWID_Pos) /*!< 0x00000030 */ |
||
| 3469 | #define FSMC_BCRx_MWID FSMC_BCRx_MWID_Msk /*!< MWID[1:0] bits (Memory data bus width) */ |
||
| 3470 | #define FSMC_BCRx_MWID_0 (0x1U << FSMC_BCRx_MWID_Pos) /*!< 0x00000010 */ |
||
| 3471 | #define FSMC_BCRx_MWID_1 (0x2U << FSMC_BCRx_MWID_Pos) /*!< 0x00000020 */ |
||
| 3472 | |||
| 3473 | #define FSMC_BCRx_FACCEN_Pos (6U) |
||
| 3474 | #define FSMC_BCRx_FACCEN_Msk (0x1U << FSMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */ |
||
| 3475 | #define FSMC_BCRx_FACCEN FSMC_BCRx_FACCEN_Msk /*!< Flash access enable */ |
||
| 3476 | #define FSMC_BCRx_BURSTEN_Pos (8U) |
||
| 3477 | #define FSMC_BCRx_BURSTEN_Msk (0x1U << FSMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */ |
||
| 3478 | #define FSMC_BCRx_BURSTEN FSMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */ |
||
| 3479 | #define FSMC_BCRx_WAITPOL_Pos (9U) |
||
| 3480 | #define FSMC_BCRx_WAITPOL_Msk (0x1U << FSMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */ |
||
| 3481 | #define FSMC_BCRx_WAITPOL FSMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */ |
||
| 3482 | #define FSMC_BCRx_WRAPMOD_Pos (10U) |
||
| 3483 | #define FSMC_BCRx_WRAPMOD_Msk (0x1U << FSMC_BCRx_WRAPMOD_Pos) /*!< 0x00000400 */ |
||
| 3484 | #define FSMC_BCRx_WRAPMOD FSMC_BCRx_WRAPMOD_Msk /*!< Wrapped burst mode support */ |
||
| 3485 | #define FSMC_BCRx_WAITCFG_Pos (11U) |
||
| 3486 | #define FSMC_BCRx_WAITCFG_Msk (0x1U << FSMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */ |
||
| 3487 | #define FSMC_BCRx_WAITCFG FSMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */ |
||
| 3488 | #define FSMC_BCRx_WREN_Pos (12U) |
||
| 3489 | #define FSMC_BCRx_WREN_Msk (0x1U << FSMC_BCRx_WREN_Pos) /*!< 0x00001000 */ |
||
| 3490 | #define FSMC_BCRx_WREN FSMC_BCRx_WREN_Msk /*!< Write enable bit */ |
||
| 3491 | #define FSMC_BCRx_WAITEN_Pos (13U) |
||
| 3492 | #define FSMC_BCRx_WAITEN_Msk (0x1U << FSMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */ |
||
| 3493 | #define FSMC_BCRx_WAITEN FSMC_BCRx_WAITEN_Msk /*!< Wait enable bit */ |
||
| 3494 | #define FSMC_BCRx_EXTMOD_Pos (14U) |
||
| 3495 | #define FSMC_BCRx_EXTMOD_Msk (0x1U << FSMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ |
||
| 3496 | #define FSMC_BCRx_EXTMOD FSMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */ |
||
| 3497 | #define FSMC_BCRx_ASYNCWAIT_Pos (15U) |
||
| 3498 | #define FSMC_BCRx_ASYNCWAIT_Msk (0x1U << FSMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
||
| 3499 | #define FSMC_BCRx_ASYNCWAIT FSMC_BCRx_ASYNCWAIT_Msk /*!< Asynchronous wait */ |
||
| 3500 | #define FSMC_BCRx_CBURSTRW_Pos (19U) |
||
| 3501 | #define FSMC_BCRx_CBURSTRW_Msk (0x1U << FSMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ |
||
| 3502 | #define FSMC_BCRx_CBURSTRW FSMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */ |
||
| 3503 | |||
| 3504 | /****************** Bit definition for FSMC_BTRx register (x=1..4) ******************/ |
||
| 3505 | #define FSMC_BTRx_ADDSET_Pos (0U) |
||
| 3506 | #define FSMC_BTRx_ADDSET_Msk (0xFU << FSMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */ |
||
| 3507 | #define FSMC_BTRx_ADDSET FSMC_BTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
||
| 3508 | #define FSMC_BTRx_ADDSET_0 (0x1U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */ |
||
| 3509 | #define FSMC_BTRx_ADDSET_1 (0x2U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */ |
||
| 3510 | #define FSMC_BTRx_ADDSET_2 (0x4U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */ |
||
| 3511 | #define FSMC_BTRx_ADDSET_3 (0x8U << FSMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */ |
||
| 3512 | |||
| 3513 | #define FSMC_BTRx_ADDHLD_Pos (4U) |
||
| 3514 | #define FSMC_BTRx_ADDHLD_Msk (0xFU << FSMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */ |
||
| 3515 | #define FSMC_BTRx_ADDHLD FSMC_BTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
||
| 3516 | #define FSMC_BTRx_ADDHLD_0 (0x1U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */ |
||
| 3517 | #define FSMC_BTRx_ADDHLD_1 (0x2U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */ |
||
| 3518 | #define FSMC_BTRx_ADDHLD_2 (0x4U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */ |
||
| 3519 | #define FSMC_BTRx_ADDHLD_3 (0x8U << FSMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */ |
||
| 3520 | |||
| 3521 | #define FSMC_BTRx_DATAST_Pos (8U) |
||
| 3522 | #define FSMC_BTRx_DATAST_Msk (0xFFU << FSMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */ |
||
| 3523 | #define FSMC_BTRx_DATAST FSMC_BTRx_DATAST_Msk /*!< DATAST [7:0] bits (Data-phase duration) */ |
||
| 3524 | #define FSMC_BTRx_DATAST_0 (0x01U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000100 */ |
||
| 3525 | #define FSMC_BTRx_DATAST_1 (0x02U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000200 */ |
||
| 3526 | #define FSMC_BTRx_DATAST_2 (0x04U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000400 */ |
||
| 3527 | #define FSMC_BTRx_DATAST_3 (0x08U << FSMC_BTRx_DATAST_Pos) /*!< 0x00000800 */ |
||
| 3528 | #define FSMC_BTRx_DATAST_4 (0x10U << FSMC_BTRx_DATAST_Pos) /*!< 0x00001000 */ |
||
| 3529 | #define FSMC_BTRx_DATAST_5 (0x20U << FSMC_BTRx_DATAST_Pos) /*!< 0x00002000 */ |
||
| 3530 | #define FSMC_BTRx_DATAST_6 (0x40U << FSMC_BTRx_DATAST_Pos) /*!< 0x00004000 */ |
||
| 3531 | #define FSMC_BTRx_DATAST_7 (0x80U << FSMC_BTRx_DATAST_Pos) /*!< 0x00008000 */ |
||
| 3532 | |||
| 3533 | #define FSMC_BTRx_BUSTURN_Pos (16U) |
||
| 3534 | #define FSMC_BTRx_BUSTURN_Msk (0xFU << FSMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */ |
||
| 3535 | #define FSMC_BTRx_BUSTURN FSMC_BTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
||
| 3536 | #define FSMC_BTRx_BUSTURN_0 (0x1U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */ |
||
| 3537 | #define FSMC_BTRx_BUSTURN_1 (0x2U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */ |
||
| 3538 | #define FSMC_BTRx_BUSTURN_2 (0x4U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */ |
||
| 3539 | #define FSMC_BTRx_BUSTURN_3 (0x8U << FSMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */ |
||
| 3540 | |||
| 3541 | #define FSMC_BTRx_CLKDIV_Pos (20U) |
||
| 3542 | #define FSMC_BTRx_CLKDIV_Msk (0xFU << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */ |
||
| 3543 | #define FSMC_BTRx_CLKDIV FSMC_BTRx_CLKDIV_Msk /*!< CLKDIV[3:0] bits (Clock divide ratio) */ |
||
| 3544 | #define FSMC_BTRx_CLKDIV_0 (0x1U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */ |
||
| 3545 | #define FSMC_BTRx_CLKDIV_1 (0x2U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */ |
||
| 3546 | #define FSMC_BTRx_CLKDIV_2 (0x4U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */ |
||
| 3547 | #define FSMC_BTRx_CLKDIV_3 (0x8U << FSMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */ |
||
| 3548 | |||
| 3549 | #define FSMC_BTRx_DATLAT_Pos (24U) |
||
| 3550 | #define FSMC_BTRx_DATLAT_Msk (0xFU << FSMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */ |
||
| 3551 | #define FSMC_BTRx_DATLAT FSMC_BTRx_DATLAT_Msk /*!< DATLA[3:0] bits (Data latency) */ |
||
| 3552 | #define FSMC_BTRx_DATLAT_0 (0x1U << FSMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */ |
||
| 3553 | #define FSMC_BTRx_DATLAT_1 (0x2U << FSMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */ |
||
| 3554 | #define FSMC_BTRx_DATLAT_2 (0x4U << FSMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */ |
||
| 3555 | #define FSMC_BTRx_DATLAT_3 (0x8U << FSMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */ |
||
| 3556 | |||
| 3557 | #define FSMC_BTRx_ACCMOD_Pos (28U) |
||
| 3558 | #define FSMC_BTRx_ACCMOD_Msk (0x3U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */ |
||
| 3559 | #define FSMC_BTRx_ACCMOD FSMC_BTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ |
||
| 3560 | #define FSMC_BTRx_ACCMOD_0 (0x1U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */ |
||
| 3561 | #define FSMC_BTRx_ACCMOD_1 (0x2U << FSMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */ |
||
| 3562 | |||
| 3563 | /****************** Bit definition for FSMC_BWTRx register (x=1..4) ******************/ |
||
| 3564 | #define FSMC_BWTRx_ADDSET_Pos (0U) |
||
| 3565 | #define FSMC_BWTRx_ADDSET_Msk (0xFU << FSMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */ |
||
| 3566 | #define FSMC_BWTRx_ADDSET FSMC_BWTRx_ADDSET_Msk /*!< ADDSET[3:0] bits (Address setup phase duration) */ |
||
| 3567 | #define FSMC_BWTRx_ADDSET_0 (0x1U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */ |
||
| 3568 | #define FSMC_BWTRx_ADDSET_1 (0x2U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */ |
||
| 3569 | #define FSMC_BWTRx_ADDSET_2 (0x4U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */ |
||
| 3570 | #define FSMC_BWTRx_ADDSET_3 (0x8U << FSMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */ |
||
| 3571 | |||
| 3572 | #define FSMC_BWTRx_ADDHLD_Pos (4U) |
||
| 3573 | #define FSMC_BWTRx_ADDHLD_Msk (0xFU << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */ |
||
| 3574 | #define FSMC_BWTRx_ADDHLD FSMC_BWTRx_ADDHLD_Msk /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ |
||
| 3575 | #define FSMC_BWTRx_ADDHLD_0 (0x1U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */ |
||
| 3576 | #define FSMC_BWTRx_ADDHLD_1 (0x2U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */ |
||
| 3577 | #define FSMC_BWTRx_ADDHLD_2 (0x4U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */ |
||
| 3578 | #define FSMC_BWTRx_ADDHLD_3 (0x8U << FSMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */ |
||
| 3579 | |||
| 3580 | #define FSMC_BWTRx_DATAST_Pos (8U) |
||
| 3581 | #define FSMC_BWTRx_DATAST_Msk (0xFFU << FSMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */ |
||
| 3582 | #define FSMC_BWTRx_DATAST FSMC_BWTRx_DATAST_Msk /*!< DATAST [7:0] bits (Data-phase duration) */ |
||
| 3583 | #define FSMC_BWTRx_DATAST_0 (0x01U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */ |
||
| 3584 | #define FSMC_BWTRx_DATAST_1 (0x02U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */ |
||
| 3585 | #define FSMC_BWTRx_DATAST_2 (0x04U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */ |
||
| 3586 | #define FSMC_BWTRx_DATAST_3 (0x08U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */ |
||
| 3587 | #define FSMC_BWTRx_DATAST_4 (0x10U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */ |
||
| 3588 | #define FSMC_BWTRx_DATAST_5 (0x20U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */ |
||
| 3589 | #define FSMC_BWTRx_DATAST_6 (0x40U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */ |
||
| 3590 | #define FSMC_BWTRx_DATAST_7 (0x80U << FSMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */ |
||
| 3591 | |||
| 3592 | #define FSMC_BWTRx_BUSTURN_Pos (16U) |
||
| 3593 | #define FSMC_BWTRx_BUSTURN_Msk (0xFU << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */ |
||
| 3594 | #define FSMC_BWTRx_BUSTURN FSMC_BWTRx_BUSTURN_Msk /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
||
| 3595 | #define FSMC_BWTRx_BUSTURN_0 (0x1U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */ |
||
| 3596 | #define FSMC_BWTRx_BUSTURN_1 (0x2U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */ |
||
| 3597 | #define FSMC_BWTRx_BUSTURN_2 (0x4U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */ |
||
| 3598 | #define FSMC_BWTRx_BUSTURN_3 (0x8U << FSMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */ |
||
| 3599 | |||
| 3600 | #define FSMC_BWTRx_ACCMOD_Pos (28U) |
||
| 3601 | #define FSMC_BWTRx_ACCMOD_Msk (0x3U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */ |
||
| 3602 | #define FSMC_BWTRx_ACCMOD FSMC_BWTRx_ACCMOD_Msk /*!< ACCMOD[1:0] bits (Access mode) */ |
||
| 3603 | #define FSMC_BWTRx_ACCMOD_0 (0x1U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */ |
||
| 3604 | #define FSMC_BWTRx_ACCMOD_1 (0x2U << FSMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */ |
||
| 3605 | |||
| 3606 | /******************************************************************************/ |
||
| 3607 | /* */ |
||
| 3608 | /* General Purpose I/O */ |
||
| 3609 | /* */ |
||
| 3610 | /******************************************************************************/ |
||
| 3611 | /****************** Bits definition for GPIO_MODER register *****************/ |
||
| 3612 | #define GPIO_MODER_MODER0_Pos (0U) |
||
| 3613 | #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ |
||
| 3614 | #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk |
||
| 3615 | #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ |
||
| 3616 | #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ |
||
| 3617 | |||
| 3618 | #define GPIO_MODER_MODER1_Pos (2U) |
||
| 3619 | #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ |
||
| 3620 | #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk |
||
| 3621 | #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ |
||
| 3622 | #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ |
||
| 3623 | |||
| 3624 | #define GPIO_MODER_MODER2_Pos (4U) |
||
| 3625 | #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ |
||
| 3626 | #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk |
||
| 3627 | #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ |
||
| 3628 | #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ |
||
| 3629 | |||
| 3630 | #define GPIO_MODER_MODER3_Pos (6U) |
||
| 3631 | #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ |
||
| 3632 | #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk |
||
| 3633 | #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ |
||
| 3634 | #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ |
||
| 3635 | |||
| 3636 | #define GPIO_MODER_MODER4_Pos (8U) |
||
| 3637 | #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ |
||
| 3638 | #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk |
||
| 3639 | #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ |
||
| 3640 | #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ |
||
| 3641 | |||
| 3642 | #define GPIO_MODER_MODER5_Pos (10U) |
||
| 3643 | #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ |
||
| 3644 | #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk |
||
| 3645 | #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ |
||
| 3646 | #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ |
||
| 3647 | |||
| 3648 | #define GPIO_MODER_MODER6_Pos (12U) |
||
| 3649 | #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ |
||
| 3650 | #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk |
||
| 3651 | #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ |
||
| 3652 | #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ |
||
| 3653 | |||
| 3654 | #define GPIO_MODER_MODER7_Pos (14U) |
||
| 3655 | #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ |
||
| 3656 | #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk |
||
| 3657 | #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ |
||
| 3658 | #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ |
||
| 3659 | |||
| 3660 | #define GPIO_MODER_MODER8_Pos (16U) |
||
| 3661 | #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ |
||
| 3662 | #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk |
||
| 3663 | #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ |
||
| 3664 | #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ |
||
| 3665 | |||
| 3666 | #define GPIO_MODER_MODER9_Pos (18U) |
||
| 3667 | #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ |
||
| 3668 | #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk |
||
| 3669 | #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ |
||
| 3670 | #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ |
||
| 3671 | |||
| 3672 | #define GPIO_MODER_MODER10_Pos (20U) |
||
| 3673 | #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ |
||
| 3674 | #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk |
||
| 3675 | #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ |
||
| 3676 | #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ |
||
| 3677 | |||
| 3678 | #define GPIO_MODER_MODER11_Pos (22U) |
||
| 3679 | #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ |
||
| 3680 | #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk |
||
| 3681 | #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ |
||
| 3682 | #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ |
||
| 3683 | |||
| 3684 | #define GPIO_MODER_MODER12_Pos (24U) |
||
| 3685 | #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ |
||
| 3686 | #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk |
||
| 3687 | #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ |
||
| 3688 | #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ |
||
| 3689 | |||
| 3690 | #define GPIO_MODER_MODER13_Pos (26U) |
||
| 3691 | #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ |
||
| 3692 | #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk |
||
| 3693 | #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ |
||
| 3694 | #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ |
||
| 3695 | |||
| 3696 | #define GPIO_MODER_MODER14_Pos (28U) |
||
| 3697 | #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ |
||
| 3698 | #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk |
||
| 3699 | #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ |
||
| 3700 | #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ |
||
| 3701 | |||
| 3702 | #define GPIO_MODER_MODER15_Pos (30U) |
||
| 3703 | #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ |
||
| 3704 | #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk |
||
| 3705 | #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ |
||
| 3706 | #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ |
||
| 3707 | |||
| 3708 | /****************** Bits definition for GPIO_OTYPER register ****************/ |
||
| 3709 | #define GPIO_OTYPER_OT_0 (0x00000001U) |
||
| 3710 | #define GPIO_OTYPER_OT_1 (0x00000002U) |
||
| 3711 | #define GPIO_OTYPER_OT_2 (0x00000004U) |
||
| 3712 | #define GPIO_OTYPER_OT_3 (0x00000008U) |
||
| 3713 | #define GPIO_OTYPER_OT_4 (0x00000010U) |
||
| 3714 | #define GPIO_OTYPER_OT_5 (0x00000020U) |
||
| 3715 | #define GPIO_OTYPER_OT_6 (0x00000040U) |
||
| 3716 | #define GPIO_OTYPER_OT_7 (0x00000080U) |
||
| 3717 | #define GPIO_OTYPER_OT_8 (0x00000100U) |
||
| 3718 | #define GPIO_OTYPER_OT_9 (0x00000200U) |
||
| 3719 | #define GPIO_OTYPER_OT_10 (0x00000400U) |
||
| 3720 | #define GPIO_OTYPER_OT_11 (0x00000800U) |
||
| 3721 | #define GPIO_OTYPER_OT_12 (0x00001000U) |
||
| 3722 | #define GPIO_OTYPER_OT_13 (0x00002000U) |
||
| 3723 | #define GPIO_OTYPER_OT_14 (0x00004000U) |
||
| 3724 | #define GPIO_OTYPER_OT_15 (0x00008000U) |
||
| 3725 | |||
| 3726 | /****************** Bits definition for GPIO_OSPEEDR register ***************/ |
||
| 3727 | #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) |
||
| 3728 | #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ |
||
| 3729 | #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk |
||
| 3730 | #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ |
||
| 3731 | #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ |
||
| 3732 | |||
| 3733 | #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) |
||
| 3734 | #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ |
||
| 3735 | #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk |
||
| 3736 | #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ |
||
| 3737 | #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ |
||
| 3738 | |||
| 3739 | #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) |
||
| 3740 | #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ |
||
| 3741 | #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk |
||
| 3742 | #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ |
||
| 3743 | #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ |
||
| 3744 | |||
| 3745 | #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) |
||
| 3746 | #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ |
||
| 3747 | #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk |
||
| 3748 | #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ |
||
| 3749 | #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ |
||
| 3750 | |||
| 3751 | #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) |
||
| 3752 | #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ |
||
| 3753 | #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk |
||
| 3754 | #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ |
||
| 3755 | #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ |
||
| 3756 | |||
| 3757 | #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) |
||
| 3758 | #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ |
||
| 3759 | #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk |
||
| 3760 | #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ |
||
| 3761 | #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ |
||
| 3762 | |||
| 3763 | #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) |
||
| 3764 | #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ |
||
| 3765 | #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk |
||
| 3766 | #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ |
||
| 3767 | #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ |
||
| 3768 | |||
| 3769 | #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) |
||
| 3770 | #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ |
||
| 3771 | #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk |
||
| 3772 | #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ |
||
| 3773 | #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ |
||
| 3774 | |||
| 3775 | #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) |
||
| 3776 | #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ |
||
| 3777 | #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk |
||
| 3778 | #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ |
||
| 3779 | #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ |
||
| 3780 | |||
| 3781 | #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) |
||
| 3782 | #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ |
||
| 3783 | #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk |
||
| 3784 | #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ |
||
| 3785 | #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ |
||
| 3786 | |||
| 3787 | #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) |
||
| 3788 | #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ |
||
| 3789 | #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk |
||
| 3790 | #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ |
||
| 3791 | #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ |
||
| 3792 | |||
| 3793 | #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) |
||
| 3794 | #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ |
||
| 3795 | #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk |
||
| 3796 | #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ |
||
| 3797 | #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ |
||
| 3798 | |||
| 3799 | #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) |
||
| 3800 | #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ |
||
| 3801 | #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk |
||
| 3802 | #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ |
||
| 3803 | #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ |
||
| 3804 | |||
| 3805 | #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) |
||
| 3806 | #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ |
||
| 3807 | #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk |
||
| 3808 | #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ |
||
| 3809 | #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ |
||
| 3810 | |||
| 3811 | #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) |
||
| 3812 | #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ |
||
| 3813 | #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk |
||
| 3814 | #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ |
||
| 3815 | #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ |
||
| 3816 | |||
| 3817 | #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) |
||
| 3818 | #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ |
||
| 3819 | #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk |
||
| 3820 | #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ |
||
| 3821 | #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ |
||
| 3822 | |||
| 3823 | /****************** Bits definition for GPIO_PUPDR register *****************/ |
||
| 3824 | #define GPIO_PUPDR_PUPDR0_Pos (0U) |
||
| 3825 | #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ |
||
| 3826 | #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk |
||
| 3827 | #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ |
||
| 3828 | #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ |
||
| 3829 | |||
| 3830 | #define GPIO_PUPDR_PUPDR1_Pos (2U) |
||
| 3831 | #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ |
||
| 3832 | #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk |
||
| 3833 | #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ |
||
| 3834 | #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ |
||
| 3835 | |||
| 3836 | #define GPIO_PUPDR_PUPDR2_Pos (4U) |
||
| 3837 | #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ |
||
| 3838 | #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk |
||
| 3839 | #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ |
||
| 3840 | #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ |
||
| 3841 | |||
| 3842 | #define GPIO_PUPDR_PUPDR3_Pos (6U) |
||
| 3843 | #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ |
||
| 3844 | #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk |
||
| 3845 | #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ |
||
| 3846 | #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ |
||
| 3847 | |||
| 3848 | #define GPIO_PUPDR_PUPDR4_Pos (8U) |
||
| 3849 | #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ |
||
| 3850 | #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk |
||
| 3851 | #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ |
||
| 3852 | #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ |
||
| 3853 | |||
| 3854 | #define GPIO_PUPDR_PUPDR5_Pos (10U) |
||
| 3855 | #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ |
||
| 3856 | #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk |
||
| 3857 | #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ |
||
| 3858 | #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ |
||
| 3859 | |||
| 3860 | #define GPIO_PUPDR_PUPDR6_Pos (12U) |
||
| 3861 | #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ |
||
| 3862 | #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk |
||
| 3863 | #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ |
||
| 3864 | #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ |
||
| 3865 | |||
| 3866 | #define GPIO_PUPDR_PUPDR7_Pos (14U) |
||
| 3867 | #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ |
||
| 3868 | #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk |
||
| 3869 | #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ |
||
| 3870 | #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ |
||
| 3871 | |||
| 3872 | #define GPIO_PUPDR_PUPDR8_Pos (16U) |
||
| 3873 | #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ |
||
| 3874 | #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk |
||
| 3875 | #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ |
||
| 3876 | #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ |
||
| 3877 | |||
| 3878 | #define GPIO_PUPDR_PUPDR9_Pos (18U) |
||
| 3879 | #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ |
||
| 3880 | #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk |
||
| 3881 | #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ |
||
| 3882 | #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ |
||
| 3883 | |||
| 3884 | #define GPIO_PUPDR_PUPDR10_Pos (20U) |
||
| 3885 | #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ |
||
| 3886 | #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk |
||
| 3887 | #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ |
||
| 3888 | #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ |
||
| 3889 | |||
| 3890 | #define GPIO_PUPDR_PUPDR11_Pos (22U) |
||
| 3891 | #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ |
||
| 3892 | #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk |
||
| 3893 | #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ |
||
| 3894 | #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ |
||
| 3895 | |||
| 3896 | #define GPIO_PUPDR_PUPDR12_Pos (24U) |
||
| 3897 | #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ |
||
| 3898 | #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk |
||
| 3899 | #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ |
||
| 3900 | #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ |
||
| 3901 | |||
| 3902 | #define GPIO_PUPDR_PUPDR13_Pos (26U) |
||
| 3903 | #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ |
||
| 3904 | #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk |
||
| 3905 | #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ |
||
| 3906 | #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ |
||
| 3907 | |||
| 3908 | #define GPIO_PUPDR_PUPDR14_Pos (28U) |
||
| 3909 | #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ |
||
| 3910 | #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk |
||
| 3911 | #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ |
||
| 3912 | #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ |
||
| 3913 | #define GPIO_PUPDR_PUPDR15_Pos (30U) |
||
| 3914 | #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ |
||
| 3915 | #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk |
||
| 3916 | #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ |
||
| 3917 | #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ |
||
| 3918 | |||
| 3919 | /****************** Bits definition for GPIO_IDR register *******************/ |
||
| 3920 | #define GPIO_IDR_IDR_0 (0x00000001U) |
||
| 3921 | #define GPIO_IDR_IDR_1 (0x00000002U) |
||
| 3922 | #define GPIO_IDR_IDR_2 (0x00000004U) |
||
| 3923 | #define GPIO_IDR_IDR_3 (0x00000008U) |
||
| 3924 | #define GPIO_IDR_IDR_4 (0x00000010U) |
||
| 3925 | #define GPIO_IDR_IDR_5 (0x00000020U) |
||
| 3926 | #define GPIO_IDR_IDR_6 (0x00000040U) |
||
| 3927 | #define GPIO_IDR_IDR_7 (0x00000080U) |
||
| 3928 | #define GPIO_IDR_IDR_8 (0x00000100U) |
||
| 3929 | #define GPIO_IDR_IDR_9 (0x00000200U) |
||
| 3930 | #define GPIO_IDR_IDR_10 (0x00000400U) |
||
| 3931 | #define GPIO_IDR_IDR_11 (0x00000800U) |
||
| 3932 | #define GPIO_IDR_IDR_12 (0x00001000U) |
||
| 3933 | #define GPIO_IDR_IDR_13 (0x00002000U) |
||
| 3934 | #define GPIO_IDR_IDR_14 (0x00004000U) |
||
| 3935 | #define GPIO_IDR_IDR_15 (0x00008000U) |
||
| 3936 | |||
| 3937 | /****************** Bits definition for GPIO_ODR register *******************/ |
||
| 3938 | #define GPIO_ODR_ODR_0 (0x00000001U) |
||
| 3939 | #define GPIO_ODR_ODR_1 (0x00000002U) |
||
| 3940 | #define GPIO_ODR_ODR_2 (0x00000004U) |
||
| 3941 | #define GPIO_ODR_ODR_3 (0x00000008U) |
||
| 3942 | #define GPIO_ODR_ODR_4 (0x00000010U) |
||
| 3943 | #define GPIO_ODR_ODR_5 (0x00000020U) |
||
| 3944 | #define GPIO_ODR_ODR_6 (0x00000040U) |
||
| 3945 | #define GPIO_ODR_ODR_7 (0x00000080U) |
||
| 3946 | #define GPIO_ODR_ODR_8 (0x00000100U) |
||
| 3947 | #define GPIO_ODR_ODR_9 (0x00000200U) |
||
| 3948 | #define GPIO_ODR_ODR_10 (0x00000400U) |
||
| 3949 | #define GPIO_ODR_ODR_11 (0x00000800U) |
||
| 3950 | #define GPIO_ODR_ODR_12 (0x00001000U) |
||
| 3951 | #define GPIO_ODR_ODR_13 (0x00002000U) |
||
| 3952 | #define GPIO_ODR_ODR_14 (0x00004000U) |
||
| 3953 | #define GPIO_ODR_ODR_15 (0x00008000U) |
||
| 3954 | |||
| 3955 | /****************** Bits definition for GPIO_BSRR register ******************/ |
||
| 3956 | #define GPIO_BSRR_BS_0 (0x00000001U) |
||
| 3957 | #define GPIO_BSRR_BS_1 (0x00000002U) |
||
| 3958 | #define GPIO_BSRR_BS_2 (0x00000004U) |
||
| 3959 | #define GPIO_BSRR_BS_3 (0x00000008U) |
||
| 3960 | #define GPIO_BSRR_BS_4 (0x00000010U) |
||
| 3961 | #define GPIO_BSRR_BS_5 (0x00000020U) |
||
| 3962 | #define GPIO_BSRR_BS_6 (0x00000040U) |
||
| 3963 | #define GPIO_BSRR_BS_7 (0x00000080U) |
||
| 3964 | #define GPIO_BSRR_BS_8 (0x00000100U) |
||
| 3965 | #define GPIO_BSRR_BS_9 (0x00000200U) |
||
| 3966 | #define GPIO_BSRR_BS_10 (0x00000400U) |
||
| 3967 | #define GPIO_BSRR_BS_11 (0x00000800U) |
||
| 3968 | #define GPIO_BSRR_BS_12 (0x00001000U) |
||
| 3969 | #define GPIO_BSRR_BS_13 (0x00002000U) |
||
| 3970 | #define GPIO_BSRR_BS_14 (0x00004000U) |
||
| 3971 | #define GPIO_BSRR_BS_15 (0x00008000U) |
||
| 3972 | #define GPIO_BSRR_BR_0 (0x00010000U) |
||
| 3973 | #define GPIO_BSRR_BR_1 (0x00020000U) |
||
| 3974 | #define GPIO_BSRR_BR_2 (0x00040000U) |
||
| 3975 | #define GPIO_BSRR_BR_3 (0x00080000U) |
||
| 3976 | #define GPIO_BSRR_BR_4 (0x00100000U) |
||
| 3977 | #define GPIO_BSRR_BR_5 (0x00200000U) |
||
| 3978 | #define GPIO_BSRR_BR_6 (0x00400000U) |
||
| 3979 | #define GPIO_BSRR_BR_7 (0x00800000U) |
||
| 3980 | #define GPIO_BSRR_BR_8 (0x01000000U) |
||
| 3981 | #define GPIO_BSRR_BR_9 (0x02000000U) |
||
| 3982 | #define GPIO_BSRR_BR_10 (0x04000000U) |
||
| 3983 | #define GPIO_BSRR_BR_11 (0x08000000U) |
||
| 3984 | #define GPIO_BSRR_BR_12 (0x10000000U) |
||
| 3985 | #define GPIO_BSRR_BR_13 (0x20000000U) |
||
| 3986 | #define GPIO_BSRR_BR_14 (0x40000000U) |
||
| 3987 | #define GPIO_BSRR_BR_15 (0x80000000U) |
||
| 3988 | |||
| 3989 | /****************** Bit definition for GPIO_LCKR register ********************/ |
||
| 3990 | #define GPIO_LCKR_LCK0_Pos (0U) |
||
| 3991 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
||
| 3992 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
||
| 3993 | #define GPIO_LCKR_LCK1_Pos (1U) |
||
| 3994 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
||
| 3995 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
||
| 3996 | #define GPIO_LCKR_LCK2_Pos (2U) |
||
| 3997 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
||
| 3998 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
||
| 3999 | #define GPIO_LCKR_LCK3_Pos (3U) |
||
| 4000 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
||
| 4001 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
||
| 4002 | #define GPIO_LCKR_LCK4_Pos (4U) |
||
| 4003 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
||
| 4004 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
||
| 4005 | #define GPIO_LCKR_LCK5_Pos (5U) |
||
| 4006 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
||
| 4007 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
||
| 4008 | #define GPIO_LCKR_LCK6_Pos (6U) |
||
| 4009 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
||
| 4010 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
||
| 4011 | #define GPIO_LCKR_LCK7_Pos (7U) |
||
| 4012 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
||
| 4013 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
||
| 4014 | #define GPIO_LCKR_LCK8_Pos (8U) |
||
| 4015 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
||
| 4016 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
||
| 4017 | #define GPIO_LCKR_LCK9_Pos (9U) |
||
| 4018 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
||
| 4019 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
||
| 4020 | #define GPIO_LCKR_LCK10_Pos (10U) |
||
| 4021 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
||
| 4022 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
||
| 4023 | #define GPIO_LCKR_LCK11_Pos (11U) |
||
| 4024 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
||
| 4025 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
||
| 4026 | #define GPIO_LCKR_LCK12_Pos (12U) |
||
| 4027 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
||
| 4028 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
||
| 4029 | #define GPIO_LCKR_LCK13_Pos (13U) |
||
| 4030 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
||
| 4031 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
||
| 4032 | #define GPIO_LCKR_LCK14_Pos (14U) |
||
| 4033 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
||
| 4034 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
||
| 4035 | #define GPIO_LCKR_LCK15_Pos (15U) |
||
| 4036 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
||
| 4037 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
||
| 4038 | #define GPIO_LCKR_LCKK_Pos (16U) |
||
| 4039 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
||
| 4040 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
||
| 4041 | |||
| 4042 | /****************** Bit definition for GPIO_AFRL register ********************/ |
||
| 4043 | #define GPIO_AFRL_AFRL0_Pos (0U) |
||
| 4044 | #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ |
||
| 4045 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk |
||
| 4046 | #define GPIO_AFRL_AFRL1_Pos (4U) |
||
| 4047 | #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ |
||
| 4048 | #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk |
||
| 4049 | #define GPIO_AFRL_AFRL2_Pos (8U) |
||
| 4050 | #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ |
||
| 4051 | #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk |
||
| 4052 | #define GPIO_AFRL_AFRL3_Pos (12U) |
||
| 4053 | #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ |
||
| 4054 | #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk |
||
| 4055 | #define GPIO_AFRL_AFRL4_Pos (16U) |
||
| 4056 | #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ |
||
| 4057 | #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk |
||
| 4058 | #define GPIO_AFRL_AFRL5_Pos (20U) |
||
| 4059 | #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ |
||
| 4060 | #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk |
||
| 4061 | #define GPIO_AFRL_AFRL6_Pos (24U) |
||
| 4062 | #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ |
||
| 4063 | #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk |
||
| 4064 | #define GPIO_AFRL_AFRL7_Pos (28U) |
||
| 4065 | #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ |
||
| 4066 | #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk |
||
| 4067 | |||
| 4068 | /****************** Bit definition for GPIO_AFRH register ********************/ |
||
| 4069 | #define GPIO_AFRH_AFRH0_Pos (0U) |
||
| 4070 | #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ |
||
| 4071 | #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk |
||
| 4072 | #define GPIO_AFRH_AFRH1_Pos (4U) |
||
| 4073 | #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ |
||
| 4074 | #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk |
||
| 4075 | #define GPIO_AFRH_AFRH2_Pos (8U) |
||
| 4076 | #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ |
||
| 4077 | #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk |
||
| 4078 | #define GPIO_AFRH_AFRH3_Pos (12U) |
||
| 4079 | #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ |
||
| 4080 | #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk |
||
| 4081 | #define GPIO_AFRH_AFRH4_Pos (16U) |
||
| 4082 | #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ |
||
| 4083 | #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk |
||
| 4084 | #define GPIO_AFRH_AFRH5_Pos (20U) |
||
| 4085 | #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ |
||
| 4086 | #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk |
||
| 4087 | #define GPIO_AFRH_AFRH6_Pos (24U) |
||
| 4088 | #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ |
||
| 4089 | #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk |
||
| 4090 | #define GPIO_AFRH_AFRH7_Pos (28U) |
||
| 4091 | #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ |
||
| 4092 | #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk |
||
| 4093 | |||
| 4094 | /****************** Bit definition for GPIO_BRR register *********************/ |
||
| 4095 | #define GPIO_BRR_BR_0 (0x00000001U) |
||
| 4096 | #define GPIO_BRR_BR_1 (0x00000002U) |
||
| 4097 | #define GPIO_BRR_BR_2 (0x00000004U) |
||
| 4098 | #define GPIO_BRR_BR_3 (0x00000008U) |
||
| 4099 | #define GPIO_BRR_BR_4 (0x00000010U) |
||
| 4100 | #define GPIO_BRR_BR_5 (0x00000020U) |
||
| 4101 | #define GPIO_BRR_BR_6 (0x00000040U) |
||
| 4102 | #define GPIO_BRR_BR_7 (0x00000080U) |
||
| 4103 | #define GPIO_BRR_BR_8 (0x00000100U) |
||
| 4104 | #define GPIO_BRR_BR_9 (0x00000200U) |
||
| 4105 | #define GPIO_BRR_BR_10 (0x00000400U) |
||
| 4106 | #define GPIO_BRR_BR_11 (0x00000800U) |
||
| 4107 | #define GPIO_BRR_BR_12 (0x00001000U) |
||
| 4108 | #define GPIO_BRR_BR_13 (0x00002000U) |
||
| 4109 | #define GPIO_BRR_BR_14 (0x00004000U) |
||
| 4110 | #define GPIO_BRR_BR_15 (0x00008000U) |
||
| 4111 | |||
| 4112 | /******************************************************************************/ |
||
| 4113 | /* */ |
||
| 4114 | /* Inter-integrated Circuit Interface (I2C) */ |
||
| 4115 | /* */ |
||
| 4116 | /******************************************************************************/ |
||
| 4117 | |||
| 4118 | /******************* Bit definition for I2C_CR1 register ********************/ |
||
| 4119 | #define I2C_CR1_PE_Pos (0U) |
||
| 4120 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
||
| 4121 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ |
||
| 4122 | #define I2C_CR1_SMBUS_Pos (1U) |
||
| 4123 | #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ |
||
| 4124 | #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ |
||
| 4125 | #define I2C_CR1_SMBTYPE_Pos (3U) |
||
| 4126 | #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ |
||
| 4127 | #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ |
||
| 4128 | #define I2C_CR1_ENARP_Pos (4U) |
||
| 4129 | #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ |
||
| 4130 | #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ |
||
| 4131 | #define I2C_CR1_ENPEC_Pos (5U) |
||
| 4132 | #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ |
||
| 4133 | #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ |
||
| 4134 | #define I2C_CR1_ENGC_Pos (6U) |
||
| 4135 | #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ |
||
| 4136 | #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ |
||
| 4137 | #define I2C_CR1_NOSTRETCH_Pos (7U) |
||
| 4138 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ |
||
| 4139 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ |
||
| 4140 | #define I2C_CR1_START_Pos (8U) |
||
| 4141 | #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ |
||
| 4142 | #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ |
||
| 4143 | #define I2C_CR1_STOP_Pos (9U) |
||
| 4144 | #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ |
||
| 4145 | #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ |
||
| 4146 | #define I2C_CR1_ACK_Pos (10U) |
||
| 4147 | #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ |
||
| 4148 | #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ |
||
| 4149 | #define I2C_CR1_POS_Pos (11U) |
||
| 4150 | #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ |
||
| 4151 | #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ |
||
| 4152 | #define I2C_CR1_PEC_Pos (12U) |
||
| 4153 | #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ |
||
| 4154 | #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ |
||
| 4155 | #define I2C_CR1_ALERT_Pos (13U) |
||
| 4156 | #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ |
||
| 4157 | #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ |
||
| 4158 | #define I2C_CR1_SWRST_Pos (15U) |
||
| 4159 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ |
||
| 4160 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ |
||
| 4161 | |||
| 4162 | /******************* Bit definition for I2C_CR2 register ********************/ |
||
| 4163 | #define I2C_CR2_FREQ_Pos (0U) |
||
| 4164 | #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ |
||
| 4165 | #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
||
| 4166 | #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ |
||
| 4167 | #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ |
||
| 4168 | #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ |
||
| 4169 | #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ |
||
| 4170 | #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ |
||
| 4171 | #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ |
||
| 4172 | |||
| 4173 | #define I2C_CR2_ITERREN_Pos (8U) |
||
| 4174 | #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ |
||
| 4175 | #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ |
||
| 4176 | #define I2C_CR2_ITEVTEN_Pos (9U) |
||
| 4177 | #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ |
||
| 4178 | #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ |
||
| 4179 | #define I2C_CR2_ITBUFEN_Pos (10U) |
||
| 4180 | #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ |
||
| 4181 | #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ |
||
| 4182 | #define I2C_CR2_DMAEN_Pos (11U) |
||
| 4183 | #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ |
||
| 4184 | #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ |
||
| 4185 | #define I2C_CR2_LAST_Pos (12U) |
||
| 4186 | #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ |
||
| 4187 | #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ |
||
| 4188 | |||
| 4189 | /******************* Bit definition for I2C_OAR1 register *******************/ |
||
| 4190 | #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */ |
||
| 4191 | #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */ |
||
| 4192 | |||
| 4193 | #define I2C_OAR1_ADD0_Pos (0U) |
||
| 4194 | #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ |
||
| 4195 | #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ |
||
| 4196 | #define I2C_OAR1_ADD1_Pos (1U) |
||
| 4197 | #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ |
||
| 4198 | #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ |
||
| 4199 | #define I2C_OAR1_ADD2_Pos (2U) |
||
| 4200 | #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ |
||
| 4201 | #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ |
||
| 4202 | #define I2C_OAR1_ADD3_Pos (3U) |
||
| 4203 | #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ |
||
| 4204 | #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ |
||
| 4205 | #define I2C_OAR1_ADD4_Pos (4U) |
||
| 4206 | #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ |
||
| 4207 | #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ |
||
| 4208 | #define I2C_OAR1_ADD5_Pos (5U) |
||
| 4209 | #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ |
||
| 4210 | #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ |
||
| 4211 | #define I2C_OAR1_ADD6_Pos (6U) |
||
| 4212 | #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ |
||
| 4213 | #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ |
||
| 4214 | #define I2C_OAR1_ADD7_Pos (7U) |
||
| 4215 | #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ |
||
| 4216 | #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ |
||
| 4217 | #define I2C_OAR1_ADD8_Pos (8U) |
||
| 4218 | #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ |
||
| 4219 | #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ |
||
| 4220 | #define I2C_OAR1_ADD9_Pos (9U) |
||
| 4221 | #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ |
||
| 4222 | #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ |
||
| 4223 | |||
| 4224 | #define I2C_OAR1_ADDMODE_Pos (15U) |
||
| 4225 | #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ |
||
| 4226 | #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ |
||
| 4227 | |||
| 4228 | /******************* Bit definition for I2C_OAR2 register *******************/ |
||
| 4229 | #define I2C_OAR2_ENDUAL_Pos (0U) |
||
| 4230 | #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ |
||
| 4231 | #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ |
||
| 4232 | #define I2C_OAR2_ADD2_Pos (1U) |
||
| 4233 | #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ |
||
| 4234 | #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ |
||
| 4235 | |||
| 4236 | /******************** Bit definition for I2C_DR register ********************/ |
||
| 4237 | #define I2C_DR_DR_Pos (0U) |
||
| 4238 | #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ |
||
| 4239 | #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ |
||
| 4240 | |||
| 4241 | /******************* Bit definition for I2C_SR1 register ********************/ |
||
| 4242 | #define I2C_SR1_SB_Pos (0U) |
||
| 4243 | #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ |
||
| 4244 | #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ |
||
| 4245 | #define I2C_SR1_ADDR_Pos (1U) |
||
| 4246 | #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ |
||
| 4247 | #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ |
||
| 4248 | #define I2C_SR1_BTF_Pos (2U) |
||
| 4249 | #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ |
||
| 4250 | #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ |
||
| 4251 | #define I2C_SR1_ADD10_Pos (3U) |
||
| 4252 | #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ |
||
| 4253 | #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ |
||
| 4254 | #define I2C_SR1_STOPF_Pos (4U) |
||
| 4255 | #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ |
||
| 4256 | #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ |
||
| 4257 | #define I2C_SR1_RXNE_Pos (6U) |
||
| 4258 | #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ |
||
| 4259 | #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ |
||
| 4260 | #define I2C_SR1_TXE_Pos (7U) |
||
| 4261 | #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ |
||
| 4262 | #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ |
||
| 4263 | #define I2C_SR1_BERR_Pos (8U) |
||
| 4264 | #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ |
||
| 4265 | #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ |
||
| 4266 | #define I2C_SR1_ARLO_Pos (9U) |
||
| 4267 | #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ |
||
| 4268 | #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ |
||
| 4269 | #define I2C_SR1_AF_Pos (10U) |
||
| 4270 | #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ |
||
| 4271 | #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ |
||
| 4272 | #define I2C_SR1_OVR_Pos (11U) |
||
| 4273 | #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ |
||
| 4274 | #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ |
||
| 4275 | #define I2C_SR1_PECERR_Pos (12U) |
||
| 4276 | #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ |
||
| 4277 | #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ |
||
| 4278 | #define I2C_SR1_TIMEOUT_Pos (14U) |
||
| 4279 | #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ |
||
| 4280 | #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ |
||
| 4281 | #define I2C_SR1_SMBALERT_Pos (15U) |
||
| 4282 | #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ |
||
| 4283 | #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ |
||
| 4284 | |||
| 4285 | /******************* Bit definition for I2C_SR2 register ********************/ |
||
| 4286 | #define I2C_SR2_MSL_Pos (0U) |
||
| 4287 | #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ |
||
| 4288 | #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ |
||
| 4289 | #define I2C_SR2_BUSY_Pos (1U) |
||
| 4290 | #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ |
||
| 4291 | #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ |
||
| 4292 | #define I2C_SR2_TRA_Pos (2U) |
||
| 4293 | #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ |
||
| 4294 | #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ |
||
| 4295 | #define I2C_SR2_GENCALL_Pos (4U) |
||
| 4296 | #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ |
||
| 4297 | #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ |
||
| 4298 | #define I2C_SR2_SMBDEFAULT_Pos (5U) |
||
| 4299 | #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ |
||
| 4300 | #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ |
||
| 4301 | #define I2C_SR2_SMBHOST_Pos (6U) |
||
| 4302 | #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ |
||
| 4303 | #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ |
||
| 4304 | #define I2C_SR2_DUALF_Pos (7U) |
||
| 4305 | #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ |
||
| 4306 | #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ |
||
| 4307 | #define I2C_SR2_PEC_Pos (8U) |
||
| 4308 | #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ |
||
| 4309 | #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ |
||
| 4310 | |||
| 4311 | /******************* Bit definition for I2C_CCR register ********************/ |
||
| 4312 | #define I2C_CCR_CCR_Pos (0U) |
||
| 4313 | #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ |
||
| 4314 | #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
||
| 4315 | #define I2C_CCR_DUTY_Pos (14U) |
||
| 4316 | #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ |
||
| 4317 | #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ |
||
| 4318 | #define I2C_CCR_FS_Pos (15U) |
||
| 4319 | #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ |
||
| 4320 | #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ |
||
| 4321 | |||
| 4322 | /****************** Bit definition for I2C_TRISE register *******************/ |
||
| 4323 | #define I2C_TRISE_TRISE_Pos (0U) |
||
| 4324 | #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ |
||
| 4325 | #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
||
| 4326 | |||
| 4327 | /******************************************************************************/ |
||
| 4328 | /* */ |
||
| 4329 | /* Independent WATCHDOG (IWDG) */ |
||
| 4330 | /* */ |
||
| 4331 | /******************************************************************************/ |
||
| 4332 | |||
| 4333 | /******************* Bit definition for IWDG_KR register ********************/ |
||
| 4334 | #define IWDG_KR_KEY_Pos (0U) |
||
| 4335 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
||
| 4336 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ |
||
| 4337 | |||
| 4338 | /******************* Bit definition for IWDG_PR register ********************/ |
||
| 4339 | #define IWDG_PR_PR_Pos (0U) |
||
| 4340 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
||
| 4341 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ |
||
| 4342 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
||
| 4343 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
||
| 4344 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
||
| 4345 | |||
| 4346 | /******************* Bit definition for IWDG_RLR register *******************/ |
||
| 4347 | #define IWDG_RLR_RL_Pos (0U) |
||
| 4348 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
||
| 4349 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ |
||
| 4350 | |||
| 4351 | /******************* Bit definition for IWDG_SR register ********************/ |
||
| 4352 | #define IWDG_SR_PVU_Pos (0U) |
||
| 4353 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
||
| 4354 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
||
| 4355 | #define IWDG_SR_RVU_Pos (1U) |
||
| 4356 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
||
| 4357 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
||
| 4358 | |||
| 4359 | /******************************************************************************/ |
||
| 4360 | /* */ |
||
| 4361 | /* LCD Controller (LCD) */ |
||
| 4362 | /* */ |
||
| 4363 | /******************************************************************************/ |
||
| 4364 | |||
| 4365 | /******************* Bit definition for LCD_CR register *********************/ |
||
| 4366 | #define LCD_CR_LCDEN_Pos (0U) |
||
| 4367 | #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ |
||
| 4368 | #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ |
||
| 4369 | #define LCD_CR_VSEL_Pos (1U) |
||
| 4370 | #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ |
||
| 4371 | #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ |
||
| 4372 | |||
| 4373 | #define LCD_CR_DUTY_Pos (2U) |
||
| 4374 | #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ |
||
| 4375 | #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ |
||
| 4376 | #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ |
||
| 4377 | #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ |
||
| 4378 | #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ |
||
| 4379 | |||
| 4380 | #define LCD_CR_BIAS_Pos (5U) |
||
| 4381 | #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ |
||
| 4382 | #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ |
||
| 4383 | #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ |
||
| 4384 | #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ |
||
| 4385 | |||
| 4386 | #define LCD_CR_MUX_SEG_Pos (7U) |
||
| 4387 | #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ |
||
| 4388 | #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ |
||
| 4389 | |||
| 4390 | /******************* Bit definition for LCD_FCR register ********************/ |
||
| 4391 | #define LCD_FCR_HD_Pos (0U) |
||
| 4392 | #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */ |
||
| 4393 | #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ |
||
| 4394 | #define LCD_FCR_SOFIE_Pos (1U) |
||
| 4395 | #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ |
||
| 4396 | #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ |
||
| 4397 | #define LCD_FCR_UDDIE_Pos (3U) |
||
| 4398 | #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ |
||
| 4399 | #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ |
||
| 4400 | |||
| 4401 | #define LCD_FCR_PON_Pos (4U) |
||
| 4402 | #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */ |
||
| 4403 | #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ |
||
| 4404 | #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */ |
||
| 4405 | #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */ |
||
| 4406 | #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */ |
||
| 4407 | |||
| 4408 | #define LCD_FCR_DEAD_Pos (7U) |
||
| 4409 | #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ |
||
| 4410 | #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ |
||
| 4411 | #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ |
||
| 4412 | #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ |
||
| 4413 | #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ |
||
| 4414 | |||
| 4415 | #define LCD_FCR_CC_Pos (10U) |
||
| 4416 | #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ |
||
| 4417 | #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ |
||
| 4418 | #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */ |
||
| 4419 | #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */ |
||
| 4420 | #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */ |
||
| 4421 | |||
| 4422 | #define LCD_FCR_BLINKF_Pos (13U) |
||
| 4423 | #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ |
||
| 4424 | #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ |
||
| 4425 | #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ |
||
| 4426 | #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ |
||
| 4427 | #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ |
||
| 4428 | |||
| 4429 | #define LCD_FCR_BLINK_Pos (16U) |
||
| 4430 | #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ |
||
| 4431 | #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ |
||
| 4432 | #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ |
||
| 4433 | #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ |
||
| 4434 | |||
| 4435 | #define LCD_FCR_DIV_Pos (18U) |
||
| 4436 | #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ |
||
| 4437 | #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ |
||
| 4438 | #define LCD_FCR_PS_Pos (22U) |
||
| 4439 | #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ |
||
| 4440 | #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ |
||
| 4441 | |||
| 4442 | /******************* Bit definition for LCD_SR register *********************/ |
||
| 4443 | #define LCD_SR_ENS_Pos (0U) |
||
| 4444 | #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */ |
||
| 4445 | #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ |
||
| 4446 | #define LCD_SR_SOF_Pos (1U) |
||
| 4447 | #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */ |
||
| 4448 | #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ |
||
| 4449 | #define LCD_SR_UDR_Pos (2U) |
||
| 4450 | #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */ |
||
| 4451 | #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ |
||
| 4452 | #define LCD_SR_UDD_Pos (3U) |
||
| 4453 | #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */ |
||
| 4454 | #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ |
||
| 4455 | #define LCD_SR_RDY_Pos (4U) |
||
| 4456 | #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */ |
||
| 4457 | #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ |
||
| 4458 | #define LCD_SR_FCRSR_Pos (5U) |
||
| 4459 | #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ |
||
| 4460 | #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ |
||
| 4461 | |||
| 4462 | /******************* Bit definition for LCD_CLR register ********************/ |
||
| 4463 | #define LCD_CLR_SOFC_Pos (1U) |
||
| 4464 | #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ |
||
| 4465 | #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ |
||
| 4466 | #define LCD_CLR_UDDC_Pos (3U) |
||
| 4467 | #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ |
||
| 4468 | #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ |
||
| 4469 | |||
| 4470 | /******************* Bit definition for LCD_RAM register ********************/ |
||
| 4471 | #define LCD_RAM_SEGMENT_DATA_Pos (0U) |
||
| 4472 | #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ |
||
| 4473 | #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ |
||
| 4474 | |||
| 4475 | /******************************************************************************/ |
||
| 4476 | /* */ |
||
| 4477 | /* Power Control (PWR) */ |
||
| 4478 | /* */ |
||
| 4479 | /******************************************************************************/ |
||
| 4480 | |||
| 4481 | #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ |
||
| 4482 | |||
| 4483 | /******************** Bit definition for PWR_CR register ********************/ |
||
| 4484 | #define PWR_CR_LPSDSR_Pos (0U) |
||
| 4485 | #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ |
||
| 4486 | #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ |
||
| 4487 | #define PWR_CR_PDDS_Pos (1U) |
||
| 4488 | #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
||
| 4489 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
||
| 4490 | #define PWR_CR_CWUF_Pos (2U) |
||
| 4491 | #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
||
| 4492 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
||
| 4493 | #define PWR_CR_CSBF_Pos (3U) |
||
| 4494 | #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
||
| 4495 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
||
| 4496 | #define PWR_CR_PVDE_Pos (4U) |
||
| 4497 | #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
||
| 4498 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
||
| 4499 | |||
| 4500 | #define PWR_CR_PLS_Pos (5U) |
||
| 4501 | #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
||
| 4502 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
||
| 4503 | #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
||
| 4504 | #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
||
| 4505 | #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
||
| 4506 | |||
| 4507 | /*!< PVD level configuration */ |
||
| 4508 | #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ |
||
| 4509 | #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ |
||
| 4510 | #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ |
||
| 4511 | #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ |
||
| 4512 | #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ |
||
| 4513 | #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ |
||
| 4514 | #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ |
||
| 4515 | #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ |
||
| 4516 | |||
| 4517 | #define PWR_CR_DBP_Pos (8U) |
||
| 4518 | #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
||
| 4519 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
||
| 4520 | #define PWR_CR_ULP_Pos (9U) |
||
| 4521 | #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ |
||
| 4522 | #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ |
||
| 4523 | #define PWR_CR_FWU_Pos (10U) |
||
| 4524 | #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ |
||
| 4525 | #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ |
||
| 4526 | |||
| 4527 | #define PWR_CR_VOS_Pos (11U) |
||
| 4528 | #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ |
||
| 4529 | #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ |
||
| 4530 | #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ |
||
| 4531 | #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ |
||
| 4532 | #define PWR_CR_LPRUN_Pos (14U) |
||
| 4533 | #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ |
||
| 4534 | #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ |
||
| 4535 | |||
| 4536 | /******************* Bit definition for PWR_CSR register ********************/ |
||
| 4537 | #define PWR_CSR_WUF_Pos (0U) |
||
| 4538 | #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
||
| 4539 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
||
| 4540 | #define PWR_CSR_SBF_Pos (1U) |
||
| 4541 | #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
||
| 4542 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
||
| 4543 | #define PWR_CSR_PVDO_Pos (2U) |
||
| 4544 | #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
||
| 4545 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
||
| 4546 | #define PWR_CSR_VREFINTRDYF_Pos (3U) |
||
| 4547 | #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ |
||
| 4548 | #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ |
||
| 4549 | #define PWR_CSR_VOSF_Pos (4U) |
||
| 4550 | #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ |
||
| 4551 | #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ |
||
| 4552 | #define PWR_CSR_REGLPF_Pos (5U) |
||
| 4553 | #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ |
||
| 4554 | #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ |
||
| 4555 | |||
| 4556 | #define PWR_CSR_EWUP1_Pos (8U) |
||
| 4557 | #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ |
||
| 4558 | #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ |
||
| 4559 | #define PWR_CSR_EWUP2_Pos (9U) |
||
| 4560 | #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ |
||
| 4561 | #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ |
||
| 4562 | #define PWR_CSR_EWUP3_Pos (10U) |
||
| 4563 | #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ |
||
| 4564 | #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ |
||
| 4565 | |||
| 4566 | /******************************************************************************/ |
||
| 4567 | /* */ |
||
| 4568 | /* Reset and Clock Control (RCC) */ |
||
| 4569 | /* */ |
||
| 4570 | /******************************************************************************/ |
||
| 4571 | /* |
||
| 4572 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) |
||
| 4573 | */ |
||
| 4574 | #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */ |
||
| 4575 | |||
| 4576 | /******************** Bit definition for RCC_CR register ********************/ |
||
| 4577 | #define RCC_CR_HSION_Pos (0U) |
||
| 4578 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
||
| 4579 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ |
||
| 4580 | #define RCC_CR_HSIRDY_Pos (1U) |
||
| 4581 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
||
| 4582 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ |
||
| 4583 | |||
| 4584 | #define RCC_CR_MSION_Pos (8U) |
||
| 4585 | #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ |
||
| 4586 | #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ |
||
| 4587 | #define RCC_CR_MSIRDY_Pos (9U) |
||
| 4588 | #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ |
||
| 4589 | #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ |
||
| 4590 | |||
| 4591 | #define RCC_CR_HSEON_Pos (16U) |
||
| 4592 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
||
| 4593 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ |
||
| 4594 | #define RCC_CR_HSERDY_Pos (17U) |
||
| 4595 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
||
| 4596 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ |
||
| 4597 | #define RCC_CR_HSEBYP_Pos (18U) |
||
| 4598 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
||
| 4599 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ |
||
| 4600 | |||
| 4601 | #define RCC_CR_PLLON_Pos (24U) |
||
| 4602 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
||
| 4603 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ |
||
| 4604 | #define RCC_CR_PLLRDY_Pos (25U) |
||
| 4605 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
||
| 4606 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ |
||
| 4607 | #define RCC_CR_CSSON_Pos (28U) |
||
| 4608 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x10000000 */ |
||
| 4609 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ |
||
| 4610 | |||
| 4611 | #define RCC_CR_RTCPRE_Pos (29U) |
||
| 4612 | #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */ |
||
| 4613 | #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */ |
||
| 4614 | #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */ |
||
| 4615 | #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */ |
||
| 4616 | |||
| 4617 | /******************** Bit definition for RCC_ICSCR register *****************/ |
||
| 4618 | #define RCC_ICSCR_HSICAL_Pos (0U) |
||
| 4619 | #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ |
||
| 4620 | #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ |
||
| 4621 | #define RCC_ICSCR_HSITRIM_Pos (8U) |
||
| 4622 | #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ |
||
| 4623 | #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ |
||
| 4624 | |||
| 4625 | #define RCC_ICSCR_MSIRANGE_Pos (13U) |
||
| 4626 | #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ |
||
| 4627 | #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ |
||
| 4628 | #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ |
||
| 4629 | #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ |
||
| 4630 | #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ |
||
| 4631 | #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ |
||
| 4632 | #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ |
||
| 4633 | #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ |
||
| 4634 | #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ |
||
| 4635 | #define RCC_ICSCR_MSICAL_Pos (16U) |
||
| 4636 | #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ |
||
| 4637 | #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ |
||
| 4638 | #define RCC_ICSCR_MSITRIM_Pos (24U) |
||
| 4639 | #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ |
||
| 4640 | #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ |
||
| 4641 | |||
| 4642 | /******************** Bit definition for RCC_CFGR register ******************/ |
||
| 4643 | #define RCC_CFGR_SW_Pos (0U) |
||
| 4644 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
||
| 4645 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
||
| 4646 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
||
| 4647 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
||
| 4648 | |||
| 4649 | /*!< SW configuration */ |
||
| 4650 | #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ |
||
| 4651 | #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ |
||
| 4652 | #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ |
||
| 4653 | #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ |
||
| 4654 | |||
| 4655 | #define RCC_CFGR_SWS_Pos (2U) |
||
| 4656 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
||
| 4657 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
||
| 4658 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
||
| 4659 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
||
| 4660 | |||
| 4661 | /*!< SWS configuration */ |
||
| 4662 | #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ |
||
| 4663 | #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ |
||
| 4664 | #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ |
||
| 4665 | #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ |
||
| 4666 | |||
| 4667 | #define RCC_CFGR_HPRE_Pos (4U) |
||
| 4668 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
||
| 4669 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
||
| 4670 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
||
| 4671 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
||
| 4672 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
||
| 4673 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
||
| 4674 | |||
| 4675 | /*!< HPRE configuration */ |
||
| 4676 | #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ |
||
| 4677 | #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ |
||
| 4678 | #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ |
||
| 4679 | #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ |
||
| 4680 | #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ |
||
| 4681 | #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ |
||
| 4682 | #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ |
||
| 4683 | #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ |
||
| 4684 | #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ |
||
| 4685 | |||
| 4686 | #define RCC_CFGR_PPRE1_Pos (8U) |
||
| 4687 | #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
||
| 4688 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
||
| 4689 | #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
||
| 4690 | #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
||
| 4691 | #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
||
| 4692 | |||
| 4693 | /*!< PPRE1 configuration */ |
||
| 4694 | #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ |
||
| 4695 | #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ |
||
| 4696 | #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ |
||
| 4697 | #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ |
||
| 4698 | #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ |
||
| 4699 | |||
| 4700 | #define RCC_CFGR_PPRE2_Pos (11U) |
||
| 4701 | #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
||
| 4702 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
||
| 4703 | #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
||
| 4704 | #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
||
| 4705 | #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
||
| 4706 | |||
| 4707 | /*!< PPRE2 configuration */ |
||
| 4708 | #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ |
||
| 4709 | #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ |
||
| 4710 | #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ |
||
| 4711 | #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ |
||
| 4712 | #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ |
||
| 4713 | |||
| 4714 | /*!< PLL entry clock source*/ |
||
| 4715 | #define RCC_CFGR_PLLSRC_Pos (16U) |
||
| 4716 | #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
||
| 4717 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
||
| 4718 | |||
| 4719 | #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ |
||
| 4720 | #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ |
||
| 4721 | |||
| 4722 | |||
| 4723 | /*!< PLLMUL configuration */ |
||
| 4724 | #define RCC_CFGR_PLLMUL_Pos (18U) |
||
| 4725 | #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ |
||
| 4726 | #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
||
| 4727 | #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ |
||
| 4728 | #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ |
||
| 4729 | #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ |
||
| 4730 | #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ |
||
| 4731 | |||
| 4732 | /*!< PLLMUL configuration */ |
||
| 4733 | #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ |
||
| 4734 | #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ |
||
| 4735 | #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ |
||
| 4736 | #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ |
||
| 4737 | #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ |
||
| 4738 | #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ |
||
| 4739 | #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ |
||
| 4740 | #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ |
||
| 4741 | #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ |
||
| 4742 | |||
| 4743 | /*!< PLLDIV configuration */ |
||
| 4744 | #define RCC_CFGR_PLLDIV_Pos (22U) |
||
| 4745 | #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ |
||
| 4746 | #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ |
||
| 4747 | #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ |
||
| 4748 | #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ |
||
| 4749 | |||
| 4750 | |||
| 4751 | /*!< PLLDIV configuration */ |
||
| 4752 | #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */ |
||
| 4753 | #define RCC_CFGR_PLLDIV2_Pos (22U) |
||
| 4754 | #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ |
||
| 4755 | #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ |
||
| 4756 | #define RCC_CFGR_PLLDIV3_Pos (23U) |
||
| 4757 | #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ |
||
| 4758 | #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ |
||
| 4759 | #define RCC_CFGR_PLLDIV4_Pos (22U) |
||
| 4760 | #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ |
||
| 4761 | #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ |
||
| 4762 | |||
| 4763 | |||
| 4764 | #define RCC_CFGR_MCOSEL_Pos (24U) |
||
| 4765 | #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ |
||
| 4766 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
||
| 4767 | #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ |
||
| 4768 | #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ |
||
| 4769 | #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ |
||
| 4770 | |||
| 4771 | /*!< MCO configuration */ |
||
| 4772 | #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ |
||
| 4773 | #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) |
||
| 4774 | #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ |
||
| 4775 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */ |
||
| 4776 | #define RCC_CFGR_MCOSEL_HSI_Pos (25U) |
||
| 4777 | #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ |
||
| 4778 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ |
||
| 4779 | #define RCC_CFGR_MCOSEL_MSI_Pos (24U) |
||
| 4780 | #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ |
||
| 4781 | #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ |
||
| 4782 | #define RCC_CFGR_MCOSEL_HSE_Pos (26U) |
||
| 4783 | #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ |
||
| 4784 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ |
||
| 4785 | #define RCC_CFGR_MCOSEL_PLL_Pos (24U) |
||
| 4786 | #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ |
||
| 4787 | #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ |
||
| 4788 | #define RCC_CFGR_MCOSEL_LSI_Pos (25U) |
||
| 4789 | #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ |
||
| 4790 | #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ |
||
| 4791 | #define RCC_CFGR_MCOSEL_LSE_Pos (24U) |
||
| 4792 | #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ |
||
| 4793 | #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ |
||
| 4794 | |||
| 4795 | #define RCC_CFGR_MCOPRE_Pos (28U) |
||
| 4796 | #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ |
||
| 4797 | #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */ |
||
| 4798 | #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ |
||
| 4799 | #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ |
||
| 4800 | #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ |
||
| 4801 | |||
| 4802 | /*!< MCO Prescaler configuration */ |
||
| 4803 | #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ |
||
| 4804 | #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ |
||
| 4805 | #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ |
||
| 4806 | #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ |
||
| 4807 | #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ |
||
| 4808 | |||
| 4809 | /* Legacy aliases */ |
||
| 4810 | #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1 |
||
| 4811 | #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2 |
||
| 4812 | #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4 |
||
| 4813 | #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8 |
||
| 4814 | #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16 |
||
| 4815 | #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK |
||
| 4816 | #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK |
||
| 4817 | #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI |
||
| 4818 | #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI |
||
| 4819 | #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE |
||
| 4820 | #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL |
||
| 4821 | #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI |
||
| 4822 | #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE |
||
| 4823 | |||
| 4824 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
||
| 4825 | #define RCC_CIR_LSIRDYF_Pos (0U) |
||
| 4826 | #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
||
| 4827 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ |
||
| 4828 | #define RCC_CIR_LSERDYF_Pos (1U) |
||
| 4829 | #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
||
| 4830 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ |
||
| 4831 | #define RCC_CIR_HSIRDYF_Pos (2U) |
||
| 4832 | #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
||
| 4833 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ |
||
| 4834 | #define RCC_CIR_HSERDYF_Pos (3U) |
||
| 4835 | #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
||
| 4836 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ |
||
| 4837 | #define RCC_CIR_PLLRDYF_Pos (4U) |
||
| 4838 | #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
||
| 4839 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ |
||
| 4840 | #define RCC_CIR_MSIRDYF_Pos (5U) |
||
| 4841 | #define RCC_CIR_MSIRDYF_Msk (0x1U << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */ |
||
| 4842 | #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ |
||
| 4843 | #define RCC_CIR_LSECSSF_Pos (6U) |
||
| 4844 | #define RCC_CIR_LSECSSF_Msk (0x1U << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */ |
||
| 4845 | #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */ |
||
| 4846 | #define RCC_CIR_CSSF_Pos (7U) |
||
| 4847 | #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
||
| 4848 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ |
||
| 4849 | |||
| 4850 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
||
| 4851 | #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
||
| 4852 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ |
||
| 4853 | #define RCC_CIR_LSERDYIE_Pos (9U) |
||
| 4854 | #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
||
| 4855 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ |
||
| 4856 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
||
| 4857 | #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
||
| 4858 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ |
||
| 4859 | #define RCC_CIR_HSERDYIE_Pos (11U) |
||
| 4860 | #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
||
| 4861 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ |
||
| 4862 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
||
| 4863 | #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
||
| 4864 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ |
||
| 4865 | #define RCC_CIR_MSIRDYIE_Pos (13U) |
||
| 4866 | #define RCC_CIR_MSIRDYIE_Msk (0x1U << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */ |
||
| 4867 | #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ |
||
| 4868 | #define RCC_CIR_LSECSSIE_Pos (14U) |
||
| 4869 | #define RCC_CIR_LSECSSIE_Msk (0x1U << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */ |
||
| 4870 | #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */ |
||
| 4871 | |||
| 4872 | #define RCC_CIR_LSIRDYC_Pos (16U) |
||
| 4873 | #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
||
| 4874 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ |
||
| 4875 | #define RCC_CIR_LSERDYC_Pos (17U) |
||
| 4876 | #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
||
| 4877 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ |
||
| 4878 | #define RCC_CIR_HSIRDYC_Pos (18U) |
||
| 4879 | #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
||
| 4880 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ |
||
| 4881 | #define RCC_CIR_HSERDYC_Pos (19U) |
||
| 4882 | #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
||
| 4883 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ |
||
| 4884 | #define RCC_CIR_PLLRDYC_Pos (20U) |
||
| 4885 | #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
||
| 4886 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ |
||
| 4887 | #define RCC_CIR_MSIRDYC_Pos (21U) |
||
| 4888 | #define RCC_CIR_MSIRDYC_Msk (0x1U << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */ |
||
| 4889 | #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ |
||
| 4890 | #define RCC_CIR_LSECSSC_Pos (22U) |
||
| 4891 | #define RCC_CIR_LSECSSC_Msk (0x1U << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */ |
||
| 4892 | #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */ |
||
| 4893 | #define RCC_CIR_CSSC_Pos (23U) |
||
| 4894 | #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
||
| 4895 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ |
||
| 4896 | |||
| 4897 | /***************** Bit definition for RCC_AHBRSTR register ******************/ |
||
| 4898 | #define RCC_AHBRSTR_GPIOARST_Pos (0U) |
||
| 4899 | #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */ |
||
| 4900 | #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */ |
||
| 4901 | #define RCC_AHBRSTR_GPIOBRST_Pos (1U) |
||
| 4902 | #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ |
||
| 4903 | #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */ |
||
| 4904 | #define RCC_AHBRSTR_GPIOCRST_Pos (2U) |
||
| 4905 | #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ |
||
| 4906 | #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */ |
||
| 4907 | #define RCC_AHBRSTR_GPIODRST_Pos (3U) |
||
| 4908 | #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */ |
||
| 4909 | #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */ |
||
| 4910 | #define RCC_AHBRSTR_GPIOERST_Pos (4U) |
||
| 4911 | #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */ |
||
| 4912 | #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */ |
||
| 4913 | #define RCC_AHBRSTR_GPIOHRST_Pos (5U) |
||
| 4914 | #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */ |
||
| 4915 | #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */ |
||
| 4916 | #define RCC_AHBRSTR_GPIOFRST_Pos (6U) |
||
| 4917 | #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */ |
||
| 4918 | #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIO port F reset */ |
||
| 4919 | #define RCC_AHBRSTR_GPIOGRST_Pos (7U) |
||
| 4920 | #define RCC_AHBRSTR_GPIOGRST_Msk (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */ |
||
| 4921 | #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIO port G reset */ |
||
| 4922 | #define RCC_AHBRSTR_CRCRST_Pos (12U) |
||
| 4923 | #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ |
||
| 4924 | #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ |
||
| 4925 | #define RCC_AHBRSTR_FLITFRST_Pos (15U) |
||
| 4926 | #define RCC_AHBRSTR_FLITFRST_Msk (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */ |
||
| 4927 | #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */ |
||
| 4928 | #define RCC_AHBRSTR_DMA1RST_Pos (24U) |
||
| 4929 | #define RCC_AHBRSTR_DMA1RST_Msk (0x1U << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */ |
||
| 4930 | #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */ |
||
| 4931 | #define RCC_AHBRSTR_DMA2RST_Pos (25U) |
||
| 4932 | #define RCC_AHBRSTR_DMA2RST_Msk (0x1U << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */ |
||
| 4933 | #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */ |
||
| 4934 | #define RCC_AHBRSTR_AESRST_Pos (27U) |
||
| 4935 | #define RCC_AHBRSTR_AESRST_Msk (0x1U << RCC_AHBRSTR_AESRST_Pos) /*!< 0x08000000 */ |
||
| 4936 | #define RCC_AHBRSTR_AESRST RCC_AHBRSTR_AESRST_Msk /*!< AES reset */ |
||
| 4937 | #define RCC_AHBRSTR_FSMCRST_Pos (30U) |
||
| 4938 | #define RCC_AHBRSTR_FSMCRST_Msk (0x1U << RCC_AHBRSTR_FSMCRST_Pos) /*!< 0x40000000 */ |
||
| 4939 | #define RCC_AHBRSTR_FSMCRST RCC_AHBRSTR_FSMCRST_Msk /*!< FSMC reset */ |
||
| 4940 | |||
| 4941 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
||
| 4942 | #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) |
||
| 4943 | #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ |
||
| 4944 | #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */ |
||
| 4945 | #define RCC_APB2RSTR_TIM9RST_Pos (2U) |
||
| 4946 | #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */ |
||
| 4947 | #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ |
||
| 4948 | #define RCC_APB2RSTR_TIM10RST_Pos (3U) |
||
| 4949 | #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */ |
||
| 4950 | #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */ |
||
| 4951 | #define RCC_APB2RSTR_TIM11RST_Pos (4U) |
||
| 4952 | #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */ |
||
| 4953 | #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */ |
||
| 4954 | #define RCC_APB2RSTR_ADC1RST_Pos (9U) |
||
| 4955 | #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ |
||
| 4956 | #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */ |
||
| 4957 | #define RCC_APB2RSTR_SDIORST_Pos (11U) |
||
| 4958 | #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ |
||
| 4959 | #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk /*!< SDIO reset */ |
||
| 4960 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
||
| 4961 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
||
| 4962 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ |
||
| 4963 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
||
| 4964 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
||
| 4965 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ |
||
| 4966 | |||
| 4967 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
||
| 4968 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
||
| 4969 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
||
| 4970 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ |
||
| 4971 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
||
| 4972 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
||
| 4973 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ |
||
| 4974 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
||
| 4975 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
||
| 4976 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ |
||
| 4977 | #define RCC_APB1RSTR_TIM5RST_Pos (3U) |
||
| 4978 | #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ |
||
| 4979 | #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ |
||
| 4980 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) |
||
| 4981 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ |
||
| 4982 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ |
||
| 4983 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) |
||
| 4984 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ |
||
| 4985 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ |
||
| 4986 | #define RCC_APB1RSTR_LCDRST_Pos (9U) |
||
| 4987 | #define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ |
||
| 4988 | #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */ |
||
| 4989 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
||
| 4990 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
||
| 4991 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ |
||
| 4992 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
||
| 4993 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
||
| 4994 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ |
||
| 4995 | #define RCC_APB1RSTR_SPI3RST_Pos (15U) |
||
| 4996 | #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ |
||
| 4997 | #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ |
||
| 4998 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
||
| 4999 | #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
||
| 5000 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ |
||
| 5001 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
||
| 5002 | #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
||
| 5003 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ |
||
| 5004 | #define RCC_APB1RSTR_UART4RST_Pos (19U) |
||
| 5005 | #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ |
||
| 5006 | #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ |
||
| 5007 | #define RCC_APB1RSTR_UART5RST_Pos (20U) |
||
| 5008 | #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ |
||
| 5009 | #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ |
||
| 5010 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
||
| 5011 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
||
| 5012 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ |
||
| 5013 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
||
| 5014 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
||
| 5015 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ |
||
| 5016 | #define RCC_APB1RSTR_USBRST_Pos (23U) |
||
| 5017 | #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ |
||
| 5018 | #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ |
||
| 5019 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
||
| 5020 | #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
||
| 5021 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ |
||
| 5022 | #define RCC_APB1RSTR_DACRST_Pos (29U) |
||
| 5023 | #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ |
||
| 5024 | #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ |
||
| 5025 | #define RCC_APB1RSTR_COMPRST_Pos (31U) |
||
| 5026 | #define RCC_APB1RSTR_COMPRST_Msk (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */ |
||
| 5027 | #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */ |
||
| 5028 | |||
| 5029 | /****************** Bit definition for RCC_AHBENR register ******************/ |
||
| 5030 | #define RCC_AHBENR_GPIOAEN_Pos (0U) |
||
| 5031 | #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */ |
||
| 5032 | #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */ |
||
| 5033 | #define RCC_AHBENR_GPIOBEN_Pos (1U) |
||
| 5034 | #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */ |
||
| 5035 | #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */ |
||
| 5036 | #define RCC_AHBENR_GPIOCEN_Pos (2U) |
||
| 5037 | #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */ |
||
| 5038 | #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */ |
||
| 5039 | #define RCC_AHBENR_GPIODEN_Pos (3U) |
||
| 5040 | #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */ |
||
| 5041 | #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */ |
||
| 5042 | #define RCC_AHBENR_GPIOEEN_Pos (4U) |
||
| 5043 | #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */ |
||
| 5044 | #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */ |
||
| 5045 | #define RCC_AHBENR_GPIOHEN_Pos (5U) |
||
| 5046 | #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */ |
||
| 5047 | #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */ |
||
| 5048 | #define RCC_AHBENR_GPIOFEN_Pos (6U) |
||
| 5049 | #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00000040 */ |
||
| 5050 | #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIO port F clock enable */ |
||
| 5051 | #define RCC_AHBENR_GPIOGEN_Pos (7U) |
||
| 5052 | #define RCC_AHBENR_GPIOGEN_Msk (0x1U << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00000080 */ |
||
| 5053 | #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIO port G clock enable */ |
||
| 5054 | #define RCC_AHBENR_CRCEN_Pos (12U) |
||
| 5055 | #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ |
||
| 5056 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ |
||
| 5057 | #define RCC_AHBENR_FLITFEN_Pos (15U) |
||
| 5058 | #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */ |
||
| 5059 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when |
||
| 5060 | the Flash memory is in power down mode) */ |
||
| 5061 | #define RCC_AHBENR_DMA1EN_Pos (24U) |
||
| 5062 | #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */ |
||
| 5063 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ |
||
| 5064 | #define RCC_AHBENR_DMA2EN_Pos (25U) |
||
| 5065 | #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */ |
||
| 5066 | #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ |
||
| 5067 | #define RCC_AHBENR_AESEN_Pos (27U) |
||
| 5068 | #define RCC_AHBENR_AESEN_Msk (0x1U << RCC_AHBENR_AESEN_Pos) /*!< 0x08000000 */ |
||
| 5069 | #define RCC_AHBENR_AESEN RCC_AHBENR_AESEN_Msk /*!< AES clock enable */ |
||
| 5070 | #define RCC_AHBENR_FSMCEN_Pos (30U) |
||
| 5071 | #define RCC_AHBENR_FSMCEN_Msk (0x1U << RCC_AHBENR_FSMCEN_Pos) /*!< 0x40000000 */ |
||
| 5072 | #define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */ |
||
| 5073 | |||
| 5074 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
||
| 5075 | #define RCC_APB2ENR_SYSCFGEN_Pos (0U) |
||
| 5076 | #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ |
||
| 5077 | #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */ |
||
| 5078 | #define RCC_APB2ENR_TIM9EN_Pos (2U) |
||
| 5079 | #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */ |
||
| 5080 | #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */ |
||
| 5081 | #define RCC_APB2ENR_TIM10EN_Pos (3U) |
||
| 5082 | #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */ |
||
| 5083 | #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */ |
||
| 5084 | #define RCC_APB2ENR_TIM11EN_Pos (4U) |
||
| 5085 | #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */ |
||
| 5086 | #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */ |
||
| 5087 | #define RCC_APB2ENR_ADC1EN_Pos (9U) |
||
| 5088 | #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ |
||
| 5089 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */ |
||
| 5090 | #define RCC_APB2ENR_SDIOEN_Pos (11U) |
||
| 5091 | #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ |
||
| 5092 | #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk /*!< SDIO clock enable */ |
||
| 5093 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
||
| 5094 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
||
| 5095 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ |
||
| 5096 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
||
| 5097 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
||
| 5098 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ |
||
| 5099 | |||
| 5100 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
||
| 5101 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
||
| 5102 | #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
||
| 5103 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ |
||
| 5104 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
||
| 5105 | #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
||
| 5106 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ |
||
| 5107 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
||
| 5108 | #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
||
| 5109 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ |
||
| 5110 | #define RCC_APB1ENR_TIM5EN_Pos (3U) |
||
| 5111 | #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ |
||
| 5112 | #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ |
||
| 5113 | #define RCC_APB1ENR_TIM6EN_Pos (4U) |
||
| 5114 | #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ |
||
| 5115 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ |
||
| 5116 | #define RCC_APB1ENR_TIM7EN_Pos (5U) |
||
| 5117 | #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ |
||
| 5118 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ |
||
| 5119 | #define RCC_APB1ENR_LCDEN_Pos (9U) |
||
| 5120 | #define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ |
||
| 5121 | #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ |
||
| 5122 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
||
| 5123 | #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
||
| 5124 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ |
||
| 5125 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
||
| 5126 | #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
||
| 5127 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ |
||
| 5128 | #define RCC_APB1ENR_SPI3EN_Pos (15U) |
||
| 5129 | #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ |
||
| 5130 | #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ |
||
| 5131 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
||
| 5132 | #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
||
| 5133 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ |
||
| 5134 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
||
| 5135 | #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
||
| 5136 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ |
||
| 5137 | #define RCC_APB1ENR_UART4EN_Pos (19U) |
||
| 5138 | #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ |
||
| 5139 | #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ |
||
| 5140 | #define RCC_APB1ENR_UART5EN_Pos (20U) |
||
| 5141 | #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ |
||
| 5142 | #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ |
||
| 5143 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
||
| 5144 | #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
||
| 5145 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ |
||
| 5146 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
||
| 5147 | #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
||
| 5148 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ |
||
| 5149 | #define RCC_APB1ENR_USBEN_Pos (23U) |
||
| 5150 | #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ |
||
| 5151 | #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ |
||
| 5152 | #define RCC_APB1ENR_PWREN_Pos (28U) |
||
| 5153 | #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
||
| 5154 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ |
||
| 5155 | #define RCC_APB1ENR_DACEN_Pos (29U) |
||
| 5156 | #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ |
||
| 5157 | #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ |
||
| 5158 | #define RCC_APB1ENR_COMPEN_Pos (31U) |
||
| 5159 | #define RCC_APB1ENR_COMPEN_Msk (0x1U << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */ |
||
| 5160 | #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */ |
||
| 5161 | |||
| 5162 | /****************** Bit definition for RCC_AHBLPENR register ****************/ |
||
| 5163 | #define RCC_AHBLPENR_GPIOALPEN_Pos (0U) |
||
| 5164 | #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ |
||
| 5165 | #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */ |
||
| 5166 | #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U) |
||
| 5167 | #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ |
||
| 5168 | #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */ |
||
| 5169 | #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U) |
||
| 5170 | #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ |
||
| 5171 | #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */ |
||
| 5172 | #define RCC_AHBLPENR_GPIODLPEN_Pos (3U) |
||
| 5173 | #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ |
||
| 5174 | #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */ |
||
| 5175 | #define RCC_AHBLPENR_GPIOELPEN_Pos (4U) |
||
| 5176 | #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ |
||
| 5177 | #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */ |
||
| 5178 | #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U) |
||
| 5179 | #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */ |
||
| 5180 | #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */ |
||
| 5181 | #define RCC_AHBLPENR_GPIOFLPEN_Pos (6U) |
||
| 5182 | #define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */ |
||
| 5183 | #define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /*!< GPIO port F clock enabled in sleep mode */ |
||
| 5184 | #define RCC_AHBLPENR_GPIOGLPEN_Pos (7U) |
||
| 5185 | #define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */ |
||
| 5186 | #define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /*!< GPIO port G clock enabled in sleep mode */ |
||
| 5187 | #define RCC_AHBLPENR_CRCLPEN_Pos (12U) |
||
| 5188 | #define RCC_AHBLPENR_CRCLPEN_Msk (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */ |
||
| 5189 | #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */ |
||
| 5190 | #define RCC_AHBLPENR_FLITFLPEN_Pos (15U) |
||
| 5191 | #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ |
||
| 5192 | #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode |
||
| 5193 | (has effect only when the Flash memory is |
||
| 5194 | in power down mode) */ |
||
| 5195 | #define RCC_AHBLPENR_SRAMLPEN_Pos (16U) |
||
| 5196 | #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */ |
||
| 5197 | #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */ |
||
| 5198 | #define RCC_AHBLPENR_DMA1LPEN_Pos (24U) |
||
| 5199 | #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */ |
||
| 5200 | #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */ |
||
| 5201 | #define RCC_AHBLPENR_DMA2LPEN_Pos (25U) |
||
| 5202 | #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */ |
||
| 5203 | #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */ |
||
| 5204 | #define RCC_AHBLPENR_AESLPEN_Pos (27U) |
||
| 5205 | #define RCC_AHBLPENR_AESLPEN_Msk (0x1U << RCC_AHBLPENR_AESLPEN_Pos) /*!< 0x08000000 */ |
||
| 5206 | #define RCC_AHBLPENR_AESLPEN RCC_AHBLPENR_AESLPEN_Msk /*!< AES clock enabled in sleep mode */ |
||
| 5207 | #define RCC_AHBLPENR_FSMCLPEN_Pos (30U) |
||
| 5208 | #define RCC_AHBLPENR_FSMCLPEN_Msk (0x1U << RCC_AHBLPENR_FSMCLPEN_Pos) /*!< 0x40000000 */ |
||
| 5209 | #define RCC_AHBLPENR_FSMCLPEN RCC_AHBLPENR_FSMCLPEN_Msk /*!< FSMC clock enabled in sleep mode */ |
||
| 5210 | |||
| 5211 | /****************** Bit definition for RCC_APB2LPENR register ***************/ |
||
| 5212 | #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U) |
||
| 5213 | #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */ |
||
| 5214 | #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */ |
||
| 5215 | #define RCC_APB2LPENR_TIM9LPEN_Pos (2U) |
||
| 5216 | #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */ |
||
| 5217 | #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */ |
||
| 5218 | #define RCC_APB2LPENR_TIM10LPEN_Pos (3U) |
||
| 5219 | #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */ |
||
| 5220 | #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */ |
||
| 5221 | #define RCC_APB2LPENR_TIM11LPEN_Pos (4U) |
||
| 5222 | #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */ |
||
| 5223 | #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */ |
||
| 5224 | #define RCC_APB2LPENR_ADC1LPEN_Pos (9U) |
||
| 5225 | #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */ |
||
| 5226 | #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */ |
||
| 5227 | #define RCC_APB2LPENR_SDIOLPEN_Pos (11U) |
||
| 5228 | #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ |
||
| 5229 | #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk /*!< SDIO clock enabled in sleep mode */ |
||
| 5230 | #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) |
||
| 5231 | #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ |
||
| 5232 | #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */ |
||
| 5233 | #define RCC_APB2LPENR_USART1LPEN_Pos (14U) |
||
| 5234 | #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ |
||
| 5235 | #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */ |
||
| 5236 | |||
| 5237 | /***************** Bit definition for RCC_APB1LPENR register ****************/ |
||
| 5238 | #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) |
||
| 5239 | #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ |
||
| 5240 | #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */ |
||
| 5241 | #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) |
||
| 5242 | #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ |
||
| 5243 | #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */ |
||
| 5244 | #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) |
||
| 5245 | #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ |
||
| 5246 | #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */ |
||
| 5247 | #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) |
||
| 5248 | #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ |
||
| 5249 | #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */ |
||
| 5250 | #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) |
||
| 5251 | #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ |
||
| 5252 | #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */ |
||
| 5253 | #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) |
||
| 5254 | #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ |
||
| 5255 | #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */ |
||
| 5256 | #define RCC_APB1LPENR_LCDLPEN_Pos (9U) |
||
| 5257 | #define RCC_APB1LPENR_LCDLPEN_Msk (0x1U << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */ |
||
| 5258 | #define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */ |
||
| 5259 | #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) |
||
| 5260 | #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ |
||
| 5261 | #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ |
||
| 5262 | #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) |
||
| 5263 | #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ |
||
| 5264 | #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */ |
||
| 5265 | #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) |
||
| 5266 | #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ |
||
| 5267 | #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */ |
||
| 5268 | #define RCC_APB1LPENR_USART2LPEN_Pos (17U) |
||
| 5269 | #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ |
||
| 5270 | #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */ |
||
| 5271 | #define RCC_APB1LPENR_USART3LPEN_Pos (18U) |
||
| 5272 | #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ |
||
| 5273 | #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */ |
||
| 5274 | #define RCC_APB1LPENR_UART4LPEN_Pos (19U) |
||
| 5275 | #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ |
||
| 5276 | #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /*!< UART 4 clock enabled in sleep mode */ |
||
| 5277 | #define RCC_APB1LPENR_UART5LPEN_Pos (20U) |
||
| 5278 | #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ |
||
| 5279 | #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /*!< UART 5 clock enabled in sleep mode */ |
||
| 5280 | #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) |
||
| 5281 | #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ |
||
| 5282 | #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */ |
||
| 5283 | #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) |
||
| 5284 | #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ |
||
| 5285 | #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */ |
||
| 5286 | #define RCC_APB1LPENR_USBLPEN_Pos (23U) |
||
| 5287 | #define RCC_APB1LPENR_USBLPEN_Msk (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */ |
||
| 5288 | #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */ |
||
| 5289 | #define RCC_APB1LPENR_PWRLPEN_Pos (28U) |
||
| 5290 | #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ |
||
| 5291 | #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */ |
||
| 5292 | #define RCC_APB1LPENR_DACLPEN_Pos (29U) |
||
| 5293 | #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ |
||
| 5294 | #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */ |
||
| 5295 | #define RCC_APB1LPENR_COMPLPEN_Pos (31U) |
||
| 5296 | #define RCC_APB1LPENR_COMPLPEN_Msk (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */ |
||
| 5297 | #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/ |
||
| 5298 | |||
| 5299 | /******************* Bit definition for RCC_CSR register ********************/ |
||
| 5300 | #define RCC_CSR_LSION_Pos (0U) |
||
| 5301 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
||
| 5302 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ |
||
| 5303 | #define RCC_CSR_LSIRDY_Pos (1U) |
||
| 5304 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
||
| 5305 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ |
||
| 5306 | |||
| 5307 | #define RCC_CSR_LSEON_Pos (8U) |
||
| 5308 | #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ |
||
| 5309 | #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ |
||
| 5310 | #define RCC_CSR_LSERDY_Pos (9U) |
||
| 5311 | #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ |
||
| 5312 | #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ |
||
| 5313 | #define RCC_CSR_LSEBYP_Pos (10U) |
||
| 5314 | #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ |
||
| 5315 | #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ |
||
| 5316 | |||
| 5317 | #define RCC_CSR_LSECSSON_Pos (11U) |
||
| 5318 | #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */ |
||
| 5319 | #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ |
||
| 5320 | #define RCC_CSR_LSECSSD_Pos (12U) |
||
| 5321 | #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */ |
||
| 5322 | #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ |
||
| 5323 | |||
| 5324 | #define RCC_CSR_RTCSEL_Pos (16U) |
||
| 5325 | #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ |
||
| 5326 | #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
||
| 5327 | #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ |
||
| 5328 | #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ |
||
| 5329 | |||
| 5330 | /*!< RTC congiguration */ |
||
| 5331 | #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ |
||
| 5332 | #define RCC_CSR_RTCSEL_LSE_Pos (16U) |
||
| 5333 | #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ |
||
| 5334 | #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ |
||
| 5335 | #define RCC_CSR_RTCSEL_LSI_Pos (17U) |
||
| 5336 | #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ |
||
| 5337 | #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ |
||
| 5338 | #define RCC_CSR_RTCSEL_HSE_Pos (16U) |
||
| 5339 | #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ |
||
| 5340 | #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */ |
||
| 5341 | |||
| 5342 | #define RCC_CSR_RTCEN_Pos (22U) |
||
| 5343 | #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */ |
||
| 5344 | #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ |
||
| 5345 | #define RCC_CSR_RTCRST_Pos (23U) |
||
| 5346 | #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */ |
||
| 5347 | #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */ |
||
| 5348 | |||
| 5349 | #define RCC_CSR_RMVF_Pos (24U) |
||
| 5350 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
||
| 5351 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ |
||
| 5352 | #define RCC_CSR_OBLRSTF_Pos (25U) |
||
| 5353 | #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ |
||
| 5354 | #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */ |
||
| 5355 | #define RCC_CSR_PINRSTF_Pos (26U) |
||
| 5356 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
||
| 5357 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ |
||
| 5358 | #define RCC_CSR_PORRSTF_Pos (27U) |
||
| 5359 | #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
||
| 5360 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ |
||
| 5361 | #define RCC_CSR_SFTRSTF_Pos (28U) |
||
| 5362 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
||
| 5363 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ |
||
| 5364 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
||
| 5365 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
||
| 5366 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ |
||
| 5367 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
||
| 5368 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
||
| 5369 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ |
||
| 5370 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
||
| 5371 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
||
| 5372 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ |
||
| 5373 | |||
| 5374 | /******************************************************************************/ |
||
| 5375 | /* */ |
||
| 5376 | /* Real-Time Clock (RTC) */ |
||
| 5377 | /* */ |
||
| 5378 | /******************************************************************************/ |
||
| 5379 | /* |
||
| 5380 | * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) |
||
| 5381 | */ |
||
| 5382 | #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ |
||
| 5383 | #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ |
||
| 5384 | #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */ |
||
| 5385 | #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ |
||
| 5386 | #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ |
||
| 5387 | #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */ |
||
| 5388 | #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */ |
||
| 5389 | |||
| 5390 | /******************** Bits definition for RTC_TR register *******************/ |
||
| 5391 | #define RTC_TR_PM_Pos (22U) |
||
| 5392 | #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ |
||
| 5393 | #define RTC_TR_PM RTC_TR_PM_Msk |
||
| 5394 | #define RTC_TR_HT_Pos (20U) |
||
| 5395 | #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ |
||
| 5396 | #define RTC_TR_HT RTC_TR_HT_Msk |
||
| 5397 | #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ |
||
| 5398 | #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ |
||
| 5399 | #define RTC_TR_HU_Pos (16U) |
||
| 5400 | #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ |
||
| 5401 | #define RTC_TR_HU RTC_TR_HU_Msk |
||
| 5402 | #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ |
||
| 5403 | #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ |
||
| 5404 | #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ |
||
| 5405 | #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ |
||
| 5406 | #define RTC_TR_MNT_Pos (12U) |
||
| 5407 | #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ |
||
| 5408 | #define RTC_TR_MNT RTC_TR_MNT_Msk |
||
| 5409 | #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ |
||
| 5410 | #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ |
||
| 5411 | #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ |
||
| 5412 | #define RTC_TR_MNU_Pos (8U) |
||
| 5413 | #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ |
||
| 5414 | #define RTC_TR_MNU RTC_TR_MNU_Msk |
||
| 5415 | #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ |
||
| 5416 | #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ |
||
| 5417 | #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ |
||
| 5418 | #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ |
||
| 5419 | #define RTC_TR_ST_Pos (4U) |
||
| 5420 | #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ |
||
| 5421 | #define RTC_TR_ST RTC_TR_ST_Msk |
||
| 5422 | #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ |
||
| 5423 | #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ |
||
| 5424 | #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ |
||
| 5425 | #define RTC_TR_SU_Pos (0U) |
||
| 5426 | #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ |
||
| 5427 | #define RTC_TR_SU RTC_TR_SU_Msk |
||
| 5428 | #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ |
||
| 5429 | #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ |
||
| 5430 | #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ |
||
| 5431 | #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ |
||
| 5432 | |||
| 5433 | /******************** Bits definition for RTC_DR register *******************/ |
||
| 5434 | #define RTC_DR_YT_Pos (20U) |
||
| 5435 | #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ |
||
| 5436 | #define RTC_DR_YT RTC_DR_YT_Msk |
||
| 5437 | #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ |
||
| 5438 | #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ |
||
| 5439 | #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ |
||
| 5440 | #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ |
||
| 5441 | #define RTC_DR_YU_Pos (16U) |
||
| 5442 | #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ |
||
| 5443 | #define RTC_DR_YU RTC_DR_YU_Msk |
||
| 5444 | #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ |
||
| 5445 | #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ |
||
| 5446 | #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ |
||
| 5447 | #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ |
||
| 5448 | #define RTC_DR_WDU_Pos (13U) |
||
| 5449 | #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ |
||
| 5450 | #define RTC_DR_WDU RTC_DR_WDU_Msk |
||
| 5451 | #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ |
||
| 5452 | #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ |
||
| 5453 | #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ |
||
| 5454 | #define RTC_DR_MT_Pos (12U) |
||
| 5455 | #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ |
||
| 5456 | #define RTC_DR_MT RTC_DR_MT_Msk |
||
| 5457 | #define RTC_DR_MU_Pos (8U) |
||
| 5458 | #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ |
||
| 5459 | #define RTC_DR_MU RTC_DR_MU_Msk |
||
| 5460 | #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ |
||
| 5461 | #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ |
||
| 5462 | #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ |
||
| 5463 | #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ |
||
| 5464 | #define RTC_DR_DT_Pos (4U) |
||
| 5465 | #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ |
||
| 5466 | #define RTC_DR_DT RTC_DR_DT_Msk |
||
| 5467 | #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ |
||
| 5468 | #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ |
||
| 5469 | #define RTC_DR_DU_Pos (0U) |
||
| 5470 | #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ |
||
| 5471 | #define RTC_DR_DU RTC_DR_DU_Msk |
||
| 5472 | #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ |
||
| 5473 | #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ |
||
| 5474 | #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ |
||
| 5475 | #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ |
||
| 5476 | |||
| 5477 | /******************** Bits definition for RTC_CR register *******************/ |
||
| 5478 | #define RTC_CR_COE_Pos (23U) |
||
| 5479 | #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ |
||
| 5480 | #define RTC_CR_COE RTC_CR_COE_Msk |
||
| 5481 | #define RTC_CR_OSEL_Pos (21U) |
||
| 5482 | #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ |
||
| 5483 | #define RTC_CR_OSEL RTC_CR_OSEL_Msk |
||
| 5484 | #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ |
||
| 5485 | #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ |
||
| 5486 | #define RTC_CR_POL_Pos (20U) |
||
| 5487 | #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ |
||
| 5488 | #define RTC_CR_POL RTC_CR_POL_Msk |
||
| 5489 | #define RTC_CR_COSEL_Pos (19U) |
||
| 5490 | #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ |
||
| 5491 | #define RTC_CR_COSEL RTC_CR_COSEL_Msk |
||
| 5492 | #define RTC_CR_BCK_Pos (18U) |
||
| 5493 | #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ |
||
| 5494 | #define RTC_CR_BCK RTC_CR_BCK_Msk |
||
| 5495 | #define RTC_CR_SUB1H_Pos (17U) |
||
| 5496 | #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ |
||
| 5497 | #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk |
||
| 5498 | #define RTC_CR_ADD1H_Pos (16U) |
||
| 5499 | #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ |
||
| 5500 | #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk |
||
| 5501 | #define RTC_CR_TSIE_Pos (15U) |
||
| 5502 | #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ |
||
| 5503 | #define RTC_CR_TSIE RTC_CR_TSIE_Msk |
||
| 5504 | #define RTC_CR_WUTIE_Pos (14U) |
||
| 5505 | #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ |
||
| 5506 | #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk |
||
| 5507 | #define RTC_CR_ALRBIE_Pos (13U) |
||
| 5508 | #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ |
||
| 5509 | #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk |
||
| 5510 | #define RTC_CR_ALRAIE_Pos (12U) |
||
| 5511 | #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ |
||
| 5512 | #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk |
||
| 5513 | #define RTC_CR_TSE_Pos (11U) |
||
| 5514 | #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ |
||
| 5515 | #define RTC_CR_TSE RTC_CR_TSE_Msk |
||
| 5516 | #define RTC_CR_WUTE_Pos (10U) |
||
| 5517 | #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ |
||
| 5518 | #define RTC_CR_WUTE RTC_CR_WUTE_Msk |
||
| 5519 | #define RTC_CR_ALRBE_Pos (9U) |
||
| 5520 | #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ |
||
| 5521 | #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk |
||
| 5522 | #define RTC_CR_ALRAE_Pos (8U) |
||
| 5523 | #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ |
||
| 5524 | #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk |
||
| 5525 | #define RTC_CR_DCE_Pos (7U) |
||
| 5526 | #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */ |
||
| 5527 | #define RTC_CR_DCE RTC_CR_DCE_Msk |
||
| 5528 | #define RTC_CR_FMT_Pos (6U) |
||
| 5529 | #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ |
||
| 5530 | #define RTC_CR_FMT RTC_CR_FMT_Msk |
||
| 5531 | #define RTC_CR_BYPSHAD_Pos (5U) |
||
| 5532 | #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ |
||
| 5533 | #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk |
||
| 5534 | #define RTC_CR_REFCKON_Pos (4U) |
||
| 5535 | #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ |
||
| 5536 | #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk |
||
| 5537 | #define RTC_CR_TSEDGE_Pos (3U) |
||
| 5538 | #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ |
||
| 5539 | #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk |
||
| 5540 | #define RTC_CR_WUCKSEL_Pos (0U) |
||
| 5541 | #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ |
||
| 5542 | #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk |
||
| 5543 | #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ |
||
| 5544 | #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ |
||
| 5545 | #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ |
||
| 5546 | |||
| 5547 | /******************** Bits definition for RTC_ISR register ******************/ |
||
| 5548 | #define RTC_ISR_RECALPF_Pos (16U) |
||
| 5549 | #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ |
||
| 5550 | #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk |
||
| 5551 | #define RTC_ISR_TAMP3F_Pos (15U) |
||
| 5552 | #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ |
||
| 5553 | #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk |
||
| 5554 | #define RTC_ISR_TAMP2F_Pos (14U) |
||
| 5555 | #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ |
||
| 5556 | #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk |
||
| 5557 | #define RTC_ISR_TAMP1F_Pos (13U) |
||
| 5558 | #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ |
||
| 5559 | #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk |
||
| 5560 | #define RTC_ISR_TSOVF_Pos (12U) |
||
| 5561 | #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ |
||
| 5562 | #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk |
||
| 5563 | #define RTC_ISR_TSF_Pos (11U) |
||
| 5564 | #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ |
||
| 5565 | #define RTC_ISR_TSF RTC_ISR_TSF_Msk |
||
| 5566 | #define RTC_ISR_WUTF_Pos (10U) |
||
| 5567 | #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ |
||
| 5568 | #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk |
||
| 5569 | #define RTC_ISR_ALRBF_Pos (9U) |
||
| 5570 | #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ |
||
| 5571 | #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk |
||
| 5572 | #define RTC_ISR_ALRAF_Pos (8U) |
||
| 5573 | #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ |
||
| 5574 | #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk |
||
| 5575 | #define RTC_ISR_INIT_Pos (7U) |
||
| 5576 | #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ |
||
| 5577 | #define RTC_ISR_INIT RTC_ISR_INIT_Msk |
||
| 5578 | #define RTC_ISR_INITF_Pos (6U) |
||
| 5579 | #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ |
||
| 5580 | #define RTC_ISR_INITF RTC_ISR_INITF_Msk |
||
| 5581 | #define RTC_ISR_RSF_Pos (5U) |
||
| 5582 | #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ |
||
| 5583 | #define RTC_ISR_RSF RTC_ISR_RSF_Msk |
||
| 5584 | #define RTC_ISR_INITS_Pos (4U) |
||
| 5585 | #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ |
||
| 5586 | #define RTC_ISR_INITS RTC_ISR_INITS_Msk |
||
| 5587 | #define RTC_ISR_SHPF_Pos (3U) |
||
| 5588 | #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ |
||
| 5589 | #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk |
||
| 5590 | #define RTC_ISR_WUTWF_Pos (2U) |
||
| 5591 | #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ |
||
| 5592 | #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk |
||
| 5593 | #define RTC_ISR_ALRBWF_Pos (1U) |
||
| 5594 | #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ |
||
| 5595 | #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk |
||
| 5596 | #define RTC_ISR_ALRAWF_Pos (0U) |
||
| 5597 | #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ |
||
| 5598 | #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk |
||
| 5599 | |||
| 5600 | /******************** Bits definition for RTC_PRER register *****************/ |
||
| 5601 | #define RTC_PRER_PREDIV_A_Pos (16U) |
||
| 5602 | #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ |
||
| 5603 | #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk |
||
| 5604 | #define RTC_PRER_PREDIV_S_Pos (0U) |
||
| 5605 | #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ |
||
| 5606 | #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk |
||
| 5607 | |||
| 5608 | /******************** Bits definition for RTC_WUTR register *****************/ |
||
| 5609 | #define RTC_WUTR_WUT_Pos (0U) |
||
| 5610 | #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ |
||
| 5611 | #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk |
||
| 5612 | |||
| 5613 | /******************** Bits definition for RTC_CALIBR register ***************/ |
||
| 5614 | #define RTC_CALIBR_DCS_Pos (7U) |
||
| 5615 | #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ |
||
| 5616 | #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk |
||
| 5617 | #define RTC_CALIBR_DC_Pos (0U) |
||
| 5618 | #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ |
||
| 5619 | #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk |
||
| 5620 | |||
| 5621 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
||
| 5622 | #define RTC_ALRMAR_MSK4_Pos (31U) |
||
| 5623 | #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ |
||
| 5624 | #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk |
||
| 5625 | #define RTC_ALRMAR_WDSEL_Pos (30U) |
||
| 5626 | #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ |
||
| 5627 | #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk |
||
| 5628 | #define RTC_ALRMAR_DT_Pos (28U) |
||
| 5629 | #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ |
||
| 5630 | #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk |
||
| 5631 | #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ |
||
| 5632 | #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ |
||
| 5633 | #define RTC_ALRMAR_DU_Pos (24U) |
||
| 5634 | #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ |
||
| 5635 | #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk |
||
| 5636 | #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ |
||
| 5637 | #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ |
||
| 5638 | #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ |
||
| 5639 | #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ |
||
| 5640 | #define RTC_ALRMAR_MSK3_Pos (23U) |
||
| 5641 | #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ |
||
| 5642 | #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk |
||
| 5643 | #define RTC_ALRMAR_PM_Pos (22U) |
||
| 5644 | #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ |
||
| 5645 | #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk |
||
| 5646 | #define RTC_ALRMAR_HT_Pos (20U) |
||
| 5647 | #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ |
||
| 5648 | #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk |
||
| 5649 | #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ |
||
| 5650 | #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ |
||
| 5651 | #define RTC_ALRMAR_HU_Pos (16U) |
||
| 5652 | #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ |
||
| 5653 | #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk |
||
| 5654 | #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ |
||
| 5655 | #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ |
||
| 5656 | #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ |
||
| 5657 | #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ |
||
| 5658 | #define RTC_ALRMAR_MSK2_Pos (15U) |
||
| 5659 | #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ |
||
| 5660 | #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk |
||
| 5661 | #define RTC_ALRMAR_MNT_Pos (12U) |
||
| 5662 | #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ |
||
| 5663 | #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk |
||
| 5664 | #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ |
||
| 5665 | #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ |
||
| 5666 | #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ |
||
| 5667 | #define RTC_ALRMAR_MNU_Pos (8U) |
||
| 5668 | #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ |
||
| 5669 | #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk |
||
| 5670 | #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ |
||
| 5671 | #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ |
||
| 5672 | #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ |
||
| 5673 | #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ |
||
| 5674 | #define RTC_ALRMAR_MSK1_Pos (7U) |
||
| 5675 | #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ |
||
| 5676 | #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk |
||
| 5677 | #define RTC_ALRMAR_ST_Pos (4U) |
||
| 5678 | #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ |
||
| 5679 | #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk |
||
| 5680 | #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ |
||
| 5681 | #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ |
||
| 5682 | #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ |
||
| 5683 | #define RTC_ALRMAR_SU_Pos (0U) |
||
| 5684 | #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ |
||
| 5685 | #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk |
||
| 5686 | #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ |
||
| 5687 | #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ |
||
| 5688 | #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ |
||
| 5689 | #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ |
||
| 5690 | |||
| 5691 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
||
| 5692 | #define RTC_ALRMBR_MSK4_Pos (31U) |
||
| 5693 | #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ |
||
| 5694 | #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk |
||
| 5695 | #define RTC_ALRMBR_WDSEL_Pos (30U) |
||
| 5696 | #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ |
||
| 5697 | #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk |
||
| 5698 | #define RTC_ALRMBR_DT_Pos (28U) |
||
| 5699 | #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ |
||
| 5700 | #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk |
||
| 5701 | #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ |
||
| 5702 | #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ |
||
| 5703 | #define RTC_ALRMBR_DU_Pos (24U) |
||
| 5704 | #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ |
||
| 5705 | #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk |
||
| 5706 | #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ |
||
| 5707 | #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ |
||
| 5708 | #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ |
||
| 5709 | #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ |
||
| 5710 | #define RTC_ALRMBR_MSK3_Pos (23U) |
||
| 5711 | #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ |
||
| 5712 | #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk |
||
| 5713 | #define RTC_ALRMBR_PM_Pos (22U) |
||
| 5714 | #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ |
||
| 5715 | #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk |
||
| 5716 | #define RTC_ALRMBR_HT_Pos (20U) |
||
| 5717 | #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ |
||
| 5718 | #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk |
||
| 5719 | #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ |
||
| 5720 | #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ |
||
| 5721 | #define RTC_ALRMBR_HU_Pos (16U) |
||
| 5722 | #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ |
||
| 5723 | #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk |
||
| 5724 | #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ |
||
| 5725 | #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ |
||
| 5726 | #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ |
||
| 5727 | #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ |
||
| 5728 | #define RTC_ALRMBR_MSK2_Pos (15U) |
||
| 5729 | #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ |
||
| 5730 | #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk |
||
| 5731 | #define RTC_ALRMBR_MNT_Pos (12U) |
||
| 5732 | #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ |
||
| 5733 | #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk |
||
| 5734 | #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ |
||
| 5735 | #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ |
||
| 5736 | #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ |
||
| 5737 | #define RTC_ALRMBR_MNU_Pos (8U) |
||
| 5738 | #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ |
||
| 5739 | #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk |
||
| 5740 | #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ |
||
| 5741 | #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ |
||
| 5742 | #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ |
||
| 5743 | #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ |
||
| 5744 | #define RTC_ALRMBR_MSK1_Pos (7U) |
||
| 5745 | #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ |
||
| 5746 | #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk |
||
| 5747 | #define RTC_ALRMBR_ST_Pos (4U) |
||
| 5748 | #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ |
||
| 5749 | #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk |
||
| 5750 | #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ |
||
| 5751 | #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ |
||
| 5752 | #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ |
||
| 5753 | #define RTC_ALRMBR_SU_Pos (0U) |
||
| 5754 | #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ |
||
| 5755 | #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk |
||
| 5756 | #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ |
||
| 5757 | #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ |
||
| 5758 | #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ |
||
| 5759 | #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ |
||
| 5760 | |||
| 5761 | /******************** Bits definition for RTC_WPR register ******************/ |
||
| 5762 | #define RTC_WPR_KEY_Pos (0U) |
||
| 5763 | #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ |
||
| 5764 | #define RTC_WPR_KEY RTC_WPR_KEY_Msk |
||
| 5765 | |||
| 5766 | /******************** Bits definition for RTC_SSR register ******************/ |
||
| 5767 | #define RTC_SSR_SS_Pos (0U) |
||
| 5768 | #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ |
||
| 5769 | #define RTC_SSR_SS RTC_SSR_SS_Msk |
||
| 5770 | |||
| 5771 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
||
| 5772 | #define RTC_SHIFTR_SUBFS_Pos (0U) |
||
| 5773 | #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ |
||
| 5774 | #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk |
||
| 5775 | #define RTC_SHIFTR_ADD1S_Pos (31U) |
||
| 5776 | #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ |
||
| 5777 | #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk |
||
| 5778 | |||
| 5779 | /******************** Bits definition for RTC_TSTR register *****************/ |
||
| 5780 | #define RTC_TSTR_PM_Pos (22U) |
||
| 5781 | #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ |
||
| 5782 | #define RTC_TSTR_PM RTC_TSTR_PM_Msk |
||
| 5783 | #define RTC_TSTR_HT_Pos (20U) |
||
| 5784 | #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ |
||
| 5785 | #define RTC_TSTR_HT RTC_TSTR_HT_Msk |
||
| 5786 | #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ |
||
| 5787 | #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ |
||
| 5788 | #define RTC_TSTR_HU_Pos (16U) |
||
| 5789 | #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ |
||
| 5790 | #define RTC_TSTR_HU RTC_TSTR_HU_Msk |
||
| 5791 | #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ |
||
| 5792 | #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ |
||
| 5793 | #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ |
||
| 5794 | #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ |
||
| 5795 | #define RTC_TSTR_MNT_Pos (12U) |
||
| 5796 | #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ |
||
| 5797 | #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk |
||
| 5798 | #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ |
||
| 5799 | #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ |
||
| 5800 | #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ |
||
| 5801 | #define RTC_TSTR_MNU_Pos (8U) |
||
| 5802 | #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ |
||
| 5803 | #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk |
||
| 5804 | #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ |
||
| 5805 | #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ |
||
| 5806 | #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ |
||
| 5807 | #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ |
||
| 5808 | #define RTC_TSTR_ST_Pos (4U) |
||
| 5809 | #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ |
||
| 5810 | #define RTC_TSTR_ST RTC_TSTR_ST_Msk |
||
| 5811 | #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ |
||
| 5812 | #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ |
||
| 5813 | #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ |
||
| 5814 | #define RTC_TSTR_SU_Pos (0U) |
||
| 5815 | #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ |
||
| 5816 | #define RTC_TSTR_SU RTC_TSTR_SU_Msk |
||
| 5817 | #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ |
||
| 5818 | #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ |
||
| 5819 | #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ |
||
| 5820 | #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ |
||
| 5821 | |||
| 5822 | /******************** Bits definition for RTC_TSDR register *****************/ |
||
| 5823 | #define RTC_TSDR_WDU_Pos (13U) |
||
| 5824 | #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ |
||
| 5825 | #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk |
||
| 5826 | #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ |
||
| 5827 | #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ |
||
| 5828 | #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ |
||
| 5829 | #define RTC_TSDR_MT_Pos (12U) |
||
| 5830 | #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ |
||
| 5831 | #define RTC_TSDR_MT RTC_TSDR_MT_Msk |
||
| 5832 | #define RTC_TSDR_MU_Pos (8U) |
||
| 5833 | #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ |
||
| 5834 | #define RTC_TSDR_MU RTC_TSDR_MU_Msk |
||
| 5835 | #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ |
||
| 5836 | #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ |
||
| 5837 | #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ |
||
| 5838 | #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ |
||
| 5839 | #define RTC_TSDR_DT_Pos (4U) |
||
| 5840 | #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ |
||
| 5841 | #define RTC_TSDR_DT RTC_TSDR_DT_Msk |
||
| 5842 | #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ |
||
| 5843 | #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ |
||
| 5844 | #define RTC_TSDR_DU_Pos (0U) |
||
| 5845 | #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ |
||
| 5846 | #define RTC_TSDR_DU RTC_TSDR_DU_Msk |
||
| 5847 | #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ |
||
| 5848 | #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ |
||
| 5849 | #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ |
||
| 5850 | #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ |
||
| 5851 | |||
| 5852 | /******************** Bits definition for RTC_TSSSR register ****************/ |
||
| 5853 | #define RTC_TSSSR_SS_Pos (0U) |
||
| 5854 | #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ |
||
| 5855 | #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk |
||
| 5856 | |||
| 5857 | /******************** Bits definition for RTC_CAL register *****************/ |
||
| 5858 | #define RTC_CALR_CALP_Pos (15U) |
||
| 5859 | #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ |
||
| 5860 | #define RTC_CALR_CALP RTC_CALR_CALP_Msk |
||
| 5861 | #define RTC_CALR_CALW8_Pos (14U) |
||
| 5862 | #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ |
||
| 5863 | #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk |
||
| 5864 | #define RTC_CALR_CALW16_Pos (13U) |
||
| 5865 | #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ |
||
| 5866 | #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk |
||
| 5867 | #define RTC_CALR_CALM_Pos (0U) |
||
| 5868 | #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ |
||
| 5869 | #define RTC_CALR_CALM RTC_CALR_CALM_Msk |
||
| 5870 | #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ |
||
| 5871 | #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ |
||
| 5872 | #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ |
||
| 5873 | #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ |
||
| 5874 | #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ |
||
| 5875 | #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ |
||
| 5876 | #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ |
||
| 5877 | #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ |
||
| 5878 | #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ |
||
| 5879 | |||
| 5880 | /******************** Bits definition for RTC_TAFCR register ****************/ |
||
| 5881 | #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) |
||
| 5882 | #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ |
||
| 5883 | #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk |
||
| 5884 | #define RTC_TAFCR_TAMPPUDIS_Pos (15U) |
||
| 5885 | #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ |
||
| 5886 | #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk |
||
| 5887 | #define RTC_TAFCR_TAMPPRCH_Pos (13U) |
||
| 5888 | #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ |
||
| 5889 | #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk |
||
| 5890 | #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ |
||
| 5891 | #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ |
||
| 5892 | #define RTC_TAFCR_TAMPFLT_Pos (11U) |
||
| 5893 | #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ |
||
| 5894 | #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk |
||
| 5895 | #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ |
||
| 5896 | #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ |
||
| 5897 | #define RTC_TAFCR_TAMPFREQ_Pos (8U) |
||
| 5898 | #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ |
||
| 5899 | #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk |
||
| 5900 | #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ |
||
| 5901 | #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ |
||
| 5902 | #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ |
||
| 5903 | #define RTC_TAFCR_TAMPTS_Pos (7U) |
||
| 5904 | #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ |
||
| 5905 | #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk |
||
| 5906 | #define RTC_TAFCR_TAMP3TRG_Pos (6U) |
||
| 5907 | #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ |
||
| 5908 | #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk |
||
| 5909 | #define RTC_TAFCR_TAMP3E_Pos (5U) |
||
| 5910 | #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ |
||
| 5911 | #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk |
||
| 5912 | #define RTC_TAFCR_TAMP2TRG_Pos (4U) |
||
| 5913 | #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ |
||
| 5914 | #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk |
||
| 5915 | #define RTC_TAFCR_TAMP2E_Pos (3U) |
||
| 5916 | #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ |
||
| 5917 | #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk |
||
| 5918 | #define RTC_TAFCR_TAMPIE_Pos (2U) |
||
| 5919 | #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ |
||
| 5920 | #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk |
||
| 5921 | #define RTC_TAFCR_TAMP1TRG_Pos (1U) |
||
| 5922 | #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ |
||
| 5923 | #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk |
||
| 5924 | #define RTC_TAFCR_TAMP1E_Pos (0U) |
||
| 5925 | #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ |
||
| 5926 | #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk |
||
| 5927 | |||
| 5928 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
||
| 5929 | #define RTC_ALRMASSR_MASKSS_Pos (24U) |
||
| 5930 | #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ |
||
| 5931 | #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk |
||
| 5932 | #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ |
||
| 5933 | #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ |
||
| 5934 | #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ |
||
| 5935 | #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ |
||
| 5936 | #define RTC_ALRMASSR_SS_Pos (0U) |
||
| 5937 | #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ |
||
| 5938 | #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk |
||
| 5939 | |||
| 5940 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
||
| 5941 | #define RTC_ALRMBSSR_MASKSS_Pos (24U) |
||
| 5942 | #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ |
||
| 5943 | #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk |
||
| 5944 | #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ |
||
| 5945 | #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ |
||
| 5946 | #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ |
||
| 5947 | #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ |
||
| 5948 | #define RTC_ALRMBSSR_SS_Pos (0U) |
||
| 5949 | #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ |
||
| 5950 | #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk |
||
| 5951 | |||
| 5952 | /******************** Bits definition for RTC_BKP0R register ****************/ |
||
| 5953 | #define RTC_BKP0R_Pos (0U) |
||
| 5954 | #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5955 | #define RTC_BKP0R RTC_BKP0R_Msk |
||
| 5956 | |||
| 5957 | /******************** Bits definition for RTC_BKP1R register ****************/ |
||
| 5958 | #define RTC_BKP1R_Pos (0U) |
||
| 5959 | #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5960 | #define RTC_BKP1R RTC_BKP1R_Msk |
||
| 5961 | |||
| 5962 | /******************** Bits definition for RTC_BKP2R register ****************/ |
||
| 5963 | #define RTC_BKP2R_Pos (0U) |
||
| 5964 | #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5965 | #define RTC_BKP2R RTC_BKP2R_Msk |
||
| 5966 | |||
| 5967 | /******************** Bits definition for RTC_BKP3R register ****************/ |
||
| 5968 | #define RTC_BKP3R_Pos (0U) |
||
| 5969 | #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5970 | #define RTC_BKP3R RTC_BKP3R_Msk |
||
| 5971 | |||
| 5972 | /******************** Bits definition for RTC_BKP4R register ****************/ |
||
| 5973 | #define RTC_BKP4R_Pos (0U) |
||
| 5974 | #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5975 | #define RTC_BKP4R RTC_BKP4R_Msk |
||
| 5976 | |||
| 5977 | /******************** Bits definition for RTC_BKP5R register ****************/ |
||
| 5978 | #define RTC_BKP5R_Pos (0U) |
||
| 5979 | #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5980 | #define RTC_BKP5R RTC_BKP5R_Msk |
||
| 5981 | |||
| 5982 | /******************** Bits definition for RTC_BKP6R register ****************/ |
||
| 5983 | #define RTC_BKP6R_Pos (0U) |
||
| 5984 | #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5985 | #define RTC_BKP6R RTC_BKP6R_Msk |
||
| 5986 | |||
| 5987 | /******************** Bits definition for RTC_BKP7R register ****************/ |
||
| 5988 | #define RTC_BKP7R_Pos (0U) |
||
| 5989 | #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5990 | #define RTC_BKP7R RTC_BKP7R_Msk |
||
| 5991 | |||
| 5992 | /******************** Bits definition for RTC_BKP8R register ****************/ |
||
| 5993 | #define RTC_BKP8R_Pos (0U) |
||
| 5994 | #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ |
||
| 5995 | #define RTC_BKP8R RTC_BKP8R_Msk |
||
| 5996 | |||
| 5997 | /******************** Bits definition for RTC_BKP9R register ****************/ |
||
| 5998 | #define RTC_BKP9R_Pos (0U) |
||
| 5999 | #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6000 | #define RTC_BKP9R RTC_BKP9R_Msk |
||
| 6001 | |||
| 6002 | /******************** Bits definition for RTC_BKP10R register ***************/ |
||
| 6003 | #define RTC_BKP10R_Pos (0U) |
||
| 6004 | #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6005 | #define RTC_BKP10R RTC_BKP10R_Msk |
||
| 6006 | |||
| 6007 | /******************** Bits definition for RTC_BKP11R register ***************/ |
||
| 6008 | #define RTC_BKP11R_Pos (0U) |
||
| 6009 | #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6010 | #define RTC_BKP11R RTC_BKP11R_Msk |
||
| 6011 | |||
| 6012 | /******************** Bits definition for RTC_BKP12R register ***************/ |
||
| 6013 | #define RTC_BKP12R_Pos (0U) |
||
| 6014 | #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6015 | #define RTC_BKP12R RTC_BKP12R_Msk |
||
| 6016 | |||
| 6017 | /******************** Bits definition for RTC_BKP13R register ***************/ |
||
| 6018 | #define RTC_BKP13R_Pos (0U) |
||
| 6019 | #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6020 | #define RTC_BKP13R RTC_BKP13R_Msk |
||
| 6021 | |||
| 6022 | /******************** Bits definition for RTC_BKP14R register ***************/ |
||
| 6023 | #define RTC_BKP14R_Pos (0U) |
||
| 6024 | #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6025 | #define RTC_BKP14R RTC_BKP14R_Msk |
||
| 6026 | |||
| 6027 | /******************** Bits definition for RTC_BKP15R register ***************/ |
||
| 6028 | #define RTC_BKP15R_Pos (0U) |
||
| 6029 | #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6030 | #define RTC_BKP15R RTC_BKP15R_Msk |
||
| 6031 | |||
| 6032 | /******************** Bits definition for RTC_BKP16R register ***************/ |
||
| 6033 | #define RTC_BKP16R_Pos (0U) |
||
| 6034 | #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6035 | #define RTC_BKP16R RTC_BKP16R_Msk |
||
| 6036 | |||
| 6037 | /******************** Bits definition for RTC_BKP17R register ***************/ |
||
| 6038 | #define RTC_BKP17R_Pos (0U) |
||
| 6039 | #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6040 | #define RTC_BKP17R RTC_BKP17R_Msk |
||
| 6041 | |||
| 6042 | /******************** Bits definition for RTC_BKP18R register ***************/ |
||
| 6043 | #define RTC_BKP18R_Pos (0U) |
||
| 6044 | #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6045 | #define RTC_BKP18R RTC_BKP18R_Msk |
||
| 6046 | |||
| 6047 | /******************** Bits definition for RTC_BKP19R register ***************/ |
||
| 6048 | #define RTC_BKP19R_Pos (0U) |
||
| 6049 | #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6050 | #define RTC_BKP19R RTC_BKP19R_Msk |
||
| 6051 | |||
| 6052 | /******************** Bits definition for RTC_BKP20R register ***************/ |
||
| 6053 | #define RTC_BKP20R_Pos (0U) |
||
| 6054 | #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6055 | #define RTC_BKP20R RTC_BKP20R_Msk |
||
| 6056 | |||
| 6057 | /******************** Bits definition for RTC_BKP21R register ***************/ |
||
| 6058 | #define RTC_BKP21R_Pos (0U) |
||
| 6059 | #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6060 | #define RTC_BKP21R RTC_BKP21R_Msk |
||
| 6061 | |||
| 6062 | /******************** Bits definition for RTC_BKP22R register ***************/ |
||
| 6063 | #define RTC_BKP22R_Pos (0U) |
||
| 6064 | #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6065 | #define RTC_BKP22R RTC_BKP22R_Msk |
||
| 6066 | |||
| 6067 | /******************** Bits definition for RTC_BKP23R register ***************/ |
||
| 6068 | #define RTC_BKP23R_Pos (0U) |
||
| 6069 | #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6070 | #define RTC_BKP23R RTC_BKP23R_Msk |
||
| 6071 | |||
| 6072 | /******************** Bits definition for RTC_BKP24R register ***************/ |
||
| 6073 | #define RTC_BKP24R_Pos (0U) |
||
| 6074 | #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6075 | #define RTC_BKP24R RTC_BKP24R_Msk |
||
| 6076 | |||
| 6077 | /******************** Bits definition for RTC_BKP25R register ***************/ |
||
| 6078 | #define RTC_BKP25R_Pos (0U) |
||
| 6079 | #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6080 | #define RTC_BKP25R RTC_BKP25R_Msk |
||
| 6081 | |||
| 6082 | /******************** Bits definition for RTC_BKP26R register ***************/ |
||
| 6083 | #define RTC_BKP26R_Pos (0U) |
||
| 6084 | #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6085 | #define RTC_BKP26R RTC_BKP26R_Msk |
||
| 6086 | |||
| 6087 | /******************** Bits definition for RTC_BKP27R register ***************/ |
||
| 6088 | #define RTC_BKP27R_Pos (0U) |
||
| 6089 | #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6090 | #define RTC_BKP27R RTC_BKP27R_Msk |
||
| 6091 | |||
| 6092 | /******************** Bits definition for RTC_BKP28R register ***************/ |
||
| 6093 | #define RTC_BKP28R_Pos (0U) |
||
| 6094 | #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6095 | #define RTC_BKP28R RTC_BKP28R_Msk |
||
| 6096 | |||
| 6097 | /******************** Bits definition for RTC_BKP29R register ***************/ |
||
| 6098 | #define RTC_BKP29R_Pos (0U) |
||
| 6099 | #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6100 | #define RTC_BKP29R RTC_BKP29R_Msk |
||
| 6101 | |||
| 6102 | /******************** Bits definition for RTC_BKP30R register ***************/ |
||
| 6103 | #define RTC_BKP30R_Pos (0U) |
||
| 6104 | #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6105 | #define RTC_BKP30R RTC_BKP30R_Msk |
||
| 6106 | |||
| 6107 | /******************** Bits definition for RTC_BKP31R register ***************/ |
||
| 6108 | #define RTC_BKP31R_Pos (0U) |
||
| 6109 | #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */ |
||
| 6110 | #define RTC_BKP31R RTC_BKP31R_Msk |
||
| 6111 | |||
| 6112 | /******************** Number of backup registers ******************************/ |
||
| 6113 | #define RTC_BKP_NUMBER 32 |
||
| 6114 | |||
| 6115 | /******************************************************************************/ |
||
| 6116 | /* */ |
||
| 6117 | /* SD host Interface */ |
||
| 6118 | /* */ |
||
| 6119 | /******************************************************************************/ |
||
| 6120 | |||
| 6121 | /****************** Bit definition for SDIO_POWER register ******************/ |
||
| 6122 | #define SDIO_POWER_PWRCTRL_Pos (0U) |
||
| 6123 | #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ |
||
| 6124 | #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ |
||
| 6125 | #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000001 */ |
||
| 6126 | #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000002 */ |
||
| 6127 | |||
| 6128 | /****************** Bit definition for SDIO_CLKCR register ******************/ |
||
| 6129 | #define SDIO_CLKCR_CLKDIV_Pos (0U) |
||
| 6130 | #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ |
||
| 6131 | #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ |
||
| 6132 | #define SDIO_CLKCR_CLKEN_Pos (8U) |
||
| 6133 | #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ |
||
| 6134 | #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ |
||
| 6135 | #define SDIO_CLKCR_PWRSAV_Pos (9U) |
||
| 6136 | #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ |
||
| 6137 | #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ |
||
| 6138 | #define SDIO_CLKCR_BYPASS_Pos (10U) |
||
| 6139 | #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ |
||
| 6140 | #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ |
||
| 6141 | |||
| 6142 | #define SDIO_CLKCR_WIDBUS_Pos (11U) |
||
| 6143 | #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ |
||
| 6144 | #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
||
| 6145 | #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */ |
||
| 6146 | #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */ |
||
| 6147 | |||
| 6148 | #define SDIO_CLKCR_NEGEDGE_Pos (13U) |
||
| 6149 | #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ |
||
| 6150 | #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ |
||
| 6151 | #define SDIO_CLKCR_HWFC_EN_Pos (14U) |
||
| 6152 | #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ |
||
| 6153 | #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ |
||
| 6154 | |||
| 6155 | /******************* Bit definition for SDIO_ARG register *******************/ |
||
| 6156 | #define SDIO_ARG_CMDARG_Pos (0U) |
||
| 6157 | #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ |
||
| 6158 | #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ |
||
| 6159 | |||
| 6160 | /******************* Bit definition for SDIO_CMD register *******************/ |
||
| 6161 | #define SDIO_CMD_CMDINDEX_Pos (0U) |
||
| 6162 | #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ |
||
| 6163 | #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ |
||
| 6164 | |||
| 6165 | #define SDIO_CMD_WAITRESP_Pos (6U) |
||
| 6166 | #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ |
||
| 6167 | #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ |
||
| 6168 | #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000040 */ |
||
| 6169 | #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x00000080 */ |
||
| 6170 | |||
| 6171 | #define SDIO_CMD_WAITINT_Pos (8U) |
||
| 6172 | #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ |
||
| 6173 | #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ |
||
| 6174 | #define SDIO_CMD_WAITPEND_Pos (9U) |
||
| 6175 | #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ |
||
| 6176 | #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
||
| 6177 | #define SDIO_CMD_CPSMEN_Pos (10U) |
||
| 6178 | #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ |
||
| 6179 | #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ |
||
| 6180 | #define SDIO_CMD_SDIOSUSPEND_Pos (11U) |
||
| 6181 | #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ |
||
| 6182 | #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ |
||
| 6183 | #define SDIO_CMD_ENCMDCOMPL_Pos (12U) |
||
| 6184 | #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ |
||
| 6185 | #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ |
||
| 6186 | #define SDIO_CMD_NIEN_Pos (13U) |
||
| 6187 | #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ |
||
| 6188 | #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ |
||
| 6189 | #define SDIO_CMD_CEATACMD_Pos (14U) |
||
| 6190 | #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ |
||
| 6191 | #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ |
||
| 6192 | |||
| 6193 | /***************** Bit definition for SDIO_RESPCMD register *****************/ |
||
| 6194 | #define SDIO_RESPCMD_RESPCMD_Pos (0U) |
||
| 6195 | #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ |
||
| 6196 | #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ |
||
| 6197 | |||
| 6198 | /****************** Bit definition for SDIO_RESP0 register ******************/ |
||
| 6199 | #define SDIO_RESP0_CARDSTATUS0_Pos (0U) |
||
| 6200 | #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ |
||
| 6201 | #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ |
||
| 6202 | |||
| 6203 | /****************** Bit definition for SDIO_RESP1 register ******************/ |
||
| 6204 | #define SDIO_RESP1_CARDSTATUS1_Pos (0U) |
||
| 6205 | #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ |
||
| 6206 | #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ |
||
| 6207 | |||
| 6208 | /****************** Bit definition for SDIO_RESP2 register ******************/ |
||
| 6209 | #define SDIO_RESP2_CARDSTATUS2_Pos (0U) |
||
| 6210 | #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ |
||
| 6211 | #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ |
||
| 6212 | |||
| 6213 | /****************** Bit definition for SDIO_RESP3 register ******************/ |
||
| 6214 | #define SDIO_RESP3_CARDSTATUS3_Pos (0U) |
||
| 6215 | #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ |
||
| 6216 | #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ |
||
| 6217 | |||
| 6218 | /****************** Bit definition for SDIO_RESP4 register ******************/ |
||
| 6219 | #define SDIO_RESP4_CARDSTATUS4_Pos (0U) |
||
| 6220 | #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ |
||
| 6221 | #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ |
||
| 6222 | |||
| 6223 | /****************** Bit definition for SDIO_DTIMER register *****************/ |
||
| 6224 | #define SDIO_DTIMER_DATATIME_Pos (0U) |
||
| 6225 | #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ |
||
| 6226 | #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ |
||
| 6227 | |||
| 6228 | /****************** Bit definition for SDIO_DLEN register *******************/ |
||
| 6229 | #define SDIO_DLEN_DATALENGTH_Pos (0U) |
||
| 6230 | #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ |
||
| 6231 | #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ |
||
| 6232 | |||
| 6233 | /****************** Bit definition for SDIO_DCTRL register ******************/ |
||
| 6234 | #define SDIO_DCTRL_DTEN_Pos (0U) |
||
| 6235 | #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ |
||
| 6236 | #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ |
||
| 6237 | #define SDIO_DCTRL_DTDIR_Pos (1U) |
||
| 6238 | #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ |
||
| 6239 | #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ |
||
| 6240 | #define SDIO_DCTRL_DTMODE_Pos (2U) |
||
| 6241 | #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ |
||
| 6242 | #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ |
||
| 6243 | #define SDIO_DCTRL_DMAEN_Pos (3U) |
||
| 6244 | #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ |
||
| 6245 | #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ |
||
| 6246 | |||
| 6247 | #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) |
||
| 6248 | #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ |
||
| 6249 | #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ |
||
| 6250 | #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */ |
||
| 6251 | #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */ |
||
| 6252 | #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */ |
||
| 6253 | #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */ |
||
| 6254 | |||
| 6255 | #define SDIO_DCTRL_RWSTART_Pos (8U) |
||
| 6256 | #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ |
||
| 6257 | #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ |
||
| 6258 | #define SDIO_DCTRL_RWSTOP_Pos (9U) |
||
| 6259 | #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ |
||
| 6260 | #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ |
||
| 6261 | #define SDIO_DCTRL_RWMOD_Pos (10U) |
||
| 6262 | #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ |
||
| 6263 | #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ |
||
| 6264 | #define SDIO_DCTRL_SDIOEN_Pos (11U) |
||
| 6265 | #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ |
||
| 6266 | #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ |
||
| 6267 | |||
| 6268 | /****************** Bit definition for SDIO_DCOUNT register *****************/ |
||
| 6269 | #define SDIO_DCOUNT_DATACOUNT_Pos (0U) |
||
| 6270 | #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ |
||
| 6271 | #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ |
||
| 6272 | |||
| 6273 | /****************** Bit definition for SDIO_STA register ********************/ |
||
| 6274 | #define SDIO_STA_CCRCFAIL_Pos (0U) |
||
| 6275 | #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ |
||
| 6276 | #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ |
||
| 6277 | #define SDIO_STA_DCRCFAIL_Pos (1U) |
||
| 6278 | #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ |
||
| 6279 | #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ |
||
| 6280 | #define SDIO_STA_CTIMEOUT_Pos (2U) |
||
| 6281 | #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ |
||
| 6282 | #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ |
||
| 6283 | #define SDIO_STA_DTIMEOUT_Pos (3U) |
||
| 6284 | #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ |
||
| 6285 | #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ |
||
| 6286 | #define SDIO_STA_TXUNDERR_Pos (4U) |
||
| 6287 | #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ |
||
| 6288 | #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ |
||
| 6289 | #define SDIO_STA_RXOVERR_Pos (5U) |
||
| 6290 | #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ |
||
| 6291 | #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ |
||
| 6292 | #define SDIO_STA_CMDREND_Pos (6U) |
||
| 6293 | #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ |
||
| 6294 | #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ |
||
| 6295 | #define SDIO_STA_CMDSENT_Pos (7U) |
||
| 6296 | #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ |
||
| 6297 | #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ |
||
| 6298 | #define SDIO_STA_DATAEND_Pos (8U) |
||
| 6299 | #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ |
||
| 6300 | #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ |
||
| 6301 | #define SDIO_STA_STBITERR_Pos (9U) |
||
| 6302 | #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ |
||
| 6303 | #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ |
||
| 6304 | #define SDIO_STA_DBCKEND_Pos (10U) |
||
| 6305 | #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ |
||
| 6306 | #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ |
||
| 6307 | #define SDIO_STA_CMDACT_Pos (11U) |
||
| 6308 | #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ |
||
| 6309 | #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ |
||
| 6310 | #define SDIO_STA_TXACT_Pos (12U) |
||
| 6311 | #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ |
||
| 6312 | #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ |
||
| 6313 | #define SDIO_STA_RXACT_Pos (13U) |
||
| 6314 | #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ |
||
| 6315 | #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ |
||
| 6316 | #define SDIO_STA_TXFIFOHE_Pos (14U) |
||
| 6317 | #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ |
||
| 6318 | #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
||
| 6319 | #define SDIO_STA_RXFIFOHF_Pos (15U) |
||
| 6320 | #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ |
||
| 6321 | #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
||
| 6322 | #define SDIO_STA_TXFIFOF_Pos (16U) |
||
| 6323 | #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ |
||
| 6324 | #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ |
||
| 6325 | #define SDIO_STA_RXFIFOF_Pos (17U) |
||
| 6326 | #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ |
||
| 6327 | #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ |
||
| 6328 | #define SDIO_STA_TXFIFOE_Pos (18U) |
||
| 6329 | #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ |
||
| 6330 | #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ |
||
| 6331 | #define SDIO_STA_RXFIFOE_Pos (19U) |
||
| 6332 | #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ |
||
| 6333 | #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ |
||
| 6334 | #define SDIO_STA_TXDAVL_Pos (20U) |
||
| 6335 | #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ |
||
| 6336 | #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ |
||
| 6337 | #define SDIO_STA_RXDAVL_Pos (21U) |
||
| 6338 | #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ |
||
| 6339 | #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ |
||
| 6340 | #define SDIO_STA_SDIOIT_Pos (22U) |
||
| 6341 | #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ |
||
| 6342 | #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ |
||
| 6343 | #define SDIO_STA_CEATAEND_Pos (23U) |
||
| 6344 | #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ |
||
| 6345 | #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ |
||
| 6346 | |||
| 6347 | /******************* Bit definition for SDIO_ICR register *******************/ |
||
| 6348 | #define SDIO_ICR_CCRCFAILC_Pos (0U) |
||
| 6349 | #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ |
||
| 6350 | #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ |
||
| 6351 | #define SDIO_ICR_DCRCFAILC_Pos (1U) |
||
| 6352 | #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ |
||
| 6353 | #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ |
||
| 6354 | #define SDIO_ICR_CTIMEOUTC_Pos (2U) |
||
| 6355 | #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ |
||
| 6356 | #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ |
||
| 6357 | #define SDIO_ICR_DTIMEOUTC_Pos (3U) |
||
| 6358 | #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ |
||
| 6359 | #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ |
||
| 6360 | #define SDIO_ICR_TXUNDERRC_Pos (4U) |
||
| 6361 | #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ |
||
| 6362 | #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ |
||
| 6363 | #define SDIO_ICR_RXOVERRC_Pos (5U) |
||
| 6364 | #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ |
||
| 6365 | #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ |
||
| 6366 | #define SDIO_ICR_CMDRENDC_Pos (6U) |
||
| 6367 | #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ |
||
| 6368 | #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ |
||
| 6369 | #define SDIO_ICR_CMDSENTC_Pos (7U) |
||
| 6370 | #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ |
||
| 6371 | #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ |
||
| 6372 | #define SDIO_ICR_DATAENDC_Pos (8U) |
||
| 6373 | #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ |
||
| 6374 | #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ |
||
| 6375 | #define SDIO_ICR_STBITERRC_Pos (9U) |
||
| 6376 | #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ |
||
| 6377 | #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ |
||
| 6378 | #define SDIO_ICR_DBCKENDC_Pos (10U) |
||
| 6379 | #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ |
||
| 6380 | #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ |
||
| 6381 | #define SDIO_ICR_SDIOITC_Pos (22U) |
||
| 6382 | #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ |
||
| 6383 | #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ |
||
| 6384 | #define SDIO_ICR_CEATAENDC_Pos (23U) |
||
| 6385 | #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ |
||
| 6386 | #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ |
||
| 6387 | |||
| 6388 | /****************** Bit definition for SDIO_MASK register *******************/ |
||
| 6389 | #define SDIO_MASK_CCRCFAILIE_Pos (0U) |
||
| 6390 | #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ |
||
| 6391 | #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ |
||
| 6392 | #define SDIO_MASK_DCRCFAILIE_Pos (1U) |
||
| 6393 | #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ |
||
| 6394 | #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ |
||
| 6395 | #define SDIO_MASK_CTIMEOUTIE_Pos (2U) |
||
| 6396 | #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ |
||
| 6397 | #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ |
||
| 6398 | #define SDIO_MASK_DTIMEOUTIE_Pos (3U) |
||
| 6399 | #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ |
||
| 6400 | #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ |
||
| 6401 | #define SDIO_MASK_TXUNDERRIE_Pos (4U) |
||
| 6402 | #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ |
||
| 6403 | #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ |
||
| 6404 | #define SDIO_MASK_RXOVERRIE_Pos (5U) |
||
| 6405 | #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ |
||
| 6406 | #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ |
||
| 6407 | #define SDIO_MASK_CMDRENDIE_Pos (6U) |
||
| 6408 | #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ |
||
| 6409 | #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ |
||
| 6410 | #define SDIO_MASK_CMDSENTIE_Pos (7U) |
||
| 6411 | #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ |
||
| 6412 | #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ |
||
| 6413 | #define SDIO_MASK_DATAENDIE_Pos (8U) |
||
| 6414 | #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ |
||
| 6415 | #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ |
||
| 6416 | #define SDIO_MASK_STBITERRIE_Pos (9U) |
||
| 6417 | #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ |
||
| 6418 | #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ |
||
| 6419 | #define SDIO_MASK_DBCKENDIE_Pos (10U) |
||
| 6420 | #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ |
||
| 6421 | #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ |
||
| 6422 | #define SDIO_MASK_CMDACTIE_Pos (11U) |
||
| 6423 | #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ |
||
| 6424 | #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ |
||
| 6425 | #define SDIO_MASK_TXACTIE_Pos (12U) |
||
| 6426 | #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ |
||
| 6427 | #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ |
||
| 6428 | #define SDIO_MASK_RXACTIE_Pos (13U) |
||
| 6429 | #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ |
||
| 6430 | #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ |
||
| 6431 | #define SDIO_MASK_TXFIFOHEIE_Pos (14U) |
||
| 6432 | #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ |
||
| 6433 | #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ |
||
| 6434 | #define SDIO_MASK_RXFIFOHFIE_Pos (15U) |
||
| 6435 | #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ |
||
| 6436 | #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ |
||
| 6437 | #define SDIO_MASK_TXFIFOFIE_Pos (16U) |
||
| 6438 | #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ |
||
| 6439 | #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ |
||
| 6440 | #define SDIO_MASK_RXFIFOFIE_Pos (17U) |
||
| 6441 | #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ |
||
| 6442 | #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ |
||
| 6443 | #define SDIO_MASK_TXFIFOEIE_Pos (18U) |
||
| 6444 | #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ |
||
| 6445 | #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ |
||
| 6446 | #define SDIO_MASK_RXFIFOEIE_Pos (19U) |
||
| 6447 | #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ |
||
| 6448 | #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ |
||
| 6449 | #define SDIO_MASK_TXDAVLIE_Pos (20U) |
||
| 6450 | #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ |
||
| 6451 | #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ |
||
| 6452 | #define SDIO_MASK_RXDAVLIE_Pos (21U) |
||
| 6453 | #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ |
||
| 6454 | #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ |
||
| 6455 | #define SDIO_MASK_SDIOITIE_Pos (22U) |
||
| 6456 | #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ |
||
| 6457 | #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ |
||
| 6458 | #define SDIO_MASK_CEATAENDIE_Pos (23U) |
||
| 6459 | #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ |
||
| 6460 | #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ |
||
| 6461 | |||
| 6462 | /***************** Bit definition for SDIO_FIFOCNT register *****************/ |
||
| 6463 | #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) |
||
| 6464 | #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ |
||
| 6465 | #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ |
||
| 6466 | |||
| 6467 | /****************** Bit definition for SDIO_FIFO register *******************/ |
||
| 6468 | #define SDIO_FIFO_FIFODATA_Pos (0U) |
||
| 6469 | #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ |
||
| 6470 | #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ |
||
| 6471 | |||
| 6472 | /******************************************************************************/ |
||
| 6473 | /* */ |
||
| 6474 | /* Serial Peripheral Interface (SPI) */ |
||
| 6475 | /* */ |
||
| 6476 | /******************************************************************************/ |
||
| 6477 | |||
| 6478 | /* |
||
| 6479 | * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) |
||
| 6480 | */ |
||
| 6481 | #define SPI_I2S_SUPPORT |
||
| 6482 | |||
| 6483 | /******************* Bit definition for SPI_CR1 register ********************/ |
||
| 6484 | #define SPI_CR1_CPHA_Pos (0U) |
||
| 6485 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
||
| 6486 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ |
||
| 6487 | #define SPI_CR1_CPOL_Pos (1U) |
||
| 6488 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
||
| 6489 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ |
||
| 6490 | #define SPI_CR1_MSTR_Pos (2U) |
||
| 6491 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
||
| 6492 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ |
||
| 6493 | |||
| 6494 | #define SPI_CR1_BR_Pos (3U) |
||
| 6495 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
||
| 6496 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ |
||
| 6497 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
||
| 6498 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
||
| 6499 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
||
| 6500 | |||
| 6501 | #define SPI_CR1_SPE_Pos (6U) |
||
| 6502 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
||
| 6503 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ |
||
| 6504 | #define SPI_CR1_LSBFIRST_Pos (7U) |
||
| 6505 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
||
| 6506 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ |
||
| 6507 | #define SPI_CR1_SSI_Pos (8U) |
||
| 6508 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
||
| 6509 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ |
||
| 6510 | #define SPI_CR1_SSM_Pos (9U) |
||
| 6511 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
||
| 6512 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ |
||
| 6513 | #define SPI_CR1_RXONLY_Pos (10U) |
||
| 6514 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
||
| 6515 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ |
||
| 6516 | #define SPI_CR1_DFF_Pos (11U) |
||
| 6517 | #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ |
||
| 6518 | #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ |
||
| 6519 | #define SPI_CR1_CRCNEXT_Pos (12U) |
||
| 6520 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
||
| 6521 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ |
||
| 6522 | #define SPI_CR1_CRCEN_Pos (13U) |
||
| 6523 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
||
| 6524 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ |
||
| 6525 | #define SPI_CR1_BIDIOE_Pos (14U) |
||
| 6526 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
||
| 6527 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ |
||
| 6528 | #define SPI_CR1_BIDIMODE_Pos (15U) |
||
| 6529 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
||
| 6530 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ |
||
| 6531 | |||
| 6532 | /******************* Bit definition for SPI_CR2 register ********************/ |
||
| 6533 | #define SPI_CR2_RXDMAEN_Pos (0U) |
||
| 6534 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
||
| 6535 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
||
| 6536 | #define SPI_CR2_TXDMAEN_Pos (1U) |
||
| 6537 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
||
| 6538 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
||
| 6539 | #define SPI_CR2_SSOE_Pos (2U) |
||
| 6540 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
||
| 6541 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
||
| 6542 | #define SPI_CR2_FRF_Pos (4U) |
||
| 6543 | #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ |
||
| 6544 | #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */ |
||
| 6545 | #define SPI_CR2_ERRIE_Pos (5U) |
||
| 6546 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
||
| 6547 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
||
| 6548 | #define SPI_CR2_RXNEIE_Pos (6U) |
||
| 6549 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
||
| 6550 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
||
| 6551 | #define SPI_CR2_TXEIE_Pos (7U) |
||
| 6552 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
||
| 6553 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
||
| 6554 | |||
| 6555 | /******************** Bit definition for SPI_SR register ********************/ |
||
| 6556 | #define SPI_SR_RXNE_Pos (0U) |
||
| 6557 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
||
| 6558 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
||
| 6559 | #define SPI_SR_TXE_Pos (1U) |
||
| 6560 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
||
| 6561 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
||
| 6562 | #define SPI_SR_CHSIDE_Pos (2U) |
||
| 6563 | #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
||
| 6564 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
||
| 6565 | #define SPI_SR_UDR_Pos (3U) |
||
| 6566 | #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
||
| 6567 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
||
| 6568 | #define SPI_SR_CRCERR_Pos (4U) |
||
| 6569 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
||
| 6570 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
||
| 6571 | #define SPI_SR_MODF_Pos (5U) |
||
| 6572 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
||
| 6573 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
||
| 6574 | #define SPI_SR_OVR_Pos (6U) |
||
| 6575 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
||
| 6576 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
||
| 6577 | #define SPI_SR_BSY_Pos (7U) |
||
| 6578 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
||
| 6579 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
||
| 6580 | #define SPI_SR_FRE_Pos (8U) |
||
| 6581 | #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ |
||
| 6582 | #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ |
||
| 6583 | |||
| 6584 | /******************** Bit definition for SPI_DR register ********************/ |
||
| 6585 | #define SPI_DR_DR_Pos (0U) |
||
| 6586 | #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
||
| 6587 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ |
||
| 6588 | |||
| 6589 | /******************* Bit definition for SPI_CRCPR register ******************/ |
||
| 6590 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
||
| 6591 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
||
| 6592 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ |
||
| 6593 | |||
| 6594 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
||
| 6595 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
||
| 6596 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
||
| 6597 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ |
||
| 6598 | |||
| 6599 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
||
| 6600 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
||
| 6601 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
||
| 6602 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ |
||
| 6603 | |||
| 6604 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
||
| 6605 | #define SPI_I2SCFGR_CHLEN_Pos (0U) |
||
| 6606 | #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ |
||
| 6607 | #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ |
||
| 6608 | |||
| 6609 | #define SPI_I2SCFGR_DATLEN_Pos (1U) |
||
| 6610 | #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ |
||
| 6611 | #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ |
||
| 6612 | #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ |
||
| 6613 | #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ |
||
| 6614 | |||
| 6615 | #define SPI_I2SCFGR_CKPOL_Pos (3U) |
||
| 6616 | #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ |
||
| 6617 | #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ |
||
| 6618 | |||
| 6619 | #define SPI_I2SCFGR_I2SSTD_Pos (4U) |
||
| 6620 | #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ |
||
| 6621 | #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ |
||
| 6622 | #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ |
||
| 6623 | #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ |
||
| 6624 | |||
| 6625 | #define SPI_I2SCFGR_PCMSYNC_Pos (7U) |
||
| 6626 | #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ |
||
| 6627 | #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ |
||
| 6628 | |||
| 6629 | #define SPI_I2SCFGR_I2SCFG_Pos (8U) |
||
| 6630 | #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ |
||
| 6631 | #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ |
||
| 6632 | #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ |
||
| 6633 | #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ |
||
| 6634 | |||
| 6635 | #define SPI_I2SCFGR_I2SE_Pos (10U) |
||
| 6636 | #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ |
||
| 6637 | #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ |
||
| 6638 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) |
||
| 6639 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ |
||
| 6640 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ |
||
| 6641 | |||
| 6642 | /****************** Bit definition for SPI_I2SPR register *******************/ |
||
| 6643 | #define SPI_I2SPR_I2SDIV_Pos (0U) |
||
| 6644 | #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ |
||
| 6645 | #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ |
||
| 6646 | #define SPI_I2SPR_ODD_Pos (8U) |
||
| 6647 | #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ |
||
| 6648 | #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ |
||
| 6649 | #define SPI_I2SPR_MCKOE_Pos (9U) |
||
| 6650 | #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ |
||
| 6651 | #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ |
||
| 6652 | |||
| 6653 | /******************************************************************************/ |
||
| 6654 | /* */ |
||
| 6655 | /* System Configuration (SYSCFG) */ |
||
| 6656 | /* */ |
||
| 6657 | /******************************************************************************/ |
||
| 6658 | /***************** Bit definition for SYSCFG_MEMRMP register ****************/ |
||
| 6659 | #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) |
||
| 6660 | #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ |
||
| 6661 | #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ |
||
| 6662 | #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ |
||
| 6663 | #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ |
||
| 6664 | #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U) |
||
| 6665 | #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */ |
||
| 6666 | #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */ |
||
| 6667 | #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */ |
||
| 6668 | #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */ |
||
| 6669 | |||
| 6670 | /***************** Bit definition for SYSCFG_PMC register *******************/ |
||
| 6671 | #define SYSCFG_PMC_USB_PU_Pos (0U) |
||
| 6672 | #define SYSCFG_PMC_USB_PU_Msk (0x1U << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */ |
||
| 6673 | #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */ |
||
| 6674 | #define SYSCFG_PMC_LCD_CAPA_Pos (1U) |
||
| 6675 | #define SYSCFG_PMC_LCD_CAPA_Msk (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */ |
||
| 6676 | #define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */ |
||
| 6677 | #define SYSCFG_PMC_LCD_CAPA_0 (0x01U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */ |
||
| 6678 | #define SYSCFG_PMC_LCD_CAPA_1 (0x02U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */ |
||
| 6679 | #define SYSCFG_PMC_LCD_CAPA_2 (0x04U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */ |
||
| 6680 | #define SYSCFG_PMC_LCD_CAPA_3 (0x08U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */ |
||
| 6681 | #define SYSCFG_PMC_LCD_CAPA_4 (0x10U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */ |
||
| 6682 | |||
| 6683 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
||
| 6684 | #define SYSCFG_EXTICR1_EXTI0_Pos (0U) |
||
| 6685 | #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
||
| 6686 | #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ |
||
| 6687 | #define SYSCFG_EXTICR1_EXTI1_Pos (4U) |
||
| 6688 | #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
||
| 6689 | #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ |
||
| 6690 | #define SYSCFG_EXTICR1_EXTI2_Pos (8U) |
||
| 6691 | #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
||
| 6692 | #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ |
||
| 6693 | #define SYSCFG_EXTICR1_EXTI3_Pos (12U) |
||
| 6694 | #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
||
| 6695 | #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ |
||
| 6696 | |||
| 6697 | /** |
||
| 6698 | * @brief EXTI0 configuration |
||
| 6699 | */ |
||
| 6700 | #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ |
||
| 6701 | #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ |
||
| 6702 | #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ |
||
| 6703 | #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ |
||
| 6704 | #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ |
||
| 6705 | #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ |
||
| 6706 | #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */ |
||
| 6707 | #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */ |
||
| 6708 | |||
| 6709 | /** |
||
| 6710 | * @brief EXTI1 configuration |
||
| 6711 | */ |
||
| 6712 | #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ |
||
| 6713 | #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ |
||
| 6714 | #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ |
||
| 6715 | #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ |
||
| 6716 | #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ |
||
| 6717 | #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ |
||
| 6718 | #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */ |
||
| 6719 | #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */ |
||
| 6720 | |||
| 6721 | /** |
||
| 6722 | * @brief EXTI2 configuration |
||
| 6723 | */ |
||
| 6724 | #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ |
||
| 6725 | #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ |
||
| 6726 | #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ |
||
| 6727 | #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ |
||
| 6728 | #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ |
||
| 6729 | #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */ |
||
| 6730 | #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */ |
||
| 6731 | #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */ |
||
| 6732 | |||
| 6733 | /** |
||
| 6734 | * @brief EXTI3 configuration |
||
| 6735 | */ |
||
| 6736 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ |
||
| 6737 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ |
||
| 6738 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ |
||
| 6739 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ |
||
| 6740 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ |
||
| 6741 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */ |
||
| 6742 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */ |
||
| 6743 | |||
| 6744 | /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ |
||
| 6745 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
||
| 6746 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
||
| 6747 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
||
| 6748 | #define SYSCFG_EXTICR2_EXTI5_Pos (4U) |
||
| 6749 | #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
||
| 6750 | #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ |
||
| 6751 | #define SYSCFG_EXTICR2_EXTI6_Pos (8U) |
||
| 6752 | #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
||
| 6753 | #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ |
||
| 6754 | #define SYSCFG_EXTICR2_EXTI7_Pos (12U) |
||
| 6755 | #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
||
| 6756 | #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ |
||
| 6757 | |||
| 6758 | /** |
||
| 6759 | * @brief EXTI4 configuration |
||
| 6760 | */ |
||
| 6761 | #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ |
||
| 6762 | #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ |
||
| 6763 | #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ |
||
| 6764 | #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ |
||
| 6765 | #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ |
||
| 6766 | #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */ |
||
| 6767 | #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */ |
||
| 6768 | |||
| 6769 | /** |
||
| 6770 | * @brief EXTI5 configuration |
||
| 6771 | */ |
||
| 6772 | #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ |
||
| 6773 | #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ |
||
| 6774 | #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ |
||
| 6775 | #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ |
||
| 6776 | #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ |
||
| 6777 | #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */ |
||
| 6778 | #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */ |
||
| 6779 | |||
| 6780 | /** |
||
| 6781 | * @brief EXTI6 configuration |
||
| 6782 | */ |
||
| 6783 | #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ |
||
| 6784 | #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ |
||
| 6785 | #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ |
||
| 6786 | #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ |
||
| 6787 | #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ |
||
| 6788 | #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */ |
||
| 6789 | #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */ |
||
| 6790 | |||
| 6791 | /** |
||
| 6792 | * @brief EXTI7 configuration |
||
| 6793 | */ |
||
| 6794 | #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ |
||
| 6795 | #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ |
||
| 6796 | #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ |
||
| 6797 | #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ |
||
| 6798 | #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ |
||
| 6799 | #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */ |
||
| 6800 | #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */ |
||
| 6801 | |||
| 6802 | /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ |
||
| 6803 | #define SYSCFG_EXTICR3_EXTI8_Pos (0U) |
||
| 6804 | #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
||
| 6805 | #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ |
||
| 6806 | #define SYSCFG_EXTICR3_EXTI9_Pos (4U) |
||
| 6807 | #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
||
| 6808 | #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ |
||
| 6809 | #define SYSCFG_EXTICR3_EXTI10_Pos (8U) |
||
| 6810 | #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
||
| 6811 | #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ |
||
| 6812 | #define SYSCFG_EXTICR3_EXTI11_Pos (12U) |
||
| 6813 | #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
||
| 6814 | #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ |
||
| 6815 | |||
| 6816 | /** |
||
| 6817 | * @brief EXTI8 configuration |
||
| 6818 | */ |
||
| 6819 | #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ |
||
| 6820 | #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ |
||
| 6821 | #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ |
||
| 6822 | #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ |
||
| 6823 | #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ |
||
| 6824 | #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */ |
||
| 6825 | #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */ |
||
| 6826 | |||
| 6827 | /** |
||
| 6828 | * @brief EXTI9 configuration |
||
| 6829 | */ |
||
| 6830 | #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ |
||
| 6831 | #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ |
||
| 6832 | #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ |
||
| 6833 | #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ |
||
| 6834 | #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ |
||
| 6835 | #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */ |
||
| 6836 | #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */ |
||
| 6837 | |||
| 6838 | /** |
||
| 6839 | * @brief EXTI10 configuration |
||
| 6840 | */ |
||
| 6841 | #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ |
||
| 6842 | #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ |
||
| 6843 | #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ |
||
| 6844 | #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ |
||
| 6845 | #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ |
||
| 6846 | #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */ |
||
| 6847 | #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */ |
||
| 6848 | |||
| 6849 | /** |
||
| 6850 | * @brief EXTI11 configuration |
||
| 6851 | */ |
||
| 6852 | #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ |
||
| 6853 | #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ |
||
| 6854 | #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ |
||
| 6855 | #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ |
||
| 6856 | #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ |
||
| 6857 | #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */ |
||
| 6858 | #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */ |
||
| 6859 | |||
| 6860 | /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ |
||
| 6861 | #define SYSCFG_EXTICR4_EXTI12_Pos (0U) |
||
| 6862 | #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
||
| 6863 | #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ |
||
| 6864 | #define SYSCFG_EXTICR4_EXTI13_Pos (4U) |
||
| 6865 | #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
||
| 6866 | #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ |
||
| 6867 | #define SYSCFG_EXTICR4_EXTI14_Pos (8U) |
||
| 6868 | #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
||
| 6869 | #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ |
||
| 6870 | #define SYSCFG_EXTICR4_EXTI15_Pos (12U) |
||
| 6871 | #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
||
| 6872 | #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ |
||
| 6873 | |||
| 6874 | /** |
||
| 6875 | * @brief EXTI12 configuration |
||
| 6876 | */ |
||
| 6877 | #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ |
||
| 6878 | #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ |
||
| 6879 | #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ |
||
| 6880 | #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ |
||
| 6881 | #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ |
||
| 6882 | #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */ |
||
| 6883 | #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */ |
||
| 6884 | |||
| 6885 | /** |
||
| 6886 | * @brief EXTI13 configuration |
||
| 6887 | */ |
||
| 6888 | #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ |
||
| 6889 | #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ |
||
| 6890 | #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ |
||
| 6891 | #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ |
||
| 6892 | #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ |
||
| 6893 | #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */ |
||
| 6894 | #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */ |
||
| 6895 | |||
| 6896 | /** |
||
| 6897 | * @brief EXTI14 configuration |
||
| 6898 | */ |
||
| 6899 | #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ |
||
| 6900 | #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ |
||
| 6901 | #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ |
||
| 6902 | #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ |
||
| 6903 | #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ |
||
| 6904 | #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */ |
||
| 6905 | #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */ |
||
| 6906 | |||
| 6907 | /** |
||
| 6908 | * @brief EXTI15 configuration |
||
| 6909 | */ |
||
| 6910 | #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ |
||
| 6911 | #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ |
||
| 6912 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ |
||
| 6913 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ |
||
| 6914 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ |
||
| 6915 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ |
||
| 6916 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ |
||
| 6917 | |||
| 6918 | /******************************************************************************/ |
||
| 6919 | /* */ |
||
| 6920 | /* Routing Interface (RI) */ |
||
| 6921 | /* */ |
||
| 6922 | /******************************************************************************/ |
||
| 6923 | |||
| 6924 | /******************** Bit definition for RI_ICR register ********************/ |
||
| 6925 | #define RI_ICR_IC1OS_Pos (0U) |
||
| 6926 | #define RI_ICR_IC1OS_Msk (0xFU << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */ |
||
| 6927 | #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */ |
||
| 6928 | #define RI_ICR_IC1OS_0 (0x1U << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */ |
||
| 6929 | #define RI_ICR_IC1OS_1 (0x2U << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */ |
||
| 6930 | #define RI_ICR_IC1OS_2 (0x4U << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */ |
||
| 6931 | #define RI_ICR_IC1OS_3 (0x8U << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */ |
||
| 6932 | |||
| 6933 | #define RI_ICR_IC2OS_Pos (4U) |
||
| 6934 | #define RI_ICR_IC2OS_Msk (0xFU << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */ |
||
| 6935 | #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */ |
||
| 6936 | #define RI_ICR_IC2OS_0 (0x1U << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */ |
||
| 6937 | #define RI_ICR_IC2OS_1 (0x2U << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */ |
||
| 6938 | #define RI_ICR_IC2OS_2 (0x4U << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */ |
||
| 6939 | #define RI_ICR_IC2OS_3 (0x8U << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */ |
||
| 6940 | |||
| 6941 | #define RI_ICR_IC3OS_Pos (8U) |
||
| 6942 | #define RI_ICR_IC3OS_Msk (0xFU << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */ |
||
| 6943 | #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */ |
||
| 6944 | #define RI_ICR_IC3OS_0 (0x1U << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */ |
||
| 6945 | #define RI_ICR_IC3OS_1 (0x2U << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */ |
||
| 6946 | #define RI_ICR_IC3OS_2 (0x4U << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */ |
||
| 6947 | #define RI_ICR_IC3OS_3 (0x8U << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */ |
||
| 6948 | |||
| 6949 | #define RI_ICR_IC4OS_Pos (12U) |
||
| 6950 | #define RI_ICR_IC4OS_Msk (0xFU << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */ |
||
| 6951 | #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */ |
||
| 6952 | #define RI_ICR_IC4OS_0 (0x1U << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */ |
||
| 6953 | #define RI_ICR_IC4OS_1 (0x2U << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */ |
||
| 6954 | #define RI_ICR_IC4OS_2 (0x4U << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */ |
||
| 6955 | #define RI_ICR_IC4OS_3 (0x8U << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */ |
||
| 6956 | |||
| 6957 | #define RI_ICR_TIM_Pos (16U) |
||
| 6958 | #define RI_ICR_TIM_Msk (0x3U << RI_ICR_TIM_Pos) /*!< 0x00030000 */ |
||
| 6959 | #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */ |
||
| 6960 | #define RI_ICR_TIM_0 (0x1U << RI_ICR_TIM_Pos) /*!< 0x00010000 */ |
||
| 6961 | #define RI_ICR_TIM_1 (0x2U << RI_ICR_TIM_Pos) /*!< 0x00020000 */ |
||
| 6962 | |||
| 6963 | #define RI_ICR_IC1_Pos (18U) |
||
| 6964 | #define RI_ICR_IC1_Msk (0x1U << RI_ICR_IC1_Pos) /*!< 0x00040000 */ |
||
| 6965 | #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */ |
||
| 6966 | #define RI_ICR_IC2_Pos (19U) |
||
| 6967 | #define RI_ICR_IC2_Msk (0x1U << RI_ICR_IC2_Pos) /*!< 0x00080000 */ |
||
| 6968 | #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */ |
||
| 6969 | #define RI_ICR_IC3_Pos (20U) |
||
| 6970 | #define RI_ICR_IC3_Msk (0x1U << RI_ICR_IC3_Pos) /*!< 0x00100000 */ |
||
| 6971 | #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */ |
||
| 6972 | #define RI_ICR_IC4_Pos (21U) |
||
| 6973 | #define RI_ICR_IC4_Msk (0x1U << RI_ICR_IC4_Pos) /*!< 0x00200000 */ |
||
| 6974 | #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */ |
||
| 6975 | |||
| 6976 | /******************** Bit definition for RI_ASCR1 register ********************/ |
||
| 6977 | #define RI_ASCR1_CH_Pos (0U) |
||
| 6978 | #define RI_ASCR1_CH_Msk (0x7BFDFFFFU << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */ |
||
| 6979 | #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */ |
||
| 6980 | #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */ |
||
| 6981 | #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */ |
||
| 6982 | #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */ |
||
| 6983 | #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */ |
||
| 6984 | #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */ |
||
| 6985 | #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */ |
||
| 6986 | #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */ |
||
| 6987 | #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */ |
||
| 6988 | #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */ |
||
| 6989 | #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */ |
||
| 6990 | #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */ |
||
| 6991 | #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */ |
||
| 6992 | #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */ |
||
| 6993 | #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */ |
||
| 6994 | #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */ |
||
| 6995 | #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */ |
||
| 6996 | #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */ |
||
| 6997 | #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */ |
||
| 6998 | #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */ |
||
| 6999 | #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */ |
||
| 7000 | #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */ |
||
| 7001 | #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */ |
||
| 7002 | #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */ |
||
| 7003 | #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */ |
||
| 7004 | #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */ |
||
| 7005 | #define RI_ASCR1_VCOMP_Pos (26U) |
||
| 7006 | #define RI_ASCR1_VCOMP_Msk (0x1U << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */ |
||
| 7007 | #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */ |
||
| 7008 | #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */ |
||
| 7009 | #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */ |
||
| 7010 | #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */ |
||
| 7011 | #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */ |
||
| 7012 | #define RI_ASCR1_SCM_Pos (31U) |
||
| 7013 | #define RI_ASCR1_SCM_Msk (0x1U << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */ |
||
| 7014 | #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */ |
||
| 7015 | |||
| 7016 | /******************** Bit definition for RI_ASCR2 register ********************/ |
||
| 7017 | #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */ |
||
| 7018 | #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */ |
||
| 7019 | #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */ |
||
| 7020 | #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */ |
||
| 7021 | #define RI_ASCR2_GR6_Pos (4U) |
||
| 7022 | #define RI_ASCR2_GR6_Msk (0x1800003U << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */ |
||
| 7023 | #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */ |
||
| 7024 | #define RI_ASCR2_GR6_1 (0x0000001U << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */ |
||
| 7025 | #define RI_ASCR2_GR6_2 (0x0000002U << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */ |
||
| 7026 | #define RI_ASCR2_GR6_3 (0x0800000U << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */ |
||
| 7027 | #define RI_ASCR2_GR6_4 (0x1000000U << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */ |
||
| 7028 | #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */ |
||
| 7029 | #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */ |
||
| 7030 | #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */ |
||
| 7031 | #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */ |
||
| 7032 | #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */ |
||
| 7033 | #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */ |
||
| 7034 | #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */ |
||
| 7035 | #define RI_ASCR2_CH0b_Pos (16U) |
||
| 7036 | #define RI_ASCR2_CH0b_Msk (0x1U << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */ |
||
| 7037 | #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */ |
||
| 7038 | #define RI_ASCR2_CH1b_Pos (17U) |
||
| 7039 | #define RI_ASCR2_CH1b_Msk (0x1U << RI_ASCR2_CH1b_Pos) /*!< 0x00020000 */ |
||
| 7040 | #define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /*!< CH1b selection bit */ |
||
| 7041 | #define RI_ASCR2_CH2b_Pos (18U) |
||
| 7042 | #define RI_ASCR2_CH2b_Msk (0x1U << RI_ASCR2_CH2b_Pos) /*!< 0x00040000 */ |
||
| 7043 | #define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /*!< CH2b selection bit */ |
||
| 7044 | #define RI_ASCR2_CH3b_Pos (19U) |
||
| 7045 | #define RI_ASCR2_CH3b_Msk (0x1U << RI_ASCR2_CH3b_Pos) /*!< 0x00080000 */ |
||
| 7046 | #define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /*!< CH3b selection bit */ |
||
| 7047 | #define RI_ASCR2_CH6b_Pos (20U) |
||
| 7048 | #define RI_ASCR2_CH6b_Msk (0x1U << RI_ASCR2_CH6b_Pos) /*!< 0x00100000 */ |
||
| 7049 | #define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /*!< CH6b selection bit */ |
||
| 7050 | #define RI_ASCR2_CH7b_Pos (21U) |
||
| 7051 | #define RI_ASCR2_CH7b_Msk (0x1U << RI_ASCR2_CH7b_Pos) /*!< 0x00200000 */ |
||
| 7052 | #define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /*!< CH7b selection bit */ |
||
| 7053 | #define RI_ASCR2_CH8b_Pos (22U) |
||
| 7054 | #define RI_ASCR2_CH8b_Msk (0x1U << RI_ASCR2_CH8b_Pos) /*!< 0x00400000 */ |
||
| 7055 | #define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /*!< CH8b selection bit */ |
||
| 7056 | #define RI_ASCR2_CH9b_Pos (23U) |
||
| 7057 | #define RI_ASCR2_CH9b_Msk (0x1U << RI_ASCR2_CH9b_Pos) /*!< 0x00800000 */ |
||
| 7058 | #define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /*!< CH9b selection bit */ |
||
| 7059 | #define RI_ASCR2_CH10b_Pos (24U) |
||
| 7060 | #define RI_ASCR2_CH10b_Msk (0x1U << RI_ASCR2_CH10b_Pos) /*!< 0x01000000 */ |
||
| 7061 | #define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /*!< CH10b selection bit */ |
||
| 7062 | #define RI_ASCR2_CH11b_Pos (25U) |
||
| 7063 | #define RI_ASCR2_CH11b_Msk (0x1U << RI_ASCR2_CH11b_Pos) /*!< 0x02000000 */ |
||
| 7064 | #define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /*!< CH11b selection bit */ |
||
| 7065 | #define RI_ASCR2_CH12b_Pos (26U) |
||
| 7066 | #define RI_ASCR2_CH12b_Msk (0x1U << RI_ASCR2_CH12b_Pos) /*!< 0x04000000 */ |
||
| 7067 | #define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /*!< CH12b selection bit */ |
||
| 7068 | |||
| 7069 | /******************** Bit definition for RI_HYSCR1 register ********************/ |
||
| 7070 | #define RI_HYSCR1_PA_Pos (0U) |
||
| 7071 | #define RI_HYSCR1_PA_Msk (0xFFFFU << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */ |
||
| 7072 | #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */ |
||
| 7073 | #define RI_HYSCR1_PA_0 (0x0001U << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */ |
||
| 7074 | #define RI_HYSCR1_PA_1 (0x0002U << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */ |
||
| 7075 | #define RI_HYSCR1_PA_2 (0x0004U << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */ |
||
| 7076 | #define RI_HYSCR1_PA_3 (0x0008U << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */ |
||
| 7077 | #define RI_HYSCR1_PA_4 (0x0010U << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */ |
||
| 7078 | #define RI_HYSCR1_PA_5 (0x0020U << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */ |
||
| 7079 | #define RI_HYSCR1_PA_6 (0x0040U << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */ |
||
| 7080 | #define RI_HYSCR1_PA_7 (0x0080U << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */ |
||
| 7081 | #define RI_HYSCR1_PA_8 (0x0100U << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */ |
||
| 7082 | #define RI_HYSCR1_PA_9 (0x0200U << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */ |
||
| 7083 | #define RI_HYSCR1_PA_10 (0x0400U << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */ |
||
| 7084 | #define RI_HYSCR1_PA_11 (0x0800U << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */ |
||
| 7085 | #define RI_HYSCR1_PA_12 (0x1000U << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */ |
||
| 7086 | #define RI_HYSCR1_PA_13 (0x2000U << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */ |
||
| 7087 | #define RI_HYSCR1_PA_14 (0x4000U << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */ |
||
| 7088 | #define RI_HYSCR1_PA_15 (0x8000U << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */ |
||
| 7089 | |||
| 7090 | #define RI_HYSCR1_PB_Pos (16U) |
||
| 7091 | #define RI_HYSCR1_PB_Msk (0xFFFFU << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */ |
||
| 7092 | #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */ |
||
| 7093 | #define RI_HYSCR1_PB_0 (0x0001U << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */ |
||
| 7094 | #define RI_HYSCR1_PB_1 (0x0002U << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */ |
||
| 7095 | #define RI_HYSCR1_PB_2 (0x0004U << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */ |
||
| 7096 | #define RI_HYSCR1_PB_3 (0x0008U << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */ |
||
| 7097 | #define RI_HYSCR1_PB_4 (0x0010U << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */ |
||
| 7098 | #define RI_HYSCR1_PB_5 (0x0020U << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */ |
||
| 7099 | #define RI_HYSCR1_PB_6 (0x0040U << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */ |
||
| 7100 | #define RI_HYSCR1_PB_7 (0x0080U << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */ |
||
| 7101 | #define RI_HYSCR1_PB_8 (0x0100U << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */ |
||
| 7102 | #define RI_HYSCR1_PB_9 (0x0200U << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */ |
||
| 7103 | #define RI_HYSCR1_PB_10 (0x0400U << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */ |
||
| 7104 | #define RI_HYSCR1_PB_11 (0x0800U << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */ |
||
| 7105 | #define RI_HYSCR1_PB_12 (0x1000U << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */ |
||
| 7106 | #define RI_HYSCR1_PB_13 (0x2000U << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */ |
||
| 7107 | #define RI_HYSCR1_PB_14 (0x4000U << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */ |
||
| 7108 | #define RI_HYSCR1_PB_15 (0x8000U << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */ |
||
| 7109 | |||
| 7110 | /******************** Bit definition for RI_HYSCR2 register ********************/ |
||
| 7111 | #define RI_HYSCR2_PC_Pos (0U) |
||
| 7112 | #define RI_HYSCR2_PC_Msk (0xFFFFU << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */ |
||
| 7113 | #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */ |
||
| 7114 | #define RI_HYSCR2_PC_0 (0x0001U << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */ |
||
| 7115 | #define RI_HYSCR2_PC_1 (0x0002U << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */ |
||
| 7116 | #define RI_HYSCR2_PC_2 (0x0004U << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */ |
||
| 7117 | #define RI_HYSCR2_PC_3 (0x0008U << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */ |
||
| 7118 | #define RI_HYSCR2_PC_4 (0x0010U << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */ |
||
| 7119 | #define RI_HYSCR2_PC_5 (0x0020U << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */ |
||
| 7120 | #define RI_HYSCR2_PC_6 (0x0040U << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */ |
||
| 7121 | #define RI_HYSCR2_PC_7 (0x0080U << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */ |
||
| 7122 | #define RI_HYSCR2_PC_8 (0x0100U << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */ |
||
| 7123 | #define RI_HYSCR2_PC_9 (0x0200U << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */ |
||
| 7124 | #define RI_HYSCR2_PC_10 (0x0400U << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */ |
||
| 7125 | #define RI_HYSCR2_PC_11 (0x0800U << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */ |
||
| 7126 | #define RI_HYSCR2_PC_12 (0x1000U << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */ |
||
| 7127 | #define RI_HYSCR2_PC_13 (0x2000U << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */ |
||
| 7128 | #define RI_HYSCR2_PC_14 (0x4000U << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */ |
||
| 7129 | #define RI_HYSCR2_PC_15 (0x8000U << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */ |
||
| 7130 | |||
| 7131 | #define RI_HYSCR2_PD_Pos (16U) |
||
| 7132 | #define RI_HYSCR2_PD_Msk (0xFFFFU << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */ |
||
| 7133 | #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */ |
||
| 7134 | #define RI_HYSCR2_PD_0 (0x0001U << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */ |
||
| 7135 | #define RI_HYSCR2_PD_1 (0x0002U << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */ |
||
| 7136 | #define RI_HYSCR2_PD_2 (0x0004U << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */ |
||
| 7137 | #define RI_HYSCR2_PD_3 (0x0008U << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */ |
||
| 7138 | #define RI_HYSCR2_PD_4 (0x0010U << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */ |
||
| 7139 | #define RI_HYSCR2_PD_5 (0x0020U << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */ |
||
| 7140 | #define RI_HYSCR2_PD_6 (0x0040U << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */ |
||
| 7141 | #define RI_HYSCR2_PD_7 (0x0080U << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */ |
||
| 7142 | #define RI_HYSCR2_PD_8 (0x0100U << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */ |
||
| 7143 | #define RI_HYSCR2_PD_9 (0x0200U << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */ |
||
| 7144 | #define RI_HYSCR2_PD_10 (0x0400U << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */ |
||
| 7145 | #define RI_HYSCR2_PD_11 (0x0800U << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */ |
||
| 7146 | #define RI_HYSCR2_PD_12 (0x1000U << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */ |
||
| 7147 | #define RI_HYSCR2_PD_13 (0x2000U << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */ |
||
| 7148 | #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ |
||
| 7149 | #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ |
||
| 7150 | |||
| 7151 | /******************** Bit definition for RI_HYSCR3 register ********************/ |
||
| 7152 | #define RI_HYSCR3_PE_Pos (0U) |
||
| 7153 | #define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ |
||
| 7154 | #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ |
||
| 7155 | #define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ |
||
| 7156 | #define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ |
||
| 7157 | #define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ |
||
| 7158 | #define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ |
||
| 7159 | #define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ |
||
| 7160 | #define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ |
||
| 7161 | #define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ |
||
| 7162 | #define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ |
||
| 7163 | #define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ |
||
| 7164 | #define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ |
||
| 7165 | #define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ |
||
| 7166 | #define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ |
||
| 7167 | #define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ |
||
| 7168 | #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ |
||
| 7169 | #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ |
||
| 7170 | #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ |
||
| 7171 | #define RI_HYSCR3_PF_Pos (16U) |
||
| 7172 | #define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ |
||
| 7173 | #define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ |
||
| 7174 | #define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ |
||
| 7175 | #define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ |
||
| 7176 | #define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ |
||
| 7177 | #define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ |
||
| 7178 | #define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ |
||
| 7179 | #define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ |
||
| 7180 | #define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ |
||
| 7181 | #define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ |
||
| 7182 | #define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ |
||
| 7183 | #define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ |
||
| 7184 | #define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ |
||
| 7185 | #define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ |
||
| 7186 | #define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ |
||
| 7187 | #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ |
||
| 7188 | #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ |
||
| 7189 | #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ |
||
| 7190 | |||
| 7191 | /******************** Bit definition for RI_HYSCR4 register ********************/ |
||
| 7192 | #define RI_HYSCR4_PG_Pos (0U) |
||
| 7193 | #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ |
||
| 7194 | #define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ |
||
| 7195 | #define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ |
||
| 7196 | #define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ |
||
| 7197 | #define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ |
||
| 7198 | #define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ |
||
| 7199 | #define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ |
||
| 7200 | #define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ |
||
| 7201 | #define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ |
||
| 7202 | #define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ |
||
| 7203 | #define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ |
||
| 7204 | #define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ |
||
| 7205 | #define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ |
||
| 7206 | #define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ |
||
| 7207 | #define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ |
||
| 7208 | #define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ |
||
| 7209 | #define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ |
||
| 7210 | #define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ |
||
| 7211 | |||
| 7212 | /******************** Bit definition for RI_ASMR1 register ********************/ |
||
| 7213 | #define RI_ASMR1_PA_Pos (0U) |
||
| 7214 | #define RI_ASMR1_PA_Msk (0xFFFFU << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */ |
||
| 7215 | #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/ |
||
| 7216 | #define RI_ASMR1_PA_0 (0x0001U << RI_ASMR1_PA_Pos) /*!< 0x00000001 */ |
||
| 7217 | #define RI_ASMR1_PA_1 (0x0002U << RI_ASMR1_PA_Pos) /*!< 0x00000002 */ |
||
| 7218 | #define RI_ASMR1_PA_2 (0x0004U << RI_ASMR1_PA_Pos) /*!< 0x00000004 */ |
||
| 7219 | #define RI_ASMR1_PA_3 (0x0008U << RI_ASMR1_PA_Pos) /*!< 0x00000008 */ |
||
| 7220 | #define RI_ASMR1_PA_4 (0x0010U << RI_ASMR1_PA_Pos) /*!< 0x00000010 */ |
||
| 7221 | #define RI_ASMR1_PA_5 (0x0020U << RI_ASMR1_PA_Pos) /*!< 0x00000020 */ |
||
| 7222 | #define RI_ASMR1_PA_6 (0x0040U << RI_ASMR1_PA_Pos) /*!< 0x00000040 */ |
||
| 7223 | #define RI_ASMR1_PA_7 (0x0080U << RI_ASMR1_PA_Pos) /*!< 0x00000080 */ |
||
| 7224 | #define RI_ASMR1_PA_8 (0x0100U << RI_ASMR1_PA_Pos) /*!< 0x00000100 */ |
||
| 7225 | #define RI_ASMR1_PA_9 (0x0200U << RI_ASMR1_PA_Pos) /*!< 0x00000200 */ |
||
| 7226 | #define RI_ASMR1_PA_10 (0x0400U << RI_ASMR1_PA_Pos) /*!< 0x00000400 */ |
||
| 7227 | #define RI_ASMR1_PA_11 (0x0800U << RI_ASMR1_PA_Pos) /*!< 0x00000800 */ |
||
| 7228 | #define RI_ASMR1_PA_12 (0x1000U << RI_ASMR1_PA_Pos) /*!< 0x00001000 */ |
||
| 7229 | #define RI_ASMR1_PA_13 (0x2000U << RI_ASMR1_PA_Pos) /*!< 0x00002000 */ |
||
| 7230 | #define RI_ASMR1_PA_14 (0x4000U << RI_ASMR1_PA_Pos) /*!< 0x00004000 */ |
||
| 7231 | #define RI_ASMR1_PA_15 (0x8000U << RI_ASMR1_PA_Pos) /*!< 0x00008000 */ |
||
| 7232 | |||
| 7233 | /******************** Bit definition for RI_CMR1 register ********************/ |
||
| 7234 | #define RI_CMR1_PA_Pos (0U) |
||
| 7235 | #define RI_CMR1_PA_Msk (0xFFFFU << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */ |
||
| 7236 | #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/ |
||
| 7237 | #define RI_CMR1_PA_0 (0x0001U << RI_CMR1_PA_Pos) /*!< 0x00000001 */ |
||
| 7238 | #define RI_CMR1_PA_1 (0x0002U << RI_CMR1_PA_Pos) /*!< 0x00000002 */ |
||
| 7239 | #define RI_CMR1_PA_2 (0x0004U << RI_CMR1_PA_Pos) /*!< 0x00000004 */ |
||
| 7240 | #define RI_CMR1_PA_3 (0x0008U << RI_CMR1_PA_Pos) /*!< 0x00000008 */ |
||
| 7241 | #define RI_CMR1_PA_4 (0x0010U << RI_CMR1_PA_Pos) /*!< 0x00000010 */ |
||
| 7242 | #define RI_CMR1_PA_5 (0x0020U << RI_CMR1_PA_Pos) /*!< 0x00000020 */ |
||
| 7243 | #define RI_CMR1_PA_6 (0x0040U << RI_CMR1_PA_Pos) /*!< 0x00000040 */ |
||
| 7244 | #define RI_CMR1_PA_7 (0x0080U << RI_CMR1_PA_Pos) /*!< 0x00000080 */ |
||
| 7245 | #define RI_CMR1_PA_8 (0x0100U << RI_CMR1_PA_Pos) /*!< 0x00000100 */ |
||
| 7246 | #define RI_CMR1_PA_9 (0x0200U << RI_CMR1_PA_Pos) /*!< 0x00000200 */ |
||
| 7247 | #define RI_CMR1_PA_10 (0x0400U << RI_CMR1_PA_Pos) /*!< 0x00000400 */ |
||
| 7248 | #define RI_CMR1_PA_11 (0x0800U << RI_CMR1_PA_Pos) /*!< 0x00000800 */ |
||
| 7249 | #define RI_CMR1_PA_12 (0x1000U << RI_CMR1_PA_Pos) /*!< 0x00001000 */ |
||
| 7250 | #define RI_CMR1_PA_13 (0x2000U << RI_CMR1_PA_Pos) /*!< 0x00002000 */ |
||
| 7251 | #define RI_CMR1_PA_14 (0x4000U << RI_CMR1_PA_Pos) /*!< 0x00004000 */ |
||
| 7252 | #define RI_CMR1_PA_15 (0x8000U << RI_CMR1_PA_Pos) /*!< 0x00008000 */ |
||
| 7253 | |||
| 7254 | /******************** Bit definition for RI_CICR1 register ********************/ |
||
| 7255 | #define RI_CICR1_PA_Pos (0U) |
||
| 7256 | #define RI_CICR1_PA_Msk (0xFFFFU << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */ |
||
| 7257 | #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/ |
||
| 7258 | #define RI_CICR1_PA_0 (0x0001U << RI_CICR1_PA_Pos) /*!< 0x00000001 */ |
||
| 7259 | #define RI_CICR1_PA_1 (0x0002U << RI_CICR1_PA_Pos) /*!< 0x00000002 */ |
||
| 7260 | #define RI_CICR1_PA_2 (0x0004U << RI_CICR1_PA_Pos) /*!< 0x00000004 */ |
||
| 7261 | #define RI_CICR1_PA_3 (0x0008U << RI_CICR1_PA_Pos) /*!< 0x00000008 */ |
||
| 7262 | #define RI_CICR1_PA_4 (0x0010U << RI_CICR1_PA_Pos) /*!< 0x00000010 */ |
||
| 7263 | #define RI_CICR1_PA_5 (0x0020U << RI_CICR1_PA_Pos) /*!< 0x00000020 */ |
||
| 7264 | #define RI_CICR1_PA_6 (0x0040U << RI_CICR1_PA_Pos) /*!< 0x00000040 */ |
||
| 7265 | #define RI_CICR1_PA_7 (0x0080U << RI_CICR1_PA_Pos) /*!< 0x00000080 */ |
||
| 7266 | #define RI_CICR1_PA_8 (0x0100U << RI_CICR1_PA_Pos) /*!< 0x00000100 */ |
||
| 7267 | #define RI_CICR1_PA_9 (0x0200U << RI_CICR1_PA_Pos) /*!< 0x00000200 */ |
||
| 7268 | #define RI_CICR1_PA_10 (0x0400U << RI_CICR1_PA_Pos) /*!< 0x00000400 */ |
||
| 7269 | #define RI_CICR1_PA_11 (0x0800U << RI_CICR1_PA_Pos) /*!< 0x00000800 */ |
||
| 7270 | #define RI_CICR1_PA_12 (0x1000U << RI_CICR1_PA_Pos) /*!< 0x00001000 */ |
||
| 7271 | #define RI_CICR1_PA_13 (0x2000U << RI_CICR1_PA_Pos) /*!< 0x00002000 */ |
||
| 7272 | #define RI_CICR1_PA_14 (0x4000U << RI_CICR1_PA_Pos) /*!< 0x00004000 */ |
||
| 7273 | #define RI_CICR1_PA_15 (0x8000U << RI_CICR1_PA_Pos) /*!< 0x00008000 */ |
||
| 7274 | |||
| 7275 | /******************** Bit definition for RI_ASMR2 register ********************/ |
||
| 7276 | #define RI_ASMR2_PB_Pos (0U) |
||
| 7277 | #define RI_ASMR2_PB_Msk (0xFFFFU << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */ |
||
| 7278 | #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */ |
||
| 7279 | #define RI_ASMR2_PB_0 (0x0001U << RI_ASMR2_PB_Pos) /*!< 0x00000001 */ |
||
| 7280 | #define RI_ASMR2_PB_1 (0x0002U << RI_ASMR2_PB_Pos) /*!< 0x00000002 */ |
||
| 7281 | #define RI_ASMR2_PB_2 (0x0004U << RI_ASMR2_PB_Pos) /*!< 0x00000004 */ |
||
| 7282 | #define RI_ASMR2_PB_3 (0x0008U << RI_ASMR2_PB_Pos) /*!< 0x00000008 */ |
||
| 7283 | #define RI_ASMR2_PB_4 (0x0010U << RI_ASMR2_PB_Pos) /*!< 0x00000010 */ |
||
| 7284 | #define RI_ASMR2_PB_5 (0x0020U << RI_ASMR2_PB_Pos) /*!< 0x00000020 */ |
||
| 7285 | #define RI_ASMR2_PB_6 (0x0040U << RI_ASMR2_PB_Pos) /*!< 0x00000040 */ |
||
| 7286 | #define RI_ASMR2_PB_7 (0x0080U << RI_ASMR2_PB_Pos) /*!< 0x00000080 */ |
||
| 7287 | #define RI_ASMR2_PB_8 (0x0100U << RI_ASMR2_PB_Pos) /*!< 0x00000100 */ |
||
| 7288 | #define RI_ASMR2_PB_9 (0x0200U << RI_ASMR2_PB_Pos) /*!< 0x00000200 */ |
||
| 7289 | #define RI_ASMR2_PB_10 (0x0400U << RI_ASMR2_PB_Pos) /*!< 0x00000400 */ |
||
| 7290 | #define RI_ASMR2_PB_11 (0x0800U << RI_ASMR2_PB_Pos) /*!< 0x00000800 */ |
||
| 7291 | #define RI_ASMR2_PB_12 (0x1000U << RI_ASMR2_PB_Pos) /*!< 0x00001000 */ |
||
| 7292 | #define RI_ASMR2_PB_13 (0x2000U << RI_ASMR2_PB_Pos) /*!< 0x00002000 */ |
||
| 7293 | #define RI_ASMR2_PB_14 (0x4000U << RI_ASMR2_PB_Pos) /*!< 0x00004000 */ |
||
| 7294 | #define RI_ASMR2_PB_15 (0x8000U << RI_ASMR2_PB_Pos) /*!< 0x00008000 */ |
||
| 7295 | |||
| 7296 | /******************** Bit definition for RI_CMR2 register ********************/ |
||
| 7297 | #define RI_CMR2_PB_Pos (0U) |
||
| 7298 | #define RI_CMR2_PB_Msk (0xFFFFU << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */ |
||
| 7299 | #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */ |
||
| 7300 | #define RI_CMR2_PB_0 (0x0001U << RI_CMR2_PB_Pos) /*!< 0x00000001 */ |
||
| 7301 | #define RI_CMR2_PB_1 (0x0002U << RI_CMR2_PB_Pos) /*!< 0x00000002 */ |
||
| 7302 | #define RI_CMR2_PB_2 (0x0004U << RI_CMR2_PB_Pos) /*!< 0x00000004 */ |
||
| 7303 | #define RI_CMR2_PB_3 (0x0008U << RI_CMR2_PB_Pos) /*!< 0x00000008 */ |
||
| 7304 | #define RI_CMR2_PB_4 (0x0010U << RI_CMR2_PB_Pos) /*!< 0x00000010 */ |
||
| 7305 | #define RI_CMR2_PB_5 (0x0020U << RI_CMR2_PB_Pos) /*!< 0x00000020 */ |
||
| 7306 | #define RI_CMR2_PB_6 (0x0040U << RI_CMR2_PB_Pos) /*!< 0x00000040 */ |
||
| 7307 | #define RI_CMR2_PB_7 (0x0080U << RI_CMR2_PB_Pos) /*!< 0x00000080 */ |
||
| 7308 | #define RI_CMR2_PB_8 (0x0100U << RI_CMR2_PB_Pos) /*!< 0x00000100 */ |
||
| 7309 | #define RI_CMR2_PB_9 (0x0200U << RI_CMR2_PB_Pos) /*!< 0x00000200 */ |
||
| 7310 | #define RI_CMR2_PB_10 (0x0400U << RI_CMR2_PB_Pos) /*!< 0x00000400 */ |
||
| 7311 | #define RI_CMR2_PB_11 (0x0800U << RI_CMR2_PB_Pos) /*!< 0x00000800 */ |
||
| 7312 | #define RI_CMR2_PB_12 (0x1000U << RI_CMR2_PB_Pos) /*!< 0x00001000 */ |
||
| 7313 | #define RI_CMR2_PB_13 (0x2000U << RI_CMR2_PB_Pos) /*!< 0x00002000 */ |
||
| 7314 | #define RI_CMR2_PB_14 (0x4000U << RI_CMR2_PB_Pos) /*!< 0x00004000 */ |
||
| 7315 | #define RI_CMR2_PB_15 (0x8000U << RI_CMR2_PB_Pos) /*!< 0x00008000 */ |
||
| 7316 | |||
| 7317 | /******************** Bit definition for RI_CICR2 register ********************/ |
||
| 7318 | #define RI_CICR2_PB_Pos (0U) |
||
| 7319 | #define RI_CICR2_PB_Msk (0xFFFFU << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */ |
||
| 7320 | #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */ |
||
| 7321 | #define RI_CICR2_PB_0 (0x0001U << RI_CICR2_PB_Pos) /*!< 0x00000001 */ |
||
| 7322 | #define RI_CICR2_PB_1 (0x0002U << RI_CICR2_PB_Pos) /*!< 0x00000002 */ |
||
| 7323 | #define RI_CICR2_PB_2 (0x0004U << RI_CICR2_PB_Pos) /*!< 0x00000004 */ |
||
| 7324 | #define RI_CICR2_PB_3 (0x0008U << RI_CICR2_PB_Pos) /*!< 0x00000008 */ |
||
| 7325 | #define RI_CICR2_PB_4 (0x0010U << RI_CICR2_PB_Pos) /*!< 0x00000010 */ |
||
| 7326 | #define RI_CICR2_PB_5 (0x0020U << RI_CICR2_PB_Pos) /*!< 0x00000020 */ |
||
| 7327 | #define RI_CICR2_PB_6 (0x0040U << RI_CICR2_PB_Pos) /*!< 0x00000040 */ |
||
| 7328 | #define RI_CICR2_PB_7 (0x0080U << RI_CICR2_PB_Pos) /*!< 0x00000080 */ |
||
| 7329 | #define RI_CICR2_PB_8 (0x0100U << RI_CICR2_PB_Pos) /*!< 0x00000100 */ |
||
| 7330 | #define RI_CICR2_PB_9 (0x0200U << RI_CICR2_PB_Pos) /*!< 0x00000200 */ |
||
| 7331 | #define RI_CICR2_PB_10 (0x0400U << RI_CICR2_PB_Pos) /*!< 0x00000400 */ |
||
| 7332 | #define RI_CICR2_PB_11 (0x0800U << RI_CICR2_PB_Pos) /*!< 0x00000800 */ |
||
| 7333 | #define RI_CICR2_PB_12 (0x1000U << RI_CICR2_PB_Pos) /*!< 0x00001000 */ |
||
| 7334 | #define RI_CICR2_PB_13 (0x2000U << RI_CICR2_PB_Pos) /*!< 0x00002000 */ |
||
| 7335 | #define RI_CICR2_PB_14 (0x4000U << RI_CICR2_PB_Pos) /*!< 0x00004000 */ |
||
| 7336 | #define RI_CICR2_PB_15 (0x8000U << RI_CICR2_PB_Pos) /*!< 0x00008000 */ |
||
| 7337 | |||
| 7338 | /******************** Bit definition for RI_ASMR3 register ********************/ |
||
| 7339 | #define RI_ASMR3_PC_Pos (0U) |
||
| 7340 | #define RI_ASMR3_PC_Msk (0xFFFFU << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */ |
||
| 7341 | #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */ |
||
| 7342 | #define RI_ASMR3_PC_0 (0x0001U << RI_ASMR3_PC_Pos) /*!< 0x00000001 */ |
||
| 7343 | #define RI_ASMR3_PC_1 (0x0002U << RI_ASMR3_PC_Pos) /*!< 0x00000002 */ |
||
| 7344 | #define RI_ASMR3_PC_2 (0x0004U << RI_ASMR3_PC_Pos) /*!< 0x00000004 */ |
||
| 7345 | #define RI_ASMR3_PC_3 (0x0008U << RI_ASMR3_PC_Pos) /*!< 0x00000008 */ |
||
| 7346 | #define RI_ASMR3_PC_4 (0x0010U << RI_ASMR3_PC_Pos) /*!< 0x00000010 */ |
||
| 7347 | #define RI_ASMR3_PC_5 (0x0020U << RI_ASMR3_PC_Pos) /*!< 0x00000020 */ |
||
| 7348 | #define RI_ASMR3_PC_6 (0x0040U << RI_ASMR3_PC_Pos) /*!< 0x00000040 */ |
||
| 7349 | #define RI_ASMR3_PC_7 (0x0080U << RI_ASMR3_PC_Pos) /*!< 0x00000080 */ |
||
| 7350 | #define RI_ASMR3_PC_8 (0x0100U << RI_ASMR3_PC_Pos) /*!< 0x00000100 */ |
||
| 7351 | #define RI_ASMR3_PC_9 (0x0200U << RI_ASMR3_PC_Pos) /*!< 0x00000200 */ |
||
| 7352 | #define RI_ASMR3_PC_10 (0x0400U << RI_ASMR3_PC_Pos) /*!< 0x00000400 */ |
||
| 7353 | #define RI_ASMR3_PC_11 (0x0800U << RI_ASMR3_PC_Pos) /*!< 0x00000800 */ |
||
| 7354 | #define RI_ASMR3_PC_12 (0x1000U << RI_ASMR3_PC_Pos) /*!< 0x00001000 */ |
||
| 7355 | #define RI_ASMR3_PC_13 (0x2000U << RI_ASMR3_PC_Pos) /*!< 0x00002000 */ |
||
| 7356 | #define RI_ASMR3_PC_14 (0x4000U << RI_ASMR3_PC_Pos) /*!< 0x00004000 */ |
||
| 7357 | #define RI_ASMR3_PC_15 (0x8000U << RI_ASMR3_PC_Pos) /*!< 0x00008000 */ |
||
| 7358 | |||
| 7359 | /******************** Bit definition for RI_CMR3 register ********************/ |
||
| 7360 | #define RI_CMR3_PC_Pos (0U) |
||
| 7361 | #define RI_CMR3_PC_Msk (0xFFFFU << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */ |
||
| 7362 | #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */ |
||
| 7363 | #define RI_CMR3_PC_0 (0x0001U << RI_CMR3_PC_Pos) /*!< 0x00000001 */ |
||
| 7364 | #define RI_CMR3_PC_1 (0x0002U << RI_CMR3_PC_Pos) /*!< 0x00000002 */ |
||
| 7365 | #define RI_CMR3_PC_2 (0x0004U << RI_CMR3_PC_Pos) /*!< 0x00000004 */ |
||
| 7366 | #define RI_CMR3_PC_3 (0x0008U << RI_CMR3_PC_Pos) /*!< 0x00000008 */ |
||
| 7367 | #define RI_CMR3_PC_4 (0x0010U << RI_CMR3_PC_Pos) /*!< 0x00000010 */ |
||
| 7368 | #define RI_CMR3_PC_5 (0x0020U << RI_CMR3_PC_Pos) /*!< 0x00000020 */ |
||
| 7369 | #define RI_CMR3_PC_6 (0x0040U << RI_CMR3_PC_Pos) /*!< 0x00000040 */ |
||
| 7370 | #define RI_CMR3_PC_7 (0x0080U << RI_CMR3_PC_Pos) /*!< 0x00000080 */ |
||
| 7371 | #define RI_CMR3_PC_8 (0x0100U << RI_CMR3_PC_Pos) /*!< 0x00000100 */ |
||
| 7372 | #define RI_CMR3_PC_9 (0x0200U << RI_CMR3_PC_Pos) /*!< 0x00000200 */ |
||
| 7373 | #define RI_CMR3_PC_10 (0x0400U << RI_CMR3_PC_Pos) /*!< 0x00000400 */ |
||
| 7374 | #define RI_CMR3_PC_11 (0x0800U << RI_CMR3_PC_Pos) /*!< 0x00000800 */ |
||
| 7375 | #define RI_CMR3_PC_12 (0x1000U << RI_CMR3_PC_Pos) /*!< 0x00001000 */ |
||
| 7376 | #define RI_CMR3_PC_13 (0x2000U << RI_CMR3_PC_Pos) /*!< 0x00002000 */ |
||
| 7377 | #define RI_CMR3_PC_14 (0x4000U << RI_CMR3_PC_Pos) /*!< 0x00004000 */ |
||
| 7378 | #define RI_CMR3_PC_15 (0x8000U << RI_CMR3_PC_Pos) /*!< 0x00008000 */ |
||
| 7379 | |||
| 7380 | /******************** Bit definition for RI_CICR3 register ********************/ |
||
| 7381 | #define RI_CICR3_PC_Pos (0U) |
||
| 7382 | #define RI_CICR3_PC_Msk (0xFFFFU << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */ |
||
| 7383 | #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */ |
||
| 7384 | #define RI_CICR3_PC_0 (0x0001U << RI_CICR3_PC_Pos) /*!< 0x00000001 */ |
||
| 7385 | #define RI_CICR3_PC_1 (0x0002U << RI_CICR3_PC_Pos) /*!< 0x00000002 */ |
||
| 7386 | #define RI_CICR3_PC_2 (0x0004U << RI_CICR3_PC_Pos) /*!< 0x00000004 */ |
||
| 7387 | #define RI_CICR3_PC_3 (0x0008U << RI_CICR3_PC_Pos) /*!< 0x00000008 */ |
||
| 7388 | #define RI_CICR3_PC_4 (0x0010U << RI_CICR3_PC_Pos) /*!< 0x00000010 */ |
||
| 7389 | #define RI_CICR3_PC_5 (0x0020U << RI_CICR3_PC_Pos) /*!< 0x00000020 */ |
||
| 7390 | #define RI_CICR3_PC_6 (0x0040U << RI_CICR3_PC_Pos) /*!< 0x00000040 */ |
||
| 7391 | #define RI_CICR3_PC_7 (0x0080U << RI_CICR3_PC_Pos) /*!< 0x00000080 */ |
||
| 7392 | #define RI_CICR3_PC_8 (0x0100U << RI_CICR3_PC_Pos) /*!< 0x00000100 */ |
||
| 7393 | #define RI_CICR3_PC_9 (0x0200U << RI_CICR3_PC_Pos) /*!< 0x00000200 */ |
||
| 7394 | #define RI_CICR3_PC_10 (0x0400U << RI_CICR3_PC_Pos) /*!< 0x00000400 */ |
||
| 7395 | #define RI_CICR3_PC_11 (0x0800U << RI_CICR3_PC_Pos) /*!< 0x00000800 */ |
||
| 7396 | #define RI_CICR3_PC_12 (0x1000U << RI_CICR3_PC_Pos) /*!< 0x00001000 */ |
||
| 7397 | #define RI_CICR3_PC_13 (0x2000U << RI_CICR3_PC_Pos) /*!< 0x00002000 */ |
||
| 7398 | #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */ |
||
| 7399 | #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */ |
||
| 7400 | |||
| 7401 | /******************** Bit definition for RI_ASMR4 register ********************/ |
||
| 7402 | #define RI_ASMR4_PF_Pos (0U) |
||
| 7403 | #define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ |
||
| 7404 | #define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ |
||
| 7405 | #define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ |
||
| 7406 | #define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ |
||
| 7407 | #define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ |
||
| 7408 | #define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ |
||
| 7409 | #define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ |
||
| 7410 | #define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ |
||
| 7411 | #define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ |
||
| 7412 | #define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ |
||
| 7413 | #define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ |
||
| 7414 | #define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ |
||
| 7415 | #define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ |
||
| 7416 | #define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ |
||
| 7417 | #define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ |
||
| 7418 | #define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ |
||
| 7419 | #define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ |
||
| 7420 | #define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ |
||
| 7421 | |||
| 7422 | /******************** Bit definition for RI_CMR4 register ********************/ |
||
| 7423 | #define RI_CMR4_PF_Pos (0U) |
||
| 7424 | #define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ |
||
| 7425 | #define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ |
||
| 7426 | #define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */ |
||
| 7427 | #define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */ |
||
| 7428 | #define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */ |
||
| 7429 | #define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */ |
||
| 7430 | #define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */ |
||
| 7431 | #define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */ |
||
| 7432 | #define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */ |
||
| 7433 | #define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */ |
||
| 7434 | #define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */ |
||
| 7435 | #define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */ |
||
| 7436 | #define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */ |
||
| 7437 | #define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */ |
||
| 7438 | #define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */ |
||
| 7439 | #define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */ |
||
| 7440 | #define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */ |
||
| 7441 | #define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */ |
||
| 7442 | |||
| 7443 | /******************** Bit definition for RI_CICR4 register ********************/ |
||
| 7444 | #define RI_CICR4_PF_Pos (0U) |
||
| 7445 | #define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ |
||
| 7446 | #define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ |
||
| 7447 | #define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */ |
||
| 7448 | #define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */ |
||
| 7449 | #define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */ |
||
| 7450 | #define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */ |
||
| 7451 | #define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */ |
||
| 7452 | #define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */ |
||
| 7453 | #define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */ |
||
| 7454 | #define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */ |
||
| 7455 | #define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */ |
||
| 7456 | #define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */ |
||
| 7457 | #define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */ |
||
| 7458 | #define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */ |
||
| 7459 | #define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */ |
||
| 7460 | #define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */ |
||
| 7461 | #define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */ |
||
| 7462 | #define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */ |
||
| 7463 | |||
| 7464 | /******************** Bit definition for RI_ASMR5 register ********************/ |
||
| 7465 | #define RI_ASMR5_PG_Pos (0U) |
||
| 7466 | #define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ |
||
| 7467 | #define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ |
||
| 7468 | #define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ |
||
| 7469 | #define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ |
||
| 7470 | #define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ |
||
| 7471 | #define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ |
||
| 7472 | #define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ |
||
| 7473 | #define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ |
||
| 7474 | #define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ |
||
| 7475 | #define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ |
||
| 7476 | #define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ |
||
| 7477 | #define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ |
||
| 7478 | #define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ |
||
| 7479 | #define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ |
||
| 7480 | #define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ |
||
| 7481 | #define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ |
||
| 7482 | #define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ |
||
| 7483 | #define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ |
||
| 7484 | |||
| 7485 | /******************** Bit definition for RI_CMR5 register ********************/ |
||
| 7486 | #define RI_CMR5_PG_Pos (0U) |
||
| 7487 | #define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ |
||
| 7488 | #define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ |
||
| 7489 | #define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */ |
||
| 7490 | #define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */ |
||
| 7491 | #define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */ |
||
| 7492 | #define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */ |
||
| 7493 | #define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */ |
||
| 7494 | #define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */ |
||
| 7495 | #define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */ |
||
| 7496 | #define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */ |
||
| 7497 | #define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */ |
||
| 7498 | #define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */ |
||
| 7499 | #define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */ |
||
| 7500 | #define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */ |
||
| 7501 | #define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */ |
||
| 7502 | #define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */ |
||
| 7503 | #define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */ |
||
| 7504 | #define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */ |
||
| 7505 | |||
| 7506 | /******************** Bit definition for RI_CICR5 register ********************/ |
||
| 7507 | #define RI_CICR5_PG_Pos (0U) |
||
| 7508 | #define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ |
||
| 7509 | #define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ |
||
| 7510 | #define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */ |
||
| 7511 | #define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */ |
||
| 7512 | #define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */ |
||
| 7513 | #define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */ |
||
| 7514 | #define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */ |
||
| 7515 | #define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */ |
||
| 7516 | #define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */ |
||
| 7517 | #define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */ |
||
| 7518 | #define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */ |
||
| 7519 | #define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */ |
||
| 7520 | #define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */ |
||
| 7521 | #define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */ |
||
| 7522 | #define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */ |
||
| 7523 | #define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */ |
||
| 7524 | #define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */ |
||
| 7525 | #define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */ |
||
| 7526 | |||
| 7527 | /******************************************************************************/ |
||
| 7528 | /* */ |
||
| 7529 | /* Timers (TIM) */ |
||
| 7530 | /* */ |
||
| 7531 | /******************************************************************************/ |
||
| 7532 | |||
| 7533 | /******************* Bit definition for TIM_CR1 register ********************/ |
||
| 7534 | #define TIM_CR1_CEN_Pos (0U) |
||
| 7535 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
||
| 7536 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
||
| 7537 | #define TIM_CR1_UDIS_Pos (1U) |
||
| 7538 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
||
| 7539 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
||
| 7540 | #define TIM_CR1_URS_Pos (2U) |
||
| 7541 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
||
| 7542 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
||
| 7543 | #define TIM_CR1_OPM_Pos (3U) |
||
| 7544 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
||
| 7545 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
||
| 7546 | #define TIM_CR1_DIR_Pos (4U) |
||
| 7547 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
||
| 7548 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
||
| 7549 | |||
| 7550 | #define TIM_CR1_CMS_Pos (5U) |
||
| 7551 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
||
| 7552 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
||
| 7553 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
||
| 7554 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
||
| 7555 | |||
| 7556 | #define TIM_CR1_ARPE_Pos (7U) |
||
| 7557 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
||
| 7558 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
||
| 7559 | |||
| 7560 | #define TIM_CR1_CKD_Pos (8U) |
||
| 7561 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
||
| 7562 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
||
| 7563 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
||
| 7564 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
||
| 7565 | |||
| 7566 | /******************* Bit definition for TIM_CR2 register ********************/ |
||
| 7567 | #define TIM_CR2_CCDS_Pos (3U) |
||
| 7568 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
||
| 7569 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
||
| 7570 | |||
| 7571 | #define TIM_CR2_MMS_Pos (4U) |
||
| 7572 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
||
| 7573 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
||
| 7574 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
||
| 7575 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
||
| 7576 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
||
| 7577 | |||
| 7578 | #define TIM_CR2_TI1S_Pos (7U) |
||
| 7579 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
||
| 7580 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
||
| 7581 | |||
| 7582 | /******************* Bit definition for TIM_SMCR register *******************/ |
||
| 7583 | #define TIM_SMCR_SMS_Pos (0U) |
||
| 7584 | #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ |
||
| 7585 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
||
| 7586 | #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ |
||
| 7587 | #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ |
||
| 7588 | #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ |
||
| 7589 | |||
| 7590 | #define TIM_SMCR_OCCS_Pos (3U) |
||
| 7591 | #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ |
||
| 7592 | #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ |
||
| 7593 | |||
| 7594 | #define TIM_SMCR_TS_Pos (4U) |
||
| 7595 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
||
| 7596 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
||
| 7597 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
||
| 7598 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
||
| 7599 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
||
| 7600 | |||
| 7601 | #define TIM_SMCR_MSM_Pos (7U) |
||
| 7602 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
||
| 7603 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
||
| 7604 | |||
| 7605 | #define TIM_SMCR_ETF_Pos (8U) |
||
| 7606 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
||
| 7607 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
||
| 7608 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
||
| 7609 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
||
| 7610 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
||
| 7611 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
||
| 7612 | |||
| 7613 | #define TIM_SMCR_ETPS_Pos (12U) |
||
| 7614 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
||
| 7615 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
||
| 7616 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
||
| 7617 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
||
| 7618 | |||
| 7619 | #define TIM_SMCR_ECE_Pos (14U) |
||
| 7620 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
||
| 7621 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
||
| 7622 | #define TIM_SMCR_ETP_Pos (15U) |
||
| 7623 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
||
| 7624 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
||
| 7625 | |||
| 7626 | /******************* Bit definition for TIM_DIER register *******************/ |
||
| 7627 | #define TIM_DIER_UIE_Pos (0U) |
||
| 7628 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
||
| 7629 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
||
| 7630 | #define TIM_DIER_CC1IE_Pos (1U) |
||
| 7631 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
||
| 7632 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
||
| 7633 | #define TIM_DIER_CC2IE_Pos (2U) |
||
| 7634 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
||
| 7635 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
||
| 7636 | #define TIM_DIER_CC3IE_Pos (3U) |
||
| 7637 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
||
| 7638 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
||
| 7639 | #define TIM_DIER_CC4IE_Pos (4U) |
||
| 7640 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
||
| 7641 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
||
| 7642 | #define TIM_DIER_TIE_Pos (6U) |
||
| 7643 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
||
| 7644 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
||
| 7645 | #define TIM_DIER_UDE_Pos (8U) |
||
| 7646 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
||
| 7647 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
||
| 7648 | #define TIM_DIER_CC1DE_Pos (9U) |
||
| 7649 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
||
| 7650 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
||
| 7651 | #define TIM_DIER_CC2DE_Pos (10U) |
||
| 7652 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
||
| 7653 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
||
| 7654 | #define TIM_DIER_CC3DE_Pos (11U) |
||
| 7655 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
||
| 7656 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
||
| 7657 | #define TIM_DIER_CC4DE_Pos (12U) |
||
| 7658 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
||
| 7659 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
||
| 7660 | #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */ |
||
| 7661 | #define TIM_DIER_TDE_Pos (14U) |
||
| 7662 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
||
| 7663 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
||
| 7664 | |||
| 7665 | /******************** Bit definition for TIM_SR register ********************/ |
||
| 7666 | #define TIM_SR_UIF_Pos (0U) |
||
| 7667 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
||
| 7668 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
||
| 7669 | #define TIM_SR_CC1IF_Pos (1U) |
||
| 7670 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
||
| 7671 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
||
| 7672 | #define TIM_SR_CC2IF_Pos (2U) |
||
| 7673 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
||
| 7674 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
||
| 7675 | #define TIM_SR_CC3IF_Pos (3U) |
||
| 7676 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
||
| 7677 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
||
| 7678 | #define TIM_SR_CC4IF_Pos (4U) |
||
| 7679 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
||
| 7680 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
||
| 7681 | #define TIM_SR_TIF_Pos (6U) |
||
| 7682 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
||
| 7683 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
||
| 7684 | #define TIM_SR_CC1OF_Pos (9U) |
||
| 7685 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
||
| 7686 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
||
| 7687 | #define TIM_SR_CC2OF_Pos (10U) |
||
| 7688 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
||
| 7689 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
||
| 7690 | #define TIM_SR_CC3OF_Pos (11U) |
||
| 7691 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
||
| 7692 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
||
| 7693 | #define TIM_SR_CC4OF_Pos (12U) |
||
| 7694 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
||
| 7695 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
||
| 7696 | |||
| 7697 | /******************* Bit definition for TIM_EGR register ********************/ |
||
| 7698 | #define TIM_EGR_UG_Pos (0U) |
||
| 7699 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
||
| 7700 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
||
| 7701 | #define TIM_EGR_CC1G_Pos (1U) |
||
| 7702 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
||
| 7703 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
||
| 7704 | #define TIM_EGR_CC2G_Pos (2U) |
||
| 7705 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
||
| 7706 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
||
| 7707 | #define TIM_EGR_CC3G_Pos (3U) |
||
| 7708 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
||
| 7709 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
||
| 7710 | #define TIM_EGR_CC4G_Pos (4U) |
||
| 7711 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
||
| 7712 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
||
| 7713 | #define TIM_EGR_TG_Pos (6U) |
||
| 7714 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
||
| 7715 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
||
| 7716 | |||
| 7717 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
||
| 7718 | #define TIM_CCMR1_CC1S_Pos (0U) |
||
| 7719 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
||
| 7720 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
||
| 7721 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
||
| 7722 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
||
| 7723 | |||
| 7724 | #define TIM_CCMR1_OC1FE_Pos (2U) |
||
| 7725 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
||
| 7726 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
||
| 7727 | #define TIM_CCMR1_OC1PE_Pos (3U) |
||
| 7728 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
||
| 7729 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
||
| 7730 | |||
| 7731 | #define TIM_CCMR1_OC1M_Pos (4U) |
||
| 7732 | #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ |
||
| 7733 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
||
| 7734 | #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ |
||
| 7735 | #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ |
||
| 7736 | #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ |
||
| 7737 | |||
| 7738 | #define TIM_CCMR1_OC1CE_Pos (7U) |
||
| 7739 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
||
| 7740 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
||
| 7741 | |||
| 7742 | #define TIM_CCMR1_CC2S_Pos (8U) |
||
| 7743 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
||
| 7744 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
||
| 7745 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
||
| 7746 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
||
| 7747 | |||
| 7748 | #define TIM_CCMR1_OC2FE_Pos (10U) |
||
| 7749 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
||
| 7750 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
||
| 7751 | #define TIM_CCMR1_OC2PE_Pos (11U) |
||
| 7752 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
||
| 7753 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
||
| 7754 | |||
| 7755 | #define TIM_CCMR1_OC2M_Pos (12U) |
||
| 7756 | #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ |
||
| 7757 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
||
| 7758 | #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ |
||
| 7759 | #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ |
||
| 7760 | #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ |
||
| 7761 | |||
| 7762 | #define TIM_CCMR1_OC2CE_Pos (15U) |
||
| 7763 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
||
| 7764 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
||
| 7765 | |||
| 7766 | /*----------------------------------------------------------------------------*/ |
||
| 7767 | |||
| 7768 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
||
| 7769 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
||
| 7770 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
||
| 7771 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
||
| 7772 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
||
| 7773 | |||
| 7774 | #define TIM_CCMR1_IC1F_Pos (4U) |
||
| 7775 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
||
| 7776 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
||
| 7777 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
||
| 7778 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
||
| 7779 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
||
| 7780 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
||
| 7781 | |||
| 7782 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
||
| 7783 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
||
| 7784 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
||
| 7785 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
||
| 7786 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
||
| 7787 | |||
| 7788 | #define TIM_CCMR1_IC2F_Pos (12U) |
||
| 7789 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
||
| 7790 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
||
| 7791 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
||
| 7792 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
||
| 7793 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
||
| 7794 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
||
| 7795 | |||
| 7796 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
||
| 7797 | #define TIM_CCMR2_CC3S_Pos (0U) |
||
| 7798 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
||
| 7799 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
||
| 7800 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
||
| 7801 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
||
| 7802 | |||
| 7803 | #define TIM_CCMR2_OC3FE_Pos (2U) |
||
| 7804 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
||
| 7805 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
||
| 7806 | #define TIM_CCMR2_OC3PE_Pos (3U) |
||
| 7807 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
||
| 7808 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
||
| 7809 | |||
| 7810 | #define TIM_CCMR2_OC3M_Pos (4U) |
||
| 7811 | #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ |
||
| 7812 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
||
| 7813 | #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ |
||
| 7814 | #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ |
||
| 7815 | #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ |
||
| 7816 | |||
| 7817 | #define TIM_CCMR2_OC3CE_Pos (7U) |
||
| 7818 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
||
| 7819 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
||
| 7820 | |||
| 7821 | #define TIM_CCMR2_CC4S_Pos (8U) |
||
| 7822 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
||
| 7823 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
||
| 7824 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
||
| 7825 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
||
| 7826 | |||
| 7827 | #define TIM_CCMR2_OC4FE_Pos (10U) |
||
| 7828 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
||
| 7829 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
||
| 7830 | #define TIM_CCMR2_OC4PE_Pos (11U) |
||
| 7831 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
||
| 7832 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
||
| 7833 | |||
| 7834 | #define TIM_CCMR2_OC4M_Pos (12U) |
||
| 7835 | #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ |
||
| 7836 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
||
| 7837 | #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ |
||
| 7838 | #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ |
||
| 7839 | #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ |
||
| 7840 | |||
| 7841 | #define TIM_CCMR2_OC4CE_Pos (15U) |
||
| 7842 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
||
| 7843 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
||
| 7844 | |||
| 7845 | /*----------------------------------------------------------------------------*/ |
||
| 7846 | |||
| 7847 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
||
| 7848 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
||
| 7849 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
||
| 7850 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
||
| 7851 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
||
| 7852 | |||
| 7853 | #define TIM_CCMR2_IC3F_Pos (4U) |
||
| 7854 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
||
| 7855 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
||
| 7856 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
||
| 7857 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
||
| 7858 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
||
| 7859 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
||
| 7860 | |||
| 7861 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
||
| 7862 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
||
| 7863 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
||
| 7864 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
||
| 7865 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
||
| 7866 | |||
| 7867 | #define TIM_CCMR2_IC4F_Pos (12U) |
||
| 7868 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
||
| 7869 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
||
| 7870 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
||
| 7871 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
||
| 7872 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
||
| 7873 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
||
| 7874 | |||
| 7875 | /******************* Bit definition for TIM_CCER register *******************/ |
||
| 7876 | #define TIM_CCER_CC1E_Pos (0U) |
||
| 7877 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
||
| 7878 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
||
| 7879 | #define TIM_CCER_CC1P_Pos (1U) |
||
| 7880 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
||
| 7881 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
||
| 7882 | #define TIM_CCER_CC1NP_Pos (3U) |
||
| 7883 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
||
| 7884 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
||
| 7885 | #define TIM_CCER_CC2E_Pos (4U) |
||
| 7886 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
||
| 7887 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
||
| 7888 | #define TIM_CCER_CC2P_Pos (5U) |
||
| 7889 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
||
| 7890 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
||
| 7891 | #define TIM_CCER_CC2NP_Pos (7U) |
||
| 7892 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
||
| 7893 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
||
| 7894 | #define TIM_CCER_CC3E_Pos (8U) |
||
| 7895 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
||
| 7896 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
||
| 7897 | #define TIM_CCER_CC3P_Pos (9U) |
||
| 7898 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
||
| 7899 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
||
| 7900 | #define TIM_CCER_CC3NP_Pos (11U) |
||
| 7901 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
||
| 7902 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
||
| 7903 | #define TIM_CCER_CC4E_Pos (12U) |
||
| 7904 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
||
| 7905 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
||
| 7906 | #define TIM_CCER_CC4P_Pos (13U) |
||
| 7907 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
||
| 7908 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
||
| 7909 | #define TIM_CCER_CC4NP_Pos (15U) |
||
| 7910 | #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ |
||
| 7911 | #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ |
||
| 7912 | |||
| 7913 | /******************* Bit definition for TIM_CNT register ********************/ |
||
| 7914 | #define TIM_CNT_CNT_Pos (0U) |
||
| 7915 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
||
| 7916 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
||
| 7917 | |||
| 7918 | /******************* Bit definition for TIM_PSC register ********************/ |
||
| 7919 | #define TIM_PSC_PSC_Pos (0U) |
||
| 7920 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
||
| 7921 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
||
| 7922 | |||
| 7923 | /******************* Bit definition for TIM_ARR register ********************/ |
||
| 7924 | #define TIM_ARR_ARR_Pos (0U) |
||
| 7925 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
||
| 7926 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
||
| 7927 | |||
| 7928 | /******************* Bit definition for TIM_CCR1 register *******************/ |
||
| 7929 | #define TIM_CCR1_CCR1_Pos (0U) |
||
| 7930 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
||
| 7931 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
||
| 7932 | |||
| 7933 | /******************* Bit definition for TIM_CCR2 register *******************/ |
||
| 7934 | #define TIM_CCR2_CCR2_Pos (0U) |
||
| 7935 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
||
| 7936 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
||
| 7937 | |||
| 7938 | /******************* Bit definition for TIM_CCR3 register *******************/ |
||
| 7939 | #define TIM_CCR3_CCR3_Pos (0U) |
||
| 7940 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
||
| 7941 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
||
| 7942 | |||
| 7943 | /******************* Bit definition for TIM_CCR4 register *******************/ |
||
| 7944 | #define TIM_CCR4_CCR4_Pos (0U) |
||
| 7945 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
||
| 7946 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
||
| 7947 | |||
| 7948 | /******************* Bit definition for TIM_DCR register ********************/ |
||
| 7949 | #define TIM_DCR_DBA_Pos (0U) |
||
| 7950 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
||
| 7951 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
||
| 7952 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
||
| 7953 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
||
| 7954 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
||
| 7955 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
||
| 7956 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
||
| 7957 | |||
| 7958 | #define TIM_DCR_DBL_Pos (8U) |
||
| 7959 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
||
| 7960 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
||
| 7961 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
||
| 7962 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
||
| 7963 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
||
| 7964 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
||
| 7965 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
||
| 7966 | |||
| 7967 | /******************* Bit definition for TIM_DMAR register *******************/ |
||
| 7968 | #define TIM_DMAR_DMAB_Pos (0U) |
||
| 7969 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
||
| 7970 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
||
| 7971 | |||
| 7972 | /******************* Bit definition for TIM_OR register *********************/ |
||
| 7973 | #define TIM_OR_TI1RMP_Pos (0U) |
||
| 7974 | #define TIM_OR_TI1RMP_Msk (0x3U << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */ |
||
| 7975 | #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */ |
||
| 7976 | #define TIM_OR_TI1RMP_0 (0x1U << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */ |
||
| 7977 | #define TIM_OR_TI1RMP_1 (0x2U << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */ |
||
| 7978 | |||
| 7979 | #define TIM_OR_ETR_RMP_Pos (2U) |
||
| 7980 | #define TIM_OR_ETR_RMP_Msk (0x1U << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */ |
||
| 7981 | #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/ |
||
| 7982 | #define TIM_OR_TI1_RMP_RI_Pos (3U) |
||
| 7983 | #define TIM_OR_TI1_RMP_RI_Msk (0x1U << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */ |
||
| 7984 | #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */ |
||
| 7985 | |||
| 7986 | /*----------------------------------------------------------------------------*/ |
||
| 7987 | #define TIM9_OR_ITR1_RMP_Pos (2U) |
||
| 7988 | #define TIM9_OR_ITR1_RMP_Msk (0x1U << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */ |
||
| 7989 | #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */ |
||
| 7990 | |||
| 7991 | /*----------------------------------------------------------------------------*/ |
||
| 7992 | #define TIM2_OR_ITR1_RMP_Pos (0U) |
||
| 7993 | #define TIM2_OR_ITR1_RMP_Msk (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */ |
||
| 7994 | #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */ |
||
| 7995 | |||
| 7996 | /*----------------------------------------------------------------------------*/ |
||
| 7997 | #define TIM3_OR_ITR2_RMP_Pos (0U) |
||
| 7998 | #define TIM3_OR_ITR2_RMP_Msk (0x1U << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */ |
||
| 7999 | #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */ |
||
| 8000 | |||
| 8001 | /*----------------------------------------------------------------------------*/ |
||
| 8002 | |||
| 8003 | /******************************************************************************/ |
||
| 8004 | /* */ |
||
| 8005 | /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ |
||
| 8006 | /* */ |
||
| 8007 | /******************************************************************************/ |
||
| 8008 | |||
| 8009 | /******************* Bit definition for USART_SR register *******************/ |
||
| 8010 | #define USART_SR_PE_Pos (0U) |
||
| 8011 | #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ |
||
| 8012 | #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ |
||
| 8013 | #define USART_SR_FE_Pos (1U) |
||
| 8014 | #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ |
||
| 8015 | #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ |
||
| 8016 | #define USART_SR_NE_Pos (2U) |
||
| 8017 | #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ |
||
| 8018 | #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ |
||
| 8019 | #define USART_SR_ORE_Pos (3U) |
||
| 8020 | #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ |
||
| 8021 | #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ |
||
| 8022 | #define USART_SR_IDLE_Pos (4U) |
||
| 8023 | #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ |
||
| 8024 | #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ |
||
| 8025 | #define USART_SR_RXNE_Pos (5U) |
||
| 8026 | #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ |
||
| 8027 | #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ |
||
| 8028 | #define USART_SR_TC_Pos (6U) |
||
| 8029 | #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ |
||
| 8030 | #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ |
||
| 8031 | #define USART_SR_TXE_Pos (7U) |
||
| 8032 | #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ |
||
| 8033 | #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ |
||
| 8034 | #define USART_SR_LBD_Pos (8U) |
||
| 8035 | #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ |
||
| 8036 | #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ |
||
| 8037 | #define USART_SR_CTS_Pos (9U) |
||
| 8038 | #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ |
||
| 8039 | #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ |
||
| 8040 | |||
| 8041 | /******************* Bit definition for USART_DR register *******************/ |
||
| 8042 | #define USART_DR_DR_Pos (0U) |
||
| 8043 | #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ |
||
| 8044 | #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ |
||
| 8045 | |||
| 8046 | /****************** Bit definition for USART_BRR register *******************/ |
||
| 8047 | #define USART_BRR_DIV_FRACTION_Pos (0U) |
||
| 8048 | #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ |
||
| 8049 | #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ |
||
| 8050 | #define USART_BRR_DIV_MANTISSA_Pos (4U) |
||
| 8051 | #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ |
||
| 8052 | #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ |
||
| 8053 | |||
| 8054 | /****************** Bit definition for USART_CR1 register *******************/ |
||
| 8055 | #define USART_CR1_SBK_Pos (0U) |
||
| 8056 | #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ |
||
| 8057 | #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ |
||
| 8058 | #define USART_CR1_RWU_Pos (1U) |
||
| 8059 | #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ |
||
| 8060 | #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ |
||
| 8061 | #define USART_CR1_RE_Pos (2U) |
||
| 8062 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
||
| 8063 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
||
| 8064 | #define USART_CR1_TE_Pos (3U) |
||
| 8065 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
||
| 8066 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
||
| 8067 | #define USART_CR1_IDLEIE_Pos (4U) |
||
| 8068 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
||
| 8069 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
||
| 8070 | #define USART_CR1_RXNEIE_Pos (5U) |
||
| 8071 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
||
| 8072 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
||
| 8073 | #define USART_CR1_TCIE_Pos (6U) |
||
| 8074 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
||
| 8075 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
||
| 8076 | #define USART_CR1_TXEIE_Pos (7U) |
||
| 8077 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
||
| 8078 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ |
||
| 8079 | #define USART_CR1_PEIE_Pos (8U) |
||
| 8080 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
||
| 8081 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
||
| 8082 | #define USART_CR1_PS_Pos (9U) |
||
| 8083 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
||
| 8084 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
||
| 8085 | #define USART_CR1_PCE_Pos (10U) |
||
| 8086 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
||
| 8087 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
||
| 8088 | #define USART_CR1_WAKE_Pos (11U) |
||
| 8089 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
||
| 8090 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ |
||
| 8091 | #define USART_CR1_M_Pos (12U) |
||
| 8092 | #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ |
||
| 8093 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
||
| 8094 | #define USART_CR1_UE_Pos (13U) |
||
| 8095 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ |
||
| 8096 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
||
| 8097 | #define USART_CR1_OVER8_Pos (15U) |
||
| 8098 | #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ |
||
| 8099 | #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */ |
||
| 8100 | |||
| 8101 | /****************** Bit definition for USART_CR2 register *******************/ |
||
| 8102 | #define USART_CR2_ADD_Pos (0U) |
||
| 8103 | #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ |
||
| 8104 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
||
| 8105 | #define USART_CR2_LBDL_Pos (5U) |
||
| 8106 | #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
||
| 8107 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
||
| 8108 | #define USART_CR2_LBDIE_Pos (6U) |
||
| 8109 | #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
||
| 8110 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
||
| 8111 | #define USART_CR2_LBCL_Pos (8U) |
||
| 8112 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
||
| 8113 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
||
| 8114 | #define USART_CR2_CPHA_Pos (9U) |
||
| 8115 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
||
| 8116 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
||
| 8117 | #define USART_CR2_CPOL_Pos (10U) |
||
| 8118 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
||
| 8119 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
||
| 8120 | #define USART_CR2_CLKEN_Pos (11U) |
||
| 8121 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
||
| 8122 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
||
| 8123 | |||
| 8124 | #define USART_CR2_STOP_Pos (12U) |
||
| 8125 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
||
| 8126 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
||
| 8127 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
||
| 8128 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
||
| 8129 | |||
| 8130 | #define USART_CR2_LINEN_Pos (14U) |
||
| 8131 | #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
||
| 8132 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
||
| 8133 | |||
| 8134 | /****************** Bit definition for USART_CR3 register *******************/ |
||
| 8135 | #define USART_CR3_EIE_Pos (0U) |
||
| 8136 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
||
| 8137 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
||
| 8138 | #define USART_CR3_IREN_Pos (1U) |
||
| 8139 | #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
||
| 8140 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
||
| 8141 | #define USART_CR3_IRLP_Pos (2U) |
||
| 8142 | #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
||
| 8143 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
||
| 8144 | #define USART_CR3_HDSEL_Pos (3U) |
||
| 8145 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
||
| 8146 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
||
| 8147 | #define USART_CR3_NACK_Pos (4U) |
||
| 8148 | #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
||
| 8149 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ |
||
| 8150 | #define USART_CR3_SCEN_Pos (5U) |
||
| 8151 | #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
||
| 8152 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ |
||
| 8153 | #define USART_CR3_DMAR_Pos (6U) |
||
| 8154 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
||
| 8155 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
||
| 8156 | #define USART_CR3_DMAT_Pos (7U) |
||
| 8157 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
||
| 8158 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
||
| 8159 | #define USART_CR3_RTSE_Pos (8U) |
||
| 8160 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
||
| 8161 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
||
| 8162 | #define USART_CR3_CTSE_Pos (9U) |
||
| 8163 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
||
| 8164 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
||
| 8165 | #define USART_CR3_CTSIE_Pos (10U) |
||
| 8166 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
||
| 8167 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
||
| 8168 | #define USART_CR3_ONEBIT_Pos (11U) |
||
| 8169 | #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ |
||
| 8170 | #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ |
||
| 8171 | |||
| 8172 | /****************** Bit definition for USART_GTPR register ******************/ |
||
| 8173 | #define USART_GTPR_PSC_Pos (0U) |
||
| 8174 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
||
| 8175 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
||
| 8176 | #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ |
||
| 8177 | #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ |
||
| 8178 | #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ |
||
| 8179 | #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ |
||
| 8180 | #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ |
||
| 8181 | #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ |
||
| 8182 | #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ |
||
| 8183 | #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ |
||
| 8184 | |||
| 8185 | #define USART_GTPR_GT_Pos (8U) |
||
| 8186 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
||
| 8187 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ |
||
| 8188 | |||
| 8189 | /******************************************************************************/ |
||
| 8190 | /* */ |
||
| 8191 | /* Universal Serial Bus (USB) */ |
||
| 8192 | /* */ |
||
| 8193 | /******************************************************************************/ |
||
| 8194 | |||
| 8195 | /*!<Endpoint-specific registers */ |
||
| 8196 | |||
| 8197 | #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ |
||
| 8198 | #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */ |
||
| 8199 | #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */ |
||
| 8200 | #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */ |
||
| 8201 | #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */ |
||
| 8202 | #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */ |
||
| 8203 | #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */ |
||
| 8204 | #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */ |
||
| 8205 | |||
| 8206 | /* bit positions */ |
||
| 8207 | #define USB_EP_CTR_RX_Pos (15U) |
||
| 8208 | #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8209 | #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ |
||
| 8210 | #define USB_EP_DTOG_RX_Pos (14U) |
||
| 8211 | #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8212 | #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ |
||
| 8213 | #define USB_EPRX_STAT_Pos (12U) |
||
| 8214 | #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ |
||
| 8215 | #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ |
||
| 8216 | #define USB_EP_SETUP_Pos (11U) |
||
| 8217 | #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8218 | #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ |
||
| 8219 | #define USB_EP_T_FIELD_Pos (9U) |
||
| 8220 | #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ |
||
| 8221 | #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ |
||
| 8222 | #define USB_EP_KIND_Pos (8U) |
||
| 8223 | #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8224 | #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ |
||
| 8225 | #define USB_EP_CTR_TX_Pos (7U) |
||
| 8226 | #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8227 | #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ |
||
| 8228 | #define USB_EP_DTOG_TX_Pos (6U) |
||
| 8229 | #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8230 | #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ |
||
| 8231 | #define USB_EPTX_STAT_Pos (4U) |
||
| 8232 | #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ |
||
| 8233 | #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ |
||
| 8234 | #define USB_EPADDR_FIELD_Pos (0U) |
||
| 8235 | #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ |
||
| 8236 | #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ |
||
| 8237 | |||
| 8238 | /* EndPoint REGister MASK (no toggle fields) */ |
||
| 8239 | #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) |
||
| 8240 | /*!< EP_TYPE[1:0] EndPoint TYPE */ |
||
| 8241 | #define USB_EP_TYPE_MASK_Pos (9U) |
||
| 8242 | #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ |
||
| 8243 | #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ |
||
| 8244 | #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */ |
||
| 8245 | #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */ |
||
| 8246 | #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */ |
||
| 8247 | #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */ |
||
| 8248 | #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) |
||
| 8249 | |||
| 8250 | #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ |
||
| 8251 | /*!< STAT_TX[1:0] STATus for TX transfer */ |
||
| 8252 | #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */ |
||
| 8253 | #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */ |
||
| 8254 | #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */ |
||
| 8255 | #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */ |
||
| 8256 | #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */ |
||
| 8257 | #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */ |
||
| 8258 | #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) |
||
| 8259 | /*!< STAT_RX[1:0] STATus for RX transfer */ |
||
| 8260 | #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */ |
||
| 8261 | #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */ |
||
| 8262 | #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */ |
||
| 8263 | #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */ |
||
| 8264 | #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */ |
||
| 8265 | #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */ |
||
| 8266 | #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) |
||
| 8267 | |||
| 8268 | /******************* Bit definition for USB_EP0R register *******************/ |
||
| 8269 | #define USB_EP0R_EA_Pos (0U) |
||
| 8270 | #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */ |
||
| 8271 | #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */ |
||
| 8272 | |||
| 8273 | #define USB_EP0R_STAT_TX_Pos (4U) |
||
| 8274 | #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8275 | #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8276 | #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8277 | #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8278 | |||
| 8279 | #define USB_EP0R_DTOG_TX_Pos (6U) |
||
| 8280 | #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8281 | #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8282 | #define USB_EP0R_CTR_TX_Pos (7U) |
||
| 8283 | #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8284 | #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8285 | #define USB_EP0R_EP_KIND_Pos (8U) |
||
| 8286 | #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8287 | #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8288 | |||
| 8289 | #define USB_EP0R_EP_TYPE_Pos (9U) |
||
| 8290 | #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8291 | #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8292 | #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8293 | #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8294 | |||
| 8295 | #define USB_EP0R_SETUP_Pos (11U) |
||
| 8296 | #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8297 | #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8298 | |||
| 8299 | #define USB_EP0R_STAT_RX_Pos (12U) |
||
| 8300 | #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8301 | #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8302 | #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8303 | #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8304 | |||
| 8305 | #define USB_EP0R_DTOG_RX_Pos (14U) |
||
| 8306 | #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8307 | #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8308 | #define USB_EP0R_CTR_RX_Pos (15U) |
||
| 8309 | #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8310 | #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8311 | |||
| 8312 | /******************* Bit definition for USB_EP1R register *******************/ |
||
| 8313 | #define USB_EP1R_EA_Pos (0U) |
||
| 8314 | #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */ |
||
| 8315 | #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */ |
||
| 8316 | |||
| 8317 | #define USB_EP1R_STAT_TX_Pos (4U) |
||
| 8318 | #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8319 | #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8320 | #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8321 | #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8322 | |||
| 8323 | #define USB_EP1R_DTOG_TX_Pos (6U) |
||
| 8324 | #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8325 | #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8326 | #define USB_EP1R_CTR_TX_Pos (7U) |
||
| 8327 | #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8328 | #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8329 | #define USB_EP1R_EP_KIND_Pos (8U) |
||
| 8330 | #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8331 | #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8332 | |||
| 8333 | #define USB_EP1R_EP_TYPE_Pos (9U) |
||
| 8334 | #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8335 | #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8336 | #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8337 | #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8338 | |||
| 8339 | #define USB_EP1R_SETUP_Pos (11U) |
||
| 8340 | #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8341 | #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8342 | |||
| 8343 | #define USB_EP1R_STAT_RX_Pos (12U) |
||
| 8344 | #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8345 | #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8346 | #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8347 | #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8348 | |||
| 8349 | #define USB_EP1R_DTOG_RX_Pos (14U) |
||
| 8350 | #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8351 | #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8352 | #define USB_EP1R_CTR_RX_Pos (15U) |
||
| 8353 | #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8354 | #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8355 | |||
| 8356 | /******************* Bit definition for USB_EP2R register *******************/ |
||
| 8357 | #define USB_EP2R_EA_Pos (0U) |
||
| 8358 | #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */ |
||
| 8359 | #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */ |
||
| 8360 | |||
| 8361 | #define USB_EP2R_STAT_TX_Pos (4U) |
||
| 8362 | #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8363 | #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8364 | #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8365 | #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8366 | |||
| 8367 | #define USB_EP2R_DTOG_TX_Pos (6U) |
||
| 8368 | #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8369 | #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8370 | #define USB_EP2R_CTR_TX_Pos (7U) |
||
| 8371 | #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8372 | #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8373 | #define USB_EP2R_EP_KIND_Pos (8U) |
||
| 8374 | #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8375 | #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8376 | |||
| 8377 | #define USB_EP2R_EP_TYPE_Pos (9U) |
||
| 8378 | #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8379 | #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8380 | #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8381 | #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8382 | |||
| 8383 | #define USB_EP2R_SETUP_Pos (11U) |
||
| 8384 | #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8385 | #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8386 | |||
| 8387 | #define USB_EP2R_STAT_RX_Pos (12U) |
||
| 8388 | #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8389 | #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8390 | #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8391 | #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8392 | |||
| 8393 | #define USB_EP2R_DTOG_RX_Pos (14U) |
||
| 8394 | #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8395 | #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8396 | #define USB_EP2R_CTR_RX_Pos (15U) |
||
| 8397 | #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8398 | #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8399 | |||
| 8400 | /******************* Bit definition for USB_EP3R register *******************/ |
||
| 8401 | #define USB_EP3R_EA_Pos (0U) |
||
| 8402 | #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */ |
||
| 8403 | #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */ |
||
| 8404 | |||
| 8405 | #define USB_EP3R_STAT_TX_Pos (4U) |
||
| 8406 | #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8407 | #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8408 | #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8409 | #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8410 | |||
| 8411 | #define USB_EP3R_DTOG_TX_Pos (6U) |
||
| 8412 | #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8413 | #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8414 | #define USB_EP3R_CTR_TX_Pos (7U) |
||
| 8415 | #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8416 | #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8417 | #define USB_EP3R_EP_KIND_Pos (8U) |
||
| 8418 | #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8419 | #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8420 | |||
| 8421 | #define USB_EP3R_EP_TYPE_Pos (9U) |
||
| 8422 | #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8423 | #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8424 | #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8425 | #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8426 | |||
| 8427 | #define USB_EP3R_SETUP_Pos (11U) |
||
| 8428 | #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8429 | #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8430 | |||
| 8431 | #define USB_EP3R_STAT_RX_Pos (12U) |
||
| 8432 | #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8433 | #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8434 | #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8435 | #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8436 | |||
| 8437 | #define USB_EP3R_DTOG_RX_Pos (14U) |
||
| 8438 | #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8439 | #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8440 | #define USB_EP3R_CTR_RX_Pos (15U) |
||
| 8441 | #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8442 | #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8443 | |||
| 8444 | /******************* Bit definition for USB_EP4R register *******************/ |
||
| 8445 | #define USB_EP4R_EA_Pos (0U) |
||
| 8446 | #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */ |
||
| 8447 | #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */ |
||
| 8448 | |||
| 8449 | #define USB_EP4R_STAT_TX_Pos (4U) |
||
| 8450 | #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8451 | #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8452 | #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8453 | #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8454 | |||
| 8455 | #define USB_EP4R_DTOG_TX_Pos (6U) |
||
| 8456 | #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8457 | #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8458 | #define USB_EP4R_CTR_TX_Pos (7U) |
||
| 8459 | #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8460 | #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8461 | #define USB_EP4R_EP_KIND_Pos (8U) |
||
| 8462 | #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8463 | #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8464 | |||
| 8465 | #define USB_EP4R_EP_TYPE_Pos (9U) |
||
| 8466 | #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8467 | #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8468 | #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8469 | #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8470 | |||
| 8471 | #define USB_EP4R_SETUP_Pos (11U) |
||
| 8472 | #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8473 | #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8474 | |||
| 8475 | #define USB_EP4R_STAT_RX_Pos (12U) |
||
| 8476 | #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8477 | #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8478 | #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8479 | #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8480 | |||
| 8481 | #define USB_EP4R_DTOG_RX_Pos (14U) |
||
| 8482 | #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8483 | #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8484 | #define USB_EP4R_CTR_RX_Pos (15U) |
||
| 8485 | #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8486 | #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8487 | |||
| 8488 | /******************* Bit definition for USB_EP5R register *******************/ |
||
| 8489 | #define USB_EP5R_EA_Pos (0U) |
||
| 8490 | #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */ |
||
| 8491 | #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */ |
||
| 8492 | |||
| 8493 | #define USB_EP5R_STAT_TX_Pos (4U) |
||
| 8494 | #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8495 | #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8496 | #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8497 | #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8498 | |||
| 8499 | #define USB_EP5R_DTOG_TX_Pos (6U) |
||
| 8500 | #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8501 | #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8502 | #define USB_EP5R_CTR_TX_Pos (7U) |
||
| 8503 | #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8504 | #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8505 | #define USB_EP5R_EP_KIND_Pos (8U) |
||
| 8506 | #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8507 | #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8508 | |||
| 8509 | #define USB_EP5R_EP_TYPE_Pos (9U) |
||
| 8510 | #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8511 | #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8512 | #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8513 | #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8514 | |||
| 8515 | #define USB_EP5R_SETUP_Pos (11U) |
||
| 8516 | #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8517 | #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8518 | |||
| 8519 | #define USB_EP5R_STAT_RX_Pos (12U) |
||
| 8520 | #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8521 | #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8522 | #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8523 | #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8524 | |||
| 8525 | #define USB_EP5R_DTOG_RX_Pos (14U) |
||
| 8526 | #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8527 | #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8528 | #define USB_EP5R_CTR_RX_Pos (15U) |
||
| 8529 | #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8530 | #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8531 | |||
| 8532 | /******************* Bit definition for USB_EP6R register *******************/ |
||
| 8533 | #define USB_EP6R_EA_Pos (0U) |
||
| 8534 | #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */ |
||
| 8535 | #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */ |
||
| 8536 | |||
| 8537 | #define USB_EP6R_STAT_TX_Pos (4U) |
||
| 8538 | #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8539 | #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8540 | #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8541 | #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8542 | |||
| 8543 | #define USB_EP6R_DTOG_TX_Pos (6U) |
||
| 8544 | #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8545 | #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8546 | #define USB_EP6R_CTR_TX_Pos (7U) |
||
| 8547 | #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8548 | #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8549 | #define USB_EP6R_EP_KIND_Pos (8U) |
||
| 8550 | #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8551 | #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8552 | |||
| 8553 | #define USB_EP6R_EP_TYPE_Pos (9U) |
||
| 8554 | #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8555 | #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8556 | #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8557 | #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8558 | |||
| 8559 | #define USB_EP6R_SETUP_Pos (11U) |
||
| 8560 | #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8561 | #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8562 | |||
| 8563 | #define USB_EP6R_STAT_RX_Pos (12U) |
||
| 8564 | #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8565 | #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8566 | #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8567 | #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8568 | |||
| 8569 | #define USB_EP6R_DTOG_RX_Pos (14U) |
||
| 8570 | #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8571 | #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8572 | #define USB_EP6R_CTR_RX_Pos (15U) |
||
| 8573 | #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8574 | #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8575 | |||
| 8576 | /******************* Bit definition for USB_EP7R register *******************/ |
||
| 8577 | #define USB_EP7R_EA_Pos (0U) |
||
| 8578 | #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */ |
||
| 8579 | #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */ |
||
| 8580 | |||
| 8581 | #define USB_EP7R_STAT_TX_Pos (4U) |
||
| 8582 | #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ |
||
| 8583 | #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ |
||
| 8584 | #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ |
||
| 8585 | #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ |
||
| 8586 | |||
| 8587 | #define USB_EP7R_DTOG_TX_Pos (6U) |
||
| 8588 | #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ |
||
| 8589 | #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ |
||
| 8590 | #define USB_EP7R_CTR_TX_Pos (7U) |
||
| 8591 | #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ |
||
| 8592 | #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */ |
||
| 8593 | #define USB_EP7R_EP_KIND_Pos (8U) |
||
| 8594 | #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ |
||
| 8595 | #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */ |
||
| 8596 | |||
| 8597 | #define USB_EP7R_EP_TYPE_Pos (9U) |
||
| 8598 | #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ |
||
| 8599 | #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ |
||
| 8600 | #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ |
||
| 8601 | #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ |
||
| 8602 | |||
| 8603 | #define USB_EP7R_SETUP_Pos (11U) |
||
| 8604 | #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ |
||
| 8605 | #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */ |
||
| 8606 | |||
| 8607 | #define USB_EP7R_STAT_RX_Pos (12U) |
||
| 8608 | #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ |
||
| 8609 | #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ |
||
| 8610 | #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ |
||
| 8611 | #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ |
||
| 8612 | |||
| 8613 | #define USB_EP7R_DTOG_RX_Pos (14U) |
||
| 8614 | #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ |
||
| 8615 | #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ |
||
| 8616 | #define USB_EP7R_CTR_RX_Pos (15U) |
||
| 8617 | #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ |
||
| 8618 | #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */ |
||
| 8619 | |||
| 8620 | /*!<Common registers */ |
||
| 8621 | |||
| 8622 | #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */ |
||
| 8623 | #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */ |
||
| 8624 | #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */ |
||
| 8625 | #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */ |
||
| 8626 | #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */ |
||
| 8627 | |||
| 8628 | |||
| 8629 | |||
| 8630 | /******************* Bit definition for USB_CNTR register *******************/ |
||
| 8631 | #define USB_CNTR_FRES_Pos (0U) |
||
| 8632 | #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ |
||
| 8633 | #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */ |
||
| 8634 | #define USB_CNTR_PDWN_Pos (1U) |
||
| 8635 | #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ |
||
| 8636 | #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */ |
||
| 8637 | #define USB_CNTR_LPMODE_Pos (2U) |
||
| 8638 | #define USB_CNTR_LPMODE_Msk (0x1U << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */ |
||
| 8639 | #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */ |
||
| 8640 | #define USB_CNTR_FSUSP_Pos (3U) |
||
| 8641 | #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ |
||
| 8642 | #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */ |
||
| 8643 | #define USB_CNTR_RESUME_Pos (4U) |
||
| 8644 | #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ |
||
| 8645 | #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */ |
||
| 8646 | #define USB_CNTR_ESOFM_Pos (8U) |
||
| 8647 | #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ |
||
| 8648 | #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */ |
||
| 8649 | #define USB_CNTR_SOFM_Pos (9U) |
||
| 8650 | #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ |
||
| 8651 | #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */ |
||
| 8652 | #define USB_CNTR_RESETM_Pos (10U) |
||
| 8653 | #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ |
||
| 8654 | #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */ |
||
| 8655 | #define USB_CNTR_SUSPM_Pos (11U) |
||
| 8656 | #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ |
||
| 8657 | #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */ |
||
| 8658 | #define USB_CNTR_WKUPM_Pos (12U) |
||
| 8659 | #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ |
||
| 8660 | #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */ |
||
| 8661 | #define USB_CNTR_ERRM_Pos (13U) |
||
| 8662 | #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ |
||
| 8663 | #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */ |
||
| 8664 | #define USB_CNTR_PMAOVRM_Pos (14U) |
||
| 8665 | #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ |
||
| 8666 | #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */ |
||
| 8667 | #define USB_CNTR_CTRM_Pos (15U) |
||
| 8668 | #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ |
||
| 8669 | #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */ |
||
| 8670 | |||
| 8671 | /******************* Bit definition for USB_ISTR register *******************/ |
||
| 8672 | #define USB_ISTR_EP_ID_Pos (0U) |
||
| 8673 | #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ |
||
| 8674 | #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */ |
||
| 8675 | #define USB_ISTR_DIR_Pos (4U) |
||
| 8676 | #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ |
||
| 8677 | #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */ |
||
| 8678 | #define USB_ISTR_ESOF_Pos (8U) |
||
| 8679 | #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ |
||
| 8680 | #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */ |
||
| 8681 | #define USB_ISTR_SOF_Pos (9U) |
||
| 8682 | #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ |
||
| 8683 | #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */ |
||
| 8684 | #define USB_ISTR_RESET_Pos (10U) |
||
| 8685 | #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ |
||
| 8686 | #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */ |
||
| 8687 | #define USB_ISTR_SUSP_Pos (11U) |
||
| 8688 | #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ |
||
| 8689 | #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */ |
||
| 8690 | #define USB_ISTR_WKUP_Pos (12U) |
||
| 8691 | #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ |
||
| 8692 | #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */ |
||
| 8693 | #define USB_ISTR_ERR_Pos (13U) |
||
| 8694 | #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ |
||
| 8695 | #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */ |
||
| 8696 | #define USB_ISTR_PMAOVR_Pos (14U) |
||
| 8697 | #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ |
||
| 8698 | #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */ |
||
| 8699 | #define USB_ISTR_CTR_Pos (15U) |
||
| 8700 | #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ |
||
| 8701 | #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */ |
||
| 8702 | |||
| 8703 | #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ |
||
| 8704 | #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ |
||
| 8705 | #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ |
||
| 8706 | #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ |
||
| 8707 | #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ |
||
| 8708 | #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ |
||
| 8709 | #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ |
||
| 8710 | #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ |
||
| 8711 | |||
| 8712 | |||
| 8713 | /******************* Bit definition for USB_FNR register ********************/ |
||
| 8714 | #define USB_FNR_FN_Pos (0U) |
||
| 8715 | #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */ |
||
| 8716 | #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */ |
||
| 8717 | #define USB_FNR_LSOF_Pos (11U) |
||
| 8718 | #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ |
||
| 8719 | #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */ |
||
| 8720 | #define USB_FNR_LCK_Pos (13U) |
||
| 8721 | #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */ |
||
| 8722 | #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */ |
||
| 8723 | #define USB_FNR_RXDM_Pos (14U) |
||
| 8724 | #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ |
||
| 8725 | #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */ |
||
| 8726 | #define USB_FNR_RXDP_Pos (15U) |
||
| 8727 | #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ |
||
| 8728 | #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */ |
||
| 8729 | |||
| 8730 | /****************** Bit definition for USB_DADDR register *******************/ |
||
| 8731 | #define USB_DADDR_ADD_Pos (0U) |
||
| 8732 | #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ |
||
| 8733 | #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */ |
||
| 8734 | #define USB_DADDR_ADD0_Pos (0U) |
||
| 8735 | #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ |
||
| 8736 | #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */ |
||
| 8737 | #define USB_DADDR_ADD1_Pos (1U) |
||
| 8738 | #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ |
||
| 8739 | #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */ |
||
| 8740 | #define USB_DADDR_ADD2_Pos (2U) |
||
| 8741 | #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ |
||
| 8742 | #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */ |
||
| 8743 | #define USB_DADDR_ADD3_Pos (3U) |
||
| 8744 | #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ |
||
| 8745 | #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */ |
||
| 8746 | #define USB_DADDR_ADD4_Pos (4U) |
||
| 8747 | #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ |
||
| 8748 | #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */ |
||
| 8749 | #define USB_DADDR_ADD5_Pos (5U) |
||
| 8750 | #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ |
||
| 8751 | #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */ |
||
| 8752 | #define USB_DADDR_ADD6_Pos (6U) |
||
| 8753 | #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ |
||
| 8754 | #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */ |
||
| 8755 | |||
| 8756 | #define USB_DADDR_EF_Pos (7U) |
||
| 8757 | #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */ |
||
| 8758 | #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */ |
||
| 8759 | |||
| 8760 | /****************** Bit definition for USB_BTABLE register ******************/ |
||
| 8761 | #define USB_BTABLE_BTABLE_Pos (3U) |
||
| 8762 | #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ |
||
| 8763 | #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */ |
||
| 8764 | |||
| 8765 | /*!< Buffer descriptor table */ |
||
| 8766 | /***************** Bit definition for USB_ADDR0_TX register *****************/ |
||
| 8767 | #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) |
||
| 8768 | #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8769 | #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ |
||
| 8770 | |||
| 8771 | /***************** Bit definition for USB_ADDR1_TX register *****************/ |
||
| 8772 | #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) |
||
| 8773 | #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8774 | #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ |
||
| 8775 | |||
| 8776 | /***************** Bit definition for USB_ADDR2_TX register *****************/ |
||
| 8777 | #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) |
||
| 8778 | #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8779 | #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ |
||
| 8780 | |||
| 8781 | /***************** Bit definition for USB_ADDR3_TX register *****************/ |
||
| 8782 | #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) |
||
| 8783 | #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8784 | #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ |
||
| 8785 | |||
| 8786 | /***************** Bit definition for USB_ADDR4_TX register *****************/ |
||
| 8787 | #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) |
||
| 8788 | #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8789 | #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ |
||
| 8790 | |||
| 8791 | /***************** Bit definition for USB_ADDR5_TX register *****************/ |
||
| 8792 | #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) |
||
| 8793 | #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8794 | #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ |
||
| 8795 | |||
| 8796 | /***************** Bit definition for USB_ADDR6_TX register *****************/ |
||
| 8797 | #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) |
||
| 8798 | #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8799 | #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ |
||
| 8800 | |||
| 8801 | /***************** Bit definition for USB_ADDR7_TX register *****************/ |
||
| 8802 | #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) |
||
| 8803 | #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ |
||
| 8804 | #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ |
||
| 8805 | |||
| 8806 | /*----------------------------------------------------------------------------*/ |
||
| 8807 | |||
| 8808 | /***************** Bit definition for USB_COUNT0_TX register ****************/ |
||
| 8809 | #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) |
||
| 8810 | #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ |
||
| 8811 | #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ |
||
| 8812 | |||
| 8813 | /***************** Bit definition for USB_COUNT1_TX register ****************/ |
||
| 8814 | #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) |
||
| 8815 | #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ |
||
| 8816 | #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ |
||
| 8817 | |||
| 8818 | /***************** Bit definition for USB_COUNT2_TX register ****************/ |
||
| 8819 | #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) |
||
| 8820 | #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ |
||
| 8821 | #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ |
||
| 8822 | |||
| 8823 | /***************** Bit definition for USB_COUNT3_TX register ****************/ |
||
| 8824 | #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) |
||
| 8825 | #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ |
||
| 8826 | #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ |
||
| 8827 | |||
| 8828 | /***************** Bit definition for USB_COUNT4_TX register ****************/ |
||
| 8829 | #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) |
||
| 8830 | #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ |
||
| 8831 | #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ |
||
| 8832 | |||
| 8833 | /***************** Bit definition for USB_COUNT5_TX register ****************/ |
||
| 8834 | #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) |
||
| 8835 | #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ |
||
| 8836 | #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ |
||
| 8837 | |||
| 8838 | /***************** Bit definition for USB_COUNT6_TX register ****************/ |
||
| 8839 | #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) |
||
| 8840 | #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ |
||
| 8841 | #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ |
||
| 8842 | |||
| 8843 | /***************** Bit definition for USB_COUNT7_TX register ****************/ |
||
| 8844 | #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) |
||
| 8845 | #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ |
||
| 8846 | #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ |
||
| 8847 | |||
| 8848 | /*----------------------------------------------------------------------------*/ |
||
| 8849 | |||
| 8850 | /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ |
||
| 8851 | #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */ |
||
| 8852 | |||
| 8853 | /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ |
||
| 8854 | #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */ |
||
| 8855 | |||
| 8856 | /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ |
||
| 8857 | #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */ |
||
| 8858 | |||
| 8859 | /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ |
||
| 8860 | #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */ |
||
| 8861 | |||
| 8862 | /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ |
||
| 8863 | #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */ |
||
| 8864 | |||
| 8865 | /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ |
||
| 8866 | #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */ |
||
| 8867 | |||
| 8868 | /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ |
||
| 8869 | #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */ |
||
| 8870 | |||
| 8871 | /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ |
||
| 8872 | #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */ |
||
| 8873 | |||
| 8874 | /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ |
||
| 8875 | #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */ |
||
| 8876 | |||
| 8877 | /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ |
||
| 8878 | #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */ |
||
| 8879 | |||
| 8880 | /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ |
||
| 8881 | #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */ |
||
| 8882 | |||
| 8883 | /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ |
||
| 8884 | #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */ |
||
| 8885 | |||
| 8886 | /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ |
||
| 8887 | #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */ |
||
| 8888 | |||
| 8889 | /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ |
||
| 8890 | #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */ |
||
| 8891 | |||
| 8892 | /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ |
||
| 8893 | #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */ |
||
| 8894 | |||
| 8895 | /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ |
||
| 8896 | #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */ |
||
| 8897 | |||
| 8898 | /*----------------------------------------------------------------------------*/ |
||
| 8899 | |||
| 8900 | /***************** Bit definition for USB_ADDR0_RX register *****************/ |
||
| 8901 | #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) |
||
| 8902 | #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8903 | #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ |
||
| 8904 | |||
| 8905 | /***************** Bit definition for USB_ADDR1_RX register *****************/ |
||
| 8906 | #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) |
||
| 8907 | #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8908 | #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ |
||
| 8909 | |||
| 8910 | /***************** Bit definition for USB_ADDR2_RX register *****************/ |
||
| 8911 | #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) |
||
| 8912 | #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8913 | #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ |
||
| 8914 | |||
| 8915 | /***************** Bit definition for USB_ADDR3_RX register *****************/ |
||
| 8916 | #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) |
||
| 8917 | #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8918 | #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ |
||
| 8919 | |||
| 8920 | /***************** Bit definition for USB_ADDR4_RX register *****************/ |
||
| 8921 | #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) |
||
| 8922 | #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8923 | #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ |
||
| 8924 | |||
| 8925 | /***************** Bit definition for USB_ADDR5_RX register *****************/ |
||
| 8926 | #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) |
||
| 8927 | #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8928 | #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ |
||
| 8929 | |||
| 8930 | /***************** Bit definition for USB_ADDR6_RX register *****************/ |
||
| 8931 | #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) |
||
| 8932 | #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8933 | #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ |
||
| 8934 | |||
| 8935 | /***************** Bit definition for USB_ADDR7_RX register *****************/ |
||
| 8936 | #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) |
||
| 8937 | #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ |
||
| 8938 | #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ |
||
| 8939 | |||
| 8940 | /*----------------------------------------------------------------------------*/ |
||
| 8941 | |||
| 8942 | /***************** Bit definition for USB_COUNT0_RX register ****************/ |
||
| 8943 | #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) |
||
| 8944 | #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ |
||
| 8945 | #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ |
||
| 8946 | |||
| 8947 | #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) |
||
| 8948 | #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 8949 | #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 8950 | #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 8951 | #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 8952 | #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 8953 | #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 8954 | #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 8955 | |||
| 8956 | #define USB_COUNT0_RX_BLSIZE_Pos (15U) |
||
| 8957 | #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 8958 | #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 8959 | |||
| 8960 | /***************** Bit definition for USB_COUNT1_RX register ****************/ |
||
| 8961 | #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) |
||
| 8962 | #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ |
||
| 8963 | #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ |
||
| 8964 | |||
| 8965 | #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) |
||
| 8966 | #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 8967 | #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 8968 | #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 8969 | #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 8970 | #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 8971 | #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 8972 | #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 8973 | |||
| 8974 | #define USB_COUNT1_RX_BLSIZE_Pos (15U) |
||
| 8975 | #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 8976 | #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 8977 | |||
| 8978 | /***************** Bit definition for USB_COUNT2_RX register ****************/ |
||
| 8979 | #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) |
||
| 8980 | #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ |
||
| 8981 | #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ |
||
| 8982 | |||
| 8983 | #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) |
||
| 8984 | #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 8985 | #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 8986 | #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 8987 | #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 8988 | #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 8989 | #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 8990 | #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 8991 | |||
| 8992 | #define USB_COUNT2_RX_BLSIZE_Pos (15U) |
||
| 8993 | #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 8994 | #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 8995 | |||
| 8996 | /***************** Bit definition for USB_COUNT3_RX register ****************/ |
||
| 8997 | #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) |
||
| 8998 | #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ |
||
| 8999 | #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ |
||
| 9000 | |||
| 9001 | #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) |
||
| 9002 | #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 9003 | #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 9004 | #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 9005 | #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 9006 | #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 9007 | #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 9008 | #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 9009 | |||
| 9010 | #define USB_COUNT3_RX_BLSIZE_Pos (15U) |
||
| 9011 | #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 9012 | #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 9013 | |||
| 9014 | /***************** Bit definition for USB_COUNT4_RX register ****************/ |
||
| 9015 | #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) |
||
| 9016 | #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ |
||
| 9017 | #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ |
||
| 9018 | |||
| 9019 | #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) |
||
| 9020 | #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 9021 | #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 9022 | #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 9023 | #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 9024 | #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 9025 | #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 9026 | #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 9027 | |||
| 9028 | #define USB_COUNT4_RX_BLSIZE_Pos (15U) |
||
| 9029 | #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 9030 | #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 9031 | |||
| 9032 | /***************** Bit definition for USB_COUNT5_RX register ****************/ |
||
| 9033 | #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) |
||
| 9034 | #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ |
||
| 9035 | #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ |
||
| 9036 | |||
| 9037 | #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) |
||
| 9038 | #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 9039 | #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 9040 | #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 9041 | #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 9042 | #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 9043 | #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 9044 | #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 9045 | |||
| 9046 | #define USB_COUNT5_RX_BLSIZE_Pos (15U) |
||
| 9047 | #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 9048 | #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 9049 | |||
| 9050 | /***************** Bit definition for USB_COUNT6_RX register ****************/ |
||
| 9051 | #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) |
||
| 9052 | #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ |
||
| 9053 | #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ |
||
| 9054 | |||
| 9055 | #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) |
||
| 9056 | #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 9057 | #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 9058 | #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 9059 | #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 9060 | #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 9061 | #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 9062 | #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 9063 | |||
| 9064 | #define USB_COUNT6_RX_BLSIZE_Pos (15U) |
||
| 9065 | #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 9066 | #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 9067 | |||
| 9068 | /***************** Bit definition for USB_COUNT7_RX register ****************/ |
||
| 9069 | #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) |
||
| 9070 | #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ |
||
| 9071 | #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ |
||
| 9072 | |||
| 9073 | #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) |
||
| 9074 | #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ |
||
| 9075 | #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ |
||
| 9076 | #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ |
||
| 9077 | #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ |
||
| 9078 | #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ |
||
| 9079 | #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ |
||
| 9080 | #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ |
||
| 9081 | |||
| 9082 | #define USB_COUNT7_RX_BLSIZE_Pos (15U) |
||
| 9083 | #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ |
||
| 9084 | #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ |
||
| 9085 | |||
| 9086 | /*----------------------------------------------------------------------------*/ |
||
| 9087 | |||
| 9088 | /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ |
||
| 9089 | #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9090 | |||
| 9091 | #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9092 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9093 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9094 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9095 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9096 | #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9097 | |||
| 9098 | #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9099 | |||
| 9100 | /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ |
||
| 9101 | #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9102 | |||
| 9103 | #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9104 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */ |
||
| 9105 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9106 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9107 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9108 | #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9109 | |||
| 9110 | #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9111 | |||
| 9112 | /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ |
||
| 9113 | #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9114 | |||
| 9115 | #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9116 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9117 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9118 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9119 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9120 | #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9121 | |||
| 9122 | #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9123 | |||
| 9124 | /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ |
||
| 9125 | #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9126 | |||
| 9127 | #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9128 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9129 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9130 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9131 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9132 | #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9133 | |||
| 9134 | #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9135 | |||
| 9136 | /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ |
||
| 9137 | #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9138 | |||
| 9139 | #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9140 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9141 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9142 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9143 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9144 | #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9145 | |||
| 9146 | #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9147 | |||
| 9148 | /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ |
||
| 9149 | #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9150 | |||
| 9151 | #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9152 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9153 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9154 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9155 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9156 | #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9157 | |||
| 9158 | #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9159 | |||
| 9160 | /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ |
||
| 9161 | #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9162 | |||
| 9163 | #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9164 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9165 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9166 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9167 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9168 | #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9169 | |||
| 9170 | #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9171 | |||
| 9172 | /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ |
||
| 9173 | #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9174 | |||
| 9175 | #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9176 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9177 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9178 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9179 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9180 | #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9181 | |||
| 9182 | #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9183 | |||
| 9184 | /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ |
||
| 9185 | #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9186 | |||
| 9187 | #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9188 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9189 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9190 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9191 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9192 | #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9193 | |||
| 9194 | #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9195 | |||
| 9196 | /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ |
||
| 9197 | #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9198 | |||
| 9199 | #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9200 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9201 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9202 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9203 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9204 | #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9205 | |||
| 9206 | #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9207 | |||
| 9208 | /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ |
||
| 9209 | #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9210 | |||
| 9211 | #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9212 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9213 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9214 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9215 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9216 | #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9217 | |||
| 9218 | #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9219 | |||
| 9220 | /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ |
||
| 9221 | #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9222 | |||
| 9223 | #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9224 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9225 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9226 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9227 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9228 | #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9229 | |||
| 9230 | #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9231 | |||
| 9232 | /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ |
||
| 9233 | #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9234 | |||
| 9235 | #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9236 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9237 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9238 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9239 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9240 | #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9241 | |||
| 9242 | #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9243 | |||
| 9244 | /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ |
||
| 9245 | #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9246 | |||
| 9247 | #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9248 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9249 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9250 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9251 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9252 | #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9253 | |||
| 9254 | #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9255 | |||
| 9256 | /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ |
||
| 9257 | #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ |
||
| 9258 | |||
| 9259 | #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ |
||
| 9260 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ |
||
| 9261 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ |
||
| 9262 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ |
||
| 9263 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ |
||
| 9264 | #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ |
||
| 9265 | |||
| 9266 | #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ |
||
| 9267 | |||
| 9268 | /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ |
||
| 9269 | #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ |
||
| 9270 | |||
| 9271 | #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ |
||
| 9272 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ |
||
| 9273 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ |
||
| 9274 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ |
||
| 9275 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ |
||
| 9276 | #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ |
||
| 9277 | |||
| 9278 | #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ |
||
| 9279 | |||
| 9280 | /******************************************************************************/ |
||
| 9281 | /* */ |
||
| 9282 | /* Window WATCHDOG (WWDG) */ |
||
| 9283 | /* */ |
||
| 9284 | /******************************************************************************/ |
||
| 9285 | |||
| 9286 | /******************* Bit definition for WWDG_CR register ********************/ |
||
| 9287 | #define WWDG_CR_T_Pos (0U) |
||
| 9288 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
||
| 9289 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
||
| 9290 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
||
| 9291 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
||
| 9292 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
||
| 9293 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
||
| 9294 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
||
| 9295 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
||
| 9296 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
||
| 9297 | |||
| 9298 | /* Legacy defines */ |
||
| 9299 | #define WWDG_CR_T0 WWDG_CR_T_0 |
||
| 9300 | #define WWDG_CR_T1 WWDG_CR_T_1 |
||
| 9301 | #define WWDG_CR_T2 WWDG_CR_T_2 |
||
| 9302 | #define WWDG_CR_T3 WWDG_CR_T_3 |
||
| 9303 | #define WWDG_CR_T4 WWDG_CR_T_4 |
||
| 9304 | #define WWDG_CR_T5 WWDG_CR_T_5 |
||
| 9305 | #define WWDG_CR_T6 WWDG_CR_T_6 |
||
| 9306 | |||
| 9307 | #define WWDG_CR_WDGA_Pos (7U) |
||
| 9308 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
||
| 9309 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ |
||
| 9310 | |||
| 9311 | /******************* Bit definition for WWDG_CFR register *******************/ |
||
| 9312 | #define WWDG_CFR_W_Pos (0U) |
||
| 9313 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
||
| 9314 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ |
||
| 9315 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
||
| 9316 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
||
| 9317 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
||
| 9318 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
||
| 9319 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
||
| 9320 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
||
| 9321 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
||
| 9322 | |||
| 9323 | /* Legacy defines */ |
||
| 9324 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
||
| 9325 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
||
| 9326 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
||
| 9327 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
||
| 9328 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
||
| 9329 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
||
| 9330 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
||
| 9331 | |||
| 9332 | #define WWDG_CFR_WDGTB_Pos (7U) |
||
| 9333 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
||
| 9334 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ |
||
| 9335 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
||
| 9336 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
||
| 9337 | |||
| 9338 | /* Legacy defines */ |
||
| 9339 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
||
| 9340 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
||
| 9341 | |||
| 9342 | #define WWDG_CFR_EWI_Pos (9U) |
||
| 9343 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
||
| 9344 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ |
||
| 9345 | |||
| 9346 | /******************* Bit definition for WWDG_SR register ********************/ |
||
| 9347 | #define WWDG_SR_EWIF_Pos (0U) |
||
| 9348 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
||
| 9349 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ |
||
| 9350 | |||
| 9351 | /******************************************************************************/ |
||
| 9352 | /* */ |
||
| 9353 | /* SystemTick (SysTick) */ |
||
| 9354 | /* */ |
||
| 9355 | /******************************************************************************/ |
||
| 9356 | |||
| 9357 | /***************** Bit definition for SysTick_CTRL register *****************/ |
||
| 9358 | #define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ |
||
| 9359 | #define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ |
||
| 9360 | #define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ |
||
| 9361 | #define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ |
||
| 9362 | |||
| 9363 | /***************** Bit definition for SysTick_LOAD register *****************/ |
||
| 9364 | #define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ |
||
| 9365 | |||
| 9366 | /***************** Bit definition for SysTick_VAL register ******************/ |
||
| 9367 | #define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ |
||
| 9368 | |||
| 9369 | /***************** Bit definition for SysTick_CALIB register ****************/ |
||
| 9370 | #define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ |
||
| 9371 | #define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ |
||
| 9372 | #define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ |
||
| 9373 | |||
| 9374 | /******************************************************************************/ |
||
| 9375 | /* */ |
||
| 9376 | /* Nested Vectored Interrupt Controller (NVIC) */ |
||
| 9377 | /* */ |
||
| 9378 | /******************************************************************************/ |
||
| 9379 | |||
| 9380 | /****************** Bit definition for NVIC_ISER register *******************/ |
||
| 9381 | #define NVIC_ISER_SETENA_Pos (0U) |
||
| 9382 | #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ |
||
| 9383 | #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ |
||
| 9384 | #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ |
||
| 9385 | #define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ |
||
| 9386 | #define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ |
||
| 9387 | #define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ |
||
| 9388 | #define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ |
||
| 9389 | #define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ |
||
| 9390 | #define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ |
||
| 9391 | #define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ |
||
| 9392 | #define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ |
||
| 9393 | #define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ |
||
| 9394 | #define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ |
||
| 9395 | #define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ |
||
| 9396 | #define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ |
||
| 9397 | #define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ |
||
| 9398 | #define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ |
||
| 9399 | #define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ |
||
| 9400 | #define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ |
||
| 9401 | #define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ |
||
| 9402 | #define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ |
||
| 9403 | #define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ |
||
| 9404 | #define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ |
||
| 9405 | #define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ |
||
| 9406 | #define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ |
||
| 9407 | #define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ |
||
| 9408 | #define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ |
||
| 9409 | #define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ |
||
| 9410 | #define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ |
||
| 9411 | #define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ |
||
| 9412 | #define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ |
||
| 9413 | #define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ |
||
| 9414 | #define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ |
||
| 9415 | #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ |
||
| 9416 | |||
| 9417 | /****************** Bit definition for NVIC_ICER register *******************/ |
||
| 9418 | #define NVIC_ICER_CLRENA_Pos (0U) |
||
| 9419 | #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ |
||
| 9420 | #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ |
||
| 9421 | #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ |
||
| 9422 | #define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ |
||
| 9423 | #define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ |
||
| 9424 | #define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ |
||
| 9425 | #define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ |
||
| 9426 | #define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ |
||
| 9427 | #define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ |
||
| 9428 | #define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ |
||
| 9429 | #define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ |
||
| 9430 | #define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ |
||
| 9431 | #define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ |
||
| 9432 | #define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ |
||
| 9433 | #define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ |
||
| 9434 | #define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ |
||
| 9435 | #define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ |
||
| 9436 | #define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ |
||
| 9437 | #define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ |
||
| 9438 | #define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ |
||
| 9439 | #define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ |
||
| 9440 | #define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ |
||
| 9441 | #define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ |
||
| 9442 | #define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ |
||
| 9443 | #define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ |
||
| 9444 | #define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ |
||
| 9445 | #define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ |
||
| 9446 | #define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ |
||
| 9447 | #define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ |
||
| 9448 | #define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ |
||
| 9449 | #define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ |
||
| 9450 | #define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ |
||
| 9451 | #define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ |
||
| 9452 | #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ |
||
| 9453 | |||
| 9454 | /****************** Bit definition for NVIC_ISPR register *******************/ |
||
| 9455 | #define NVIC_ISPR_SETPEND_Pos (0U) |
||
| 9456 | #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ |
||
| 9457 | #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ |
||
| 9458 | #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ |
||
| 9459 | #define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ |
||
| 9460 | #define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ |
||
| 9461 | #define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ |
||
| 9462 | #define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ |
||
| 9463 | #define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ |
||
| 9464 | #define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ |
||
| 9465 | #define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ |
||
| 9466 | #define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ |
||
| 9467 | #define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ |
||
| 9468 | #define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ |
||
| 9469 | #define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ |
||
| 9470 | #define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ |
||
| 9471 | #define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ |
||
| 9472 | #define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ |
||
| 9473 | #define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ |
||
| 9474 | #define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ |
||
| 9475 | #define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ |
||
| 9476 | #define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ |
||
| 9477 | #define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ |
||
| 9478 | #define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ |
||
| 9479 | #define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ |
||
| 9480 | #define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ |
||
| 9481 | #define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ |
||
| 9482 | #define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ |
||
| 9483 | #define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ |
||
| 9484 | #define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ |
||
| 9485 | #define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ |
||
| 9486 | #define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ |
||
| 9487 | #define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ |
||
| 9488 | #define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ |
||
| 9489 | #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ |
||
| 9490 | |||
| 9491 | /****************** Bit definition for NVIC_ICPR register *******************/ |
||
| 9492 | #define NVIC_ICPR_CLRPEND_Pos (0U) |
||
| 9493 | #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ |
||
| 9494 | #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ |
||
| 9495 | #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ |
||
| 9496 | #define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ |
||
| 9497 | #define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ |
||
| 9498 | #define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ |
||
| 9499 | #define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ |
||
| 9500 | #define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ |
||
| 9501 | #define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ |
||
| 9502 | #define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ |
||
| 9503 | #define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ |
||
| 9504 | #define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ |
||
| 9505 | #define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ |
||
| 9506 | #define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ |
||
| 9507 | #define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ |
||
| 9508 | #define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ |
||
| 9509 | #define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ |
||
| 9510 | #define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ |
||
| 9511 | #define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ |
||
| 9512 | #define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ |
||
| 9513 | #define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ |
||
| 9514 | #define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ |
||
| 9515 | #define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ |
||
| 9516 | #define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ |
||
| 9517 | #define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ |
||
| 9518 | #define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ |
||
| 9519 | #define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ |
||
| 9520 | #define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ |
||
| 9521 | #define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ |
||
| 9522 | #define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ |
||
| 9523 | #define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ |
||
| 9524 | #define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ |
||
| 9525 | #define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ |
||
| 9526 | #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ |
||
| 9527 | |||
| 9528 | /****************** Bit definition for NVIC_IABR register *******************/ |
||
| 9529 | #define NVIC_IABR_ACTIVE_Pos (0U) |
||
| 9530 | #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ |
||
| 9531 | #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ |
||
| 9532 | #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ |
||
| 9533 | #define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ |
||
| 9534 | #define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ |
||
| 9535 | #define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ |
||
| 9536 | #define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ |
||
| 9537 | #define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ |
||
| 9538 | #define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ |
||
| 9539 | #define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ |
||
| 9540 | #define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ |
||
| 9541 | #define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ |
||
| 9542 | #define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ |
||
| 9543 | #define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ |
||
| 9544 | #define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ |
||
| 9545 | #define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ |
||
| 9546 | #define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ |
||
| 9547 | #define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ |
||
| 9548 | #define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ |
||
| 9549 | #define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ |
||
| 9550 | #define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ |
||
| 9551 | #define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ |
||
| 9552 | #define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ |
||
| 9553 | #define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ |
||
| 9554 | #define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ |
||
| 9555 | #define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ |
||
| 9556 | #define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ |
||
| 9557 | #define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ |
||
| 9558 | #define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ |
||
| 9559 | #define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ |
||
| 9560 | #define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ |
||
| 9561 | #define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ |
||
| 9562 | #define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ |
||
| 9563 | #define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ |
||
| 9564 | |||
| 9565 | /****************** Bit definition for NVIC_PRI0 register *******************/ |
||
| 9566 | #define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ |
||
| 9567 | #define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ |
||
| 9568 | #define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ |
||
| 9569 | #define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ |
||
| 9570 | |||
| 9571 | /****************** Bit definition for NVIC_PRI1 register *******************/ |
||
| 9572 | #define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ |
||
| 9573 | #define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ |
||
| 9574 | #define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ |
||
| 9575 | #define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ |
||
| 9576 | |||
| 9577 | /****************** Bit definition for NVIC_PRI2 register *******************/ |
||
| 9578 | #define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ |
||
| 9579 | #define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ |
||
| 9580 | #define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ |
||
| 9581 | #define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ |
||
| 9582 | |||
| 9583 | /****************** Bit definition for NVIC_PRI3 register *******************/ |
||
| 9584 | #define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ |
||
| 9585 | #define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ |
||
| 9586 | #define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ |
||
| 9587 | #define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ |
||
| 9588 | |||
| 9589 | /****************** Bit definition for NVIC_PRI4 register *******************/ |
||
| 9590 | #define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ |
||
| 9591 | #define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ |
||
| 9592 | #define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ |
||
| 9593 | #define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ |
||
| 9594 | |||
| 9595 | /****************** Bit definition for NVIC_PRI5 register *******************/ |
||
| 9596 | #define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ |
||
| 9597 | #define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ |
||
| 9598 | #define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ |
||
| 9599 | #define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ |
||
| 9600 | |||
| 9601 | /****************** Bit definition for NVIC_PRI6 register *******************/ |
||
| 9602 | #define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ |
||
| 9603 | #define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ |
||
| 9604 | #define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ |
||
| 9605 | #define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ |
||
| 9606 | |||
| 9607 | /****************** Bit definition for NVIC_PRI7 register *******************/ |
||
| 9608 | #define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ |
||
| 9609 | #define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ |
||
| 9610 | #define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ |
||
| 9611 | #define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ |
||
| 9612 | |||
| 9613 | /****************** Bit definition for SCB_CPUID register *******************/ |
||
| 9614 | #define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ |
||
| 9615 | #define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ |
||
| 9616 | #define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ |
||
| 9617 | #define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ |
||
| 9618 | #define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ |
||
| 9619 | |||
| 9620 | /******************* Bit definition for SCB_ICSR register *******************/ |
||
| 9621 | #define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ |
||
| 9622 | #define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ |
||
| 9623 | #define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ |
||
| 9624 | #define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ |
||
| 9625 | #define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ |
||
| 9626 | #define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ |
||
| 9627 | #define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ |
||
| 9628 | #define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ |
||
| 9629 | #define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ |
||
| 9630 | #define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ |
||
| 9631 | |||
| 9632 | /******************* Bit definition for SCB_VTOR register *******************/ |
||
| 9633 | #define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ |
||
| 9634 | #define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ |
||
| 9635 | |||
| 9636 | /*!<***************** Bit definition for SCB_AIRCR register *******************/ |
||
| 9637 | #define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ |
||
| 9638 | #define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ |
||
| 9639 | #define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ |
||
| 9640 | |||
| 9641 | #define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ |
||
| 9642 | #define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ |
||
| 9643 | #define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ |
||
| 9644 | #define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ |
||
| 9645 | |||
| 9646 | /* prority group configuration */ |
||
| 9647 | #define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ |
||
| 9648 | #define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ |
||
| 9649 | #define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ |
||
| 9650 | #define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ |
||
| 9651 | #define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ |
||
| 9652 | #define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ |
||
| 9653 | #define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ |
||
| 9654 | #define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ |
||
| 9655 | |||
| 9656 | #define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ |
||
| 9657 | #define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ |
||
| 9658 | |||
| 9659 | /******************* Bit definition for SCB_SCR register ********************/ |
||
| 9660 | #define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ |
||
| 9661 | #define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ |
||
| 9662 | #define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ |
||
| 9663 | |||
| 9664 | /******************** Bit definition for SCB_CCR register *******************/ |
||
| 9665 | #define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ |
||
| 9666 | #define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ |
||
| 9667 | #define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ |
||
| 9668 | #define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ |
||
| 9669 | #define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ |
||
| 9670 | #define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ |
||
| 9671 | |||
| 9672 | /******************* Bit definition for SCB_SHPR register ********************/ |
||
| 9673 | #define SCB_SHPR_PRI_N_Pos (0U) |
||
| 9674 | #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ |
||
| 9675 | #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ |
||
| 9676 | #define SCB_SHPR_PRI_N1_Pos (8U) |
||
| 9677 | #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ |
||
| 9678 | #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ |
||
| 9679 | #define SCB_SHPR_PRI_N2_Pos (16U) |
||
| 9680 | #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ |
||
| 9681 | #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ |
||
| 9682 | #define SCB_SHPR_PRI_N3_Pos (24U) |
||
| 9683 | #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ |
||
| 9684 | #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ |
||
| 9685 | |||
| 9686 | /****************** Bit definition for SCB_SHCSR register *******************/ |
||
| 9687 | #define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ |
||
| 9688 | #define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ |
||
| 9689 | #define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ |
||
| 9690 | #define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ |
||
| 9691 | #define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ |
||
| 9692 | #define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ |
||
| 9693 | #define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ |
||
| 9694 | #define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ |
||
| 9695 | #define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ |
||
| 9696 | #define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ |
||
| 9697 | #define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ |
||
| 9698 | #define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ |
||
| 9699 | #define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ |
||
| 9700 | #define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ |
||
| 9701 | |||
| 9702 | /******************* Bit definition for SCB_CFSR register *******************/ |
||
| 9703 | /*!< MFSR */ |
||
| 9704 | #define SCB_CFSR_IACCVIOL_Pos (0U) |
||
| 9705 | #define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */ |
||
| 9706 | #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ |
||
| 9707 | #define SCB_CFSR_DACCVIOL_Pos (1U) |
||
| 9708 | #define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */ |
||
| 9709 | #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ |
||
| 9710 | #define SCB_CFSR_MUNSTKERR_Pos (3U) |
||
| 9711 | #define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */ |
||
| 9712 | #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ |
||
| 9713 | #define SCB_CFSR_MSTKERR_Pos (4U) |
||
| 9714 | #define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */ |
||
| 9715 | #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ |
||
| 9716 | #define SCB_CFSR_MMARVALID_Pos (7U) |
||
| 9717 | #define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */ |
||
| 9718 | #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ |
||
| 9719 | /*!< BFSR */ |
||
| 9720 | #define SCB_CFSR_IBUSERR_Pos (8U) |
||
| 9721 | #define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */ |
||
| 9722 | #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ |
||
| 9723 | #define SCB_CFSR_PRECISERR_Pos (9U) |
||
| 9724 | #define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */ |
||
| 9725 | #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ |
||
| 9726 | #define SCB_CFSR_IMPRECISERR_Pos (10U) |
||
| 9727 | #define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */ |
||
| 9728 | #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ |
||
| 9729 | #define SCB_CFSR_UNSTKERR_Pos (11U) |
||
| 9730 | #define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */ |
||
| 9731 | #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ |
||
| 9732 | #define SCB_CFSR_STKERR_Pos (12U) |
||
| 9733 | #define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */ |
||
| 9734 | #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ |
||
| 9735 | #define SCB_CFSR_BFARVALID_Pos (15U) |
||
| 9736 | #define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */ |
||
| 9737 | #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ |
||
| 9738 | /*!< UFSR */ |
||
| 9739 | #define SCB_CFSR_UNDEFINSTR_Pos (16U) |
||
| 9740 | #define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */ |
||
| 9741 | #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ |
||
| 9742 | #define SCB_CFSR_INVSTATE_Pos (17U) |
||
| 9743 | #define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */ |
||
| 9744 | #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ |
||
| 9745 | #define SCB_CFSR_INVPC_Pos (18U) |
||
| 9746 | #define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */ |
||
| 9747 | #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ |
||
| 9748 | #define SCB_CFSR_NOCP_Pos (19U) |
||
| 9749 | #define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */ |
||
| 9750 | #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ |
||
| 9751 | #define SCB_CFSR_UNALIGNED_Pos (24U) |
||
| 9752 | #define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */ |
||
| 9753 | #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ |
||
| 9754 | #define SCB_CFSR_DIVBYZERO_Pos (25U) |
||
| 9755 | #define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */ |
||
| 9756 | #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ |
||
| 9757 | |||
| 9758 | /******************* Bit definition for SCB_HFSR register *******************/ |
||
| 9759 | #define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ |
||
| 9760 | #define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ |
||
| 9761 | #define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ |
||
| 9762 | |||
| 9763 | /******************* Bit definition for SCB_DFSR register *******************/ |
||
| 9764 | #define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ |
||
| 9765 | #define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ |
||
| 9766 | #define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ |
||
| 9767 | #define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ |
||
| 9768 | #define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ |
||
| 9769 | |||
| 9770 | /******************* Bit definition for SCB_MMFAR register ******************/ |
||
| 9771 | #define SCB_MMFAR_ADDRESS_Pos (0U) |
||
| 9772 | #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ |
||
| 9773 | #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ |
||
| 9774 | |||
| 9775 | /******************* Bit definition for SCB_BFAR register *******************/ |
||
| 9776 | #define SCB_BFAR_ADDRESS_Pos (0U) |
||
| 9777 | #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ |
||
| 9778 | #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ |
||
| 9779 | |||
| 9780 | /******************* Bit definition for SCB_afsr register *******************/ |
||
| 9781 | #define SCB_AFSR_IMPDEF_Pos (0U) |
||
| 9782 | #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ |
||
| 9783 | #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ |
||
| 9784 | /** |
||
| 9785 | * @} |
||
| 9786 | */ |
||
| 9787 | |||
| 9788 | /** |
||
| 9789 | * @} |
||
| 9790 | */ |
||
| 9791 | /** @addtogroup Exported_macro |
||
| 9792 | * @{ |
||
| 9793 | */ |
||
| 9794 | |||
| 9795 | /****************************** ADC Instances *********************************/ |
||
| 9796 | #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
||
| 9797 | |||
| 9798 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) |
||
| 9799 | |||
| 9800 | /****************************** AES Instances *********************************/ |
||
| 9801 | #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES) |
||
| 9802 | |||
| 9803 | /******************************** COMP Instances ******************************/ |
||
| 9804 | #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ |
||
| 9805 | ((INSTANCE) == COMP2)) |
||
| 9806 | |||
| 9807 | #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) |
||
| 9808 | |||
| 9809 | /****************************** CRC Instances *********************************/ |
||
| 9810 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
||
| 9811 | |||
| 9812 | /****************************** DAC Instances *********************************/ |
||
| 9813 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) |
||
| 9814 | |||
| 9815 | /****************************** DMA Instances *********************************/ |
||
| 9816 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
||
| 9817 | ((INSTANCE) == DMA1_Channel2) || \ |
||
| 9818 | ((INSTANCE) == DMA1_Channel3) || \ |
||
| 9819 | ((INSTANCE) == DMA1_Channel4) || \ |
||
| 9820 | ((INSTANCE) == DMA1_Channel5) || \ |
||
| 9821 | ((INSTANCE) == DMA1_Channel6) || \ |
||
| 9822 | ((INSTANCE) == DMA1_Channel7) || \ |
||
| 9823 | ((INSTANCE) == DMA2_Channel1) || \ |
||
| 9824 | ((INSTANCE) == DMA2_Channel2) || \ |
||
| 9825 | ((INSTANCE) == DMA2_Channel3) || \ |
||
| 9826 | ((INSTANCE) == DMA2_Channel4) || \ |
||
| 9827 | ((INSTANCE) == DMA2_Channel5)) |
||
| 9828 | |||
| 9829 | /******************************* GPIO Instances *******************************/ |
||
| 9830 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
||
| 9831 | ((INSTANCE) == GPIOB) || \ |
||
| 9832 | ((INSTANCE) == GPIOC) || \ |
||
| 9833 | ((INSTANCE) == GPIOD) || \ |
||
| 9834 | ((INSTANCE) == GPIOE) || \ |
||
| 9835 | ((INSTANCE) == GPIOF) || \ |
||
| 9836 | ((INSTANCE) == GPIOG) || \ |
||
| 9837 | ((INSTANCE) == GPIOH)) |
||
| 9838 | |||
| 9839 | /**************************** GPIO Alternate Function Instances ***************/ |
||
| 9840 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 9841 | |||
| 9842 | /**************************** GPIO Lock Instances *****************************/ |
||
| 9843 | /* On L1, all GPIO Bank support the Lock mechanism */ |
||
| 9844 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
||
| 9845 | |||
| 9846 | /******************************** I2C Instances *******************************/ |
||
| 9847 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
||
| 9848 | ((INSTANCE) == I2C2)) |
||
| 9849 | |||
| 9850 | /****************************** SMBUS Instances *******************************/ |
||
| 9851 | #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
||
| 9852 | |||
| 9853 | /******************************** I2S Instances *******************************/ |
||
| 9854 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
||
| 9855 | ((INSTANCE) == SPI3)) |
||
| 9856 | /****************************** IWDG Instances ********************************/ |
||
| 9857 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
||
| 9858 | |||
| 9859 | /****************************** OPAMP Instances *******************************/ |
||
| 9860 | #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ |
||
| 9861 | ((INSTANCE) == OPAMP2) || \ |
||
| 9862 | ((INSTANCE) == OPAMP3)) |
||
| 9863 | |||
| 9864 | #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP123_COMMON) |
||
| 9865 | |||
| 9866 | /****************************** RTC Instances *********************************/ |
||
| 9867 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
||
| 9868 | |||
| 9869 | /****************************** SDIO Instances *********************************/ |
||
| 9870 | #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) |
||
| 9871 | |||
| 9872 | /******************************** SPI Instances *******************************/ |
||
| 9873 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
||
| 9874 | ((INSTANCE) == SPI2) || \ |
||
| 9875 | ((INSTANCE) == SPI3)) |
||
| 9876 | |||
| 9877 | /****************************** TIM Instances *********************************/ |
||
| 9878 | #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9879 | ((INSTANCE) == TIM3) || \ |
||
| 9880 | ((INSTANCE) == TIM4) || \ |
||
| 9881 | ((INSTANCE) == TIM5) || \ |
||
| 9882 | ((INSTANCE) == TIM6) || \ |
||
| 9883 | ((INSTANCE) == TIM7) || \ |
||
| 9884 | ((INSTANCE) == TIM9) || \ |
||
| 9885 | ((INSTANCE) == TIM10) || \ |
||
| 9886 | ((INSTANCE) == TIM11)) |
||
| 9887 | |||
| 9888 | #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9889 | ((INSTANCE) == TIM3) || \ |
||
| 9890 | ((INSTANCE) == TIM4) || \ |
||
| 9891 | ((INSTANCE) == TIM5) || \ |
||
| 9892 | ((INSTANCE) == TIM9) || \ |
||
| 9893 | ((INSTANCE) == TIM10) || \ |
||
| 9894 | ((INSTANCE) == TIM11)) |
||
| 9895 | |||
| 9896 | #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9897 | ((INSTANCE) == TIM3) || \ |
||
| 9898 | ((INSTANCE) == TIM4) || \ |
||
| 9899 | ((INSTANCE) == TIM5) || \ |
||
| 9900 | ((INSTANCE) == TIM9)) |
||
| 9901 | |||
| 9902 | #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9903 | ((INSTANCE) == TIM3) || \ |
||
| 9904 | ((INSTANCE) == TIM4) || \ |
||
| 9905 | ((INSTANCE) == TIM5)) |
||
| 9906 | |||
| 9907 | #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9908 | ((INSTANCE) == TIM3) || \ |
||
| 9909 | ((INSTANCE) == TIM4) || \ |
||
| 9910 | ((INSTANCE) == TIM5)) |
||
| 9911 | |||
| 9912 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9913 | ((INSTANCE) == TIM3) || \ |
||
| 9914 | ((INSTANCE) == TIM4) || \ |
||
| 9915 | ((INSTANCE) == TIM5) || \ |
||
| 9916 | ((INSTANCE) == TIM9)) |
||
| 9917 | |||
| 9918 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9919 | ((INSTANCE) == TIM3) || \ |
||
| 9920 | ((INSTANCE) == TIM4) || \ |
||
| 9921 | ((INSTANCE) == TIM5) || \ |
||
| 9922 | ((INSTANCE) == TIM9) || \ |
||
| 9923 | ((INSTANCE) == TIM10) || \ |
||
| 9924 | ((INSTANCE) == TIM11)) |
||
| 9925 | |||
| 9926 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9927 | ((INSTANCE) == TIM3) || \ |
||
| 9928 | ((INSTANCE) == TIM4) || \ |
||
| 9929 | ((INSTANCE) == TIM5) || \ |
||
| 9930 | ((INSTANCE) == TIM9)) |
||
| 9931 | |||
| 9932 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9933 | ((INSTANCE) == TIM3) || \ |
||
| 9934 | ((INSTANCE) == TIM4) || \ |
||
| 9935 | ((INSTANCE) == TIM5) || \ |
||
| 9936 | ((INSTANCE) == TIM9)) |
||
| 9937 | |||
| 9938 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9939 | ((INSTANCE) == TIM3) || \ |
||
| 9940 | ((INSTANCE) == TIM4)) |
||
| 9941 | |||
| 9942 | #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9943 | ((INSTANCE) == TIM3) || \ |
||
| 9944 | ((INSTANCE) == TIM4) || \ |
||
| 9945 | ((INSTANCE) == TIM5)) |
||
| 9946 | |||
| 9947 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9948 | ((INSTANCE) == TIM3) || \ |
||
| 9949 | ((INSTANCE) == TIM4) || \ |
||
| 9950 | ((INSTANCE) == TIM5)) |
||
| 9951 | |||
| 9952 | |||
| 9953 | #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9954 | ((INSTANCE) == TIM3) || \ |
||
| 9955 | ((INSTANCE) == TIM4) || \ |
||
| 9956 | ((INSTANCE) == TIM5) || \ |
||
| 9957 | ((INSTANCE) == TIM6) || \ |
||
| 9958 | ((INSTANCE) == TIM7) || \ |
||
| 9959 | ((INSTANCE) == TIM9)) |
||
| 9960 | |||
| 9961 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9962 | ((INSTANCE) == TIM3) || \ |
||
| 9963 | ((INSTANCE) == TIM4) || \ |
||
| 9964 | ((INSTANCE) == TIM5) || \ |
||
| 9965 | ((INSTANCE) == TIM9)) |
||
| 9966 | |||
| 9967 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5) |
||
| 9968 | |||
| 9969 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 9970 | ((INSTANCE) == TIM3) || \ |
||
| 9971 | ((INSTANCE) == TIM4) || \ |
||
| 9972 | ((INSTANCE) == TIM5)) |
||
| 9973 | |||
| 9974 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
||
| 9975 | ((((INSTANCE) == TIM2) && \ |
||
| 9976 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 9977 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 9978 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 9979 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 9980 | || \ |
||
| 9981 | (((INSTANCE) == TIM3) && \ |
||
| 9982 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 9983 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 9984 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 9985 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 9986 | || \ |
||
| 9987 | (((INSTANCE) == TIM4) && \ |
||
| 9988 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 9989 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 9990 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 9991 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 9992 | || \ |
||
| 9993 | (((INSTANCE) == TIM5) && \ |
||
| 9994 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 9995 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
||
| 9996 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
||
| 9997 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
||
| 9998 | || \ |
||
| 9999 | (((INSTANCE) == TIM9) && \ |
||
| 10000 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
||
| 10001 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
||
| 10002 | || \ |
||
| 10003 | (((INSTANCE) == TIM10) && \ |
||
| 10004 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
||
| 10005 | || \ |
||
| 10006 | (((INSTANCE) == TIM11) && \ |
||
| 10007 | (((CHANNEL) == TIM_CHANNEL_1)))) |
||
| 10008 | |||
| 10009 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 10010 | ((INSTANCE) == TIM3) || \ |
||
| 10011 | ((INSTANCE) == TIM4) || \ |
||
| 10012 | ((INSTANCE) == TIM5) || \ |
||
| 10013 | ((INSTANCE) == TIM9) || \ |
||
| 10014 | ((INSTANCE) == TIM10) || \ |
||
| 10015 | ((INSTANCE) == TIM11)) |
||
| 10016 | |||
| 10017 | #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 10018 | ((INSTANCE) == TIM3) || \ |
||
| 10019 | ((INSTANCE) == TIM4) || \ |
||
| 10020 | ((INSTANCE) == TIM5) || \ |
||
| 10021 | ((INSTANCE) == TIM6) || \ |
||
| 10022 | ((INSTANCE) == TIM7)) |
||
| 10023 | |||
| 10024 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 10025 | ((INSTANCE) == TIM3) || \ |
||
| 10026 | ((INSTANCE) == TIM4) || \ |
||
| 10027 | ((INSTANCE) == TIM5)) |
||
| 10028 | |||
| 10029 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 10030 | ((INSTANCE) == TIM3) || \ |
||
| 10031 | ((INSTANCE) == TIM4) || \ |
||
| 10032 | ((INSTANCE) == TIM5) || \ |
||
| 10033 | ((INSTANCE) == TIM9)) |
||
| 10034 | |||
| 10035 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 10036 | ((INSTANCE) == TIM3) || \ |
||
| 10037 | ((INSTANCE) == TIM4) || \ |
||
| 10038 | ((INSTANCE) == TIM5) || \ |
||
| 10039 | ((INSTANCE) == TIM9)) |
||
| 10040 | |||
| 10041 | #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
||
| 10042 | ((INSTANCE) == TIM3) || \ |
||
| 10043 | ((INSTANCE) == TIM9) || \ |
||
| 10044 | ((INSTANCE) == TIM10) || \ |
||
| 10045 | ((INSTANCE) == TIM11)) |
||
| 10046 | |||
| 10047 | /******************** USART Instances : Synchronous mode **********************/ |
||
| 10048 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10049 | ((INSTANCE) == USART2) || \ |
||
| 10050 | ((INSTANCE) == USART3)) |
||
| 10051 | |||
| 10052 | /******************** UART Instances : Asynchronous mode **********************/ |
||
| 10053 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10054 | ((INSTANCE) == USART2) || \ |
||
| 10055 | ((INSTANCE) == USART3) || \ |
||
| 10056 | ((INSTANCE) == UART4) || \ |
||
| 10057 | ((INSTANCE) == UART5)) |
||
| 10058 | |||
| 10059 | /******************** UART Instances : Half-Duplex mode **********************/ |
||
| 10060 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10061 | ((INSTANCE) == USART2) || \ |
||
| 10062 | ((INSTANCE) == USART3) || \ |
||
| 10063 | ((INSTANCE) == UART4) || \ |
||
| 10064 | ((INSTANCE) == UART5)) |
||
| 10065 | |||
| 10066 | /******************** UART Instances : LIN mode **********************/ |
||
| 10067 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10068 | ((INSTANCE) == USART2) || \ |
||
| 10069 | ((INSTANCE) == USART3) || \ |
||
| 10070 | ((INSTANCE) == UART4) || \ |
||
| 10071 | ((INSTANCE) == UART5)) |
||
| 10072 | |||
| 10073 | /****************** UART Instances : Hardware Flow control ********************/ |
||
| 10074 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10075 | ((INSTANCE) == USART2) || \ |
||
| 10076 | ((INSTANCE) == USART3)) |
||
| 10077 | |||
| 10078 | /********************* UART Instances : Smard card mode ***********************/ |
||
| 10079 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10080 | ((INSTANCE) == USART2) || \ |
||
| 10081 | ((INSTANCE) == USART3)) |
||
| 10082 | |||
| 10083 | /*********************** UART Instances : IRDA mode ***************************/ |
||
| 10084 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10085 | ((INSTANCE) == USART2) || \ |
||
| 10086 | ((INSTANCE) == USART3) || \ |
||
| 10087 | ((INSTANCE) == UART4) || \ |
||
| 10088 | ((INSTANCE) == UART5)) |
||
| 10089 | |||
| 10090 | /***************** UART Instances : Multi-Processor mode **********************/ |
||
| 10091 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
||
| 10092 | ((INSTANCE) == USART2) || \ |
||
| 10093 | ((INSTANCE) == USART3) || \ |
||
| 10094 | ((INSTANCE) == UART4) || \ |
||
| 10095 | ((INSTANCE) == UART5)) |
||
| 10096 | |||
| 10097 | /****************************** WWDG Instances ********************************/ |
||
| 10098 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
||
| 10099 | |||
| 10100 | |||
| 10101 | /****************************** LCD Instances ********************************/ |
||
| 10102 | #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) |
||
| 10103 | |||
| 10104 | /****************************** USB Instances ********************************/ |
||
| 10105 | #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
||
| 10106 | |||
| 10107 | /** |
||
| 10108 | * @} |
||
| 10109 | */ |
||
| 10110 | |||
| 10111 | /******************************************************************************/ |
||
| 10112 | /* For a painless codes migration between the STM32L1xx device product */ |
||
| 10113 | /* lines, the aliases defined below are put in place to overcome the */ |
||
| 10114 | /* differences in the interrupt handlers and IRQn definitions. */ |
||
| 10115 | /* No need to update developed interrupt code when moving across */ |
||
| 10116 | /* product lines within the same STM32L1 Family */ |
||
| 10117 | /******************************************************************************/ |
||
| 10118 | |||
| 10119 | /* Aliases for __IRQn */ |
||
| 10120 | |||
| 10121 | /* Aliases for __IRQHandler */ |
||
| 10122 | |||
| 10123 | /** |
||
| 10124 | * @} |
||
| 10125 | */ |
||
| 10126 | |||
| 10127 | /** |
||
| 10128 | * @} |
||
| 10129 | */ |
||
| 10130 | |||
| 10131 | #ifdef __cplusplus |
||
| 10132 | } |
||
| 10133 | #endif /* __cplusplus */ |
||
| 10134 | |||
| 10135 | #endif /* __STM32L162xD_H */ |
||
| 10136 | |||
| 10137 | |||
| 10138 | |||
| 10139 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |