WebSVN – EngineBay2 – Blame – /trunk/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	******************************************************************************
		3	* @file stm32l151xdx.h
		4	* @author MCD Application Team
		5	* @version V2.2.0
		6	* @date 01-July-2016
		7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
		8	* This file contains all the peripheral register's definitions, bits
		9	* definitions and memory mapping for STM32L1xx devices.
		10	*
		11	* This file contains:
		12	* - Data structures and the address mapping for all peripherals
		13	* - Peripheral's registers declarations and bits definition
		14	* - Macros to access peripheral�s registers hardware
		15	*
		16	******************************************************************************
		17	* @attention
		18	*
		19	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
		20	*
		21	* Redistribution and use in source and binary forms, with or without modification,
		22	* are permitted provided that the following conditions are met:
		23	* 1. Redistributions of source code must retain the above copyright notice,
		24	* this list of conditions and the following disclaimer.
		25	* 2. Redistributions in binary form must reproduce the above copyright notice,
		26	* this list of conditions and the following disclaimer in the documentation
		27	* and/or other materials provided with the distribution.
		28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
		29	* may be used to endorse or promote products derived from this software
		30	* without specific prior written permission.
		31	*
		32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
		35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
		36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
		37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
		38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
		39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
		40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		42	*
		43	******************************************************************************
		44	*/
		45
		46	/** @addtogroup CMSIS
		47	* @{
		48	*/
		49
		50	/** @addtogroup stm32l151xdx
		51	* @{
		52	*/
		53
		54	#ifndef __STM32L151xDX_H
		55	#define __STM32L151xDX_H
		56
		57	#ifdef __cplusplus
		58	extern "C" {
		59	#endif
		60
		61
		62	/** @addtogroup Configuration_section_for_CMSIS
		63	* @{
		64	*/
		65	/**
		66	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
		67	*/
		68	#define __CM3_REV 0x200U /!< Cortex-M3 Revision r2p0 /
		69	#define __MPU_PRESENT 1U /!< STM32L1xx provides MPU /
		70	#define __NVIC_PRIO_BITS 4U /!< STM32L1xx uses 4 Bits for the Priority Levels /
		71	#define __Vendor_SysTickConfig 0U /!< Set to 1 if different SysTick Config is used /
		72
		73	/**
		74	* @}
		75	*/
		76
		77	/** @addtogroup Peripheral_interrupt_number_definition
		78	* @{
		79	*/
		80
		81	/**
		82	* @brief STM32L1xx Interrupt Number Definition, according to the selected device
		83	* in @ref Library_configuration_section
		84	*/
		85
		86	/!< Interrupt Number Definition /
		87	typedef enum
		88	{
		89	/**** Cortex-M3 Processor Exceptions Numbers ****************************************************/
		90	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
		91	HardFault_IRQn = -13, /!< 3 Cortex-M3 Hard Fault Interrupt /
		92	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
		93	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
		94	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
		95	SVC_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
		96	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
		97	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
		98	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
		99
		100	/**** STM32L specific Interrupt Numbers *********************************************************/
		101	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
		102	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
		103	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
		104	RTC_WKUP_IRQn = 3, /!< RTC Wakeup Timer through EXTI Line Interrupt /
		105	FLASH_IRQn = 4, /!< FLASH global Interrupt /
		106	RCC_IRQn = 5, /!< RCC global Interrupt /
		107	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
		108	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
		109	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
		110	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
		111	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
		112	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
		113	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
		114	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
		115	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
		116	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
		117	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
		118	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
		119	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
		120	USB_HP_IRQn = 19, /!< USB High Priority Interrupt /
		121	USB_LP_IRQn = 20, /!< USB Low Priority Interrupt /
		122	DAC_IRQn = 21, /!< DAC Interrupt /
		123	COMP_IRQn = 22, /!< Comparator through EXTI Line Interrupt /
		124	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
		125	TIM9_IRQn = 25, /!< TIM9 global Interrupt /
		126	TIM10_IRQn = 26, /!< TIM10 global Interrupt /
		127	TIM11_IRQn = 27, /!< TIM11 global Interrupt /
		128	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
		129	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
		130	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
		131	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
		132	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
		133	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
		134	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
		135	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
		136	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
		137	USART1_IRQn = 37, /!< USART1 global Interrupt /
		138	USART2_IRQn = 38, /!< USART2 global Interrupt /
		139	USART3_IRQn = 39, /!< USART3 global Interrupt /
		140	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
		141	RTC_Alarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
		142	USB_FS_WKUP_IRQn = 42, /!< USB FS WakeUp from suspend through EXTI Line Interrupt /
		143	TIM6_IRQn = 43, /!< TIM6 global Interrupt /
		144	TIM7_IRQn = 44, /!< TIM7 global Interrupt /
		145	TIM5_IRQn = 46, /!< TIM5 global Interrupt /
		146	SPI3_IRQn = 47, /!< SPI3 global Interrupt /
		147	UART4_IRQn = 48, /!< UART4 global Interrupt /
		148	UART5_IRQn = 49, /!< UART5 global Interrupt /
		149	DMA2_Channel1_IRQn = 50, /!< DMA2 Channel 1 global Interrupt /
		150	DMA2_Channel2_IRQn = 51, /!< DMA2 Channel 2 global Interrupt /
		151	DMA2_Channel3_IRQn = 52, /!< DMA2 Channel 3 global Interrupt /
		152	DMA2_Channel4_IRQn = 53, /!< DMA2 Channel 4 global Interrupt /
		153	DMA2_Channel5_IRQn = 54, /!< DMA2 Channel 5 global Interrupt /
		154	COMP_ACQ_IRQn = 56 /!< Comparator Channel Acquisition global Interrupt /
		155	} IRQn_Type;
		156
		157	/**
		158	* @}
		159	*/
		160
		161	#include "core_cm3.h"
		162	#include "system_stm32l1xx.h"
		163	#include <stdint.h>
		164
		165	/** @addtogroup Peripheral_registers_structures
		166	* @{
		167	*/
		168
		169	/**
		170	* @brief Analog to Digital Converter
		171	*/
		172
		173	typedef struct
		174	{
		175	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
		176	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
		177	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
		178	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
		179	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
		180	__IO uint32_t SMPR3; /!< ADC sample time register 3, Address offset: 0x14 /
		181	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x18 /
		182	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x1C /
		183	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x20 /
		184	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x24 /
		185	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x28 /
		186	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x2C /
		187	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
		188	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
		189	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
		190	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
		191	__IO uint32_t SQR5; /!< ADC regular sequence register 5, Address offset: 0x40 /
		192	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x44 /
		193	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x48 /
		194	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x4C /
		195	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x50 /
		196	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x54 /
		197	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x58 /
		198	__IO uint32_t SMPR0; /!< ADC sample time register 0, Address offset: 0x5C /
		199	} ADC_TypeDef;
		200
		201	typedef struct
		202	{
		203	__IO uint32_t CSR; /!< ADC common status register, Address offset: ADC1 base address + 0x300 /
		204	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
		205	} ADC_Common_TypeDef;
		206
		207	/**
		208	* @brief Comparator
		209	*/
		210
		211	typedef struct
		212	{
		213	__IO uint32_t CSR; /!< COMP control and status register, Address offset: 0x00 /
		214	} COMP_TypeDef;
		215
		216	typedef struct
		217	{
		218	__IO uint32_t CSR; /!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 /
		219	} COMP_Common_TypeDef;
		220
		221	/**
		222	* @brief CRC calculation unit
		223	*/
		224
		225	typedef struct
		226	{
		227	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
		228	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
		229	uint8_t RESERVED0; /!< Reserved, Address offset: 0x05 /
		230	uint16_t RESERVED1; /!< Reserved, Address offset: 0x06 /
		231	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
		232	} CRC_TypeDef;
		233
		234	/**
		235	* @brief Digital to Analog Converter
		236	*/
		237
		238	typedef struct
		239	{
		240	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
		241	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
		242	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
		243	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
		244	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
		245	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
		246	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
		247	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
		248	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
		249	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
		250	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
		251	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
		252	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
		253	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
		254	} DAC_TypeDef;
		255
		256	/**
		257	* @brief Debug MCU
		258	*/
		259
		260	typedef struct
		261	{
		262	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
		263	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
		264	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
		265	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
		266	}DBGMCU_TypeDef;
		267
		268	/**
		269	* @brief DMA Controller
		270	*/
		271
		272	typedef struct
		273	{
		274	__IO uint32_t CCR; /!< DMA channel x configuration register /
		275	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
		276	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
		277	__IO uint32_t CMAR; /!< DMA channel x memory address register /
		278	} DMA_Channel_TypeDef;
		279
		280	typedef struct
		281	{
		282	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
		283	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
		284	} DMA_TypeDef;
		285
		286	/**
		287	* @brief External Interrupt/Event Controller
		288	*/
		289
		290	typedef struct
		291	{
		292	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
		293	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
		294	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
		295	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
		296	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
		297	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
		298	} EXTI_TypeDef;
		299
		300	/**
		301	* @brief FLASH Registers
		302	*/
		303	typedef struct
		304	{
		305	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
		306	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
		307	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
		308	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
		309	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
		310	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
		311	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
		312	__IO uint32_t OBR; /!< Option byte register, Address offset: 0x1c /
		313	__IO uint32_t WRPR1; /!< Write protection register 1, Address offset: 0x20 /
		314	uint32_t RESERVED[23]; /!< Reserved, Address offset: 0x24 /
		315	__IO uint32_t WRPR2; /!< Write protection register 2, Address offset: 0x80 /
		316	__IO uint32_t WRPR3; /!< Write protection register 3, Address offset: 0x84 /
		317	__IO uint32_t WRPR4; /!< Write protection register 4, Address offset: 0x88 /
		318	} FLASH_TypeDef;
		319
		320	/**
		321	* @brief Option Bytes Registers
		322	*/
		323	typedef struct
		324	{
		325	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
		326	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
		327	__IO uint32_t WRP01; /!< write protection register 0 1, Address offset: 0x08 /
		328	__IO uint32_t WRP23; /!< write protection register 2 3, Address offset: 0x0C /
		329	__IO uint32_t WRP45; /!< write protection register 4 5, Address offset: 0x10 /
		330	__IO uint32_t WRP67; /!< write protection register 6 7, Address offset: 0x14 /
		331	__IO uint32_t WRP89; /!< write protection register 8 9, Address offset: 0x18 /
		332	__IO uint32_t WRP1011; /!< write protection register 10 11, Address offset: 0x1C /
		333	uint32_t RESERVED[24]; /!< Reserved, 0x20 -> 0x7C /
		334	__IO uint32_t WRP1213; /!< write protection register 12 13, Address offset: 0x80 /
		335	__IO uint32_t WRP1415; /!< write protection register 14 15, Address offset: 0x84 /
		336	} OB_TypeDef;
		337
		338	/**
		339	* @brief Operational Amplifier (OPAMP)
		340	*/
		341	typedef struct
		342	{
		343	__IO uint32_t CSR; /!< OPAMP control and status register, Address offset: 0x00 /
		344	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, Address offset: 0x04 /
		345	__IO uint32_t LPOTR; /!< OPAMP offset trimming register for low power mode, Address offset: 0x08 /
		346	} OPAMP_TypeDef;
		347
		348	typedef struct
		349	{
		350	__IO uint32_t CSR; /!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 /
		351	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 /
		352	} OPAMP_Common_TypeDef;
		353
		354	/**
		355	* @brief General Purpose IO
		356	*/
		357
		358	typedef struct
		359	{
		360	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
		361	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
		362	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
		363	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
		364	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
		365	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
		366	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
		367	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
		368	__IO uint32_t AFR[2]; /!< GPIO alternate function register, Address offset: 0x20-0x24 /
		369	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
		370	} GPIO_TypeDef;
		371
		372	/**
		373	* @brief SysTem Configuration
		374	*/
		375
		376	typedef struct
		377	{
		378	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
		379	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
		380	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
		381	} SYSCFG_TypeDef;
		382
		383	/**
		384	* @brief Inter-integrated Circuit Interface
		385	*/
		386
		387	typedef struct
		388	{
		389	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
		390	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
		391	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
		392	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
		393	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
		394	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
		395	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
		396	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
		397	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
		398	} I2C_TypeDef;
		399
		400	/**
		401	* @brief Independent WATCHDOG
		402	*/
		403
		404	typedef struct
		405	{
		406	__IO uint32_t KR; /!< Key register, Address offset: 0x00 /
		407	__IO uint32_t PR; /!< Prescaler register, Address offset: 0x04 /
		408	__IO uint32_t RLR; /!< Reload register, Address offset: 0x08 /
		409	__IO uint32_t SR; /!< Status register, Address offset: 0x0C /
		410	} IWDG_TypeDef;
		411
		412	/**
		413	* @brief Power Control
		414	*/
		415
		416	typedef struct
		417	{
		418	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
		419	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
		420	} PWR_TypeDef;
		421
		422	/**
		423	* @brief Reset and Clock Control
		424	*/
		425
		426	typedef struct
		427	{
		428	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
		429	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
		430	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x08 /
		431	__IO uint32_t CIR; /!< RCC Clock interrupt register, Address offset: 0x0C /
		432	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x10 /
		433	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x14 /
		434	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x18 /
		435	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x1C /
		436	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x20 /
		437	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x24 /
		438	__IO uint32_t AHBLPENR; /!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 /
		439	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C /
		440	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 /
		441	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x34 /
		442	} RCC_TypeDef;
		443
		444	/**
		445	* @brief Routing Interface
		446	*/
		447
		448	typedef struct
		449	{
		450	__IO uint32_t ICR; /!< RI input capture register, Address offset: 0x00 /
		451	__IO uint32_t ASCR1; /!< RI analog switches control register, Address offset: 0x04 /
		452	__IO uint32_t ASCR2; /!< RI analog switch control register 2, Address offset: 0x08 /
		453	__IO uint32_t HYSCR1; /!< RI hysteresis control register, Address offset: 0x0C /
		454	__IO uint32_t HYSCR2; /!< RI Hysteresis control register, Address offset: 0x10 /
		455	__IO uint32_t HYSCR3; /!< RI Hysteresis control register, Address offset: 0x14 /
		456	__IO uint32_t HYSCR4; /!< RI Hysteresis control register, Address offset: 0x18 /
		457	__IO uint32_t ASMR1; /!< RI Analog switch mode register 1, Address offset: 0x1C /
		458	__IO uint32_t CMR1; /!< RI Channel mask register 1, Address offset: 0x20 /
		459	__IO uint32_t CICR1; /!< RI Channel Iden for capture register 1, Address offset: 0x24 /
		460	__IO uint32_t ASMR2; /!< RI Analog switch mode register 2, Address offset: 0x28 /
		461	__IO uint32_t CMR2; /!< RI Channel mask register 2, Address offset: 0x2C /
		462	__IO uint32_t CICR2; /!< RI Channel Iden for capture register 2, Address offset: 0x30 /
		463	__IO uint32_t ASMR3; /!< RI Analog switch mode register 3, Address offset: 0x34 /
		464	__IO uint32_t CMR3; /!< RI Channel mask register 3, Address offset: 0x38 /
		465	__IO uint32_t CICR3; /!< RI Channel Iden for capture register 3, Address offset: 0x3C /
		466	__IO uint32_t ASMR4; /!< RI Analog switch mode register 4, Address offset: 0x40 /
		467	__IO uint32_t CMR4; /!< RI Channel mask register 4, Address offset: 0x44 /
		468	__IO uint32_t CICR4; /!< RI Channel Iden for capture register 4, Address offset: 0x48 /
		469	__IO uint32_t ASMR5; /!< RI Analog switch mode register 5, Address offset: 0x4C /
		470	__IO uint32_t CMR5; /!< RI Channel mask register 5, Address offset: 0x50 /
		471	__IO uint32_t CICR5; /!< RI Channel Iden for capture register 5, Address offset: 0x54 /
		472	} RI_TypeDef;
		473
		474	/**
		475	* @brief Real-Time Clock
		476	*/
		477	typedef struct
		478	{
		479	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
		480	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
		481	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
		482	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
		483	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
		484	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
		485	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
		486	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
		487	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
		488	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
		489	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
		490	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
		491	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
		492	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
		493	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
		494	__IO uint32_t CALR; /!< RRTC calibration register, Address offset: 0x3C /
		495	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
		496	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
		497	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
		498	uint32_t RESERVED7; /!< Reserved, 0x4C /
		499	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
		500	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
		501	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
		502	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
		503	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
		504	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
		505	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
		506	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
		507	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
		508	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
		509	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
		510	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
		511	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
		512	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
		513	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
		514	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
		515	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
		516	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
		517	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
		518	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
		519	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
		520	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
		521	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
		522	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
		523	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
		524	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
		525	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
		526	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
		527	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
		528	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
		529	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
		530	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
		531	} RTC_TypeDef;
		532
		533	/**
		534	* @brief Serial Peripheral Interface
		535	*/
		536
		537	typedef struct
		538	{
		539	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
		540	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
		541	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
		542	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
		543	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
		544	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
		545	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
		546	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
		547	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
		548	} SPI_TypeDef;
		549
		550	/**
		551	* @brief TIM
		552	*/
		553	typedef struct
		554	{
		555	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
		556	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
		557	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
		558	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
		559	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
		560	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
		561	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
		562	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
		563	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
		564	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
		565	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
		566	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
		567	uint32_t RESERVED12; /!< Reserved, 0x30 /
		568	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
		569	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
		570	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
		571	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
		572	uint32_t RESERVED17; /!< Reserved, 0x44 /
		573	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
		574	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
		575	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
		576	} TIM_TypeDef;
		577	/**
		578	* @brief Universal Synchronous Asynchronous Receiver Transmitter
		579	*/
		580
		581	typedef struct
		582	{
		583	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
		584	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
		585	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
		586	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
		587	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
		588	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
		589	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
		590	} USART_TypeDef;
		591
		592	/**
		593	* @brief Universal Serial Bus Full Speed Device
		594	*/
		595
		596	typedef struct
		597	{
		598	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
		599	__IO uint16_t RESERVED0; /!< Reserved /
		600	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
		601	__IO uint16_t RESERVED1; /!< Reserved /
		602	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
		603	__IO uint16_t RESERVED2; /!< Reserved /
		604	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
		605	__IO uint16_t RESERVED3; /!< Reserved /
		606	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
		607	__IO uint16_t RESERVED4; /!< Reserved /
		608	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
		609	__IO uint16_t RESERVED5; /!< Reserved /
		610	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
		611	__IO uint16_t RESERVED6; /!< Reserved /
		612	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
		613	__IO uint16_t RESERVED7[17]; /!< Reserved /
		614	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
		615	__IO uint16_t RESERVED8; /!< Reserved /
		616	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
		617	__IO uint16_t RESERVED9; /!< Reserved /
		618	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
		619	__IO uint16_t RESERVEDA; /!< Reserved /
		620	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
		621	__IO uint16_t RESERVEDB; /!< Reserved /
		622	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
		623	__IO uint16_t RESERVEDC; /!< Reserved /
		624	} USB_TypeDef;
		625
		626	/**
		627	* @brief Window WATCHDOG
		628	*/
		629	typedef struct
		630	{
		631	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
		632	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
		633	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
		634	} WWDG_TypeDef;
		635
		636	/**
		637	* @brief Universal Serial Bus Full Speed Device
		638	*/
		639	/**
		640	* @}
		641	*/
		642
		643	/** @addtogroup Peripheral_memory_map
		644	* @{
		645	*/
		646
		647	#define FLASH_BASE ((uint32_t)0x08000000U) /!< FLASH base address in the alias region /
		648	#define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /!< FLASH EEPROM base address in the alias region /
		649	#define SRAM_BASE ((uint32_t)0x20000000U) /!< SRAM base address in the alias region /
		650	#define PERIPH_BASE ((uint32_t)0x40000000U) /!< Peripheral base address in the alias region /
		651	#define SRAM_BB_BASE ((uint32_t)0x22000000U) /!< SRAM base address in the bit-band region /
		652	#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /!< Peripheral base address in the bit-band region /
		653	#define FLASH_BANK2_BASE ((uint32_t)0x08040000U) /!< FLASH BANK2 base address in the alias region /
		654	#define FLASH_BANK1_END ((uint32_t)0x0802FFFFU) /!< Program end FLASH BANK1 address /
		655	#define FLASH_BANK2_END ((uint32_t)0x0806FFFFU) /!< Program end FLASH BANK2 address /
		656	#define FLASH_EEPROM_END ((uint32_t)0x08083FFFU) /!< FLASH EEPROM end address (16KB) /
		657
		658	/!< Peripheral memory map /
		659	#define APB1PERIPH_BASE PERIPH_BASE
		660	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
		661	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
		662
		663	/!< APB1 peripherals /
		664	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
		665	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
		666	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
		667	#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
		668	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
		669	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
		670	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
		671	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
		672	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
		673	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
		674	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
		675	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
		676	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
		677	#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
		678	#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
		679	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
		680	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
		681
		682	/* USB device FS */
		683	#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /!< USB_IP Peripheral Registers base address /
		684	#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /!< USB_IP Packet Memory Area base address /
		685
		686	/* USB device FS SRAM */
		687	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
		688	#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
		689	#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
		690	#define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
		691	#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)
		692
		693	/!< APB2 peripherals /
		694	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
		695	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
		696	#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U)
		697	#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U)
		698	#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U)
		699	#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
		700	#define ADC_BASE (APB2PERIPH_BASE + 0x00002700U)
		701	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
		702	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
		703
		704	/!< AHB peripherals /
		705	#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U)
		706	#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U)
		707	#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U)
		708	#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U)
		709	#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U)
		710	#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U)
		711	#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U)
		712	#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U)
		713	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
		714	#define RCC_BASE (AHBPERIPH_BASE + 0x00003800U)
		715	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /!< FLASH registers base address /
		716	#define OB_BASE ((uint32_t)0x1FF80000U) /!< FLASH Option Bytes base address /
		717	#define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices /
		718	#define UID_BASE ((uint32_t)0x1FF800D0U) /!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices /
		719	#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U)
		720	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
		721	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
		722	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
		723	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
		724	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
		725	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
		726	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
		727	#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U)
		728	#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U)
		729	#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU)
		730	#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U)
		731	#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U)
		732	#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U)
		733	#define DBGMCU_BASE ((uint32_t)0xE0042000U) /!< Debug MCU registers base address /
		734
		735	/**
		736	* @}
		737	*/
		738
		739	/** @addtogroup Peripheral_declaration
		740	* @{
		741	*/
		742
		743	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
		744	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
		745	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
		746	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
		747	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
		748	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
		749	#define RTC ((RTC_TypeDef *) RTC_BASE)
		750	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
		751	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
		752	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
		753	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
		754	#define USART2 ((USART_TypeDef *) USART2_BASE)
		755	#define USART3 ((USART_TypeDef *) USART3_BASE)
		756	#define UART4 ((USART_TypeDef *) UART4_BASE)
		757	#define UART5 ((USART_TypeDef *) UART5_BASE)
		758	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
		759	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
		760	/* USB device FS */
		761	#define USB ((USB_TypeDef *) USB_BASE)
		762	/* USB device FS SRAM */
		763	#define PWR ((PWR_TypeDef *) PWR_BASE)
		764
		765	#define DAC1 ((DAC_TypeDef *) DAC_BASE)
		766	/* Legacy define */
		767	#define DAC DAC1
		768
		769	#define COMP ((COMP_TypeDef ) COMP_BASE) / COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
		770	#define COMP1 ((COMP_TypeDef ) COMP_BASE) / COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
		771	#define COMP2 ((COMP_TypeDef ) (COMP_BASE + 0x00000001U)) / COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
		772	#define COMP12_COMMON ((COMP_Common_TypeDef ) COMP_BASE) / COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
		773
		774	#define RI ((RI_TypeDef *) RI_BASE)
		775
		776	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
		777	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
		778	#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
		779	#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE)
		780	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
		781	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
		782	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
		783	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
		784	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
		785
		786	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
		787	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
		788	/* Legacy defines */
		789	#define ADC ADC1_COMMON
		790
		791	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
		792	#define USART1 ((USART_TypeDef *) USART1_BASE)
		793	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
		794	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
		795	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
		796	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
		797	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
		798	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
		799	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
		800	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
		801	#define CRC ((CRC_TypeDef *) CRC_BASE)
		802	#define RCC ((RCC_TypeDef *) RCC_BASE)
		803	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
		804	#define OB ((OB_TypeDef *) OB_BASE)
		805	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
		806	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
		807	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
		808	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
		809	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
		810	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
		811	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
		812	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
		813	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
		814	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
		815	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
		816	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
		817	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
		818	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
		819	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
		820
		821	/**
		822	* @}
		823	*/
		824
		825	/** @addtogroup Exported_constants
		826	* @{
		827	*/
		828
		829	/** @addtogroup Peripheral_Registers_Bits_Definition
		830	* @{
		831	*/
		832
		833	/******************************************************************************/
		834	/* Peripheral Registers Bits Definition */
		835	/******************************************************************************/
		836	/******************************************************************************/
		837	/* */
		838	/* Analog to Digital Converter (ADC) */
		839	/* */
		840	/******************************************************************************/
		841
		842	/****************** Bit definition for ADC_SR register ******************/
		843	#define ADC_SR_AWD_Pos (0U)
		844	#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /!< 0x00000001 /
		845	#define ADC_SR_AWD ADC_SR_AWD_Msk /!< ADC analog watchdog 1 flag /
		846	#define ADC_SR_EOCS_Pos (1U)
		847	#define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /!< 0x00000002 /
		848	#define ADC_SR_EOCS ADC_SR_EOCS_Msk /!< ADC group regular end of unitary conversion or end of sequence conversions flag /
		849	#define ADC_SR_JEOS_Pos (2U)
		850	#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /!< 0x00000004 /
		851	#define ADC_SR_JEOS ADC_SR_JEOS_Msk /!< ADC group injected end of sequence conversions flag /
		852	#define ADC_SR_JSTRT_Pos (3U)
		853	#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /!< 0x00000008 /
		854	#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /!< ADC group injected conversion start flag /
		855	#define ADC_SR_STRT_Pos (4U)
		856	#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /!< 0x00000010 /
		857	#define ADC_SR_STRT ADC_SR_STRT_Msk /!< ADC group regular conversion start flag /
		858	#define ADC_SR_OVR_Pos (5U)
		859	#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /!< 0x00000020 /
		860	#define ADC_SR_OVR ADC_SR_OVR_Msk /!< ADC group regular overrun flag /
		861	#define ADC_SR_ADONS_Pos (6U)
		862	#define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /!< 0x00000040 /
		863	#define ADC_SR_ADONS ADC_SR_ADONS_Msk /!< ADC ready flag /
		864	#define ADC_SR_RCNR_Pos (8U)
		865	#define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /!< 0x00000100 /
		866	#define ADC_SR_RCNR ADC_SR_RCNR_Msk /!< ADC group regular not ready flag /
		867	#define ADC_SR_JCNR_Pos (9U)
		868	#define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /!< 0x00000200 /
		869	#define ADC_SR_JCNR ADC_SR_JCNR_Msk /!< ADC group injected not ready flag /
		870
		871	/* Legacy defines */
		872	#define ADC_SR_EOC (ADC_SR_EOCS)
		873	#define ADC_SR_JEOC (ADC_SR_JEOS)
		874
		875	/***************** Bit definition for ADC_CR1 register ******************/
		876	#define ADC_CR1_AWDCH_Pos (0U)
		877	#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /!< 0x0000001F /
		878	#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /!< ADC analog watchdog 1 monitored channel selection /
		879	#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /!< 0x00000001 /
		880	#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /!< 0x00000002 /
		881	#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /!< 0x00000004 /
		882	#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /!< 0x00000008 /
		883	#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /!< 0x00000010 /
		884
		885	#define ADC_CR1_EOCSIE_Pos (5U)
		886	#define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /!< 0x00000020 /
		887	#define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /!< ADC group regular end of unitary conversion or end of sequence conversions interrupt /
		888	#define ADC_CR1_AWDIE_Pos (6U)
		889	#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /!< 0x00000040 /
		890	#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /!< ADC analog watchdog 1 interrupt /
		891	#define ADC_CR1_JEOSIE_Pos (7U)
		892	#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /!< 0x00000080 /
		893	#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /!< ADC group injected end of sequence conversions interrupt /
		894	#define ADC_CR1_SCAN_Pos (8U)
		895	#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /!< 0x00000100 /
		896	#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /!< ADC scan mode /
		897	#define ADC_CR1_AWDSGL_Pos (9U)
		898	#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /!< 0x00000200 /
		899	#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /!< ADC analog watchdog 1 monitoring a single channel or all channels /
		900	#define ADC_CR1_JAUTO_Pos (10U)
		901	#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /!< 0x00000400 /
		902	#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /!< ADC group injected automatic trigger mode /
		903	#define ADC_CR1_DISCEN_Pos (11U)
		904	#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /!< 0x00000800 /
		905	#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /
		906	#define ADC_CR1_JDISCEN_Pos (12U)
		907	#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /!< 0x00001000 /
		908	#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /!< ADC group injected sequencer discontinuous mode /
		909
		910	#define ADC_CR1_DISCNUM_Pos (13U)
		911	#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /!< 0x0000E000 /
		912	#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /!< ADC group regular sequencer discontinuous number of ranks /
		913	#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /!< 0x00002000 /
		914	#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /!< 0x00004000 /
		915	#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /!< 0x00008000 /
		916
		917	#define ADC_CR1_PDD_Pos (16U)
		918	#define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /!< 0x00010000 /
		919	#define ADC_CR1_PDD ADC_CR1_PDD_Msk /!< ADC power down during auto delay phase /
		920	#define ADC_CR1_PDI_Pos (17U)
		921	#define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /!< 0x00020000 /
		922	#define ADC_CR1_PDI ADC_CR1_PDI_Msk /!< ADC power down during idle phase /
		923
		924	#define ADC_CR1_JAWDEN_Pos (22U)
		925	#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /!< 0x00400000 /
		926	#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group injected /
		927	#define ADC_CR1_AWDEN_Pos (23U)
		928	#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /!< 0x00800000 /
		929	#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /!< ADC analog watchdog 1 enable on scope ADC group regular /
		930
		931	#define ADC_CR1_RES_Pos (24U)
		932	#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /!< 0x03000000 /
		933	#define ADC_CR1_RES ADC_CR1_RES_Msk /!< ADC resolution /
		934	#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /!< 0x01000000 /
		935	#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /!< 0x02000000 /
		936
		937	#define ADC_CR1_OVRIE_Pos (26U)
		938	#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /!< 0x04000000 /
		939	#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /!< ADC group regular overrun interrupt /
		940
		941	/* Legacy defines */
		942	#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
		943	#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
		944
		945	/***************** Bit definition for ADC_CR2 register ******************/
		946	#define ADC_CR2_ADON_Pos (0U)
		947	#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /!< 0x00000001 /
		948	#define ADC_CR2_ADON ADC_CR2_ADON_Msk /!< ADC enable /
		949	#define ADC_CR2_CONT_Pos (1U)
		950	#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /!< 0x00000002 /
		951	#define ADC_CR2_CONT ADC_CR2_CONT_Msk /!< ADC group regular continuous conversion mode /
		952	#define ADC_CR2_CFG_Pos (2U)
		953	#define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /!< 0x00000004 /
		954	#define ADC_CR2_CFG ADC_CR2_CFG_Msk /!< ADC channels bank selection /
		955
		956	#define ADC_CR2_DELS_Pos (4U)
		957	#define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /!< 0x00000070 /
		958	#define ADC_CR2_DELS ADC_CR2_DELS_Msk /!< ADC auto delay selection /
		959	#define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /!< 0x00000010 /
		960	#define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /!< 0x00000020 /
		961	#define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /!< 0x00000040 /
		962
		963	#define ADC_CR2_DMA_Pos (8U)
		964	#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /!< 0x00000100 /
		965	#define ADC_CR2_DMA ADC_CR2_DMA_Msk /!< ADC DMA transfer enable /
		966	#define ADC_CR2_DDS_Pos (9U)
		967	#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /!< 0x00000200 /
		968	#define ADC_CR2_DDS ADC_CR2_DDS_Msk /!< ADC DMA transfer configuration /
		969	#define ADC_CR2_EOCS_Pos (10U)
		970	#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /!< 0x00000400 /
		971	#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /!< ADC end of unitary or end of sequence conversions selection /
		972	#define ADC_CR2_ALIGN_Pos (11U)
		973	#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /!< 0x00000800 /
		974	#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /!< ADC data alignement /
		975
		976	#define ADC_CR2_JEXTSEL_Pos (16U)
		977	#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /!< 0x000F0000 /
		978	#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /!< ADC group injected external trigger source /
		979	#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /!< 0x00010000 /
		980	#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /!< 0x00020000 /
		981	#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /!< 0x00040000 /
		982	#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /!< 0x00080000 /
		983
		984	#define ADC_CR2_JEXTEN_Pos (20U)
		985	#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /!< 0x00300000 /
		986	#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /!< ADC group injected external trigger polarity /
		987	#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /!< 0x00100000 /
		988	#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /!< 0x00200000 /
		989
		990	#define ADC_CR2_JSWSTART_Pos (22U)
		991	#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /!< 0x00400000 /
		992	#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /!< ADC group injected conversion start /
		993
		994	#define ADC_CR2_EXTSEL_Pos (24U)
		995	#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /!< 0x0F000000 /
		996	#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /!< ADC group regular external trigger source /
		997	#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /!< 0x01000000 /
		998	#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /!< 0x02000000 /
		999	#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /!< 0x04000000 /
		1000	#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /!< 0x08000000 /
		1001
		1002	#define ADC_CR2_EXTEN_Pos (28U)
		1003	#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /!< 0x30000000 /
		1004	#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /!< ADC group regular external trigger polarity /
		1005	#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /!< 0x10000000 /
		1006	#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /!< 0x20000000 /
		1007
		1008	#define ADC_CR2_SWSTART_Pos (30U)
		1009	#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /!< 0x40000000 /
		1010	#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /!< ADC group regular conversion start /
		1011
		1012	/**************** Bit definition for ADC_SMPR1 register *****************/
		1013	#define ADC_SMPR1_SMP20_Pos (0U)
		1014	#define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /!< 0x00000007 /
		1015	#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /!< ADC channel 20 sampling time selection /
		1016	#define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /!< 0x00000001 /
		1017	#define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /!< 0x00000002 /
		1018	#define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /!< 0x00000004 /
		1019
		1020	#define ADC_SMPR1_SMP21_Pos (3U)
		1021	#define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /!< 0x00000038 /
		1022	#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /!< ADC channel 21 sampling time selection /
		1023	#define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /!< 0x00000008 /
		1024	#define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /!< 0x00000010 /
		1025	#define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /!< 0x00000020 /
		1026
		1027	#define ADC_SMPR1_SMP22_Pos (6U)
		1028	#define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /!< 0x000001C0 /
		1029	#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /!< ADC channel 22 sampling time selection /
		1030	#define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /!< 0x00000040 /
		1031	#define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /!< 0x00000080 /
		1032	#define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /!< 0x00000100 /
		1033
		1034	#define ADC_SMPR1_SMP23_Pos (9U)
		1035	#define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /!< 0x00000E00 /
		1036	#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /!< ADC channel 23 sampling time selection /
		1037	#define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /!< 0x00000200 /
		1038	#define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /!< 0x00000400 /
		1039	#define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /!< 0x00000800 /
		1040
		1041	#define ADC_SMPR1_SMP24_Pos (12U)
		1042	#define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /!< 0x00007000 /
		1043	#define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /!< ADC channel 24 sampling time selection /
		1044	#define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /!< 0x00001000 /
		1045	#define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /!< 0x00002000 /
		1046	#define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /!< 0x00004000 /
		1047
		1048	#define ADC_SMPR1_SMP25_Pos (15U)
		1049	#define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /!< 0x00038000 /
		1050	#define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /!< ADC channel 25 sampling time selection /
		1051	#define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /!< 0x00008000 /
		1052	#define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /!< 0x00010000 /
		1053	#define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /!< 0x00020000 /
		1054
		1055	#define ADC_SMPR1_SMP26_Pos (18U)
		1056	#define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /!< 0x001C0000 /
		1057	#define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /!< ADC channel 26 sampling time selection /
		1058	#define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /!< 0x00040000 /
		1059	#define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /!< 0x00080000 /
		1060	#define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /!< 0x00100000 /
		1061
		1062	#define ADC_SMPR1_SMP27_Pos (21U)
		1063	#define ADC_SMPR1_SMP27_Msk (0x7U << ADC_SMPR1_SMP27_Pos) /!< 0x00E00000 /
		1064	#define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /!< ADC channel 27 sampling time selection /
		1065	#define ADC_SMPR1_SMP27_0 (0x1U << ADC_SMPR1_SMP27_Pos) /!< 0x00200000 /
		1066	#define ADC_SMPR1_SMP27_1 (0x2U << ADC_SMPR1_SMP27_Pos) /!< 0x00400000 /
		1067	#define ADC_SMPR1_SMP27_2 (0x4U << ADC_SMPR1_SMP27_Pos) /!< 0x00800000 /
		1068
		1069	#define ADC_SMPR1_SMP28_Pos (24U)
		1070	#define ADC_SMPR1_SMP28_Msk (0x7U << ADC_SMPR1_SMP28_Pos) /!< 0x07000000 /
		1071	#define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /!< ADC channel 28 sampling time selection /
		1072	#define ADC_SMPR1_SMP28_0 (0x1U << ADC_SMPR1_SMP28_Pos) /!< 0x01000000 /
		1073	#define ADC_SMPR1_SMP28_1 (0x2U << ADC_SMPR1_SMP28_Pos) /!< 0x02000000 /
		1074	#define ADC_SMPR1_SMP28_2 (0x4U << ADC_SMPR1_SMP28_Pos) /!< 0x04000000 /
		1075
		1076	#define ADC_SMPR1_SMP29_Pos (27U)
		1077	#define ADC_SMPR1_SMP29_Msk (0x7U << ADC_SMPR1_SMP29_Pos) /!< 0x38000000 /
		1078	#define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /!< ADC channel 29 sampling time selection /
		1079	#define ADC_SMPR1_SMP29_0 (0x1U << ADC_SMPR1_SMP29_Pos) /!< 0x08000000 /
		1080	#define ADC_SMPR1_SMP29_1 (0x2U << ADC_SMPR1_SMP29_Pos) /!< 0x10000000 /
		1081	#define ADC_SMPR1_SMP29_2 (0x4U << ADC_SMPR1_SMP29_Pos) /!< 0x20000000 /
		1082
		1083	/**************** Bit definition for ADC_SMPR2 register *****************/
		1084	#define ADC_SMPR2_SMP10_Pos (0U)
		1085	#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /!< 0x00000007 /
		1086	#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /!< ADC channel 10 sampling time selection /
		1087	#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /!< 0x00000001 /
		1088	#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /!< 0x00000002 /
		1089	#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /!< 0x00000004 /
		1090
		1091	#define ADC_SMPR2_SMP11_Pos (3U)
		1092	#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /!< 0x00000038 /
		1093	#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /!< ADC channel 11 sampling time selection /
		1094	#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /!< 0x00000008 /
		1095	#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /!< 0x00000010 /
		1096	#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /!< 0x00000020 /
		1097
		1098	#define ADC_SMPR2_SMP12_Pos (6U)
		1099	#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /!< 0x000001C0 /
		1100	#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /!< ADC channel 12 sampling time selection /
		1101	#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /!< 0x00000040 /
		1102	#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /!< 0x00000080 /
		1103	#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /!< 0x00000100 /
		1104
		1105	#define ADC_SMPR2_SMP13_Pos (9U)
		1106	#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /!< 0x00000E00 /
		1107	#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /!< ADC channel 13 sampling time selection /
		1108	#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /!< 0x00000200 /
		1109	#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /!< 0x00000400 /
		1110	#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /!< 0x00000800 /
		1111
		1112	#define ADC_SMPR2_SMP14_Pos (12U)
		1113	#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /!< 0x00007000 /
		1114	#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /!< ADC channel 14 sampling time selection /
		1115	#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /!< 0x00001000 /
		1116	#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /!< 0x00002000 /
		1117	#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /!< 0x00004000 /
		1118
		1119	#define ADC_SMPR2_SMP15_Pos (15U)
		1120	#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /!< 0x00038000 /
		1121	#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /!< ADC channel 5 sampling time selection /
		1122	#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /!< 0x00008000 /
		1123	#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /!< 0x00010000 /
		1124	#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /!< 0x00020000 /
		1125
		1126	#define ADC_SMPR2_SMP16_Pos (18U)
		1127	#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /!< 0x001C0000 /
		1128	#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /!< ADC channel 16 sampling time selection /
		1129	#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /!< 0x00040000 /
		1130	#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /!< 0x00080000 /
		1131	#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /!< 0x00100000 /
		1132
		1133	#define ADC_SMPR2_SMP17_Pos (21U)
		1134	#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /!< 0x00E00000 /
		1135	#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /!< ADC channel 17 sampling time selection /
		1136	#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /!< 0x00200000 /
		1137	#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /!< 0x00400000 /
		1138	#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /!< 0x00800000 /
		1139
		1140	#define ADC_SMPR2_SMP18_Pos (24U)
		1141	#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /!< 0x07000000 /
		1142	#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /!< ADC channel 18 sampling time selection /
		1143	#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /!< 0x01000000 /
		1144	#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /!< 0x02000000 /
		1145	#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /!< 0x04000000 /
		1146
		1147	#define ADC_SMPR2_SMP19_Pos (27U)
		1148	#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /!< 0x38000000 /
		1149	#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /!< ADC channel 19 sampling time selection /
		1150	#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /!< 0x08000000 /
		1151	#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /!< 0x10000000 /
		1152	#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /!< 0x20000000 /
		1153
		1154	/**************** Bit definition for ADC_SMPR3 register *****************/
		1155	#define ADC_SMPR3_SMP0_Pos (0U)
		1156	#define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /!< 0x00000007 /
		1157	#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /!< ADC channel 0 sampling time selection /
		1158	#define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /!< 0x00000001 /
		1159	#define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /!< 0x00000002 /
		1160	#define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /!< 0x00000004 /
		1161
		1162	#define ADC_SMPR3_SMP1_Pos (3U)
		1163	#define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /!< 0x00000038 /
		1164	#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /!< ADC channel 1 sampling time selection /
		1165	#define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /!< 0x00000008 /
		1166	#define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /!< 0x00000010 /
		1167	#define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /!< 0x00000020 /
		1168
		1169	#define ADC_SMPR3_SMP2_Pos (6U)
		1170	#define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /!< 0x000001C0 /
		1171	#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /!< ADC channel 2 sampling time selection /
		1172	#define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /!< 0x00000040 /
		1173	#define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /!< 0x00000080 /
		1174	#define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /!< 0x00000100 /
		1175
		1176	#define ADC_SMPR3_SMP3_Pos (9U)
		1177	#define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /!< 0x00000E00 /
		1178	#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /!< ADC channel 3 sampling time selection /
		1179	#define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /!< 0x00000200 /
		1180	#define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /!< 0x00000400 /
		1181	#define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /!< 0x00000800 /
		1182
		1183	#define ADC_SMPR3_SMP4_Pos (12U)
		1184	#define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /!< 0x00007000 /
		1185	#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /!< ADC channel 4 sampling time selection /
		1186	#define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /!< 0x00001000 /
		1187	#define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /!< 0x00002000 /
		1188	#define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /!< 0x00004000 /
		1189
		1190	#define ADC_SMPR3_SMP5_Pos (15U)
		1191	#define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /!< 0x00038000 /
		1192	#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /!< ADC channel 5 sampling time selection /
		1193	#define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /!< 0x00008000 /
		1194	#define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /!< 0x00010000 /
		1195	#define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /!< 0x00020000 /
		1196
		1197	#define ADC_SMPR3_SMP6_Pos (18U)
		1198	#define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /!< 0x001C0000 /
		1199	#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /!< ADC channel 6 sampling time selection /
		1200	#define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /!< 0x00040000 /
		1201	#define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /!< 0x00080000 /
		1202	#define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /!< 0x00100000 /
		1203
		1204	#define ADC_SMPR3_SMP7_Pos (21U)
		1205	#define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /!< 0x00E00000 /
		1206	#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /!< ADC channel 7 sampling time selection /
		1207	#define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /!< 0x00200000 /
		1208	#define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /!< 0x00400000 /
		1209	#define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /!< 0x00800000 /
		1210
		1211	#define ADC_SMPR3_SMP8_Pos (24U)
		1212	#define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /!< 0x07000000 /
		1213	#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /!< ADC channel 8 sampling time selection /
		1214	#define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /!< 0x01000000 /
		1215	#define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /!< 0x02000000 /
		1216	#define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /!< 0x04000000 /
		1217
		1218	#define ADC_SMPR3_SMP9_Pos (27U)
		1219	#define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /!< 0x38000000 /
		1220	#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /!< ADC channel 9 sampling time selection /
		1221	#define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /!< 0x08000000 /
		1222	#define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /!< 0x10000000 /
		1223	#define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /!< 0x20000000 /
		1224
		1225	/**************** Bit definition for ADC_JOFR1 register *****************/
		1226	#define ADC_JOFR1_JOFFSET1_Pos (0U)
		1227	#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /!< 0x00000FFF /
		1228	#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /!< ADC group injected sequencer rank 1 offset value /
		1229
		1230	/**************** Bit definition for ADC_JOFR2 register *****************/
		1231	#define ADC_JOFR2_JOFFSET2_Pos (0U)
		1232	#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /!< 0x00000FFF /
		1233	#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /!< ADC group injected sequencer rank 2 offset value /
		1234
		1235	/**************** Bit definition for ADC_JOFR3 register *****************/
		1236	#define ADC_JOFR3_JOFFSET3_Pos (0U)
		1237	#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /!< 0x00000FFF /
		1238	#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /!< ADC group injected sequencer rank 3 offset value /
		1239
		1240	/**************** Bit definition for ADC_JOFR4 register *****************/
		1241	#define ADC_JOFR4_JOFFSET4_Pos (0U)
		1242	#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /!< 0x00000FFF /
		1243	#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /!< ADC group injected sequencer rank 4 offset value /
		1244
		1245	/***************** Bit definition for ADC_HTR register ******************/
		1246	#define ADC_HTR_HT_Pos (0U)
		1247	#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /!< 0x00000FFF /
		1248	#define ADC_HTR_HT ADC_HTR_HT_Msk /!< ADC analog watchdog 1 threshold high /
		1249
		1250	/***************** Bit definition for ADC_LTR register ******************/
		1251	#define ADC_LTR_LT_Pos (0U)
		1252	#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /!< 0x00000FFF /
		1253	#define ADC_LTR_LT ADC_LTR_LT_Msk /!< ADC analog watchdog 1 threshold low /
		1254
		1255	/***************** Bit definition for ADC_SQR1 register *****************/
		1256	#define ADC_SQR1_L_Pos (20U)
		1257	#define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /!< 0x01F00000 /
		1258	#define ADC_SQR1_L ADC_SQR1_L_Msk /!< ADC group regular sequencer scan length /
		1259	#define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /!< 0x00100000 /
		1260	#define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /!< 0x00200000 /
		1261	#define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /!< 0x00400000 /
		1262	#define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /!< 0x00800000 /
		1263	#define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /!< 0x01000000 /
		1264
		1265	#define ADC_SQR1_SQ28_Pos (15U)
		1266	#define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /!< 0x000F8000 /
		1267	#define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /!< ADC group regular sequencer rank 28 /
		1268	#define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /!< 0x00008000 /
		1269	#define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /!< 0x00010000 /
		1270	#define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /!< 0x00020000 /
		1271	#define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /!< 0x00040000 /
		1272	#define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /!< 0x00080000 /
		1273
		1274	#define ADC_SQR1_SQ27_Pos (10U)
		1275	#define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /!< 0x00007C00 /
		1276	#define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /!< ADC group regular sequencer rank 27 /
		1277	#define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /!< 0x00000400 /
		1278	#define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /!< 0x00000800 /
		1279	#define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /!< 0x00001000 /
		1280	#define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /!< 0x00002000 /
		1281	#define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /!< 0x00004000 /
		1282
		1283	#define ADC_SQR1_SQ26_Pos (5U)
		1284	#define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /!< 0x000003E0 /
		1285	#define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /!< ADC group regular sequencer rank 26 /
		1286	#define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /!< 0x00000020 /
		1287	#define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /!< 0x00000040 /
		1288	#define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /!< 0x00000080 /
		1289	#define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /!< 0x00000100 /
		1290	#define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /!< 0x00000200 /
		1291
		1292	#define ADC_SQR1_SQ25_Pos (0U)
		1293	#define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /!< 0x0000001F /
		1294	#define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /!< ADC group regular sequencer rank 25 /
		1295	#define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /!< 0x00000001 /
		1296	#define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /!< 0x00000002 /
		1297	#define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /!< 0x00000004 /
		1298	#define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /!< 0x00000008 /
		1299	#define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /!< 0x00000010 /
		1300
		1301	/***************** Bit definition for ADC_SQR2 register *****************/
		1302	#define ADC_SQR2_SQ19_Pos (0U)
		1303	#define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /!< 0x0000001F /
		1304	#define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /!< ADC group regular sequencer rank 19 /
		1305	#define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /!< 0x00000001 /
		1306	#define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /!< 0x00000002 /
		1307	#define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /!< 0x00000004 /
		1308	#define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /!< 0x00000008 /
		1309	#define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /!< 0x00000010 /
		1310
		1311	#define ADC_SQR2_SQ20_Pos (5U)
		1312	#define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /!< 0x000003E0 /
		1313	#define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /!< ADC group regular sequencer rank 20 /
		1314	#define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /!< 0x00000020 /
		1315	#define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /!< 0x00000040 /
		1316	#define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /!< 0x00000080 /
		1317	#define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /!< 0x00000100 /
		1318	#define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /!< 0x00000200 /
		1319
		1320	#define ADC_SQR2_SQ21_Pos (10U)
		1321	#define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /!< 0x00007C00 /
		1322	#define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /!< ADC group regular sequencer rank 21 /
		1323	#define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /!< 0x00000400 /
		1324	#define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /!< 0x00000800 /
		1325	#define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /!< 0x00001000 /
		1326	#define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /!< 0x00002000 /
		1327	#define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /!< 0x00004000 /
		1328
		1329	#define ADC_SQR2_SQ22_Pos (15U)
		1330	#define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /!< 0x000F8000 /
		1331	#define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /!< ADC group regular sequencer rank 22 /
		1332	#define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /!< 0x00008000 /
		1333	#define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /!< 0x00010000 /
		1334	#define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /!< 0x00020000 /
		1335	#define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /!< 0x00040000 /
		1336	#define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /!< 0x00080000 /
		1337
		1338	#define ADC_SQR2_SQ23_Pos (20U)
		1339	#define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /!< 0x01F00000 /
		1340	#define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /!< ADC group regular sequencer rank 23 /
		1341	#define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /!< 0x00100000 /
		1342	#define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /!< 0x00200000 /
		1343	#define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /!< 0x00400000 /
		1344	#define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /!< 0x00800000 /
		1345	#define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /!< 0x01000000 /
		1346
		1347	#define ADC_SQR2_SQ24_Pos (25U)
		1348	#define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /!< 0x3E000000 /
		1349	#define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /!< ADC group regular sequencer rank 24 /
		1350	#define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /!< 0x02000000 /
		1351	#define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /!< 0x04000000 /
		1352	#define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /!< 0x08000000 /
		1353	#define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /!< 0x10000000 /
		1354	#define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /!< 0x20000000 /
		1355
		1356	/***************** Bit definition for ADC_SQR3 register *****************/
		1357	#define ADC_SQR3_SQ13_Pos (0U)
		1358	#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /!< 0x0000001F /
		1359	#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /!< ADC group regular sequencer rank 13 /
		1360	#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /!< 0x00000001 /
		1361	#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /!< 0x00000002 /
		1362	#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /!< 0x00000004 /
		1363	#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /!< 0x00000008 /
		1364	#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /!< 0x00000010 /
		1365
		1366	#define ADC_SQR3_SQ14_Pos (5U)
		1367	#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /!< 0x000003E0 /
		1368	#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /!< ADC group regular sequencer rank 14 /
		1369	#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /!< 0x00000020 /
		1370	#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /!< 0x00000040 /
		1371	#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /!< 0x00000080 /
		1372	#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /!< 0x00000100 /
		1373	#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /!< 0x00000200 /
		1374
		1375	#define ADC_SQR3_SQ15_Pos (10U)
		1376	#define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /!< 0x00007C00 /
		1377	#define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /!< ADC group regular sequencer rank 15 /
		1378	#define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /!< 0x00000400 /
		1379	#define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /!< 0x00000800 /
		1380	#define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /!< 0x00001000 /
		1381	#define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /!< 0x00002000 /
		1382	#define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /!< 0x00004000 /
		1383
		1384	#define ADC_SQR3_SQ16_Pos (15U)
		1385	#define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /!< 0x000F8000 /
		1386	#define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /!< ADC group regular sequencer rank 16 /
		1387	#define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /!< 0x00008000 /
		1388	#define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /!< 0x00010000 /
		1389	#define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /!< 0x00020000 /
		1390	#define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /!< 0x00040000 /
		1391	#define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /!< 0x00080000 /
		1392
		1393	#define ADC_SQR3_SQ17_Pos (20U)
		1394	#define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /!< 0x01F00000 /
		1395	#define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /!< ADC group regular sequencer rank 17 /
		1396	#define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /!< 0x00100000 /
		1397	#define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /!< 0x00200000 /
		1398	#define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /!< 0x00400000 /
		1399	#define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /!< 0x00800000 /
		1400	#define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /!< 0x01000000 /
		1401
		1402	#define ADC_SQR3_SQ18_Pos (25U)
		1403	#define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /!< 0x3E000000 /
		1404	#define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /!< ADC group regular sequencer rank 18 /
		1405	#define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /!< 0x02000000 /
		1406	#define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /!< 0x04000000 /
		1407	#define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /!< 0x08000000 /
		1408	#define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /!< 0x10000000 /
		1409	#define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /!< 0x20000000 /
		1410
		1411	/***************** Bit definition for ADC_SQR4 register *****************/
		1412	#define ADC_SQR4_SQ7_Pos (0U)
		1413	#define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /!< 0x0000001F /
		1414	#define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /!< ADC group regular sequencer rank 7 /
		1415	#define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /!< 0x00000001 /
		1416	#define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /!< 0x00000002 /
		1417	#define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /!< 0x00000004 /
		1418	#define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /!< 0x00000008 /
		1419	#define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /!< 0x00000010 /
		1420
		1421	#define ADC_SQR4_SQ8_Pos (5U)
		1422	#define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /!< 0x000003E0 /
		1423	#define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /!< ADC group regular sequencer rank 8 /
		1424	#define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /!< 0x00000020 /
		1425	#define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /!< 0x00000040 /
		1426	#define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /!< 0x00000080 /
		1427	#define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /!< 0x00000100 /
		1428	#define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /!< 0x00000200 /
		1429
		1430	#define ADC_SQR4_SQ9_Pos (10U)
		1431	#define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /!< 0x00007C00 /
		1432	#define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /!< ADC group regular sequencer rank 9 /
		1433	#define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /!< 0x00000400 /
		1434	#define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /!< 0x00000800 /
		1435	#define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /!< 0x00001000 /
		1436	#define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /!< 0x00002000 /
		1437	#define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /!< 0x00004000 /
		1438
		1439	#define ADC_SQR4_SQ10_Pos (15U)
		1440	#define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /!< 0x000F8000 /
		1441	#define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /!< ADC group regular sequencer rank 10 /
		1442	#define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /!< 0x00008000 /
		1443	#define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /!< 0x00010000 /
		1444	#define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /!< 0x00020000 /
		1445	#define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /!< 0x00040000 /
		1446	#define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /!< 0x00080000 /
		1447
		1448	#define ADC_SQR4_SQ11_Pos (20U)
		1449	#define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /!< 0x01F00000 /
		1450	#define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /!< ADC group regular sequencer rank 11 /
		1451	#define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /!< 0x00100000 /
		1452	#define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /!< 0x00200000 /
		1453	#define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /!< 0x00400000 /
		1454	#define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /!< 0x00800000 /
		1455	#define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /!< 0x01000000 /
		1456
		1457	#define ADC_SQR4_SQ12_Pos (25U)
		1458	#define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /!< 0x3E000000 /
		1459	#define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /!< ADC group regular sequencer rank 12 /
		1460	#define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /!< 0x02000000 /
		1461	#define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /!< 0x04000000 /
		1462	#define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /!< 0x08000000 /
		1463	#define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /!< 0x10000000 /
		1464	#define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /!< 0x20000000 /
		1465
		1466	/***************** Bit definition for ADC_SQR5 register *****************/
		1467	#define ADC_SQR5_SQ1_Pos (0U)
		1468	#define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /!< 0x0000001F /
		1469	#define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /!< ADC group regular sequencer rank 1 /
		1470	#define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /!< 0x00000001 /
		1471	#define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /!< 0x00000002 /
		1472	#define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /!< 0x00000004 /
		1473	#define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /!< 0x00000008 /
		1474	#define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /!< 0x00000010 /
		1475
		1476	#define ADC_SQR5_SQ2_Pos (5U)
		1477	#define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /!< 0x000003E0 /
		1478	#define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /!< ADC group regular sequencer rank 2 /
		1479	#define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /!< 0x00000020 /
		1480	#define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /!< 0x00000040 /
		1481	#define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /!< 0x00000080 /
		1482	#define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /!< 0x00000100 /
		1483	#define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /!< 0x00000200 /
		1484
		1485	#define ADC_SQR5_SQ3_Pos (10U)
		1486	#define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /!< 0x00007C00 /
		1487	#define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /!< ADC group regular sequencer rank 3 /
		1488	#define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /!< 0x00000400 /
		1489	#define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /!< 0x00000800 /
		1490	#define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /!< 0x00001000 /
		1491	#define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /!< 0x00002000 /
		1492	#define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /!< 0x00004000 /
		1493
		1494	#define ADC_SQR5_SQ4_Pos (15U)
		1495	#define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /!< 0x000F8000 /
		1496	#define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /!< ADC group regular sequencer rank 4 /
		1497	#define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /!< 0x00008000 /
		1498	#define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /!< 0x00010000 /
		1499	#define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /!< 0x00020000 /
		1500	#define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /!< 0x00040000 /
		1501	#define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /!< 0x00080000 /
		1502
		1503	#define ADC_SQR5_SQ5_Pos (20U)
		1504	#define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /!< 0x01F00000 /
		1505	#define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /!< ADC group regular sequencer rank 5 /
		1506	#define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /!< 0x00100000 /
		1507	#define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /!< 0x00200000 /
		1508	#define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /!< 0x00400000 /
		1509	#define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /!< 0x00800000 /
		1510	#define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /!< 0x01000000 /
		1511
		1512	#define ADC_SQR5_SQ6_Pos (25U)
		1513	#define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /!< 0x3E000000 /
		1514	#define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /!< ADC group regular sequencer rank 6 /
		1515	#define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /!< 0x02000000 /
		1516	#define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /!< 0x04000000 /
		1517	#define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /!< 0x08000000 /
		1518	#define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /!< 0x10000000 /
		1519	#define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /!< 0x20000000 /
		1520
		1521
		1522	/***************** Bit definition for ADC_JSQR register *****************/
		1523	#define ADC_JSQR_JSQ1_Pos (0U)
		1524	#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /!< 0x0000001F /
		1525	#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /!< ADC group injected sequencer rank 1 /
		1526	#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /!< 0x00000001 /
		1527	#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /!< 0x00000002 /
		1528	#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /!< 0x00000004 /
		1529	#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /!< 0x00000008 /
		1530	#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /!< 0x00000010 /
		1531
		1532	#define ADC_JSQR_JSQ2_Pos (5U)
		1533	#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /!< 0x000003E0 /
		1534	#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /!< ADC group injected sequencer rank 2 /
		1535	#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /!< 0x00000020 /
		1536	#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /!< 0x00000040 /
		1537	#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /!< 0x00000080 /
		1538	#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /!< 0x00000100 /
		1539	#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /!< 0x00000200 /
		1540
		1541	#define ADC_JSQR_JSQ3_Pos (10U)
		1542	#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /!< 0x00007C00 /
		1543	#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /!< ADC group injected sequencer rank 3 /
		1544	#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /!< 0x00000400 /
		1545	#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /!< 0x00000800 /
		1546	#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /!< 0x00001000 /
		1547	#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /!< 0x00002000 /
		1548	#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /!< 0x00004000 /
		1549
		1550	#define ADC_JSQR_JSQ4_Pos (15U)
		1551	#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /!< 0x000F8000 /
		1552	#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /!< ADC group injected sequencer rank 4 /
		1553	#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /!< 0x00008000 /
		1554	#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /!< 0x00010000 /
		1555	#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /!< 0x00020000 /
		1556	#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /!< 0x00040000 /
		1557	#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /!< 0x00080000 /
		1558
		1559	#define ADC_JSQR_JL_Pos (20U)
		1560	#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /!< 0x00300000 /
		1561	#define ADC_JSQR_JL ADC_JSQR_JL_Msk /!< ADC group injected sequencer scan length /
		1562	#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /!< 0x00100000 /
		1563	#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /!< 0x00200000 /
		1564
		1565	/***************** Bit definition for ADC_JDR1 register *****************/
		1566	#define ADC_JDR1_JDATA_Pos (0U)
		1567	#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /!< 0x0000FFFF /
		1568	#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /!< ADC group injected sequencer rank 1 conversion data /
		1569
		1570	/***************** Bit definition for ADC_JDR2 register *****************/
		1571	#define ADC_JDR2_JDATA_Pos (0U)
		1572	#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /!< 0x0000FFFF /
		1573	#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /!< ADC group injected sequencer rank 2 conversion data /
		1574
		1575	/***************** Bit definition for ADC_JDR3 register *****************/
		1576	#define ADC_JDR3_JDATA_Pos (0U)
		1577	#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /!< 0x0000FFFF /
		1578	#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /!< ADC group injected sequencer rank 3 conversion data /
		1579
		1580	/***************** Bit definition for ADC_JDR4 register *****************/
		1581	#define ADC_JDR4_JDATA_Pos (0U)
		1582	#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /!< 0x0000FFFF /
		1583	#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /!< ADC group injected sequencer rank 4 conversion data /
		1584
		1585	/****************** Bit definition for ADC_DR register ******************/
		1586	#define ADC_DR_DATA_Pos (0U)
		1587	#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /!< 0x0000FFFF /
		1588	#define ADC_DR_DATA ADC_DR_DATA_Msk /!< ADC group regular conversion data /
		1589
		1590	/**************** Bit definition for ADC_SMPR0 register *****************/
		1591	#define ADC_SMPR0_SMP30_Pos (0U)
		1592	#define ADC_SMPR0_SMP30_Msk (0x7U << ADC_SMPR0_SMP30_Pos) /!< 0x00000007 /
		1593	#define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /!< ADC channel 30 sampling time selection /
		1594	#define ADC_SMPR0_SMP30_0 (0x1U << ADC_SMPR0_SMP30_Pos) /!< 0x00000001 /
		1595	#define ADC_SMPR0_SMP30_1 (0x2U << ADC_SMPR0_SMP30_Pos) /!< 0x00000002 /
		1596	#define ADC_SMPR0_SMP30_2 (0x4U << ADC_SMPR0_SMP30_Pos) /!< 0x00000004 /
		1597
		1598	#define ADC_SMPR0_SMP31_Pos (3U)
		1599	#define ADC_SMPR0_SMP31_Msk (0x7U << ADC_SMPR0_SMP31_Pos) /!< 0x00000038 /
		1600	#define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /!< ADC channel 31 sampling time selection /
		1601	#define ADC_SMPR0_SMP31_0 (0x1U << ADC_SMPR0_SMP31_Pos) /!< 0x00000008 /
		1602	#define ADC_SMPR0_SMP31_1 (0x2U << ADC_SMPR0_SMP31_Pos) /!< 0x00000010 /
		1603	#define ADC_SMPR0_SMP31_2 (0x4U << ADC_SMPR0_SMP31_Pos) /!< 0x00000020 /
		1604
		1605	/***************** Bit definition for ADC_CSR register ******************/
		1606	#define ADC_CSR_AWD1_Pos (0U)
		1607	#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /!< 0x00000001 /
		1608	#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /!< ADC multimode master analog watchdog 1 flag /
		1609	#define ADC_CSR_EOCS1_Pos (1U)
		1610	#define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /!< 0x00000002 /
		1611	#define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag /
		1612	#define ADC_CSR_JEOS1_Pos (2U)
		1613	#define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /!< 0x00000004 /
		1614	#define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /!< ADC multimode master group injected end of sequence conversions flag /
		1615	#define ADC_CSR_JSTRT1_Pos (3U)
		1616	#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /!< 0x00000008 /
		1617	#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /!< ADC multimode master group injected conversion start flag /
		1618	#define ADC_CSR_STRT1_Pos (4U)
		1619	#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /!< 0x00000010 /
		1620	#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /!< ADC multimode master group regular conversion start flag /
		1621	#define ADC_CSR_OVR1_Pos (5U)
		1622	#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /!< 0x00000020 /
		1623	#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /!< ADC multimode master group regular overrun flag /
		1624	#define ADC_CSR_ADONS1_Pos (6U)
		1625	#define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /!< 0x00000040 /
		1626	#define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /!< ADC multimode master ready flag /
		1627
		1628	/* Legacy defines */
		1629	#define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
		1630	#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
		1631
		1632	/***************** Bit definition for ADC_CCR register ******************/
		1633	#define ADC_CCR_ADCPRE_Pos (16U)
		1634	#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /!< 0x00030000 /
		1635	#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /!< ADC clock source asynchronous prescaler /
		1636	#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /!< 0x00010000 /
		1637	#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /!< 0x00020000 /
		1638	#define ADC_CCR_TSVREFE_Pos (23U)
		1639	#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /!< 0x00800000 /
		1640	#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /!< ADC internal path to VrefInt and temperature sensor enable /
		1641
		1642	/******************************************************************************/
		1643	/* */
		1644	/* Analog Comparators (COMP) */
		1645	/* */
		1646	/******************************************************************************/
		1647
		1648	/**************** Bit definition for COMP_CSR register ******************/
		1649	#define COMP_CSR_10KPU (0x00000001U) /!< Comparator 1 input plus 10K pull-up resistor /
		1650	#define COMP_CSR_400KPU (0x00000002U) /!< Comparator 1 input plus 400K pull-up resistor /
		1651	#define COMP_CSR_10KPD (0x00000004U) /!< Comparator 1 input plus 10K pull-down resistor /
		1652	#define COMP_CSR_400KPD (0x00000008U) /!< Comparator 1 input plus 400K pull-down resistor /
		1653	#define COMP_CSR_CMP1EN_Pos (4U)
		1654	#define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /!< 0x00000010 /
		1655	#define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /!< Comparator 1 enable /
		1656	#define COMP_CSR_CMP1OUT_Pos (7U)
		1657	#define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /!< 0x00000080 /
		1658	#define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /!< Comparator 1 output level /
		1659	#define COMP_CSR_SPEED_Pos (12U)
		1660	#define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /!< 0x00001000 /
		1661	#define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /!< Comparator 2 power mode /
		1662	#define COMP_CSR_CMP2OUT_Pos (13U)
		1663	#define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /!< 0x00002000 /
		1664	#define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /!< Comparator 2 output level /
		1665
		1666	#define COMP_CSR_WNDWE_Pos (17U)
		1667	#define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /!< 0x00020000 /
		1668	#define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) /
		1669
		1670	#define COMP_CSR_INSEL_Pos (18U)
		1671	#define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /!< 0x001C0000 /
		1672	#define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /!< Comparator 2 input minus selection /
		1673	#define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /!< 0x00040000 /
		1674	#define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /!< 0x00080000 /
		1675	#define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /!< 0x00100000 /
		1676	#define COMP_CSR_OUTSEL_Pos (21U)
		1677	#define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /!< 0x00E00000 /
		1678	#define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /!< Comparator 2 output redirection /
		1679	#define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /!< 0x00200000 /
		1680	#define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /!< 0x00400000 /
		1681	#define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /!< 0x00800000 /
		1682
		1683	/* Bits present in COMP register but not related to comparator */
		1684	/* (or partially related to comparator, in addition to other peripherals) */
		1685	#define COMP_CSR_SW1_Pos (5U)
		1686	#define COMP_CSR_SW1_Msk (0x1U << COMP_CSR_SW1_Pos) /!< 0x00000020 /
		1687	#define COMP_CSR_SW1 COMP_CSR_SW1_Msk /!< SW1 analog switch enable /
		1688	#define COMP_CSR_VREFOUTEN_Pos (16U)
		1689	#define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /!< 0x00010000 /
		1690	#define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /!< VrefInt output enable on GPIO group 3 /
		1691
		1692	#define COMP_CSR_FCH3_Pos (26U)
		1693	#define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /!< 0x04000000 /
		1694	#define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /!< Bit 26 /
		1695	#define COMP_CSR_FCH8_Pos (27U)
		1696	#define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /!< 0x08000000 /
		1697	#define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /!< Bit 27 /
		1698	#define COMP_CSR_RCH13_Pos (28U)
		1699	#define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /!< 0x10000000 /
		1700	#define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /!< Bit 28 /
		1701
		1702	#define COMP_CSR_CAIE_Pos (29U)
		1703	#define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /!< 0x20000000 /
		1704	#define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /!< Bit 29 /
		1705	#define COMP_CSR_CAIF_Pos (30U)
		1706	#define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /!< 0x40000000 /
		1707	#define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /!< Bit 30 /
		1708	#define COMP_CSR_TSUSP_Pos (31U)
		1709	#define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /!< 0x80000000 /
		1710	#define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /!< Bit 31 /
		1711
		1712	/******************************************************************************/
		1713	/* */
		1714	/* Operational Amplifier (OPAMP) */
		1715	/* */
		1716	/******************************************************************************/
		1717	/***************** Bit definition for OPAMP_CSR register ****************/
		1718	#define OPAMP_CSR_OPA1PD_Pos (0U)
		1719	#define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /!< 0x00000001 /
		1720	#define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /!< OPAMP1 disable /
		1721	#define OPAMP_CSR_S3SEL1_Pos (1U)
		1722	#define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /!< 0x00000002 /
		1723	#define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /!< Switch 3 for OPAMP1 Enable /
		1724	#define OPAMP_CSR_S4SEL1_Pos (2U)
		1725	#define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /!< 0x00000004 /
		1726	#define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /!< Switch 4 for OPAMP1 Enable /
		1727	#define OPAMP_CSR_S5SEL1_Pos (3U)
		1728	#define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /!< 0x00000008 /
		1729	#define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /!< Switch 5 for OPAMP1 Enable /
		1730	#define OPAMP_CSR_S6SEL1_Pos (4U)
		1731	#define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /!< 0x00000010 /
		1732	#define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /!< Switch 6 for OPAMP1 Enable /
		1733	#define OPAMP_CSR_OPA1CAL_L_Pos (5U)
		1734	#define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /!< 0x00000020 /
		1735	#define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /!< OPAMP1 Offset calibration for P differential pair /
		1736	#define OPAMP_CSR_OPA1CAL_H_Pos (6U)
		1737	#define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /!< 0x00000040 /
		1738	#define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /!< OPAMP1 Offset calibration for N differential pair /
		1739	#define OPAMP_CSR_OPA1LPM_Pos (7U)
		1740	#define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /!< 0x00000080 /
		1741	#define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /!< OPAMP1 Low power enable /
		1742	#define OPAMP_CSR_OPA2PD_Pos (8U)
		1743	#define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /!< 0x00000100 /
		1744	#define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /!< OPAMP2 disable /
		1745	#define OPAMP_CSR_S3SEL2_Pos (9U)
		1746	#define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /!< 0x00000200 /
		1747	#define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /!< Switch 3 for OPAMP2 Enable /
		1748	#define OPAMP_CSR_S4SEL2_Pos (10U)
		1749	#define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /!< 0x00000400 /
		1750	#define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /!< Switch 4 for OPAMP2 Enable /
		1751	#define OPAMP_CSR_S5SEL2_Pos (11U)
		1752	#define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /!< 0x00000800 /
		1753	#define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /!< Switch 5 for OPAMP2 Enable /
		1754	#define OPAMP_CSR_S6SEL2_Pos (12U)
		1755	#define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /!< 0x00001000 /
		1756	#define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /!< Switch 6 for OPAMP2 Enable /
		1757	#define OPAMP_CSR_OPA2CAL_L_Pos (13U)
		1758	#define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /!< 0x00002000 /
		1759	#define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /!< OPAMP2 Offset calibration for P differential pair /
		1760	#define OPAMP_CSR_OPA2CAL_H_Pos (14U)
		1761	#define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /!< 0x00004000 /
		1762	#define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /!< OPAMP2 Offset calibration for N differential pair /
		1763	#define OPAMP_CSR_OPA2LPM_Pos (15U)
		1764	#define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /!< 0x00008000 /
		1765	#define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /!< OPAMP2 Low power enable /
		1766	#define OPAMP_CSR_ANAWSEL1_Pos (24U)
		1767	#define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /!< 0x01000000 /
		1768	#define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /!< Switch ANA Enable for OPAMP1 /
		1769	#define OPAMP_CSR_ANAWSEL2_Pos (25U)
		1770	#define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /!< 0x02000000 /
		1771	#define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /!< Switch ANA Enable for OPAMP2 /
		1772	#define OPAMP_CSR_S7SEL2_Pos (27U)
		1773	#define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /!< 0x08000000 /
		1774	#define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /!< Switch 7 for OPAMP2 Enable /
		1775	#define OPAMP_CSR_AOP_RANGE_Pos (28U)
		1776	#define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /!< 0x10000000 /
		1777	#define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) /
		1778	#define OPAMP_CSR_OPA1CALOUT_Pos (29U)
		1779	#define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /!< 0x20000000 /
		1780	#define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /!< OPAMP1 calibration output /
		1781	#define OPAMP_CSR_OPA2CALOUT_Pos (30U)
		1782	#define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /!< 0x40000000 /
		1783	#define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /!< OPAMP2 calibration output /
		1784
		1785	/***************** Bit definition for OPAMP_OTR register ****************/
		1786	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
		1787	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /!< 0x0000001F /
		1788	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /!< Offset trim for transistors differential pair PMOS of OPAMP1 /
		1789	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
		1790	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /!< 0x000003E0 /
		1791	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /!< Offset trim for transistors differential pair NMOS of OPAMP1 /
		1792	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
		1793	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /!< 0x00007C00 /
		1794	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /!< Offset trim for transistors differential pair PMOS of OPAMP2 /
		1795	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
		1796	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /!< 0x000F8000 /
		1797	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /!< Offset trim for transistors differential pair NMOS of OPAMP2 /
		1798	#define OPAMP_OTR_OT_USER_Pos (31U)
		1799	#define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /!< 0x80000000 /
		1800	#define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /!< Switch to OPAMP offset user trimmed values /
		1801
		1802	/***************** Bit definition for OPAMP_LPOTR register **************/
		1803	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
		1804	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /!< 0x0000001F /
		1805	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /!< Offset trim for transistors differential pair PMOS of OPAMP1 /
		1806	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
		1807	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /!< 0x000003E0 /
		1808	#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /!< Offset trim for transistors differential pair NMOS of OPAMP1 /
		1809	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
		1810	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /!< 0x00007C00 /
		1811	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /!< Offset trim for transistors differential pair PMOS of OPAMP2 /
		1812	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
		1813	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /!< 0x000F8000 /
		1814	#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /!< Offset trim for transistors differential pair NMOS of OPAMP2 /
		1815
		1816	/******************************************************************************/
		1817	/* */
		1818	/* CRC calculation unit (CRC) */
		1819	/* */
		1820	/******************************************************************************/
		1821
		1822	/***************** Bit definition for CRC_DR register *******************/
		1823	#define CRC_DR_DR_Pos (0U)
		1824	#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /!< 0xFFFFFFFF /
		1825	#define CRC_DR_DR CRC_DR_DR_Msk /!< Data register bits /
		1826
		1827	/***************** Bit definition for CRC_IDR register ******************/
		1828	#define CRC_IDR_IDR_Pos (0U)
		1829	#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /!< 0x000000FF /
		1830	#define CRC_IDR_IDR CRC_IDR_IDR_Msk /!< General-purpose 8-bit data register bits /
		1831
		1832	/****************** Bit definition for CRC_CR register ******************/
		1833	#define CRC_CR_RESET_Pos (0U)
		1834	#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /!< 0x00000001 /
		1835	#define CRC_CR_RESET CRC_CR_RESET_Msk /!< RESET bit /
		1836
		1837	/******************************************************************************/
		1838	/* */
		1839	/* Digital to Analog Converter (DAC) */
		1840	/* */
		1841	/******************************************************************************/
		1842
		1843	/****************** Bit definition for DAC_CR register ******************/
		1844	#define DAC_CR_EN1_Pos (0U)
		1845	#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /!< 0x00000001 /
		1846	#define DAC_CR_EN1 DAC_CR_EN1_Msk /!<DAC channel1 enable /
		1847	#define DAC_CR_BOFF1_Pos (1U)
		1848	#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /!< 0x00000002 /
		1849	#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /!<DAC channel1 output buffer disable /
		1850	#define DAC_CR_TEN1_Pos (2U)
		1851	#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /!< 0x00000004 /
		1852	#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /!<DAC channel1 Trigger enable /
		1853
		1854	#define DAC_CR_TSEL1_Pos (3U)
		1855	#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /!< 0x00000038 /
		1856	#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
		1857	#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /!< 0x00000008 /
		1858	#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /!< 0x00000010 /
		1859	#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /!< 0x00000020 /
		1860
		1861	#define DAC_CR_WAVE1_Pos (6U)
		1862	#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /!< 0x000000C0 /
		1863	#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
		1864	#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /!< 0x00000040 /
		1865	#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /!< 0x00000080 /
		1866
		1867	#define DAC_CR_MAMP1_Pos (8U)
		1868	#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /!< 0x00000F00 /
		1869	#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
		1870	#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /!< 0x00000100 /
		1871	#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /!< 0x00000200 /
		1872	#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /!< 0x00000400 /
		1873	#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /!< 0x00000800 /
		1874
		1875	#define DAC_CR_DMAEN1_Pos (12U)
		1876	#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /!< 0x00001000 /
		1877	#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /!<DAC channel1 DMA enable /
		1878	#define DAC_CR_DMAUDRIE1_Pos (13U)
		1879	#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /!< 0x00002000 /
		1880	#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /!<DAC channel1 DMA Interrupt enable /
		1881	#define DAC_CR_EN2_Pos (16U)
		1882	#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /!< 0x00010000 /
		1883	#define DAC_CR_EN2 DAC_CR_EN2_Msk /!<DAC channel2 enable /
		1884	#define DAC_CR_BOFF2_Pos (17U)
		1885	#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /!< 0x00020000 /
		1886	#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /!<DAC channel2 output buffer disable /
		1887	#define DAC_CR_TEN2_Pos (18U)
		1888	#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /!< 0x00040000 /
		1889	#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /!<DAC channel2 Trigger enable /
		1890
		1891	#define DAC_CR_TSEL2_Pos (19U)
		1892	#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /!< 0x00380000 /
		1893	#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
		1894	#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /!< 0x00080000 /
		1895	#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /!< 0x00100000 /
		1896	#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /!< 0x00200000 /
		1897
		1898	#define DAC_CR_WAVE2_Pos (22U)
		1899	#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /!< 0x00C00000 /
		1900	#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
		1901	#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /!< 0x00400000 /
		1902	#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /!< 0x00800000 /
		1903
		1904	#define DAC_CR_MAMP2_Pos (24U)
		1905	#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /!< 0x0F000000 /
		1906	#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
		1907	#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /!< 0x01000000 /
		1908	#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /!< 0x02000000 /
		1909	#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /!< 0x04000000 /
		1910	#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /!< 0x08000000 /
		1911
		1912	#define DAC_CR_DMAEN2_Pos (28U)
		1913	#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /!< 0x10000000 /
		1914	#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /!<DAC channel2 DMA enabled /
		1915	#define DAC_CR_DMAUDRIE2_Pos (29U)
		1916	#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /!< 0x20000000 /
		1917	#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /!<DAC channel2 DMA underrun interrupt enable /
		1918	/*************** Bit definition for DAC_SWTRIGR register ****************/
		1919	#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
		1920	#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /!< 0x00000001 /
		1921	#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /!<DAC channel1 software trigger /
		1922	#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
		1923	#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /!< 0x00000002 /
		1924	#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /!<DAC channel2 software trigger /
		1925
		1926	/*************** Bit definition for DAC_DHR12R1 register ****************/
		1927	#define DAC_DHR12R1_DACC1DHR_Pos (0U)
		1928	#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /!< 0x00000FFF /
		1929	#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /!<DAC channel1 12-bit Right aligned data /
		1930
		1931	/*************** Bit definition for DAC_DHR12L1 register ****************/
		1932	#define DAC_DHR12L1_DACC1DHR_Pos (4U)
		1933	#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /!< 0x0000FFF0 /
		1934	#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /!<DAC channel1 12-bit Left aligned data /
		1935
		1936	/**************** Bit definition for DAC_DHR8R1 register ****************/
		1937	#define DAC_DHR8R1_DACC1DHR_Pos (0U)
		1938	#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /!< 0x000000FF /
		1939	#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /!<DAC channel1 8-bit Right aligned data /
		1940
		1941	/*************** Bit definition for DAC_DHR12R2 register ****************/
		1942	#define DAC_DHR12R2_DACC2DHR_Pos (0U)
		1943	#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /!< 0x00000FFF /
		1944	#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /!<DAC channel2 12-bit Right aligned data /
		1945
		1946	/*************** Bit definition for DAC_DHR12L2 register ****************/
		1947	#define DAC_DHR12L2_DACC2DHR_Pos (4U)
		1948	#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /!< 0x0000FFF0 /
		1949	#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /!<DAC channel2 12-bit Left aligned data /
		1950
		1951	/**************** Bit definition for DAC_DHR8R2 register ****************/
		1952	#define DAC_DHR8R2_DACC2DHR_Pos (0U)
		1953	#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /!< 0x000000FF /
		1954	#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /!<DAC channel2 8-bit Right aligned data /
		1955
		1956	/*************** Bit definition for DAC_DHR12RD register ****************/
		1957	#define DAC_DHR12RD_DACC1DHR_Pos (0U)
		1958	#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /!< 0x00000FFF /
		1959	#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /!<DAC channel1 12-bit Right aligned data /
		1960	#define DAC_DHR12RD_DACC2DHR_Pos (16U)
		1961	#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /!< 0x0FFF0000 /
		1962	#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /!<DAC channel2 12-bit Right aligned data /
		1963
		1964	/*************** Bit definition for DAC_DHR12LD register ****************/
		1965	#define DAC_DHR12LD_DACC1DHR_Pos (4U)
		1966	#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /!< 0x0000FFF0 /
		1967	#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /!<DAC channel1 12-bit Left aligned data /
		1968	#define DAC_DHR12LD_DACC2DHR_Pos (20U)
		1969	#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /!< 0xFFF00000 /
		1970	#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /!<DAC channel2 12-bit Left aligned data /
		1971
		1972	/**************** Bit definition for DAC_DHR8RD register ****************/
		1973	#define DAC_DHR8RD_DACC1DHR_Pos (0U)
		1974	#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /!< 0x000000FF /
		1975	#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /!<DAC channel1 8-bit Right aligned data /
		1976	#define DAC_DHR8RD_DACC2DHR_Pos (8U)
		1977	#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /!< 0x0000FF00 /
		1978	#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /!<DAC channel2 8-bit Right aligned data /
		1979
		1980	/***************** Bit definition for DAC_DOR1 register *****************/
		1981	#define DAC_DOR1_DACC1DOR_Pos (0U)
		1982	#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /!< 0x00000FFF /
		1983	#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /!<DAC channel1 data output /
		1984
		1985	/***************** Bit definition for DAC_DOR2 register *****************/
		1986	#define DAC_DOR2_DACC2DOR_Pos (0U)
		1987	#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /!< 0x00000FFF /
		1988	#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /!<DAC channel2 data output /
		1989
		1990	/****************** Bit definition for DAC_SR register ******************/
		1991	#define DAC_SR_DMAUDR1_Pos (13U)
		1992	#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /!< 0x00002000 /
		1993	#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /!<DAC channel1 DMA underrun flag /
		1994	#define DAC_SR_DMAUDR2_Pos (29U)
		1995	#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /!< 0x20000000 /
		1996	#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /!<DAC channel2 DMA underrun flag /
		1997
		1998	/******************************************************************************/
		1999	/* */
		2000	/* Debug MCU (DBGMCU) */
		2001	/* */
		2002	/******************************************************************************/
		2003
		2004	/************** Bit definition for DBGMCU_IDCODE register ***************/
		2005	#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
		2006	#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /!< 0x00000FFF /
		2007	#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /!< Device Identifier /
		2008
		2009	#define DBGMCU_IDCODE_REV_ID_Pos (16U)
		2010	#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /!< 0xFFFF0000 /
		2011	#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /!< REV_ID[15:0] bits (Revision Identifier) /
		2012	#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00010000 /
		2013	#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00020000 /
		2014	#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00040000 /
		2015	#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00080000 /
		2016	#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00100000 /
		2017	#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00200000 /
		2018	#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00400000 /
		2019	#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x00800000 /
		2020	#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x01000000 /
		2021	#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x02000000 /
		2022	#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x04000000 /
		2023	#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x08000000 /
		2024	#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x10000000 /
		2025	#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x20000000 /
		2026	#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x40000000 /
		2027	#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /!< 0x80000000 /
		2028
		2029	/**************** Bit definition for DBGMCU_CR register *****************/
		2030	#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
		2031	#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /!< 0x00000001 /
		2032	#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /!< Debug Sleep Mode /
		2033	#define DBGMCU_CR_DBG_STOP_Pos (1U)
		2034	#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /!< 0x00000002 /
		2035	#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /!< Debug Stop Mode /
		2036	#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
		2037	#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /!< 0x00000004 /
		2038	#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /!< Debug Standby mode /
		2039	#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
		2040	#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /!< 0x00000020 /
		2041	#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /!< Trace Pin Assignment Control /
		2042
		2043	#define DBGMCU_CR_TRACE_MODE_Pos (6U)
		2044	#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x000000C0 /
		2045	#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
		2046	#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000040 /
		2047	#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /!< 0x00000080 /
		2048
		2049	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
		2050
		2051	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
		2052	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /!< 0x00000001 /
		2053	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /!< TIM2 counter stopped when core is halted /
		2054	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
		2055	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /!< 0x00000002 /
		2056	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /!< TIM3 counter stopped when core is halted /
		2057	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
		2058	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /!< 0x00000004 /
		2059	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /!< TIM4 counter stopped when core is halted /
		2060	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
		2061	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /!< 0x00000008 /
		2062	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /!< TIM5 counter stopped when core is halted /
		2063	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
		2064	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /!< 0x00000010 /
		2065	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /!< TIM6 counter stopped when core is halted /
		2066	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
		2067	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /!< 0x00000020 /
		2068	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /!< TIM7 counter stopped when core is halted /
		2069	#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
		2070	#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /!< 0x00000400 /
		2071	#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /!< RTC Counter stopped when Core is halted /
		2072	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
		2073	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /!< 0x00000800 /
		2074	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /!< Debug Window Watchdog stopped when Core is halted /
		2075	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
		2076	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /!< 0x00001000 /
		2077	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /!< Debug Independent Watchdog stopped when Core is halted /
		2078	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
		2079	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /!< 0x00200000 /
		2080	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		2081	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
		2082	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /!< 0x00400000 /
		2083	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /!< SMBUS timeout mode stopped when Core is halted /
		2084
		2085	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
		2086
		2087	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U)
		2088	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /!< 0x00000004 /
		2089	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /!< TIM9 counter stopped when core is halted /
		2090	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U)
		2091	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /!< 0x00000008 /
		2092	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /!< TIM10 counter stopped when core is halted /
		2093	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U)
		2094	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /!< 0x00000010 /
		2095	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /!< TIM11 counter stopped when core is halted /
		2096
		2097	/******************************************************************************/
		2098	/* */
		2099	/* DMA Controller (DMA) */
		2100	/* */
		2101	/******************************************************************************/
		2102
		2103	/***************** Bit definition for DMA_ISR register ******************/
		2104	#define DMA_ISR_GIF1_Pos (0U)
		2105	#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /!< 0x00000001 /
		2106	#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /!< Channel 1 Global interrupt flag /
		2107	#define DMA_ISR_TCIF1_Pos (1U)
		2108	#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /!< 0x00000002 /
		2109	#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /!< Channel 1 Transfer Complete flag /
		2110	#define DMA_ISR_HTIF1_Pos (2U)
		2111	#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /!< 0x00000004 /
		2112	#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /!< Channel 1 Half Transfer flag /
		2113	#define DMA_ISR_TEIF1_Pos (3U)
		2114	#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /!< 0x00000008 /
		2115	#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /!< Channel 1 Transfer Error flag /
		2116	#define DMA_ISR_GIF2_Pos (4U)
		2117	#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /!< 0x00000010 /
		2118	#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /!< Channel 2 Global interrupt flag /
		2119	#define DMA_ISR_TCIF2_Pos (5U)
		2120	#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /!< 0x00000020 /
		2121	#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /!< Channel 2 Transfer Complete flag /
		2122	#define DMA_ISR_HTIF2_Pos (6U)
		2123	#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /!< 0x00000040 /
		2124	#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /!< Channel 2 Half Transfer flag /
		2125	#define DMA_ISR_TEIF2_Pos (7U)
		2126	#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /!< 0x00000080 /
		2127	#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /!< Channel 2 Transfer Error flag /
		2128	#define DMA_ISR_GIF3_Pos (8U)
		2129	#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /!< 0x00000100 /
		2130	#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /!< Channel 3 Global interrupt flag /
		2131	#define DMA_ISR_TCIF3_Pos (9U)
		2132	#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /!< 0x00000200 /
		2133	#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /!< Channel 3 Transfer Complete flag /
		2134	#define DMA_ISR_HTIF3_Pos (10U)
		2135	#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /!< 0x00000400 /
		2136	#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /!< Channel 3 Half Transfer flag /
		2137	#define DMA_ISR_TEIF3_Pos (11U)
		2138	#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /!< 0x00000800 /
		2139	#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /!< Channel 3 Transfer Error flag /
		2140	#define DMA_ISR_GIF4_Pos (12U)
		2141	#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /!< 0x00001000 /
		2142	#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /!< Channel 4 Global interrupt flag /
		2143	#define DMA_ISR_TCIF4_Pos (13U)
		2144	#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /!< 0x00002000 /
		2145	#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /!< Channel 4 Transfer Complete flag /
		2146	#define DMA_ISR_HTIF4_Pos (14U)
		2147	#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /!< 0x00004000 /
		2148	#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /!< Channel 4 Half Transfer flag /
		2149	#define DMA_ISR_TEIF4_Pos (15U)
		2150	#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /!< 0x00008000 /
		2151	#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /!< Channel 4 Transfer Error flag /
		2152	#define DMA_ISR_GIF5_Pos (16U)
		2153	#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /!< 0x00010000 /
		2154	#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /!< Channel 5 Global interrupt flag /
		2155	#define DMA_ISR_TCIF5_Pos (17U)
		2156	#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /!< 0x00020000 /
		2157	#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /!< Channel 5 Transfer Complete flag /
		2158	#define DMA_ISR_HTIF5_Pos (18U)
		2159	#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /!< 0x00040000 /
		2160	#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /!< Channel 5 Half Transfer flag /
		2161	#define DMA_ISR_TEIF5_Pos (19U)
		2162	#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /!< 0x00080000 /
		2163	#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /!< Channel 5 Transfer Error flag /
		2164	#define DMA_ISR_GIF6_Pos (20U)
		2165	#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /!< 0x00100000 /
		2166	#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /!< Channel 6 Global interrupt flag /
		2167	#define DMA_ISR_TCIF6_Pos (21U)
		2168	#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /!< 0x00200000 /
		2169	#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /!< Channel 6 Transfer Complete flag /
		2170	#define DMA_ISR_HTIF6_Pos (22U)
		2171	#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /!< 0x00400000 /
		2172	#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /!< Channel 6 Half Transfer flag /
		2173	#define DMA_ISR_TEIF6_Pos (23U)
		2174	#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /!< 0x00800000 /
		2175	#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /!< Channel 6 Transfer Error flag /
		2176	#define DMA_ISR_GIF7_Pos (24U)
		2177	#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /!< 0x01000000 /
		2178	#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /!< Channel 7 Global interrupt flag /
		2179	#define DMA_ISR_TCIF7_Pos (25U)
		2180	#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /!< 0x02000000 /
		2181	#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /!< Channel 7 Transfer Complete flag /
		2182	#define DMA_ISR_HTIF7_Pos (26U)
		2183	#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /!< 0x04000000 /
		2184	#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /!< Channel 7 Half Transfer flag /
		2185	#define DMA_ISR_TEIF7_Pos (27U)
		2186	#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /!< 0x08000000 /
		2187	#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /!< Channel 7 Transfer Error flag /
		2188
		2189	/***************** Bit definition for DMA_IFCR register *****************/
		2190	#define DMA_IFCR_CGIF1_Pos (0U)
		2191	#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /!< 0x00000001 /
		2192	#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /!< Channel 1 Global interrupt clear /
		2193	#define DMA_IFCR_CTCIF1_Pos (1U)
		2194	#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /!< 0x00000002 /
		2195	#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /!< Channel 1 Transfer Complete clear /
		2196	#define DMA_IFCR_CHTIF1_Pos (2U)
		2197	#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /!< 0x00000004 /
		2198	#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /!< Channel 1 Half Transfer clear /
		2199	#define DMA_IFCR_CTEIF1_Pos (3U)
		2200	#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /!< 0x00000008 /
		2201	#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /!< Channel 1 Transfer Error clear /
		2202	#define DMA_IFCR_CGIF2_Pos (4U)
		2203	#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /!< 0x00000010 /
		2204	#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /!< Channel 2 Global interrupt clear /
		2205	#define DMA_IFCR_CTCIF2_Pos (5U)
		2206	#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /!< 0x00000020 /
		2207	#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /!< Channel 2 Transfer Complete clear /
		2208	#define DMA_IFCR_CHTIF2_Pos (6U)
		2209	#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /!< 0x00000040 /
		2210	#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /!< Channel 2 Half Transfer clear /
		2211	#define DMA_IFCR_CTEIF2_Pos (7U)
		2212	#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /!< 0x00000080 /
		2213	#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /!< Channel 2 Transfer Error clear /
		2214	#define DMA_IFCR_CGIF3_Pos (8U)
		2215	#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /!< 0x00000100 /
		2216	#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /!< Channel 3 Global interrupt clear /
		2217	#define DMA_IFCR_CTCIF3_Pos (9U)
		2218	#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /!< 0x00000200 /
		2219	#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /!< Channel 3 Transfer Complete clear /
		2220	#define DMA_IFCR_CHTIF3_Pos (10U)
		2221	#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /!< 0x00000400 /
		2222	#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /!< Channel 3 Half Transfer clear /
		2223	#define DMA_IFCR_CTEIF3_Pos (11U)
		2224	#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /!< 0x00000800 /
		2225	#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /!< Channel 3 Transfer Error clear /
		2226	#define DMA_IFCR_CGIF4_Pos (12U)
		2227	#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /!< 0x00001000 /
		2228	#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /!< Channel 4 Global interrupt clear /
		2229	#define DMA_IFCR_CTCIF4_Pos (13U)
		2230	#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /!< 0x00002000 /
		2231	#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /!< Channel 4 Transfer Complete clear /
		2232	#define DMA_IFCR_CHTIF4_Pos (14U)
		2233	#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /!< 0x00004000 /
		2234	#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /!< Channel 4 Half Transfer clear /
		2235	#define DMA_IFCR_CTEIF4_Pos (15U)
		2236	#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /!< 0x00008000 /
		2237	#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /!< Channel 4 Transfer Error clear /
		2238	#define DMA_IFCR_CGIF5_Pos (16U)
		2239	#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /!< 0x00010000 /
		2240	#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /!< Channel 5 Global interrupt clear /
		2241	#define DMA_IFCR_CTCIF5_Pos (17U)
		2242	#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /!< 0x00020000 /
		2243	#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /!< Channel 5 Transfer Complete clear /
		2244	#define DMA_IFCR_CHTIF5_Pos (18U)
		2245	#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /!< 0x00040000 /
		2246	#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /!< Channel 5 Half Transfer clear /
		2247	#define DMA_IFCR_CTEIF5_Pos (19U)
		2248	#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /!< 0x00080000 /
		2249	#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /!< Channel 5 Transfer Error clear /
		2250	#define DMA_IFCR_CGIF6_Pos (20U)
		2251	#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /!< 0x00100000 /
		2252	#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /!< Channel 6 Global interrupt clear /
		2253	#define DMA_IFCR_CTCIF6_Pos (21U)
		2254	#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /!< 0x00200000 /
		2255	#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /!< Channel 6 Transfer Complete clear /
		2256	#define DMA_IFCR_CHTIF6_Pos (22U)
		2257	#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /!< 0x00400000 /
		2258	#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /!< Channel 6 Half Transfer clear /
		2259	#define DMA_IFCR_CTEIF6_Pos (23U)
		2260	#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /!< 0x00800000 /
		2261	#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /!< Channel 6 Transfer Error clear /
		2262	#define DMA_IFCR_CGIF7_Pos (24U)
		2263	#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /!< 0x01000000 /
		2264	#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /!< Channel 7 Global interrupt clear /
		2265	#define DMA_IFCR_CTCIF7_Pos (25U)
		2266	#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /!< 0x02000000 /
		2267	#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /!< Channel 7 Transfer Complete clear /
		2268	#define DMA_IFCR_CHTIF7_Pos (26U)
		2269	#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /!< 0x04000000 /
		2270	#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /!< Channel 7 Half Transfer clear /
		2271	#define DMA_IFCR_CTEIF7_Pos (27U)
		2272	#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /!< 0x08000000 /
		2273	#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /!< Channel 7 Transfer Error clear /
		2274
		2275	/***************** Bit definition for DMA_CCR register *****************/
		2276	#define DMA_CCR_EN_Pos (0U)
		2277	#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /!< 0x00000001 /
		2278	#define DMA_CCR_EN DMA_CCR_EN_Msk /!< Channel enable/
		2279	#define DMA_CCR_TCIE_Pos (1U)
		2280	#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /!< 0x00000002 /
		2281	#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /!< Transfer complete interrupt enable /
		2282	#define DMA_CCR_HTIE_Pos (2U)
		2283	#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /!< 0x00000004 /
		2284	#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /!< Half Transfer interrupt enable /
		2285	#define DMA_CCR_TEIE_Pos (3U)
		2286	#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /!< 0x00000008 /
		2287	#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /!< Transfer error interrupt enable /
		2288	#define DMA_CCR_DIR_Pos (4U)
		2289	#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /!< 0x00000010 /
		2290	#define DMA_CCR_DIR DMA_CCR_DIR_Msk /!< Data transfer direction /
		2291	#define DMA_CCR_CIRC_Pos (5U)
		2292	#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /!< 0x00000020 /
		2293	#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /!< Circular mode /
		2294	#define DMA_CCR_PINC_Pos (6U)
		2295	#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /!< 0x00000040 /
		2296	#define DMA_CCR_PINC DMA_CCR_PINC_Msk /!< Peripheral increment mode /
		2297	#define DMA_CCR_MINC_Pos (7U)
		2298	#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /!< 0x00000080 /
		2299	#define DMA_CCR_MINC DMA_CCR_MINC_Msk /!< Memory increment mode /
		2300
		2301	#define DMA_CCR_PSIZE_Pos (8U)
		2302	#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /!< 0x00000300 /
		2303	#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /!< PSIZE[1:0] bits (Peripheral size) /
		2304	#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /!< 0x00000100 /
		2305	#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /!< 0x00000200 /
		2306
		2307	#define DMA_CCR_MSIZE_Pos (10U)
		2308	#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /!< 0x00000C00 /
		2309	#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /!< MSIZE[1:0] bits (Memory size) /
		2310	#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /!< 0x00000400 /
		2311	#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /!< 0x00000800 /
		2312
		2313	#define DMA_CCR_PL_Pos (12U)
		2314	#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /!< 0x00003000 /
		2315	#define DMA_CCR_PL DMA_CCR_PL_Msk /!< PL[1:0] bits(Channel Priority level) /
		2316	#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /!< 0x00001000 /
		2317	#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /!< 0x00002000 /
		2318
		2319	#define DMA_CCR_MEM2MEM_Pos (14U)
		2320	#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /!< 0x00004000 /
		2321	#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /!< Memory to memory mode /
		2322
		2323	/**************** Bit definition generic for DMA_CNDTR register *****************/
		2324	#define DMA_CNDTR_NDT_Pos (0U)
		2325	#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /!< 0x0000FFFF /
		2326	#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /!< Number of data to Transfer /
		2327
		2328	/**************** Bit definition for DMA_CNDTR1 register ****************/
		2329	#define DMA_CNDTR1_NDT_Pos (0U)
		2330	#define DMA_CNDTR1_NDT_Msk (0xFFFFU << DMA_CNDTR1_NDT_Pos) /!< 0x0000FFFF /
		2331	#define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /!< Number of data to Transfer /
		2332
		2333	/**************** Bit definition for DMA_CNDTR2 register ****************/
		2334	#define DMA_CNDTR2_NDT_Pos (0U)
		2335	#define DMA_CNDTR2_NDT_Msk (0xFFFFU << DMA_CNDTR2_NDT_Pos) /!< 0x0000FFFF /
		2336	#define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /!< Number of data to Transfer /
		2337
		2338	/**************** Bit definition for DMA_CNDTR3 register ****************/
		2339	#define DMA_CNDTR3_NDT_Pos (0U)
		2340	#define DMA_CNDTR3_NDT_Msk (0xFFFFU << DMA_CNDTR3_NDT_Pos) /!< 0x0000FFFF /
		2341	#define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /!< Number of data to Transfer /
		2342
		2343	/**************** Bit definition for DMA_CNDTR4 register ****************/
		2344	#define DMA_CNDTR4_NDT_Pos (0U)
		2345	#define DMA_CNDTR4_NDT_Msk (0xFFFFU << DMA_CNDTR4_NDT_Pos) /!< 0x0000FFFF /
		2346	#define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /!< Number of data to Transfer /
		2347
		2348	/**************** Bit definition for DMA_CNDTR5 register ****************/
		2349	#define DMA_CNDTR5_NDT_Pos (0U)
		2350	#define DMA_CNDTR5_NDT_Msk (0xFFFFU << DMA_CNDTR5_NDT_Pos) /!< 0x0000FFFF /
		2351	#define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /!< Number of data to Transfer /
		2352
		2353	/**************** Bit definition for DMA_CNDTR6 register ****************/
		2354	#define DMA_CNDTR6_NDT_Pos (0U)
		2355	#define DMA_CNDTR6_NDT_Msk (0xFFFFU << DMA_CNDTR6_NDT_Pos) /!< 0x0000FFFF /
		2356	#define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /!< Number of data to Transfer /
		2357
		2358	/**************** Bit definition for DMA_CNDTR7 register ****************/
		2359	#define DMA_CNDTR7_NDT_Pos (0U)
		2360	#define DMA_CNDTR7_NDT_Msk (0xFFFFU << DMA_CNDTR7_NDT_Pos) /!< 0x0000FFFF /
		2361	#define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /!< Number of data to Transfer /
		2362
		2363	/**************** Bit definition generic for DMA_CPAR register ******************/
		2364	#define DMA_CPAR_PA_Pos (0U)
		2365	#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /!< 0xFFFFFFFF /
		2366	#define DMA_CPAR_PA DMA_CPAR_PA_Msk /!< Peripheral Address /
		2367
		2368	/**************** Bit definition for DMA_CPAR1 register *****************/
		2369	#define DMA_CPAR1_PA_Pos (0U)
		2370	#define DMA_CPAR1_PA_Msk (0xFFFFFFFFU << DMA_CPAR1_PA_Pos) /!< 0xFFFFFFFF /
		2371	#define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /!< Peripheral Address /
		2372
		2373	/**************** Bit definition for DMA_CPAR2 register *****************/
		2374	#define DMA_CPAR2_PA_Pos (0U)
		2375	#define DMA_CPAR2_PA_Msk (0xFFFFFFFFU << DMA_CPAR2_PA_Pos) /!< 0xFFFFFFFF /
		2376	#define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /!< Peripheral Address /
		2377
		2378	/**************** Bit definition for DMA_CPAR3 register *****************/
		2379	#define DMA_CPAR3_PA_Pos (0U)
		2380	#define DMA_CPAR3_PA_Msk (0xFFFFFFFFU << DMA_CPAR3_PA_Pos) /!< 0xFFFFFFFF /
		2381	#define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /!< Peripheral Address /
		2382
		2383
		2384	/**************** Bit definition for DMA_CPAR4 register *****************/
		2385	#define DMA_CPAR4_PA_Pos (0U)
		2386	#define DMA_CPAR4_PA_Msk (0xFFFFFFFFU << DMA_CPAR4_PA_Pos) /!< 0xFFFFFFFF /
		2387	#define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /!< Peripheral Address /
		2388
		2389	/**************** Bit definition for DMA_CPAR5 register *****************/
		2390	#define DMA_CPAR5_PA_Pos (0U)
		2391	#define DMA_CPAR5_PA_Msk (0xFFFFFFFFU << DMA_CPAR5_PA_Pos) /!< 0xFFFFFFFF /
		2392	#define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /!< Peripheral Address /
		2393
		2394	/**************** Bit definition for DMA_CPAR6 register *****************/
		2395	#define DMA_CPAR6_PA_Pos (0U)
		2396	#define DMA_CPAR6_PA_Msk (0xFFFFFFFFU << DMA_CPAR6_PA_Pos) /!< 0xFFFFFFFF /
		2397	#define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /!< Peripheral Address /
		2398
		2399
		2400	/**************** Bit definition for DMA_CPAR7 register *****************/
		2401	#define DMA_CPAR7_PA_Pos (0U)
		2402	#define DMA_CPAR7_PA_Msk (0xFFFFFFFFU << DMA_CPAR7_PA_Pos) /!< 0xFFFFFFFF /
		2403	#define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /!< Peripheral Address /
		2404
		2405	/**************** Bit definition generic for DMA_CMAR register ******************/
		2406	#define DMA_CMAR_MA_Pos (0U)
		2407	#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /!< 0xFFFFFFFF /
		2408	#define DMA_CMAR_MA DMA_CMAR_MA_Msk /!< Memory Address /
		2409
		2410	/**************** Bit definition for DMA_CMAR1 register *****************/
		2411	#define DMA_CMAR1_MA_Pos (0U)
		2412	#define DMA_CMAR1_MA_Msk (0xFFFFFFFFU << DMA_CMAR1_MA_Pos) /!< 0xFFFFFFFF /
		2413	#define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /!< Memory Address /
		2414
		2415	/**************** Bit definition for DMA_CMAR2 register *****************/
		2416	#define DMA_CMAR2_MA_Pos (0U)
		2417	#define DMA_CMAR2_MA_Msk (0xFFFFFFFFU << DMA_CMAR2_MA_Pos) /!< 0xFFFFFFFF /
		2418	#define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /!< Memory Address /
		2419
		2420	/**************** Bit definition for DMA_CMAR3 register *****************/
		2421	#define DMA_CMAR3_MA_Pos (0U)
		2422	#define DMA_CMAR3_MA_Msk (0xFFFFFFFFU << DMA_CMAR3_MA_Pos) /!< 0xFFFFFFFF /
		2423	#define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /!< Memory Address /
		2424
		2425
		2426	/**************** Bit definition for DMA_CMAR4 register *****************/
		2427	#define DMA_CMAR4_MA_Pos (0U)
		2428	#define DMA_CMAR4_MA_Msk (0xFFFFFFFFU << DMA_CMAR4_MA_Pos) /!< 0xFFFFFFFF /
		2429	#define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /!< Memory Address /
		2430
		2431	/**************** Bit definition for DMA_CMAR5 register *****************/
		2432	#define DMA_CMAR5_MA_Pos (0U)
		2433	#define DMA_CMAR5_MA_Msk (0xFFFFFFFFU << DMA_CMAR5_MA_Pos) /!< 0xFFFFFFFF /
		2434	#define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /!< Memory Address /
		2435
		2436	/**************** Bit definition for DMA_CMAR6 register *****************/
		2437	#define DMA_CMAR6_MA_Pos (0U)
		2438	#define DMA_CMAR6_MA_Msk (0xFFFFFFFFU << DMA_CMAR6_MA_Pos) /!< 0xFFFFFFFF /
		2439	#define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /!< Memory Address /
		2440
		2441	/**************** Bit definition for DMA_CMAR7 register *****************/
		2442	#define DMA_CMAR7_MA_Pos (0U)
		2443	#define DMA_CMAR7_MA_Msk (0xFFFFFFFFU << DMA_CMAR7_MA_Pos) /!< 0xFFFFFFFF /
		2444	#define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /!< Memory Address /
		2445
		2446	/******************************************************************************/
		2447	/* */
		2448	/* External Interrupt/Event Controller (EXTI) */
		2449	/* */
		2450	/******************************************************************************/
		2451
		2452	/***************** Bit definition for EXTI_IMR register *****************/
		2453	#define EXTI_IMR_MR0_Pos (0U)
		2454	#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /!< 0x00000001 /
		2455	#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /!< Interrupt Mask on line 0 /
		2456	#define EXTI_IMR_MR1_Pos (1U)
		2457	#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /!< 0x00000002 /
		2458	#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /!< Interrupt Mask on line 1 /
		2459	#define EXTI_IMR_MR2_Pos (2U)
		2460	#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /!< 0x00000004 /
		2461	#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /!< Interrupt Mask on line 2 /
		2462	#define EXTI_IMR_MR3_Pos (3U)
		2463	#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /!< 0x00000008 /
		2464	#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /!< Interrupt Mask on line 3 /
		2465	#define EXTI_IMR_MR4_Pos (4U)
		2466	#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /!< 0x00000010 /
		2467	#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /!< Interrupt Mask on line 4 /
		2468	#define EXTI_IMR_MR5_Pos (5U)
		2469	#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /!< 0x00000020 /
		2470	#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /!< Interrupt Mask on line 5 /
		2471	#define EXTI_IMR_MR6_Pos (6U)
		2472	#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /!< 0x00000040 /
		2473	#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /!< Interrupt Mask on line 6 /
		2474	#define EXTI_IMR_MR7_Pos (7U)
		2475	#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /!< 0x00000080 /
		2476	#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /!< Interrupt Mask on line 7 /
		2477	#define EXTI_IMR_MR8_Pos (8U)
		2478	#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /!< 0x00000100 /
		2479	#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /!< Interrupt Mask on line 8 /
		2480	#define EXTI_IMR_MR9_Pos (9U)
		2481	#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /!< 0x00000200 /
		2482	#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /!< Interrupt Mask on line 9 /
		2483	#define EXTI_IMR_MR10_Pos (10U)
		2484	#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /!< 0x00000400 /
		2485	#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /!< Interrupt Mask on line 10 /
		2486	#define EXTI_IMR_MR11_Pos (11U)
		2487	#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /!< 0x00000800 /
		2488	#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /!< Interrupt Mask on line 11 /
		2489	#define EXTI_IMR_MR12_Pos (12U)
		2490	#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /!< 0x00001000 /
		2491	#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /!< Interrupt Mask on line 12 /
		2492	#define EXTI_IMR_MR13_Pos (13U)
		2493	#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /!< 0x00002000 /
		2494	#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /!< Interrupt Mask on line 13 /
		2495	#define EXTI_IMR_MR14_Pos (14U)
		2496	#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /!< 0x00004000 /
		2497	#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /!< Interrupt Mask on line 14 /
		2498	#define EXTI_IMR_MR15_Pos (15U)
		2499	#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /!< 0x00008000 /
		2500	#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /!< Interrupt Mask on line 15 /
		2501	#define EXTI_IMR_MR16_Pos (16U)
		2502	#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /!< 0x00010000 /
		2503	#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /!< Interrupt Mask on line 16 /
		2504	#define EXTI_IMR_MR17_Pos (17U)
		2505	#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /!< 0x00020000 /
		2506	#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /!< Interrupt Mask on line 17 /
		2507	#define EXTI_IMR_MR18_Pos (18U)
		2508	#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /!< 0x00040000 /
		2509	#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /!< Interrupt Mask on line 18 /
		2510	#define EXTI_IMR_MR19_Pos (19U)
		2511	#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /!< 0x00080000 /
		2512	#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /!< Interrupt Mask on line 19 /
		2513	#define EXTI_IMR_MR20_Pos (20U)
		2514	#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /!< 0x00100000 /
		2515	#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /!< Interrupt Mask on line 20 /
		2516	#define EXTI_IMR_MR21_Pos (21U)
		2517	#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /!< 0x00200000 /
		2518	#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /!< Interrupt Mask on line 21 /
		2519	#define EXTI_IMR_MR22_Pos (22U)
		2520	#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /!< 0x00400000 /
		2521	#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /!< Interrupt Mask on line 22 /
		2522	#define EXTI_IMR_MR23_Pos (23U)
		2523	#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /!< 0x00800000 /
		2524	#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /!< Interrupt Mask on line 23 /
		2525
		2526	/* References Defines */
		2527	#define EXTI_IMR_IM0 EXTI_IMR_MR0
		2528	#define EXTI_IMR_IM1 EXTI_IMR_MR1
		2529	#define EXTI_IMR_IM2 EXTI_IMR_MR2
		2530	#define EXTI_IMR_IM3 EXTI_IMR_MR3
		2531	#define EXTI_IMR_IM4 EXTI_IMR_MR4
		2532	#define EXTI_IMR_IM5 EXTI_IMR_MR5
		2533	#define EXTI_IMR_IM6 EXTI_IMR_MR6
		2534	#define EXTI_IMR_IM7 EXTI_IMR_MR7
		2535	#define EXTI_IMR_IM8 EXTI_IMR_MR8
		2536	#define EXTI_IMR_IM9 EXTI_IMR_MR9
		2537	#define EXTI_IMR_IM10 EXTI_IMR_MR10
		2538	#define EXTI_IMR_IM11 EXTI_IMR_MR11
		2539	#define EXTI_IMR_IM12 EXTI_IMR_MR12
		2540	#define EXTI_IMR_IM13 EXTI_IMR_MR13
		2541	#define EXTI_IMR_IM14 EXTI_IMR_MR14
		2542	#define EXTI_IMR_IM15 EXTI_IMR_MR15
		2543	#define EXTI_IMR_IM16 EXTI_IMR_MR16
		2544	#define EXTI_IMR_IM17 EXTI_IMR_MR17
		2545	#define EXTI_IMR_IM18 EXTI_IMR_MR18
		2546	#define EXTI_IMR_IM19 EXTI_IMR_MR19
		2547	#define EXTI_IMR_IM20 EXTI_IMR_MR20
		2548	#define EXTI_IMR_IM21 EXTI_IMR_MR21
		2549	#define EXTI_IMR_IM22 EXTI_IMR_MR22
		2550	/* Category 3, 4 & 5 */
		2551	#define EXTI_IMR_IM23 EXTI_IMR_MR23
		2552	#define EXTI_IMR_IM_Pos (0U)
		2553	#define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /!< 0x00FFFFFF /
		2554	#define EXTI_IMR_IM EXTI_IMR_IM_Msk /!< Interrupt Mask All /
		2555
		2556	/***************** Bit definition for EXTI_EMR register *****************/
		2557	#define EXTI_EMR_MR0_Pos (0U)
		2558	#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /!< 0x00000001 /
		2559	#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /!< Event Mask on line 0 /
		2560	#define EXTI_EMR_MR1_Pos (1U)
		2561	#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /!< 0x00000002 /
		2562	#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /!< Event Mask on line 1 /
		2563	#define EXTI_EMR_MR2_Pos (2U)
		2564	#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /!< 0x00000004 /
		2565	#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /!< Event Mask on line 2 /
		2566	#define EXTI_EMR_MR3_Pos (3U)
		2567	#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /!< 0x00000008 /
		2568	#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /!< Event Mask on line 3 /
		2569	#define EXTI_EMR_MR4_Pos (4U)
		2570	#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /!< 0x00000010 /
		2571	#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /!< Event Mask on line 4 /
		2572	#define EXTI_EMR_MR5_Pos (5U)
		2573	#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /!< 0x00000020 /
		2574	#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /!< Event Mask on line 5 /
		2575	#define EXTI_EMR_MR6_Pos (6U)
		2576	#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /!< 0x00000040 /
		2577	#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /!< Event Mask on line 6 /
		2578	#define EXTI_EMR_MR7_Pos (7U)
		2579	#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /!< 0x00000080 /
		2580	#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /!< Event Mask on line 7 /
		2581	#define EXTI_EMR_MR8_Pos (8U)
		2582	#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /!< 0x00000100 /
		2583	#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /!< Event Mask on line 8 /
		2584	#define EXTI_EMR_MR9_Pos (9U)
		2585	#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /!< 0x00000200 /
		2586	#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /!< Event Mask on line 9 /
		2587	#define EXTI_EMR_MR10_Pos (10U)
		2588	#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /!< 0x00000400 /
		2589	#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /!< Event Mask on line 10 /
		2590	#define EXTI_EMR_MR11_Pos (11U)
		2591	#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /!< 0x00000800 /
		2592	#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /!< Event Mask on line 11 /
		2593	#define EXTI_EMR_MR12_Pos (12U)
		2594	#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /!< 0x00001000 /
		2595	#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /!< Event Mask on line 12 /
		2596	#define EXTI_EMR_MR13_Pos (13U)
		2597	#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /!< 0x00002000 /
		2598	#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /!< Event Mask on line 13 /
		2599	#define EXTI_EMR_MR14_Pos (14U)
		2600	#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /!< 0x00004000 /
		2601	#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /!< Event Mask on line 14 /
		2602	#define EXTI_EMR_MR15_Pos (15U)
		2603	#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /!< 0x00008000 /
		2604	#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /!< Event Mask on line 15 /
		2605	#define EXTI_EMR_MR16_Pos (16U)
		2606	#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /!< 0x00010000 /
		2607	#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /!< Event Mask on line 16 /
		2608	#define EXTI_EMR_MR17_Pos (17U)
		2609	#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /!< 0x00020000 /
		2610	#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /!< Event Mask on line 17 /
		2611	#define EXTI_EMR_MR18_Pos (18U)
		2612	#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /!< 0x00040000 /
		2613	#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /!< Event Mask on line 18 /
		2614	#define EXTI_EMR_MR19_Pos (19U)
		2615	#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /!< 0x00080000 /
		2616	#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /!< Event Mask on line 19 /
		2617	#define EXTI_EMR_MR20_Pos (20U)
		2618	#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /!< 0x00100000 /
		2619	#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /!< Event Mask on line 20 /
		2620	#define EXTI_EMR_MR21_Pos (21U)
		2621	#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /!< 0x00200000 /
		2622	#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /!< Event Mask on line 21 /
		2623	#define EXTI_EMR_MR22_Pos (22U)
		2624	#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /!< 0x00400000 /
		2625	#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /!< Event Mask on line 22 /
		2626	#define EXTI_EMR_MR23_Pos (23U)
		2627	#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /!< 0x00800000 /
		2628	#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /!< Event Mask on line 23 /
		2629
		2630	/* References Defines */
		2631	#define EXTI_EMR_EM0 EXTI_EMR_MR0
		2632	#define EXTI_EMR_EM1 EXTI_EMR_MR1
		2633	#define EXTI_EMR_EM2 EXTI_EMR_MR2
		2634	#define EXTI_EMR_EM3 EXTI_EMR_MR3
		2635	#define EXTI_EMR_EM4 EXTI_EMR_MR4
		2636	#define EXTI_EMR_EM5 EXTI_EMR_MR5
		2637	#define EXTI_EMR_EM6 EXTI_EMR_MR6
		2638	#define EXTI_EMR_EM7 EXTI_EMR_MR7
		2639	#define EXTI_EMR_EM8 EXTI_EMR_MR8
		2640	#define EXTI_EMR_EM9 EXTI_EMR_MR9
		2641	#define EXTI_EMR_EM10 EXTI_EMR_MR10
		2642	#define EXTI_EMR_EM11 EXTI_EMR_MR11
		2643	#define EXTI_EMR_EM12 EXTI_EMR_MR12
		2644	#define EXTI_EMR_EM13 EXTI_EMR_MR13
		2645	#define EXTI_EMR_EM14 EXTI_EMR_MR14
		2646	#define EXTI_EMR_EM15 EXTI_EMR_MR15
		2647	#define EXTI_EMR_EM16 EXTI_EMR_MR16
		2648	#define EXTI_EMR_EM17 EXTI_EMR_MR17
		2649	#define EXTI_EMR_EM18 EXTI_EMR_MR18
		2650	#define EXTI_EMR_EM19 EXTI_EMR_MR19
		2651	#define EXTI_EMR_EM20 EXTI_EMR_MR20
		2652	#define EXTI_EMR_EM21 EXTI_EMR_MR21
		2653	#define EXTI_EMR_EM22 EXTI_EMR_MR22
		2654	#define EXTI_EMR_EM23 EXTI_EMR_MR23
		2655
		2656	/**************** Bit definition for EXTI_RTSR register *****************/
		2657	#define EXTI_RTSR_TR0_Pos (0U)
		2658	#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /!< 0x00000001 /
		2659	#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /!< Rising trigger event configuration bit of line 0 /
		2660	#define EXTI_RTSR_TR1_Pos (1U)
		2661	#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /!< 0x00000002 /
		2662	#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /!< Rising trigger event configuration bit of line 1 /
		2663	#define EXTI_RTSR_TR2_Pos (2U)
		2664	#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /!< 0x00000004 /
		2665	#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /!< Rising trigger event configuration bit of line 2 /
		2666	#define EXTI_RTSR_TR3_Pos (3U)
		2667	#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /!< 0x00000008 /
		2668	#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /!< Rising trigger event configuration bit of line 3 /
		2669	#define EXTI_RTSR_TR4_Pos (4U)
		2670	#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /!< 0x00000010 /
		2671	#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /!< Rising trigger event configuration bit of line 4 /
		2672	#define EXTI_RTSR_TR5_Pos (5U)
		2673	#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /!< 0x00000020 /
		2674	#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /!< Rising trigger event configuration bit of line 5 /
		2675	#define EXTI_RTSR_TR6_Pos (6U)
		2676	#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /!< 0x00000040 /
		2677	#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /!< Rising trigger event configuration bit of line 6 /
		2678	#define EXTI_RTSR_TR7_Pos (7U)
		2679	#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /!< 0x00000080 /
		2680	#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /!< Rising trigger event configuration bit of line 7 /
		2681	#define EXTI_RTSR_TR8_Pos (8U)
		2682	#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /!< 0x00000100 /
		2683	#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /!< Rising trigger event configuration bit of line 8 /
		2684	#define EXTI_RTSR_TR9_Pos (9U)
		2685	#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /!< 0x00000200 /
		2686	#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /!< Rising trigger event configuration bit of line 9 /
		2687	#define EXTI_RTSR_TR10_Pos (10U)
		2688	#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /!< 0x00000400 /
		2689	#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /!< Rising trigger event configuration bit of line 10 /
		2690	#define EXTI_RTSR_TR11_Pos (11U)
		2691	#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /!< 0x00000800 /
		2692	#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /!< Rising trigger event configuration bit of line 11 /
		2693	#define EXTI_RTSR_TR12_Pos (12U)
		2694	#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /!< 0x00001000 /
		2695	#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /!< Rising trigger event configuration bit of line 12 /
		2696	#define EXTI_RTSR_TR13_Pos (13U)
		2697	#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /!< 0x00002000 /
		2698	#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /!< Rising trigger event configuration bit of line 13 /
		2699	#define EXTI_RTSR_TR14_Pos (14U)
		2700	#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /!< 0x00004000 /
		2701	#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /!< Rising trigger event configuration bit of line 14 /
		2702	#define EXTI_RTSR_TR15_Pos (15U)
		2703	#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /!< 0x00008000 /
		2704	#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /!< Rising trigger event configuration bit of line 15 /
		2705	#define EXTI_RTSR_TR16_Pos (16U)
		2706	#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /!< 0x00010000 /
		2707	#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /!< Rising trigger event configuration bit of line 16 /
		2708	#define EXTI_RTSR_TR17_Pos (17U)
		2709	#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /!< 0x00020000 /
		2710	#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /!< Rising trigger event configuration bit of line 17 /
		2711	#define EXTI_RTSR_TR18_Pos (18U)
		2712	#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /!< 0x00040000 /
		2713	#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /!< Rising trigger event configuration bit of line 18 /
		2714	#define EXTI_RTSR_TR19_Pos (19U)
		2715	#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /!< 0x00080000 /
		2716	#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /!< Rising trigger event configuration bit of line 19 /
		2717	#define EXTI_RTSR_TR20_Pos (20U)
		2718	#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /!< 0x00100000 /
		2719	#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /!< Rising trigger event configuration bit of line 20 /
		2720	#define EXTI_RTSR_TR21_Pos (21U)
		2721	#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /!< 0x00200000 /
		2722	#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /!< Rising trigger event configuration bit of line 21 /
		2723	#define EXTI_RTSR_TR22_Pos (22U)
		2724	#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /!< 0x00400000 /
		2725	#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /!< Rising trigger event configuration bit of line 22 /
		2726	#define EXTI_RTSR_TR23_Pos (23U)
		2727	#define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /!< 0x00800000 /
		2728	#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /!< Rising trigger event configuration bit of line 23 /
		2729
		2730	/* References Defines */
		2731	#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
		2732	#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
		2733	#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
		2734	#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
		2735	#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
		2736	#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
		2737	#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
		2738	#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
		2739	#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
		2740	#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
		2741	#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
		2742	#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
		2743	#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
		2744	#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
		2745	#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
		2746	#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
		2747	#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
		2748	#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
		2749	#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
		2750	#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
		2751	#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
		2752	#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
		2753	#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
		2754	#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
		2755
		2756	/**************** Bit definition for EXTI_FTSR register *****************/
		2757	#define EXTI_FTSR_TR0_Pos (0U)
		2758	#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /!< 0x00000001 /
		2759	#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /!< Falling trigger event configuration bit of line 0 /
		2760	#define EXTI_FTSR_TR1_Pos (1U)
		2761	#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /!< 0x00000002 /
		2762	#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /!< Falling trigger event configuration bit of line 1 /
		2763	#define EXTI_FTSR_TR2_Pos (2U)
		2764	#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /!< 0x00000004 /
		2765	#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /!< Falling trigger event configuration bit of line 2 /
		2766	#define EXTI_FTSR_TR3_Pos (3U)
		2767	#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /!< 0x00000008 /
		2768	#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /!< Falling trigger event configuration bit of line 3 /
		2769	#define EXTI_FTSR_TR4_Pos (4U)
		2770	#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /!< 0x00000010 /
		2771	#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /!< Falling trigger event configuration bit of line 4 /
		2772	#define EXTI_FTSR_TR5_Pos (5U)
		2773	#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /!< 0x00000020 /
		2774	#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /!< Falling trigger event configuration bit of line 5 /
		2775	#define EXTI_FTSR_TR6_Pos (6U)
		2776	#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /!< 0x00000040 /
		2777	#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /!< Falling trigger event configuration bit of line 6 /
		2778	#define EXTI_FTSR_TR7_Pos (7U)
		2779	#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /!< 0x00000080 /
		2780	#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /!< Falling trigger event configuration bit of line 7 /
		2781	#define EXTI_FTSR_TR8_Pos (8U)
		2782	#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /!< 0x00000100 /
		2783	#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /!< Falling trigger event configuration bit of line 8 /
		2784	#define EXTI_FTSR_TR9_Pos (9U)
		2785	#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /!< 0x00000200 /
		2786	#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /!< Falling trigger event configuration bit of line 9 /
		2787	#define EXTI_FTSR_TR10_Pos (10U)
		2788	#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /!< 0x00000400 /
		2789	#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /!< Falling trigger event configuration bit of line 10 /
		2790	#define EXTI_FTSR_TR11_Pos (11U)
		2791	#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /!< 0x00000800 /
		2792	#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /!< Falling trigger event configuration bit of line 11 /
		2793	#define EXTI_FTSR_TR12_Pos (12U)
		2794	#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /!< 0x00001000 /
		2795	#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /!< Falling trigger event configuration bit of line 12 /
		2796	#define EXTI_FTSR_TR13_Pos (13U)
		2797	#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /!< 0x00002000 /
		2798	#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /!< Falling trigger event configuration bit of line 13 /
		2799	#define EXTI_FTSR_TR14_Pos (14U)
		2800	#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /!< 0x00004000 /
		2801	#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /!< Falling trigger event configuration bit of line 14 /
		2802	#define EXTI_FTSR_TR15_Pos (15U)
		2803	#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /!< 0x00008000 /
		2804	#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /!< Falling trigger event configuration bit of line 15 /
		2805	#define EXTI_FTSR_TR16_Pos (16U)
		2806	#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /!< 0x00010000 /
		2807	#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /!< Falling trigger event configuration bit of line 16 /
		2808	#define EXTI_FTSR_TR17_Pos (17U)
		2809	#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /!< 0x00020000 /
		2810	#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /!< Falling trigger event configuration bit of line 17 /
		2811	#define EXTI_FTSR_TR18_Pos (18U)
		2812	#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /!< 0x00040000 /
		2813	#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /!< Falling trigger event configuration bit of line 18 /
		2814	#define EXTI_FTSR_TR19_Pos (19U)
		2815	#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /!< 0x00080000 /
		2816	#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /!< Falling trigger event configuration bit of line 19 /
		2817	#define EXTI_FTSR_TR20_Pos (20U)
		2818	#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /!< 0x00100000 /
		2819	#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /!< Falling trigger event configuration bit of line 20 /
		2820	#define EXTI_FTSR_TR21_Pos (21U)
		2821	#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /!< 0x00200000 /
		2822	#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /!< Falling trigger event configuration bit of line 21 /
		2823	#define EXTI_FTSR_TR22_Pos (22U)
		2824	#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /!< 0x00400000 /
		2825	#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /!< Falling trigger event configuration bit of line 22 /
		2826	#define EXTI_FTSR_TR23_Pos (23U)
		2827	#define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /!< 0x00800000 /
		2828	#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /!< Falling trigger event configuration bit of line 23 /
		2829
		2830	/* References Defines */
		2831	#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
		2832	#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
		2833	#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
		2834	#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
		2835	#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
		2836	#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
		2837	#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
		2838	#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
		2839	#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
		2840	#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
		2841	#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
		2842	#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
		2843	#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
		2844	#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
		2845	#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
		2846	#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
		2847	#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
		2848	#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
		2849	#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
		2850	#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
		2851	#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
		2852	#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
		2853	#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
		2854	#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
		2855
		2856	/**************** Bit definition for EXTI_SWIER register ****************/
		2857	#define EXTI_SWIER_SWIER0_Pos (0U)
		2858	#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /!< 0x00000001 /
		2859	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /!< Software Interrupt on line 0 /
		2860	#define EXTI_SWIER_SWIER1_Pos (1U)
		2861	#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /!< 0x00000002 /
		2862	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /!< Software Interrupt on line 1 /
		2863	#define EXTI_SWIER_SWIER2_Pos (2U)
		2864	#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /!< 0x00000004 /
		2865	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /!< Software Interrupt on line 2 /
		2866	#define EXTI_SWIER_SWIER3_Pos (3U)
		2867	#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /!< 0x00000008 /
		2868	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /!< Software Interrupt on line 3 /
		2869	#define EXTI_SWIER_SWIER4_Pos (4U)
		2870	#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /!< 0x00000010 /
		2871	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /!< Software Interrupt on line 4 /
		2872	#define EXTI_SWIER_SWIER5_Pos (5U)
		2873	#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /!< 0x00000020 /
		2874	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /!< Software Interrupt on line 5 /
		2875	#define EXTI_SWIER_SWIER6_Pos (6U)
		2876	#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /!< 0x00000040 /
		2877	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /!< Software Interrupt on line 6 /
		2878	#define EXTI_SWIER_SWIER7_Pos (7U)
		2879	#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /!< 0x00000080 /
		2880	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /!< Software Interrupt on line 7 /
		2881	#define EXTI_SWIER_SWIER8_Pos (8U)
		2882	#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /!< 0x00000100 /
		2883	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /!< Software Interrupt on line 8 /
		2884	#define EXTI_SWIER_SWIER9_Pos (9U)
		2885	#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /!< 0x00000200 /
		2886	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /!< Software Interrupt on line 9 /
		2887	#define EXTI_SWIER_SWIER10_Pos (10U)
		2888	#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /!< 0x00000400 /
		2889	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /!< Software Interrupt on line 10 /
		2890	#define EXTI_SWIER_SWIER11_Pos (11U)
		2891	#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /!< 0x00000800 /
		2892	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /!< Software Interrupt on line 11 /
		2893	#define EXTI_SWIER_SWIER12_Pos (12U)
		2894	#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /!< 0x00001000 /
		2895	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /!< Software Interrupt on line 12 /
		2896	#define EXTI_SWIER_SWIER13_Pos (13U)
		2897	#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /!< 0x00002000 /
		2898	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /!< Software Interrupt on line 13 /
		2899	#define EXTI_SWIER_SWIER14_Pos (14U)
		2900	#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /!< 0x00004000 /
		2901	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /!< Software Interrupt on line 14 /
		2902	#define EXTI_SWIER_SWIER15_Pos (15U)
		2903	#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /!< 0x00008000 /
		2904	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /!< Software Interrupt on line 15 /
		2905	#define EXTI_SWIER_SWIER16_Pos (16U)
		2906	#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /!< 0x00010000 /
		2907	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /!< Software Interrupt on line 16 /
		2908	#define EXTI_SWIER_SWIER17_Pos (17U)
		2909	#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /!< 0x00020000 /
		2910	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /!< Software Interrupt on line 17 /
		2911	#define EXTI_SWIER_SWIER18_Pos (18U)
		2912	#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /!< 0x00040000 /
		2913	#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /!< Software Interrupt on line 18 /
		2914	#define EXTI_SWIER_SWIER19_Pos (19U)
		2915	#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /!< 0x00080000 /
		2916	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /!< Software Interrupt on line 19 /
		2917	#define EXTI_SWIER_SWIER20_Pos (20U)
		2918	#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /!< 0x00100000 /
		2919	#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /!< Software Interrupt on line 20 /
		2920	#define EXTI_SWIER_SWIER21_Pos (21U)
		2921	#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /!< 0x00200000 /
		2922	#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /!< Software Interrupt on line 21 /
		2923	#define EXTI_SWIER_SWIER22_Pos (22U)
		2924	#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /!< 0x00400000 /
		2925	#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /!< Software Interrupt on line 22 /
		2926	#define EXTI_SWIER_SWIER23_Pos (23U)
		2927	#define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /!< 0x00800000 /
		2928	#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /!< Software Interrupt on line 23 /
		2929
		2930	/* References Defines */
		2931	#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
		2932	#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
		2933	#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
		2934	#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
		2935	#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
		2936	#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
		2937	#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
		2938	#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
		2939	#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
		2940	#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
		2941	#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
		2942	#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
		2943	#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
		2944	#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
		2945	#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
		2946	#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
		2947	#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
		2948	#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
		2949	#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
		2950	#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
		2951	#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
		2952	#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
		2953	#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
		2954	#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
		2955
		2956	/***************** Bit definition for EXTI_PR register ******************/
		2957	#define EXTI_PR_PR0_Pos (0U)
		2958	#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /!< 0x00000001 /
		2959	#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /!< Pending bit for line 0 /
		2960	#define EXTI_PR_PR1_Pos (1U)
		2961	#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /!< 0x00000002 /
		2962	#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /!< Pending bit for line 1 /
		2963	#define EXTI_PR_PR2_Pos (2U)
		2964	#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /!< 0x00000004 /
		2965	#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /!< Pending bit for line 2 /
		2966	#define EXTI_PR_PR3_Pos (3U)
		2967	#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /!< 0x00000008 /
		2968	#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /!< Pending bit for line 3 /
		2969	#define EXTI_PR_PR4_Pos (4U)
		2970	#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /!< 0x00000010 /
		2971	#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /!< Pending bit for line 4 /
		2972	#define EXTI_PR_PR5_Pos (5U)
		2973	#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /!< 0x00000020 /
		2974	#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /!< Pending bit for line 5 /
		2975	#define EXTI_PR_PR6_Pos (6U)
		2976	#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /!< 0x00000040 /
		2977	#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /!< Pending bit for line 6 /
		2978	#define EXTI_PR_PR7_Pos (7U)
		2979	#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /!< 0x00000080 /
		2980	#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /!< Pending bit for line 7 /
		2981	#define EXTI_PR_PR8_Pos (8U)
		2982	#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /!< 0x00000100 /
		2983	#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /!< Pending bit for line 8 /
		2984	#define EXTI_PR_PR9_Pos (9U)
		2985	#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /!< 0x00000200 /
		2986	#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /!< Pending bit for line 9 /
		2987	#define EXTI_PR_PR10_Pos (10U)
		2988	#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /!< 0x00000400 /
		2989	#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /!< Pending bit for line 10 /
		2990	#define EXTI_PR_PR11_Pos (11U)
		2991	#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /!< 0x00000800 /
		2992	#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /!< Pending bit for line 11 /
		2993	#define EXTI_PR_PR12_Pos (12U)
		2994	#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /!< 0x00001000 /
		2995	#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /!< Pending bit for line 12 /
		2996	#define EXTI_PR_PR13_Pos (13U)
		2997	#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /!< 0x00002000 /
		2998	#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /!< Pending bit for line 13 /
		2999	#define EXTI_PR_PR14_Pos (14U)
		3000	#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /!< 0x00004000 /
		3001	#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /!< Pending bit for line 14 /
		3002	#define EXTI_PR_PR15_Pos (15U)
		3003	#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /!< 0x00008000 /
		3004	#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /!< Pending bit for line 15 /
		3005	#define EXTI_PR_PR16_Pos (16U)
		3006	#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /!< 0x00010000 /
		3007	#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /!< Pending bit for line 16 /
		3008	#define EXTI_PR_PR17_Pos (17U)
		3009	#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /!< 0x00020000 /
		3010	#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /!< Pending bit for line 17 /
		3011	#define EXTI_PR_PR18_Pos (18U)
		3012	#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /!< 0x00040000 /
		3013	#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /!< Pending bit for line 18 /
		3014	#define EXTI_PR_PR19_Pos (19U)
		3015	#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /!< 0x00080000 /
		3016	#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /!< Pending bit for line 19 /
		3017	#define EXTI_PR_PR20_Pos (20U)
		3018	#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /!< 0x00100000 /
		3019	#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /!< Pending bit for line 20 /
		3020	#define EXTI_PR_PR21_Pos (21U)
		3021	#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /!< 0x00200000 /
		3022	#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /!< Pending bit for line 21 /
		3023	#define EXTI_PR_PR22_Pos (22U)
		3024	#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /!< 0x00400000 /
		3025	#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /!< Pending bit for line 22 /
		3026	#define EXTI_PR_PR23_Pos (23U)
		3027	#define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /!< 0x00800000 /
		3028	#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /!< Pending bit for line 23 /
		3029
		3030	/* References Defines */
		3031	#define EXTI_PR_PIF0 EXTI_PR_PR0
		3032	#define EXTI_PR_PIF1 EXTI_PR_PR1
		3033	#define EXTI_PR_PIF2 EXTI_PR_PR2
		3034	#define EXTI_PR_PIF3 EXTI_PR_PR3
		3035	#define EXTI_PR_PIF4 EXTI_PR_PR4
		3036	#define EXTI_PR_PIF5 EXTI_PR_PR5
		3037	#define EXTI_PR_PIF6 EXTI_PR_PR6
		3038	#define EXTI_PR_PIF7 EXTI_PR_PR7
		3039	#define EXTI_PR_PIF8 EXTI_PR_PR8
		3040	#define EXTI_PR_PIF9 EXTI_PR_PR9
		3041	#define EXTI_PR_PIF10 EXTI_PR_PR10
		3042	#define EXTI_PR_PIF11 EXTI_PR_PR11
		3043	#define EXTI_PR_PIF12 EXTI_PR_PR12
		3044	#define EXTI_PR_PIF13 EXTI_PR_PR13
		3045	#define EXTI_PR_PIF14 EXTI_PR_PR14
		3046	#define EXTI_PR_PIF15 EXTI_PR_PR15
		3047	#define EXTI_PR_PIF16 EXTI_PR_PR16
		3048	#define EXTI_PR_PIF17 EXTI_PR_PR17
		3049	#define EXTI_PR_PIF18 EXTI_PR_PR18
		3050	#define EXTI_PR_PIF19 EXTI_PR_PR19
		3051	#define EXTI_PR_PIF20 EXTI_PR_PR20
		3052	#define EXTI_PR_PIF21 EXTI_PR_PR21
		3053	#define EXTI_PR_PIF22 EXTI_PR_PR22
		3054	#define EXTI_PR_PIF23 EXTI_PR_PR23
		3055
		3056	/******************************************************************************/
		3057	/* */
		3058	/* FLASH, DATA EEPROM and Option Bytes Registers */
		3059	/* (FLASH, DATA_EEPROM, OB) */
		3060	/* */
		3061	/******************************************************************************/
		3062
		3063	/***************** Bit definition for FLASH_ACR register ****************/
		3064	#define FLASH_ACR_LATENCY_Pos (0U)
		3065	#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /!< 0x00000001 /
		3066	#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /!< Latency /
		3067	#define FLASH_ACR_PRFTEN_Pos (1U)
		3068	#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /!< 0x00000002 /
		3069	#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /!< Prefetch Buffer Enable /
		3070	#define FLASH_ACR_ACC64_Pos (2U)
		3071	#define FLASH_ACR_ACC64_Msk (0x1U << FLASH_ACR_ACC64_Pos) /!< 0x00000004 /
		3072	#define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /!< Access 64 bits /
		3073	#define FLASH_ACR_SLEEP_PD_Pos (3U)
		3074	#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /!< 0x00000008 /
		3075	#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /!< Flash mode during sleep mode /
		3076	#define FLASH_ACR_RUN_PD_Pos (4U)
		3077	#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /!< 0x00000010 /
		3078	#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /!< Flash mode during RUN mode /
		3079
		3080	/***************** Bit definition for FLASH_PECR register ****************/
		3081	#define FLASH_PECR_PELOCK_Pos (0U)
		3082	#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /!< 0x00000001 /
		3083	#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /!< FLASH_PECR and Flash data Lock /
		3084	#define FLASH_PECR_PRGLOCK_Pos (1U)
		3085	#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /!< 0x00000002 /
		3086	#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /!< Program matrix Lock /
		3087	#define FLASH_PECR_OPTLOCK_Pos (2U)
		3088	#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /!< 0x00000004 /
		3089	#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /!< Option byte matrix Lock /
		3090	#define FLASH_PECR_PROG_Pos (3U)
		3091	#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /!< 0x00000008 /
		3092	#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /!< Program matrix selection /
		3093	#define FLASH_PECR_DATA_Pos (4U)
		3094	#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /!< 0x00000010 /
		3095	#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /!< Data matrix selection /
		3096	#define FLASH_PECR_FTDW_Pos (8U)
		3097	#define FLASH_PECR_FTDW_Msk (0x1U << FLASH_PECR_FTDW_Pos) /!< 0x00000100 /
		3098	#define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /!< Fixed Time Data write for Word/Half Word/Byte programming /
		3099	#define FLASH_PECR_ERASE_Pos (9U)
		3100	#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /!< 0x00000200 /
		3101	#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /!< Page erasing mode /
		3102	#define FLASH_PECR_FPRG_Pos (10U)
		3103	#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /!< 0x00000400 /
		3104	#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /!< Fast Page/Half Page programming mode /
		3105	#define FLASH_PECR_PARALLBANK_Pos (15U)
		3106	#define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /!< 0x00008000 /
		3107	#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /!< Parallel Bank mode /
		3108	#define FLASH_PECR_EOPIE_Pos (16U)
		3109	#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /!< 0x00010000 /
		3110	#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /!< End of programming interrupt /
		3111	#define FLASH_PECR_ERRIE_Pos (17U)
		3112	#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /!< 0x00020000 /
		3113	#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /!< Error interrupt /
		3114	#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
		3115	#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /!< 0x00040000 /
		3116	#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /!< Launch the option byte loading /
		3117
		3118	/**************** Bit definition for FLASH_PDKEYR register ****************/
		3119	#define FLASH_PDKEYR_PDKEYR_Pos (0U)
		3120	#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /!< 0xFFFFFFFF /
		3121	#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /!< FLASH_PEC and data matrix Key /
		3122
		3123	/**************** Bit definition for FLASH_PEKEYR register ****************/
		3124	#define FLASH_PEKEYR_PEKEYR_Pos (0U)
		3125	#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /!< 0xFFFFFFFF /
		3126	#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /!< FLASH_PEC and data matrix Key /
		3127
		3128	/**************** Bit definition for FLASH_PRGKEYR register ****************/
		3129	#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
		3130	#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /!< 0xFFFFFFFF /
		3131	#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /!< Program matrix Key /
		3132
		3133	/**************** Bit definition for FLASH_OPTKEYR register ****************/
		3134	#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
		3135	#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /!< 0xFFFFFFFF /
		3136	#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /!< Option bytes matrix Key /
		3137
		3138	/**************** Bit definition for FLASH_SR register *****************/
		3139	#define FLASH_SR_BSY_Pos (0U)
		3140	#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /!< 0x00000001 /
		3141	#define FLASH_SR_BSY FLASH_SR_BSY_Msk /!< Busy /
		3142	#define FLASH_SR_EOP_Pos (1U)
		3143	#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /!< 0x00000002 /
		3144	#define FLASH_SR_EOP FLASH_SR_EOP_Msk /!< End Of Programming/
		3145	#define FLASH_SR_ENDHV_Pos (2U)
		3146	#define FLASH_SR_ENDHV_Msk (0x1U << FLASH_SR_ENDHV_Pos) /!< 0x00000004 /
		3147	#define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /!< End of high voltage /
		3148	#define FLASH_SR_READY_Pos (3U)
		3149	#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /!< 0x00000008 /
		3150	#define FLASH_SR_READY FLASH_SR_READY_Msk /!< Flash ready after low power mode /
		3151
		3152	#define FLASH_SR_WRPERR_Pos (8U)
		3153	#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /!< 0x00000100 /
		3154	#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /!< Write protected error /
		3155	#define FLASH_SR_PGAERR_Pos (9U)
		3156	#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /!< 0x00000200 /
		3157	#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /!< Programming Alignment Error /
		3158	#define FLASH_SR_SIZERR_Pos (10U)
		3159	#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /!< 0x00000400 /
		3160	#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /!< Size error /
		3161	#define FLASH_SR_OPTVERR_Pos (11U)
		3162	#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /!< 0x00000800 /
		3163	#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /!< Option validity error /
		3164	#define FLASH_SR_OPTVERRUSR_Pos (12U)
		3165	#define FLASH_SR_OPTVERRUSR_Msk (0x1U << FLASH_SR_OPTVERRUSR_Pos) /!< 0x00001000 /
		3166	#define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /!< Option User validity error /
		3167
		3168	/**************** Bit definition for FLASH_OBR register *****************/
		3169	#define FLASH_OBR_RDPRT_Pos (0U)
		3170	#define FLASH_OBR_RDPRT_Msk (0xFFU << FLASH_OBR_RDPRT_Pos) /!< 0x000000FF /
		3171	#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /!< Read Protection /
		3172	#define FLASH_OBR_BOR_LEV_Pos (16U)
		3173	#define FLASH_OBR_BOR_LEV_Msk (0xFU << FLASH_OBR_BOR_LEV_Pos) /!< 0x000F0000 /
		3174	#define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
		3175	#define FLASH_OBR_USER_Pos (20U)
		3176	#define FLASH_OBR_USER_Msk (0xFU << FLASH_OBR_USER_Pos) /!< 0x00F00000 /
		3177	#define FLASH_OBR_USER FLASH_OBR_USER_Msk /!< User Option Bytes /
		3178	#define FLASH_OBR_IWDG_SW_Pos (20U)
		3179	#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /!< 0x00100000 /
		3180	#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /!< IWDG_SW /
		3181	#define FLASH_OBR_nRST_STOP_Pos (21U)
		3182	#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /!< 0x00200000 /
		3183	#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /!< nRST_STOP /
		3184	#define FLASH_OBR_nRST_STDBY_Pos (22U)
		3185	#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /!< 0x00400000 /
		3186	#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /!< nRST_STDBY /
		3187	#define FLASH_OBR_nRST_BFB2_Pos (23U)
		3188	#define FLASH_OBR_nRST_BFB2_Msk (0x1U << FLASH_OBR_nRST_BFB2_Pos) /!< 0x00800000 /
		3189	#define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /!< BFB2 /
		3190
		3191	/**************** Bit definition for FLASH_WRPR register ****************/
		3192	#define FLASH_WRPR1_WRP_Pos (0U)
		3193	#define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /!< 0xFFFFFFFF /
		3194	#define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /!< Write Protect sectors 0 to 31 /
		3195	#define FLASH_WRPR2_WRP_Pos (0U)
		3196	#define FLASH_WRPR2_WRP_Msk (0xFFFFU << FLASH_WRPR2_WRP_Pos) /!< 0x0000FFFF /
		3197	#define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /!< Write Protect sectors 32 to 47 /
		3198	#define FLASH_WRPR3_WRP_Pos (0U)
		3199	#define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR3_WRP_Pos) /!< 0xFFFFFFFF /
		3200	#define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /!< Write Protect sectors 64 to 95 /
		3201	#define FLASH_WRPR4_WRP_Pos (0U)
		3202	#define FLASH_WRPR4_WRP_Msk (0xFFFFU << FLASH_WRPR4_WRP_Pos) /!< 0x0000FFFF /
		3203	#define FLASH_WRPR4_WRP FLASH_WRPR4_WRP_Msk /!< Write Protect sectors 96 to 111 /
		3204
		3205	/******************************************************************************/
		3206	/* */
		3207	/* General Purpose I/O */
		3208	/* */
		3209	/******************************************************************************/
		3210	/**************** Bits definition for GPIO_MODER register ***************/
		3211	#define GPIO_MODER_MODER0_Pos (0U)
		3212	#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /!< 0x00000003 /
		3213	#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
		3214	#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /!< 0x00000001 /
		3215	#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /!< 0x00000002 /
		3216
		3217	#define GPIO_MODER_MODER1_Pos (2U)
		3218	#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /!< 0x0000000C /
		3219	#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
		3220	#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /!< 0x00000004 /
		3221	#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /!< 0x00000008 /
		3222
		3223	#define GPIO_MODER_MODER2_Pos (4U)
		3224	#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /!< 0x00000030 /
		3225	#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
		3226	#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /!< 0x00000010 /
		3227	#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /!< 0x00000020 /
		3228
		3229	#define GPIO_MODER_MODER3_Pos (6U)
		3230	#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /!< 0x000000C0 /
		3231	#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
		3232	#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /!< 0x00000040 /
		3233	#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /!< 0x00000080 /
		3234
		3235	#define GPIO_MODER_MODER4_Pos (8U)
		3236	#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /!< 0x00000300 /
		3237	#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
		3238	#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /!< 0x00000100 /
		3239	#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /!< 0x00000200 /
		3240
		3241	#define GPIO_MODER_MODER5_Pos (10U)
		3242	#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /!< 0x00000C00 /
		3243	#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
		3244	#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /!< 0x00000400 /
		3245	#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /!< 0x00000800 /
		3246
		3247	#define GPIO_MODER_MODER6_Pos (12U)
		3248	#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /!< 0x00003000 /
		3249	#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
		3250	#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /!< 0x00001000 /
		3251	#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /!< 0x00002000 /
		3252
		3253	#define GPIO_MODER_MODER7_Pos (14U)
		3254	#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /!< 0x0000C000 /
		3255	#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
		3256	#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /!< 0x00004000 /
		3257	#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /!< 0x00008000 /
		3258
		3259	#define GPIO_MODER_MODER8_Pos (16U)
		3260	#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /!< 0x00030000 /
		3261	#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
		3262	#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /!< 0x00010000 /
		3263	#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /!< 0x00020000 /
		3264
		3265	#define GPIO_MODER_MODER9_Pos (18U)
		3266	#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /!< 0x000C0000 /
		3267	#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
		3268	#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /!< 0x00040000 /
		3269	#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /!< 0x00080000 /
		3270
		3271	#define GPIO_MODER_MODER10_Pos (20U)
		3272	#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /!< 0x00300000 /
		3273	#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
		3274	#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /!< 0x00100000 /
		3275	#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /!< 0x00200000 /
		3276
		3277	#define GPIO_MODER_MODER11_Pos (22U)
		3278	#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /!< 0x00C00000 /
		3279	#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
		3280	#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /!< 0x00400000 /
		3281	#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /!< 0x00800000 /
		3282
		3283	#define GPIO_MODER_MODER12_Pos (24U)
		3284	#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /!< 0x03000000 /
		3285	#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
		3286	#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /!< 0x01000000 /
		3287	#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /!< 0x02000000 /
		3288
		3289	#define GPIO_MODER_MODER13_Pos (26U)
		3290	#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /!< 0x0C000000 /
		3291	#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
		3292	#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /!< 0x04000000 /
		3293	#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /!< 0x08000000 /
		3294
		3295	#define GPIO_MODER_MODER14_Pos (28U)
		3296	#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /!< 0x30000000 /
		3297	#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
		3298	#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /!< 0x10000000 /
		3299	#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /!< 0x20000000 /
		3300
		3301	#define GPIO_MODER_MODER15_Pos (30U)
		3302	#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /!< 0xC0000000 /
		3303	#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
		3304	#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /!< 0x40000000 /
		3305	#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /!< 0x80000000 /
		3306
		3307	/**************** Bits definition for GPIO_OTYPER register **************/
		3308	#define GPIO_OTYPER_OT_0 (0x00000001U)
		3309	#define GPIO_OTYPER_OT_1 (0x00000002U)
		3310	#define GPIO_OTYPER_OT_2 (0x00000004U)
		3311	#define GPIO_OTYPER_OT_3 (0x00000008U)
		3312	#define GPIO_OTYPER_OT_4 (0x00000010U)
		3313	#define GPIO_OTYPER_OT_5 (0x00000020U)
		3314	#define GPIO_OTYPER_OT_6 (0x00000040U)
		3315	#define GPIO_OTYPER_OT_7 (0x00000080U)
		3316	#define GPIO_OTYPER_OT_8 (0x00000100U)
		3317	#define GPIO_OTYPER_OT_9 (0x00000200U)
		3318	#define GPIO_OTYPER_OT_10 (0x00000400U)
		3319	#define GPIO_OTYPER_OT_11 (0x00000800U)
		3320	#define GPIO_OTYPER_OT_12 (0x00001000U)
		3321	#define GPIO_OTYPER_OT_13 (0x00002000U)
		3322	#define GPIO_OTYPER_OT_14 (0x00004000U)
		3323	#define GPIO_OTYPER_OT_15 (0x00008000U)
		3324
		3325	/**************** Bits definition for GPIO_OSPEEDR register *************/
		3326	#define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
		3327	#define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /!< 0x00000003 /
		3328	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
		3329	#define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /!< 0x00000001 /
		3330	#define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /!< 0x00000002 /
		3331
		3332	#define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
		3333	#define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /!< 0x0000000C /
		3334	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
		3335	#define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /!< 0x00000004 /
		3336	#define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /!< 0x00000008 /
		3337
		3338	#define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
		3339	#define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /!< 0x00000030 /
		3340	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
		3341	#define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /!< 0x00000010 /
		3342	#define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /!< 0x00000020 /
		3343
		3344	#define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
		3345	#define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /!< 0x000000C0 /
		3346	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
		3347	#define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /!< 0x00000040 /
		3348	#define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /!< 0x00000080 /
		3349
		3350	#define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
		3351	#define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /!< 0x00000300 /
		3352	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
		3353	#define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /!< 0x00000100 /
		3354	#define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /!< 0x00000200 /
		3355
		3356	#define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
		3357	#define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /!< 0x00000C00 /
		3358	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
		3359	#define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /!< 0x00000400 /
		3360	#define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /!< 0x00000800 /
		3361
		3362	#define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
		3363	#define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /!< 0x00003000 /
		3364	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
		3365	#define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /!< 0x00001000 /
		3366	#define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /!< 0x00002000 /
		3367
		3368	#define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
		3369	#define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /!< 0x0000C000 /
		3370	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
		3371	#define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /!< 0x00004000 /
		3372	#define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /!< 0x00008000 /
		3373
		3374	#define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
		3375	#define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /!< 0x00030000 /
		3376	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
		3377	#define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /!< 0x00010000 /
		3378	#define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /!< 0x00020000 /
		3379
		3380	#define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
		3381	#define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /!< 0x000C0000 /
		3382	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
		3383	#define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /!< 0x00040000 /
		3384	#define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /!< 0x00080000 /
		3385
		3386	#define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
		3387	#define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /!< 0x00300000 /
		3388	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
		3389	#define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /!< 0x00100000 /
		3390	#define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /!< 0x00200000 /
		3391
		3392	#define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
		3393	#define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /!< 0x00C00000 /
		3394	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
		3395	#define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /!< 0x00400000 /
		3396	#define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /!< 0x00800000 /
		3397
		3398	#define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
		3399	#define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /!< 0x03000000 /
		3400	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
		3401	#define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /!< 0x01000000 /
		3402	#define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /!< 0x02000000 /
		3403
		3404	#define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
		3405	#define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /!< 0x0C000000 /
		3406	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
		3407	#define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /!< 0x04000000 /
		3408	#define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /!< 0x08000000 /
		3409
		3410	#define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
		3411	#define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /!< 0x30000000 /
		3412	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
		3413	#define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /!< 0x10000000 /
		3414	#define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /!< 0x20000000 /
		3415
		3416	#define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
		3417	#define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /!< 0xC0000000 /
		3418	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
		3419	#define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /!< 0x40000000 /
		3420	#define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /!< 0x80000000 /
		3421
		3422	/**************** Bits definition for GPIO_PUPDR register ***************/
		3423	#define GPIO_PUPDR_PUPDR0_Pos (0U)
		3424	#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000003 /
		3425	#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
		3426	#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000001 /
		3427	#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /!< 0x00000002 /
		3428
		3429	#define GPIO_PUPDR_PUPDR1_Pos (2U)
		3430	#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /!< 0x0000000C /
		3431	#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
		3432	#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /!< 0x00000004 /
		3433	#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /!< 0x00000008 /
		3434
		3435	#define GPIO_PUPDR_PUPDR2_Pos (4U)
		3436	#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000030 /
		3437	#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
		3438	#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000010 /
		3439	#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /!< 0x00000020 /
		3440
		3441	#define GPIO_PUPDR_PUPDR3_Pos (6U)
		3442	#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /!< 0x000000C0 /
		3443	#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
		3444	#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /!< 0x00000040 /
		3445	#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /!< 0x00000080 /
		3446
		3447	#define GPIO_PUPDR_PUPDR4_Pos (8U)
		3448	#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000300 /
		3449	#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
		3450	#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000100 /
		3451	#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /!< 0x00000200 /
		3452
		3453	#define GPIO_PUPDR_PUPDR5_Pos (10U)
		3454	#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000C00 /
		3455	#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
		3456	#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000400 /
		3457	#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /!< 0x00000800 /
		3458
		3459	#define GPIO_PUPDR_PUPDR6_Pos (12U)
		3460	#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00003000 /
		3461	#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
		3462	#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00001000 /
		3463	#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /!< 0x00002000 /
		3464
		3465	#define GPIO_PUPDR_PUPDR7_Pos (14U)
		3466	#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /!< 0x0000C000 /
		3467	#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
		3468	#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /!< 0x00004000 /
		3469	#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /!< 0x00008000 /
		3470
		3471	#define GPIO_PUPDR_PUPDR8_Pos (16U)
		3472	#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00030000 /
		3473	#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
		3474	#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00010000 /
		3475	#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /!< 0x00020000 /
		3476
		3477	#define GPIO_PUPDR_PUPDR9_Pos (18U)
		3478	#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /!< 0x000C0000 /
		3479	#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
		3480	#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /!< 0x00040000 /
		3481	#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /!< 0x00080000 /
		3482
		3483	#define GPIO_PUPDR_PUPDR10_Pos (20U)
		3484	#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00300000 /
		3485	#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
		3486	#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00100000 /
		3487	#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /!< 0x00200000 /
		3488
		3489	#define GPIO_PUPDR_PUPDR11_Pos (22U)
		3490	#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00C00000 /
		3491	#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
		3492	#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00400000 /
		3493	#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /!< 0x00800000 /
		3494
		3495	#define GPIO_PUPDR_PUPDR12_Pos (24U)
		3496	#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /!< 0x03000000 /
		3497	#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
		3498	#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /!< 0x01000000 /
		3499	#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /!< 0x02000000 /
		3500
		3501	#define GPIO_PUPDR_PUPDR13_Pos (26U)
		3502	#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /!< 0x0C000000 /
		3503	#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
		3504	#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /!< 0x04000000 /
		3505	#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /!< 0x08000000 /
		3506
		3507	#define GPIO_PUPDR_PUPDR14_Pos (28U)
		3508	#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /!< 0x30000000 /
		3509	#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
		3510	#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /!< 0x10000000 /
		3511	#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /!< 0x20000000 /
		3512	#define GPIO_PUPDR_PUPDR15_Pos (30U)
		3513	#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /!< 0xC0000000 /
		3514	#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
		3515	#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /!< 0x40000000 /
		3516	#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /!< 0x80000000 /
		3517
		3518	/**************** Bits definition for GPIO_IDR register *****************/
		3519	#define GPIO_IDR_IDR_0 (0x00000001U)
		3520	#define GPIO_IDR_IDR_1 (0x00000002U)
		3521	#define GPIO_IDR_IDR_2 (0x00000004U)
		3522	#define GPIO_IDR_IDR_3 (0x00000008U)
		3523	#define GPIO_IDR_IDR_4 (0x00000010U)
		3524	#define GPIO_IDR_IDR_5 (0x00000020U)
		3525	#define GPIO_IDR_IDR_6 (0x00000040U)
		3526	#define GPIO_IDR_IDR_7 (0x00000080U)
		3527	#define GPIO_IDR_IDR_8 (0x00000100U)
		3528	#define GPIO_IDR_IDR_9 (0x00000200U)
		3529	#define GPIO_IDR_IDR_10 (0x00000400U)
		3530	#define GPIO_IDR_IDR_11 (0x00000800U)
		3531	#define GPIO_IDR_IDR_12 (0x00001000U)
		3532	#define GPIO_IDR_IDR_13 (0x00002000U)
		3533	#define GPIO_IDR_IDR_14 (0x00004000U)
		3534	#define GPIO_IDR_IDR_15 (0x00008000U)
		3535
		3536	/**************** Bits definition for GPIO_ODR register *****************/
		3537	#define GPIO_ODR_ODR_0 (0x00000001U)
		3538	#define GPIO_ODR_ODR_1 (0x00000002U)
		3539	#define GPIO_ODR_ODR_2 (0x00000004U)
		3540	#define GPIO_ODR_ODR_3 (0x00000008U)
		3541	#define GPIO_ODR_ODR_4 (0x00000010U)
		3542	#define GPIO_ODR_ODR_5 (0x00000020U)
		3543	#define GPIO_ODR_ODR_6 (0x00000040U)
		3544	#define GPIO_ODR_ODR_7 (0x00000080U)
		3545	#define GPIO_ODR_ODR_8 (0x00000100U)
		3546	#define GPIO_ODR_ODR_9 (0x00000200U)
		3547	#define GPIO_ODR_ODR_10 (0x00000400U)
		3548	#define GPIO_ODR_ODR_11 (0x00000800U)
		3549	#define GPIO_ODR_ODR_12 (0x00001000U)
		3550	#define GPIO_ODR_ODR_13 (0x00002000U)
		3551	#define GPIO_ODR_ODR_14 (0x00004000U)
		3552	#define GPIO_ODR_ODR_15 (0x00008000U)
		3553
		3554	/**************** Bits definition for GPIO_BSRR register ****************/
		3555	#define GPIO_BSRR_BS_0 (0x00000001U)
		3556	#define GPIO_BSRR_BS_1 (0x00000002U)
		3557	#define GPIO_BSRR_BS_2 (0x00000004U)
		3558	#define GPIO_BSRR_BS_3 (0x00000008U)
		3559	#define GPIO_BSRR_BS_4 (0x00000010U)
		3560	#define GPIO_BSRR_BS_5 (0x00000020U)
		3561	#define GPIO_BSRR_BS_6 (0x00000040U)
		3562	#define GPIO_BSRR_BS_7 (0x00000080U)
		3563	#define GPIO_BSRR_BS_8 (0x00000100U)
		3564	#define GPIO_BSRR_BS_9 (0x00000200U)
		3565	#define GPIO_BSRR_BS_10 (0x00000400U)
		3566	#define GPIO_BSRR_BS_11 (0x00000800U)
		3567	#define GPIO_BSRR_BS_12 (0x00001000U)
		3568	#define GPIO_BSRR_BS_13 (0x00002000U)
		3569	#define GPIO_BSRR_BS_14 (0x00004000U)
		3570	#define GPIO_BSRR_BS_15 (0x00008000U)
		3571	#define GPIO_BSRR_BR_0 (0x00010000U)
		3572	#define GPIO_BSRR_BR_1 (0x00020000U)
		3573	#define GPIO_BSRR_BR_2 (0x00040000U)
		3574	#define GPIO_BSRR_BR_3 (0x00080000U)
		3575	#define GPIO_BSRR_BR_4 (0x00100000U)
		3576	#define GPIO_BSRR_BR_5 (0x00200000U)
		3577	#define GPIO_BSRR_BR_6 (0x00400000U)
		3578	#define GPIO_BSRR_BR_7 (0x00800000U)
		3579	#define GPIO_BSRR_BR_8 (0x01000000U)
		3580	#define GPIO_BSRR_BR_9 (0x02000000U)
		3581	#define GPIO_BSRR_BR_10 (0x04000000U)
		3582	#define GPIO_BSRR_BR_11 (0x08000000U)
		3583	#define GPIO_BSRR_BR_12 (0x10000000U)
		3584	#define GPIO_BSRR_BR_13 (0x20000000U)
		3585	#define GPIO_BSRR_BR_14 (0x40000000U)
		3586	#define GPIO_BSRR_BR_15 (0x80000000U)
		3587
		3588	/**************** Bit definition for GPIO_LCKR register ******************/
		3589	#define GPIO_LCKR_LCK0_Pos (0U)
		3590	#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /!< 0x00000001 /
		3591	#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
		3592	#define GPIO_LCKR_LCK1_Pos (1U)
		3593	#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /!< 0x00000002 /
		3594	#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
		3595	#define GPIO_LCKR_LCK2_Pos (2U)
		3596	#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /!< 0x00000004 /
		3597	#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
		3598	#define GPIO_LCKR_LCK3_Pos (3U)
		3599	#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /!< 0x00000008 /
		3600	#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
		3601	#define GPIO_LCKR_LCK4_Pos (4U)
		3602	#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /!< 0x00000010 /
		3603	#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
		3604	#define GPIO_LCKR_LCK5_Pos (5U)
		3605	#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /!< 0x00000020 /
		3606	#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
		3607	#define GPIO_LCKR_LCK6_Pos (6U)
		3608	#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /!< 0x00000040 /
		3609	#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
		3610	#define GPIO_LCKR_LCK7_Pos (7U)
		3611	#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /!< 0x00000080 /
		3612	#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
		3613	#define GPIO_LCKR_LCK8_Pos (8U)
		3614	#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /!< 0x00000100 /
		3615	#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
		3616	#define GPIO_LCKR_LCK9_Pos (9U)
		3617	#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /!< 0x00000200 /
		3618	#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
		3619	#define GPIO_LCKR_LCK10_Pos (10U)
		3620	#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /!< 0x00000400 /
		3621	#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
		3622	#define GPIO_LCKR_LCK11_Pos (11U)
		3623	#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /!< 0x00000800 /
		3624	#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
		3625	#define GPIO_LCKR_LCK12_Pos (12U)
		3626	#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /!< 0x00001000 /
		3627	#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
		3628	#define GPIO_LCKR_LCK13_Pos (13U)
		3629	#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /!< 0x00002000 /
		3630	#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
		3631	#define GPIO_LCKR_LCK14_Pos (14U)
		3632	#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /!< 0x00004000 /
		3633	#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
		3634	#define GPIO_LCKR_LCK15_Pos (15U)
		3635	#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /!< 0x00008000 /
		3636	#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
		3637	#define GPIO_LCKR_LCKK_Pos (16U)
		3638	#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /!< 0x00010000 /
		3639	#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
		3640
		3641	/**************** Bit definition for GPIO_AFRL register ******************/
		3642	#define GPIO_AFRL_AFRL0_Pos (0U)
		3643	#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /!< 0x0000000F /
		3644	#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
		3645	#define GPIO_AFRL_AFRL1_Pos (4U)
		3646	#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /!< 0x000000F0 /
		3647	#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
		3648	#define GPIO_AFRL_AFRL2_Pos (8U)
		3649	#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /!< 0x00000F00 /
		3650	#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
		3651	#define GPIO_AFRL_AFRL3_Pos (12U)
		3652	#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /!< 0x0000F000 /
		3653	#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
		3654	#define GPIO_AFRL_AFRL4_Pos (16U)
		3655	#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /!< 0x000F0000 /
		3656	#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
		3657	#define GPIO_AFRL_AFRL5_Pos (20U)
		3658	#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /!< 0x00F00000 /
		3659	#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
		3660	#define GPIO_AFRL_AFRL6_Pos (24U)
		3661	#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /!< 0x0F000000 /
		3662	#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
		3663	#define GPIO_AFRL_AFRL7_Pos (28U)
		3664	#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /!< 0xF0000000 /
		3665	#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
		3666
		3667	/**************** Bit definition for GPIO_AFRH register ******************/
		3668	#define GPIO_AFRH_AFRH0_Pos (0U)
		3669	#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /!< 0x0000000F /
		3670	#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
		3671	#define GPIO_AFRH_AFRH1_Pos (4U)
		3672	#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /!< 0x000000F0 /
		3673	#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
		3674	#define GPIO_AFRH_AFRH2_Pos (8U)
		3675	#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /!< 0x00000F00 /
		3676	#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
		3677	#define GPIO_AFRH_AFRH3_Pos (12U)
		3678	#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /!< 0x0000F000 /
		3679	#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
		3680	#define GPIO_AFRH_AFRH4_Pos (16U)
		3681	#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /!< 0x000F0000 /
		3682	#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
		3683	#define GPIO_AFRH_AFRH5_Pos (20U)
		3684	#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /!< 0x00F00000 /
		3685	#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
		3686	#define GPIO_AFRH_AFRH6_Pos (24U)
		3687	#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /!< 0x0F000000 /
		3688	#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
		3689	#define GPIO_AFRH_AFRH7_Pos (28U)
		3690	#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /!< 0xF0000000 /
		3691	#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
		3692
		3693	/**************** Bit definition for GPIO_BRR register *******************/
		3694	#define GPIO_BRR_BR_0 (0x00000001U)
		3695	#define GPIO_BRR_BR_1 (0x00000002U)
		3696	#define GPIO_BRR_BR_2 (0x00000004U)
		3697	#define GPIO_BRR_BR_3 (0x00000008U)
		3698	#define GPIO_BRR_BR_4 (0x00000010U)
		3699	#define GPIO_BRR_BR_5 (0x00000020U)
		3700	#define GPIO_BRR_BR_6 (0x00000040U)
		3701	#define GPIO_BRR_BR_7 (0x00000080U)
		3702	#define GPIO_BRR_BR_8 (0x00000100U)
		3703	#define GPIO_BRR_BR_9 (0x00000200U)
		3704	#define GPIO_BRR_BR_10 (0x00000400U)
		3705	#define GPIO_BRR_BR_11 (0x00000800U)
		3706	#define GPIO_BRR_BR_12 (0x00001000U)
		3707	#define GPIO_BRR_BR_13 (0x00002000U)
		3708	#define GPIO_BRR_BR_14 (0x00004000U)
		3709	#define GPIO_BRR_BR_15 (0x00008000U)
		3710
		3711	/******************************************************************************/
		3712	/* */
		3713	/* Inter-integrated Circuit Interface (I2C) */
		3714	/* */
		3715	/******************************************************************************/
		3716
		3717	/***************** Bit definition for I2C_CR1 register ******************/
		3718	#define I2C_CR1_PE_Pos (0U)
		3719	#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /!< 0x00000001 /
		3720	#define I2C_CR1_PE I2C_CR1_PE_Msk /!< Peripheral Enable /
		3721	#define I2C_CR1_SMBUS_Pos (1U)
		3722	#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /!< 0x00000002 /
		3723	#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /!< SMBus Mode /
		3724	#define I2C_CR1_SMBTYPE_Pos (3U)
		3725	#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /!< 0x00000008 /
		3726	#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /!< SMBus Type /
		3727	#define I2C_CR1_ENARP_Pos (4U)
		3728	#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /!< 0x00000010 /
		3729	#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /!< ARP Enable /
		3730	#define I2C_CR1_ENPEC_Pos (5U)
		3731	#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /!< 0x00000020 /
		3732	#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /!< PEC Enable /
		3733	#define I2C_CR1_ENGC_Pos (6U)
		3734	#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /!< 0x00000040 /
		3735	#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /!< General Call Enable /
		3736	#define I2C_CR1_NOSTRETCH_Pos (7U)
		3737	#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /!< 0x00000080 /
		3738	#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /!< Clock Stretching Disable (Slave mode) /
		3739	#define I2C_CR1_START_Pos (8U)
		3740	#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /!< 0x00000100 /
		3741	#define I2C_CR1_START I2C_CR1_START_Msk /!< Start Generation /
		3742	#define I2C_CR1_STOP_Pos (9U)
		3743	#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /!< 0x00000200 /
		3744	#define I2C_CR1_STOP I2C_CR1_STOP_Msk /!< Stop Generation /
		3745	#define I2C_CR1_ACK_Pos (10U)
		3746	#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /!< 0x00000400 /
		3747	#define I2C_CR1_ACK I2C_CR1_ACK_Msk /!< Acknowledge Enable /
		3748	#define I2C_CR1_POS_Pos (11U)
		3749	#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /!< 0x00000800 /
		3750	#define I2C_CR1_POS I2C_CR1_POS_Msk /!< Acknowledge/PEC Position (for data reception) /
		3751	#define I2C_CR1_PEC_Pos (12U)
		3752	#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /!< 0x00001000 /
		3753	#define I2C_CR1_PEC I2C_CR1_PEC_Msk /!< Packet Error Checking /
		3754	#define I2C_CR1_ALERT_Pos (13U)
		3755	#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /!< 0x00002000 /
		3756	#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /!< SMBus Alert /
		3757	#define I2C_CR1_SWRST_Pos (15U)
		3758	#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /!< 0x00008000 /
		3759	#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /!< Software Reset /
		3760
		3761	/***************** Bit definition for I2C_CR2 register ******************/
		3762	#define I2C_CR2_FREQ_Pos (0U)
		3763	#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /!< 0x0000003F /
		3764	#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
		3765	#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /!< 0x00000001 /
		3766	#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /!< 0x00000002 /
		3767	#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /!< 0x00000004 /
		3768	#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /!< 0x00000008 /
		3769	#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /!< 0x00000010 /
		3770	#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /!< 0x00000020 /
		3771
		3772	#define I2C_CR2_ITERREN_Pos (8U)
		3773	#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /!< 0x00000100 /
		3774	#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /!< Error Interrupt Enable /
		3775	#define I2C_CR2_ITEVTEN_Pos (9U)
		3776	#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /!< 0x00000200 /
		3777	#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /!< Event Interrupt Enable /
		3778	#define I2C_CR2_ITBUFEN_Pos (10U)
		3779	#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /!< 0x00000400 /
		3780	#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /!< Buffer Interrupt Enable /
		3781	#define I2C_CR2_DMAEN_Pos (11U)
		3782	#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /!< 0x00000800 /
		3783	#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /!< DMA Requests Enable /
		3784	#define I2C_CR2_LAST_Pos (12U)
		3785	#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /!< 0x00001000 /
		3786	#define I2C_CR2_LAST I2C_CR2_LAST_Msk /!< DMA Last Transfer /
		3787
		3788	/***************** Bit definition for I2C_OAR1 register *****************/
		3789	#define I2C_OAR1_ADD1_7 (0x000000FEU) /!< Interface Address /
		3790	#define I2C_OAR1_ADD8_9 (0x00000300U) /!< Interface Address /
		3791
		3792	#define I2C_OAR1_ADD0_Pos (0U)
		3793	#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /!< 0x00000001 /
		3794	#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /!< Bit 0 /
		3795	#define I2C_OAR1_ADD1_Pos (1U)
		3796	#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /!< 0x00000002 /
		3797	#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /!< Bit 1 /
		3798	#define I2C_OAR1_ADD2_Pos (2U)
		3799	#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /!< 0x00000004 /
		3800	#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /!< Bit 2 /
		3801	#define I2C_OAR1_ADD3_Pos (3U)
		3802	#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /!< 0x00000008 /
		3803	#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /!< Bit 3 /
		3804	#define I2C_OAR1_ADD4_Pos (4U)
		3805	#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /!< 0x00000010 /
		3806	#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /!< Bit 4 /
		3807	#define I2C_OAR1_ADD5_Pos (5U)
		3808	#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /!< 0x00000020 /
		3809	#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /!< Bit 5 /
		3810	#define I2C_OAR1_ADD6_Pos (6U)
		3811	#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /!< 0x00000040 /
		3812	#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /!< Bit 6 /
		3813	#define I2C_OAR1_ADD7_Pos (7U)
		3814	#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /!< 0x00000080 /
		3815	#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /!< Bit 7 /
		3816	#define I2C_OAR1_ADD8_Pos (8U)
		3817	#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /!< 0x00000100 /
		3818	#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /!< Bit 8 /
		3819	#define I2C_OAR1_ADD9_Pos (9U)
		3820	#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /!< 0x00000200 /
		3821	#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /!< Bit 9 /
		3822
		3823	#define I2C_OAR1_ADDMODE_Pos (15U)
		3824	#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /!< 0x00008000 /
		3825	#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /!< Addressing Mode (Slave mode) /
		3826
		3827	/***************** Bit definition for I2C_OAR2 register *****************/
		3828	#define I2C_OAR2_ENDUAL_Pos (0U)
		3829	#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /!< 0x00000001 /
		3830	#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /!< Dual addressing mode enable /
		3831	#define I2C_OAR2_ADD2_Pos (1U)
		3832	#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /!< 0x000000FE /
		3833	#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /!< Interface address /
		3834
		3835	/****************** Bit definition for I2C_DR register ******************/
		3836	#define I2C_DR_DR_Pos (0U)
		3837	#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /!< 0x000000FF /
		3838	#define I2C_DR_DR I2C_DR_DR_Msk /!< 8-bit Data Register /
		3839
		3840	/***************** Bit definition for I2C_SR1 register ******************/
		3841	#define I2C_SR1_SB_Pos (0U)
		3842	#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /!< 0x00000001 /
		3843	#define I2C_SR1_SB I2C_SR1_SB_Msk /!< Start Bit (Master mode) /
		3844	#define I2C_SR1_ADDR_Pos (1U)
		3845	#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /!< 0x00000002 /
		3846	#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /!< Address sent (master mode)/matched (slave mode) /
		3847	#define I2C_SR1_BTF_Pos (2U)
		3848	#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /!< 0x00000004 /
		3849	#define I2C_SR1_BTF I2C_SR1_BTF_Msk /!< Byte Transfer Finished /
		3850	#define I2C_SR1_ADD10_Pos (3U)
		3851	#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /!< 0x00000008 /
		3852	#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /!< 10-bit header sent (Master mode) /
		3853	#define I2C_SR1_STOPF_Pos (4U)
		3854	#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /!< 0x00000010 /
		3855	#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /!< Stop detection (Slave mode) /
		3856	#define I2C_SR1_RXNE_Pos (6U)
		3857	#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /!< 0x00000040 /
		3858	#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /!< Data Register not Empty (receivers) /
		3859	#define I2C_SR1_TXE_Pos (7U)
		3860	#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /!< 0x00000080 /
		3861	#define I2C_SR1_TXE I2C_SR1_TXE_Msk /!< Data Register Empty (transmitters) /
		3862	#define I2C_SR1_BERR_Pos (8U)
		3863	#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /!< 0x00000100 /
		3864	#define I2C_SR1_BERR I2C_SR1_BERR_Msk /!< Bus Error /
		3865	#define I2C_SR1_ARLO_Pos (9U)
		3866	#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /!< 0x00000200 /
		3867	#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /!< Arbitration Lost (master mode) /
		3868	#define I2C_SR1_AF_Pos (10U)
		3869	#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /!< 0x00000400 /
		3870	#define I2C_SR1_AF I2C_SR1_AF_Msk /!< Acknowledge Failure /
		3871	#define I2C_SR1_OVR_Pos (11U)
		3872	#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /!< 0x00000800 /
		3873	#define I2C_SR1_OVR I2C_SR1_OVR_Msk /!< Overrun/Underrun /
		3874	#define I2C_SR1_PECERR_Pos (12U)
		3875	#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /!< 0x00001000 /
		3876	#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /!< PEC Error in reception /
		3877	#define I2C_SR1_TIMEOUT_Pos (14U)
		3878	#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /!< 0x00004000 /
		3879	#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /!< Timeout or Tlow Error /
		3880	#define I2C_SR1_SMBALERT_Pos (15U)
		3881	#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /!< 0x00008000 /
		3882	#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /!< SMBus Alert /
		3883
		3884	/***************** Bit definition for I2C_SR2 register ******************/
		3885	#define I2C_SR2_MSL_Pos (0U)
		3886	#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /!< 0x00000001 /
		3887	#define I2C_SR2_MSL I2C_SR2_MSL_Msk /!< Master/Slave /
		3888	#define I2C_SR2_BUSY_Pos (1U)
		3889	#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /!< 0x00000002 /
		3890	#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /!< Bus Busy /
		3891	#define I2C_SR2_TRA_Pos (2U)
		3892	#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /!< 0x00000004 /
		3893	#define I2C_SR2_TRA I2C_SR2_TRA_Msk /!< Transmitter/Receiver /
		3894	#define I2C_SR2_GENCALL_Pos (4U)
		3895	#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /!< 0x00000010 /
		3896	#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /!< General Call Address (Slave mode) /
		3897	#define I2C_SR2_SMBDEFAULT_Pos (5U)
		3898	#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /!< 0x00000020 /
		3899	#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /!< SMBus Device Default Address (Slave mode) /
		3900	#define I2C_SR2_SMBHOST_Pos (6U)
		3901	#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /!< 0x00000040 /
		3902	#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /!< SMBus Host Header (Slave mode) /
		3903	#define I2C_SR2_DUALF_Pos (7U)
		3904	#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /!< 0x00000080 /
		3905	#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /!< Dual Flag (Slave mode) /
		3906	#define I2C_SR2_PEC_Pos (8U)
		3907	#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /!< 0x0000FF00 /
		3908	#define I2C_SR2_PEC I2C_SR2_PEC_Msk /!< Packet Error Checking Register /
		3909
		3910	/***************** Bit definition for I2C_CCR register ******************/
		3911	#define I2C_CCR_CCR_Pos (0U)
		3912	#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /!< 0x00000FFF /
		3913	#define I2C_CCR_CCR I2C_CCR_CCR_Msk /!< Clock Control Register in Fast/Standard mode (Master mode) /
		3914	#define I2C_CCR_DUTY_Pos (14U)
		3915	#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /!< 0x00004000 /
		3916	#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /!< Fast Mode Duty Cycle /
		3917	#define I2C_CCR_FS_Pos (15U)
		3918	#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /!< 0x00008000 /
		3919	#define I2C_CCR_FS I2C_CCR_FS_Msk /!< I2C Master Mode Selection /
		3920
		3921	/**************** Bit definition for I2C_TRISE register *****************/
		3922	#define I2C_TRISE_TRISE_Pos (0U)
		3923	#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /!< 0x0000003F /
		3924	#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
		3925
		3926	/******************************************************************************/
		3927	/* */
		3928	/* Independent WATCHDOG (IWDG) */
		3929	/* */
		3930	/******************************************************************************/
		3931
		3932	/***************** Bit definition for IWDG_KR register ******************/
		3933	#define IWDG_KR_KEY_Pos (0U)
		3934	#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /!< 0x0000FFFF /
		3935	#define IWDG_KR_KEY IWDG_KR_KEY_Msk /!< Key value (write only, read 0000h) /
		3936
		3937	/***************** Bit definition for IWDG_PR register ******************/
		3938	#define IWDG_PR_PR_Pos (0U)
		3939	#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /!< 0x00000007 /
		3940	#define IWDG_PR_PR IWDG_PR_PR_Msk /!< PR[2:0] (Prescaler divider) /
		3941	#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /!< 0x00000001 /
		3942	#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /!< 0x00000002 /
		3943	#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /!< 0x00000004 /
		3944
		3945	/***************** Bit definition for IWDG_RLR register *****************/
		3946	#define IWDG_RLR_RL_Pos (0U)
		3947	#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /!< 0x00000FFF /
		3948	#define IWDG_RLR_RL IWDG_RLR_RL_Msk /!< Watchdog counter reload value /
		3949
		3950	/***************** Bit definition for IWDG_SR register ******************/
		3951	#define IWDG_SR_PVU_Pos (0U)
		3952	#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /!< 0x00000001 /
		3953	#define IWDG_SR_PVU IWDG_SR_PVU_Msk /!< Watchdog prescaler value update /
		3954	#define IWDG_SR_RVU_Pos (1U)
		3955	#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /!< 0x00000002 /
		3956	#define IWDG_SR_RVU IWDG_SR_RVU_Msk /!< Watchdog counter reload value update /
		3957
		3958	/******************************************************************************/
		3959	/* */
		3960	/* Power Control (PWR) */
		3961	/* */
		3962	/******************************************************************************/
		3963
		3964	#define PWR_PVD_SUPPORT /!< PWR feature available only on specific devices: Power Voltage Detection feature /
		3965
		3966	/****************** Bit definition for PWR_CR register ******************/
		3967	#define PWR_CR_LPSDSR_Pos (0U)
		3968	#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /!< 0x00000001 /
		3969	#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /!< Low-power deepsleep/sleep/low power run /
		3970	#define PWR_CR_PDDS_Pos (1U)
		3971	#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /!< 0x00000002 /
		3972	#define PWR_CR_PDDS PWR_CR_PDDS_Msk /!< Power Down Deepsleep /
		3973	#define PWR_CR_CWUF_Pos (2U)
		3974	#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /!< 0x00000004 /
		3975	#define PWR_CR_CWUF PWR_CR_CWUF_Msk /!< Clear Wakeup Flag /
		3976	#define PWR_CR_CSBF_Pos (3U)
		3977	#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /!< 0x00000008 /
		3978	#define PWR_CR_CSBF PWR_CR_CSBF_Msk /!< Clear Standby Flag /
		3979	#define PWR_CR_PVDE_Pos (4U)
		3980	#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /!< 0x00000010 /
		3981	#define PWR_CR_PVDE PWR_CR_PVDE_Msk /!< Power Voltage Detector Enable /
		3982
		3983	#define PWR_CR_PLS_Pos (5U)
		3984	#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /!< 0x000000E0 /
		3985	#define PWR_CR_PLS PWR_CR_PLS_Msk /!< PLS[2:0] bits (PVD Level Selection) /
		3986	#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /!< 0x00000020 /
		3987	#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /!< 0x00000040 /
		3988	#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /!< 0x00000080 /
		3989
		3990	/!< PVD level configuration /
		3991	#define PWR_CR_PLS_LEV0 (0x00000000U) /!< PVD level 0 /
		3992	#define PWR_CR_PLS_LEV1 (0x00000020U) /!< PVD level 1 /
		3993	#define PWR_CR_PLS_LEV2 (0x00000040U) /!< PVD level 2 /
		3994	#define PWR_CR_PLS_LEV3 (0x00000060U) /!< PVD level 3 /
		3995	#define PWR_CR_PLS_LEV4 (0x00000080U) /!< PVD level 4 /
		3996	#define PWR_CR_PLS_LEV5 (0x000000A0U) /!< PVD level 5 /
		3997	#define PWR_CR_PLS_LEV6 (0x000000C0U) /!< PVD level 6 /
		3998	#define PWR_CR_PLS_LEV7 (0x000000E0U) /!< PVD level 7 /
		3999
		4000	#define PWR_CR_DBP_Pos (8U)
		4001	#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /!< 0x00000100 /
		4002	#define PWR_CR_DBP PWR_CR_DBP_Msk /!< Disable Backup Domain write protection /
		4003	#define PWR_CR_ULP_Pos (9U)
		4004	#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /!< 0x00000200 /
		4005	#define PWR_CR_ULP PWR_CR_ULP_Msk /!< Ultra Low Power mode /
		4006	#define PWR_CR_FWU_Pos (10U)
		4007	#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /!< 0x00000400 /
		4008	#define PWR_CR_FWU PWR_CR_FWU_Msk /!< Fast wakeup /
		4009
		4010	#define PWR_CR_VOS_Pos (11U)
		4011	#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /!< 0x00001800 /
		4012	#define PWR_CR_VOS PWR_CR_VOS_Msk /!< VOS[1:0] bits (Voltage scaling range selection) /
		4013	#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /!< 0x00000800 /
		4014	#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /!< 0x00001000 /
		4015	#define PWR_CR_LPRUN_Pos (14U)
		4016	#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /!< 0x00004000 /
		4017	#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /!< Low power run mode /
		4018
		4019	/***************** Bit definition for PWR_CSR register ******************/
		4020	#define PWR_CSR_WUF_Pos (0U)
		4021	#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /!< 0x00000001 /
		4022	#define PWR_CSR_WUF PWR_CSR_WUF_Msk /!< Wakeup Flag /
		4023	#define PWR_CSR_SBF_Pos (1U)
		4024	#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /!< 0x00000002 /
		4025	#define PWR_CSR_SBF PWR_CSR_SBF_Msk /!< Standby Flag /
		4026	#define PWR_CSR_PVDO_Pos (2U)
		4027	#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /!< 0x00000004 /
		4028	#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /!< PVD Output /
		4029	#define PWR_CSR_VREFINTRDYF_Pos (3U)
		4030	#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /!< 0x00000008 /
		4031	#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /!< Internal voltage reference (VREFINT) ready flag /
		4032	#define PWR_CSR_VOSF_Pos (4U)
		4033	#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /!< 0x00000010 /
		4034	#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /!< Voltage Scaling select flag /
		4035	#define PWR_CSR_REGLPF_Pos (5U)
		4036	#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /!< 0x00000020 /
		4037	#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /!< Regulator LP flag /
		4038
		4039	#define PWR_CSR_EWUP1_Pos (8U)
		4040	#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /!< 0x00000100 /
		4041	#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /!< Enable WKUP pin 1 /
		4042	#define PWR_CSR_EWUP2_Pos (9U)
		4043	#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /!< 0x00000200 /
		4044	#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /!< Enable WKUP pin 2 /
		4045	#define PWR_CSR_EWUP3_Pos (10U)
		4046	#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /!< 0x00000400 /
		4047	#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /!< Enable WKUP pin 3 /
		4048
		4049	/******************************************************************************/
		4050	/* */
		4051	/* Reset and Clock Control (RCC) */
		4052	/* */
		4053	/******************************************************************************/
		4054	/*
		4055	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
		4056	*/
		4057	#define RCC_LSECSS_SUPPORT /!< LSE CSS feature support /
		4058
		4059	/****************** Bit definition for RCC_CR register ******************/
		4060	#define RCC_CR_HSION_Pos (0U)
		4061	#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /!< 0x00000001 /
		4062	#define RCC_CR_HSION RCC_CR_HSION_Msk /!< Internal High Speed clock enable /
		4063	#define RCC_CR_HSIRDY_Pos (1U)
		4064	#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /!< 0x00000002 /
		4065	#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /!< Internal High Speed clock ready flag /
		4066
		4067	#define RCC_CR_MSION_Pos (8U)
		4068	#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /!< 0x00000100 /
		4069	#define RCC_CR_MSION RCC_CR_MSION_Msk /!< Internal Multi Speed clock enable /
		4070	#define RCC_CR_MSIRDY_Pos (9U)
		4071	#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /!< 0x00000200 /
		4072	#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /!< Internal Multi Speed clock ready flag /
		4073
		4074	#define RCC_CR_HSEON_Pos (16U)
		4075	#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /!< 0x00010000 /
		4076	#define RCC_CR_HSEON RCC_CR_HSEON_Msk /!< External High Speed clock enable /
		4077	#define RCC_CR_HSERDY_Pos (17U)
		4078	#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /!< 0x00020000 /
		4079	#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /!< External High Speed clock ready flag /
		4080	#define RCC_CR_HSEBYP_Pos (18U)
		4081	#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /!< 0x00040000 /
		4082	#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /!< External High Speed clock Bypass /
		4083
		4084	#define RCC_CR_PLLON_Pos (24U)
		4085	#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /!< 0x01000000 /
		4086	#define RCC_CR_PLLON RCC_CR_PLLON_Msk /!< PLL enable /
		4087	#define RCC_CR_PLLRDY_Pos (25U)
		4088	#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /!< 0x02000000 /
		4089	#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /!< PLL clock ready flag /
		4090	#define RCC_CR_CSSON_Pos (28U)
		4091	#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /!< 0x10000000 /
		4092	#define RCC_CR_CSSON RCC_CR_CSSON_Msk /!< Clock Security System enable /
		4093
		4094	#define RCC_CR_RTCPRE_Pos (29U)
		4095	#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /!< 0x60000000 /
		4096	#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /!< RTC Prescaler /
		4097	#define RCC_CR_RTCPRE_0 (0x20000000U) /!< Bit0 /
		4098	#define RCC_CR_RTCPRE_1 (0x40000000U) /!< Bit1 /
		4099
		4100	/****************** Bit definition for RCC_ICSCR register ***************/
		4101	#define RCC_ICSCR_HSICAL_Pos (0U)
		4102	#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /!< 0x000000FF /
		4103	#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /!< Internal High Speed clock Calibration /
		4104	#define RCC_ICSCR_HSITRIM_Pos (8U)
		4105	#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /!< 0x00001F00 /
		4106	#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /!< Internal High Speed clock trimming /
		4107
		4108	#define RCC_ICSCR_MSIRANGE_Pos (13U)
		4109	#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x0000E000 /
		4110	#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /!< Internal Multi Speed clock Range /
		4111	#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00000000 /
		4112	#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00002000 /
		4113	#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00004000 /
		4114	#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00006000 /
		4115	#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x00008000 /
		4116	#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x0000A000 /
		4117	#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /!< 0x0000C000 /
		4118	#define RCC_ICSCR_MSICAL_Pos (16U)
		4119	#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /!< 0x00FF0000 /
		4120	#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /!< Internal Multi Speed clock Calibration /
		4121	#define RCC_ICSCR_MSITRIM_Pos (24U)
		4122	#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /!< 0xFF000000 /
		4123	#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /!< Internal Multi Speed clock trimming /
		4124
		4125	/****************** Bit definition for RCC_CFGR register ****************/
		4126	#define RCC_CFGR_SW_Pos (0U)
		4127	#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /!< 0x00000003 /
		4128	#define RCC_CFGR_SW RCC_CFGR_SW_Msk /!< SW[1:0] bits (System clock Switch) /
		4129	#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /!< 0x00000001 /
		4130	#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /!< 0x00000002 /
		4131
		4132	/!< SW configuration /
		4133	#define RCC_CFGR_SW_MSI (0x00000000U) /!< MSI selected as system clock /
		4134	#define RCC_CFGR_SW_HSI (0x00000001U) /!< HSI selected as system clock /
		4135	#define RCC_CFGR_SW_HSE (0x00000002U) /!< HSE selected as system clock /
		4136	#define RCC_CFGR_SW_PLL (0x00000003U) /!< PLL selected as system clock /
		4137
		4138	#define RCC_CFGR_SWS_Pos (2U)
		4139	#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /!< 0x0000000C /
		4140	#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /!< SWS[1:0] bits (System Clock Switch Status) /
		4141	#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /!< 0x00000004 /
		4142	#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /!< 0x00000008 /
		4143
		4144	/!< SWS configuration /
		4145	#define RCC_CFGR_SWS_MSI (0x00000000U) /!< MSI oscillator used as system clock /
		4146	#define RCC_CFGR_SWS_HSI (0x00000004U) /!< HSI oscillator used as system clock /
		4147	#define RCC_CFGR_SWS_HSE (0x00000008U) /!< HSE oscillator used as system clock /
		4148	#define RCC_CFGR_SWS_PLL (0x0000000CU) /!< PLL used as system clock /
		4149
		4150	#define RCC_CFGR_HPRE_Pos (4U)
		4151	#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /!< 0x000000F0 /
		4152	#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /!< HPRE[3:0] bits (AHB prescaler) /
		4153	#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /!< 0x00000010 /
		4154	#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /!< 0x00000020 /
		4155	#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /!< 0x00000040 /
		4156	#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /!< 0x00000080 /
		4157
		4158	/!< HPRE configuration /
		4159	#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /!< SYSCLK not divided /
		4160	#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /!< SYSCLK divided by 2 /
		4161	#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /!< SYSCLK divided by 4 /
		4162	#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /!< SYSCLK divided by 8 /
		4163	#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /!< SYSCLK divided by 16 /
		4164	#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /!< SYSCLK divided by 64 /
		4165	#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /!< SYSCLK divided by 128 /
		4166	#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /!< SYSCLK divided by 256 /
		4167	#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /!< SYSCLK divided by 512 /
		4168
		4169	#define RCC_CFGR_PPRE1_Pos (8U)
		4170	#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /!< 0x00000700 /
		4171	#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /!< PRE1[2:0] bits (APB1 prescaler) /
		4172	#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /!< 0x00000100 /
		4173	#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /!< 0x00000200 /
		4174	#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /!< 0x00000400 /
		4175
		4176	/!< PPRE1 configuration /
		4177	#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /!< HCLK not divided /
		4178	#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /!< HCLK divided by 2 /
		4179	#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /!< HCLK divided by 4 /
		4180	#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /!< HCLK divided by 8 /
		4181	#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /!< HCLK divided by 16 /
		4182
		4183	#define RCC_CFGR_PPRE2_Pos (11U)
		4184	#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /!< 0x00003800 /
		4185	#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /!< PRE2[2:0] bits (APB2 prescaler) /
		4186	#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /!< 0x00000800 /
		4187	#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /!< 0x00001000 /
		4188	#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /!< 0x00002000 /
		4189
		4190	/!< PPRE2 configuration /
		4191	#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /!< HCLK not divided /
		4192	#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /!< HCLK divided by 2 /
		4193	#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /!< HCLK divided by 4 /
		4194	#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /!< HCLK divided by 8 /
		4195	#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /!< HCLK divided by 16 /
		4196
		4197	/!< PLL entry clock source/
		4198	#define RCC_CFGR_PLLSRC_Pos (16U)
		4199	#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /!< 0x00010000 /
		4200	#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /!< PLL entry clock source /
		4201
		4202	#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /!< HSI as PLL entry clock source /
		4203	#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /!< HSE as PLL entry clock source /
		4204
		4205
		4206	/!< PLLMUL configuration /
		4207	#define RCC_CFGR_PLLMUL_Pos (18U)
		4208	#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /!< 0x003C0000 /
		4209	#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /!< PLLMUL[3:0] bits (PLL multiplication factor) /
		4210	#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /!< 0x00040000 /
		4211	#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /!< 0x00080000 /
		4212	#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /!< 0x00100000 /
		4213	#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /!< 0x00200000 /
		4214
		4215	/!< PLLMUL configuration /
		4216	#define RCC_CFGR_PLLMUL3 (0x00000000U) /!< PLL input clock 3 */
		4217	#define RCC_CFGR_PLLMUL4 (0x00040000U) /!< PLL input clock 4 */
		4218	#define RCC_CFGR_PLLMUL6 (0x00080000U) /!< PLL input clock 6 */
		4219	#define RCC_CFGR_PLLMUL8 (0x000C0000U) /!< PLL input clock 8 */
		4220	#define RCC_CFGR_PLLMUL12 (0x00100000U) /!< PLL input clock 12 */
		4221	#define RCC_CFGR_PLLMUL16 (0x00140000U) /!< PLL input clock 16 */
		4222	#define RCC_CFGR_PLLMUL24 (0x00180000U) /!< PLL input clock 24 */
		4223	#define RCC_CFGR_PLLMUL32 (0x001C0000U) /!< PLL input clock 32 */
		4224	#define RCC_CFGR_PLLMUL48 (0x00200000U) /!< PLL input clock 48 */
		4225
		4226	/!< PLLDIV configuration /
		4227	#define RCC_CFGR_PLLDIV_Pos (22U)
		4228	#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /!< 0x00C00000 /
		4229	#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /!< PLLDIV[1:0] bits (PLL Output Division) /
		4230	#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /!< 0x00400000 /
		4231	#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /!< 0x00800000 /
		4232
		4233
		4234	/!< PLLDIV configuration /
		4235	#define RCC_CFGR_PLLDIV1 (0x00000000U) /!< PLL clock output = CKVCO / 1 /
		4236	#define RCC_CFGR_PLLDIV2_Pos (22U)
		4237	#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /!< 0x00400000 /
		4238	#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /!< PLL clock output = CKVCO / 2 /
		4239	#define RCC_CFGR_PLLDIV3_Pos (23U)
		4240	#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /!< 0x00800000 /
		4241	#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /!< PLL clock output = CKVCO / 3 /
		4242	#define RCC_CFGR_PLLDIV4_Pos (22U)
		4243	#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /!< 0x00C00000 /
		4244	#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /!< PLL clock output = CKVCO / 4 /
		4245
		4246
		4247	#define RCC_CFGR_MCOSEL_Pos (24U)
		4248	#define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /!< 0x07000000 /
		4249	#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /!< MCO[2:0] bits (Microcontroller Clock Output) /
		4250	#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /!< 0x01000000 /
		4251	#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /!< 0x02000000 /
		4252	#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /!< 0x04000000 /
		4253
		4254	/!< MCO configuration /
		4255	#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /!< No clock /
		4256	#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
		4257	#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /!< 0x01000000 /
		4258	#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /!< System clock selected /
		4259	#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
		4260	#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /!< 0x02000000 /
		4261	#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /!< Internal 16 MHz RC oscillator clock selected /
		4262	#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
		4263	#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /!< 0x03000000 /
		4264	#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /!< Internal Medium Speed RC oscillator clock selected /
		4265	#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
		4266	#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /!< 0x04000000 /
		4267	#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /!< External 1-25 MHz oscillator clock selected /
		4268	#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
		4269	#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /!< 0x05000000 /
		4270	#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /!< PLL clock divided /
		4271	#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
		4272	#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /!< 0x06000000 /
		4273	#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /!< LSI selected /
		4274	#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
		4275	#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /!< 0x07000000 /
		4276	#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /!< LSE selected /
		4277
		4278	#define RCC_CFGR_MCOPRE_Pos (28U)
		4279	#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /!< 0x70000000 /
		4280	#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) /
		4281	#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /!< 0x10000000 /
		4282	#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /!< 0x20000000 /
		4283	#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /!< 0x40000000 /
		4284
		4285	/!< MCO Prescaler configuration /
		4286	#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /!< MCO is divided by 1 /
		4287	#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /!< MCO is divided by 2 /
		4288	#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /!< MCO is divided by 4 /
		4289	#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /!< MCO is divided by 8 /
		4290	#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /!< MCO is divided by 16 /
		4291
		4292	/* Legacy aliases */
		4293	#define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
		4294	#define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
		4295	#define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
		4296	#define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
		4297	#define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
		4298	#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
		4299	#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
		4300	#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
		4301	#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
		4302	#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
		4303	#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
		4304	#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
		4305	#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
		4306
		4307	/!<*************** Bit definition for RCC_CIR register ******************/
		4308	#define RCC_CIR_LSIRDYF_Pos (0U)
		4309	#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /!< 0x00000001 /
		4310	#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /!< LSI Ready Interrupt flag /
		4311	#define RCC_CIR_LSERDYF_Pos (1U)
		4312	#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /!< 0x00000002 /
		4313	#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /!< LSE Ready Interrupt flag /
		4314	#define RCC_CIR_HSIRDYF_Pos (2U)
		4315	#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /!< 0x00000004 /
		4316	#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /!< HSI Ready Interrupt flag /
		4317	#define RCC_CIR_HSERDYF_Pos (3U)
		4318	#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /!< 0x00000008 /
		4319	#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /!< HSE Ready Interrupt flag /
		4320	#define RCC_CIR_PLLRDYF_Pos (4U)
		4321	#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /!< 0x00000010 /
		4322	#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /!< PLL Ready Interrupt flag /
		4323	#define RCC_CIR_MSIRDYF_Pos (5U)
		4324	#define RCC_CIR_MSIRDYF_Msk (0x1U << RCC_CIR_MSIRDYF_Pos) /!< 0x00000020 /
		4325	#define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /!< MSI Ready Interrupt flag /
		4326	#define RCC_CIR_LSECSSF_Pos (6U)
		4327	#define RCC_CIR_LSECSSF_Msk (0x1U << RCC_CIR_LSECSSF_Pos) /!< 0x00000040 /
		4328	#define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /!< LSE CSS Interrupt flag /
		4329	#define RCC_CIR_CSSF_Pos (7U)
		4330	#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /!< 0x00000080 /
		4331	#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /!< Clock Security System Interrupt flag /
		4332
		4333	#define RCC_CIR_LSIRDYIE_Pos (8U)
		4334	#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /!< 0x00000100 /
		4335	#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /!< LSI Ready Interrupt Enable /
		4336	#define RCC_CIR_LSERDYIE_Pos (9U)
		4337	#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /!< 0x00000200 /
		4338	#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /!< LSE Ready Interrupt Enable /
		4339	#define RCC_CIR_HSIRDYIE_Pos (10U)
		4340	#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /!< 0x00000400 /
		4341	#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /!< HSI Ready Interrupt Enable /
		4342	#define RCC_CIR_HSERDYIE_Pos (11U)
		4343	#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /!< 0x00000800 /
		4344	#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /!< HSE Ready Interrupt Enable /
		4345	#define RCC_CIR_PLLRDYIE_Pos (12U)
		4346	#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /!< 0x00001000 /
		4347	#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /!< PLL Ready Interrupt Enable /
		4348	#define RCC_CIR_MSIRDYIE_Pos (13U)
		4349	#define RCC_CIR_MSIRDYIE_Msk (0x1U << RCC_CIR_MSIRDYIE_Pos) /!< 0x00002000 /
		4350	#define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /!< MSI Ready Interrupt Enable /
		4351	#define RCC_CIR_LSECSSIE_Pos (14U)
		4352	#define RCC_CIR_LSECSSIE_Msk (0x1U << RCC_CIR_LSECSSIE_Pos) /!< 0x00004000 /
		4353	#define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /!< LSE CSS Interrupt Enable /
		4354
		4355	#define RCC_CIR_LSIRDYC_Pos (16U)
		4356	#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /!< 0x00010000 /
		4357	#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /!< LSI Ready Interrupt Clear /
		4358	#define RCC_CIR_LSERDYC_Pos (17U)
		4359	#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /!< 0x00020000 /
		4360	#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /!< LSE Ready Interrupt Clear /
		4361	#define RCC_CIR_HSIRDYC_Pos (18U)
		4362	#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /!< 0x00040000 /
		4363	#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /!< HSI Ready Interrupt Clear /
		4364	#define RCC_CIR_HSERDYC_Pos (19U)
		4365	#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /!< 0x00080000 /
		4366	#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /!< HSE Ready Interrupt Clear /
		4367	#define RCC_CIR_PLLRDYC_Pos (20U)
		4368	#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /!< 0x00100000 /
		4369	#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /!< PLL Ready Interrupt Clear /
		4370	#define RCC_CIR_MSIRDYC_Pos (21U)
		4371	#define RCC_CIR_MSIRDYC_Msk (0x1U << RCC_CIR_MSIRDYC_Pos) /!< 0x00200000 /
		4372	#define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /!< MSI Ready Interrupt Clear /
		4373	#define RCC_CIR_LSECSSC_Pos (22U)
		4374	#define RCC_CIR_LSECSSC_Msk (0x1U << RCC_CIR_LSECSSC_Pos) /!< 0x00400000 /
		4375	#define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /!< LSE CSS Interrupt Clear /
		4376	#define RCC_CIR_CSSC_Pos (23U)
		4377	#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /!< 0x00800000 /
		4378	#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /!< Clock Security System Interrupt Clear /
		4379
		4380	/*************** Bit definition for RCC_AHBRSTR register ****************/
		4381	#define RCC_AHBRSTR_GPIOARST_Pos (0U)
		4382	#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /!< 0x00000001 /
		4383	#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /!< GPIO port A reset /
		4384	#define RCC_AHBRSTR_GPIOBRST_Pos (1U)
		4385	#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /!< 0x00000002 /
		4386	#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /!< GPIO port B reset /
		4387	#define RCC_AHBRSTR_GPIOCRST_Pos (2U)
		4388	#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /!< 0x00000004 /
		4389	#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /!< GPIO port C reset /
		4390	#define RCC_AHBRSTR_GPIODRST_Pos (3U)
		4391	#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /!< 0x00000008 /
		4392	#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /!< GPIO port D reset /
		4393	#define RCC_AHBRSTR_GPIOERST_Pos (4U)
		4394	#define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /!< 0x00000010 /
		4395	#define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /!< GPIO port E reset /
		4396	#define RCC_AHBRSTR_GPIOHRST_Pos (5U)
		4397	#define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /!< 0x00000020 /
		4398	#define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /!< GPIO port H reset /
		4399	#define RCC_AHBRSTR_GPIOFRST_Pos (6U)
		4400	#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /!< 0x00000040 /
		4401	#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /!< GPIO port F reset /
		4402	#define RCC_AHBRSTR_GPIOGRST_Pos (7U)
		4403	#define RCC_AHBRSTR_GPIOGRST_Msk (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /!< 0x00000080 /
		4404	#define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /!< GPIO port G reset /
		4405	#define RCC_AHBRSTR_CRCRST_Pos (12U)
		4406	#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /!< 0x00001000 /
		4407	#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /!< CRC reset /
		4408	#define RCC_AHBRSTR_FLITFRST_Pos (15U)
		4409	#define RCC_AHBRSTR_FLITFRST_Msk (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /!< 0x00008000 /
		4410	#define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /!< FLITF reset /
		4411	#define RCC_AHBRSTR_DMA1RST_Pos (24U)
		4412	#define RCC_AHBRSTR_DMA1RST_Msk (0x1U << RCC_AHBRSTR_DMA1RST_Pos) /!< 0x01000000 /
		4413	#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /!< DMA1 reset /
		4414	#define RCC_AHBRSTR_DMA2RST_Pos (25U)
		4415	#define RCC_AHBRSTR_DMA2RST_Msk (0x1U << RCC_AHBRSTR_DMA2RST_Pos) /!< 0x02000000 /
		4416	#define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /!< DMA2 reset /
		4417
		4418	/*************** Bit definition for RCC_APB2RSTR register ***************/
		4419	#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
		4420	#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /!< 0x00000001 /
		4421	#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /!< System Configuration SYSCFG reset /
		4422	#define RCC_APB2RSTR_TIM9RST_Pos (2U)
		4423	#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /!< 0x00000004 /
		4424	#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /!< TIM9 reset /
		4425	#define RCC_APB2RSTR_TIM10RST_Pos (3U)
		4426	#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /!< 0x00000008 /
		4427	#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /!< TIM10 reset /
		4428	#define RCC_APB2RSTR_TIM11RST_Pos (4U)
		4429	#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /!< 0x00000010 /
		4430	#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /!< TIM11 reset /
		4431	#define RCC_APB2RSTR_ADC1RST_Pos (9U)
		4432	#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /!< 0x00000200 /
		4433	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /!< ADC1 reset /
		4434	#define RCC_APB2RSTR_SPI1RST_Pos (12U)
		4435	#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /!< 0x00001000 /
		4436	#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /!< SPI1 reset /
		4437	#define RCC_APB2RSTR_USART1RST_Pos (14U)
		4438	#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /!< 0x00004000 /
		4439	#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /!< USART1 reset /
		4440
		4441	/*************** Bit definition for RCC_APB1RSTR register ***************/
		4442	#define RCC_APB1RSTR_TIM2RST_Pos (0U)
		4443	#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /!< 0x00000001 /
		4444	#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /!< Timer 2 reset /
		4445	#define RCC_APB1RSTR_TIM3RST_Pos (1U)
		4446	#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /!< 0x00000002 /
		4447	#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /!< Timer 3 reset /
		4448	#define RCC_APB1RSTR_TIM4RST_Pos (2U)
		4449	#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /!< 0x00000004 /
		4450	#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /!< Timer 4 reset /
		4451	#define RCC_APB1RSTR_TIM5RST_Pos (3U)
		4452	#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /!< 0x00000008 /
		4453	#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /!< Timer 5 reset /
		4454	#define RCC_APB1RSTR_TIM6RST_Pos (4U)
		4455	#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /!< 0x00000010 /
		4456	#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /!< Timer 6 reset /
		4457	#define RCC_APB1RSTR_TIM7RST_Pos (5U)
		4458	#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /!< 0x00000020 /
		4459	#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /!< Timer 7 reset /
		4460	#define RCC_APB1RSTR_WWDGRST_Pos (11U)
		4461	#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /!< 0x00000800 /
		4462	#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /!< Window Watchdog reset /
		4463	#define RCC_APB1RSTR_SPI2RST_Pos (14U)
		4464	#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /!< 0x00004000 /
		4465	#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /!< SPI 2 reset /
		4466	#define RCC_APB1RSTR_SPI3RST_Pos (15U)
		4467	#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /!< 0x00008000 /
		4468	#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /!< SPI 3 reset /
		4469	#define RCC_APB1RSTR_USART2RST_Pos (17U)
		4470	#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /!< 0x00020000 /
		4471	#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /!< USART 2 reset /
		4472	#define RCC_APB1RSTR_USART3RST_Pos (18U)
		4473	#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /!< 0x00040000 /
		4474	#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /!< USART 3 reset /
		4475	#define RCC_APB1RSTR_UART4RST_Pos (19U)
		4476	#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /!< 0x00080000 /
		4477	#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /!< UART 4 reset /
		4478	#define RCC_APB1RSTR_UART5RST_Pos (20U)
		4479	#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /!< 0x00100000 /
		4480	#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /!< UART 5 reset /
		4481	#define RCC_APB1RSTR_I2C1RST_Pos (21U)
		4482	#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /!< 0x00200000 /
		4483	#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /!< I2C 1 reset /
		4484	#define RCC_APB1RSTR_I2C2RST_Pos (22U)
		4485	#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /!< 0x00400000 /
		4486	#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /!< I2C 2 reset /
		4487	#define RCC_APB1RSTR_USBRST_Pos (23U)
		4488	#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /!< 0x00800000 /
		4489	#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /!< USB reset /
		4490	#define RCC_APB1RSTR_PWRRST_Pos (28U)
		4491	#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /!< 0x10000000 /
		4492	#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /!< Power interface reset /
		4493	#define RCC_APB1RSTR_DACRST_Pos (29U)
		4494	#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /!< 0x20000000 /
		4495	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /!< DAC interface reset /
		4496	#define RCC_APB1RSTR_COMPRST_Pos (31U)
		4497	#define RCC_APB1RSTR_COMPRST_Msk (0x1U << RCC_APB1RSTR_COMPRST_Pos) /!< 0x80000000 /
		4498	#define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /!< Comparator interface reset /
		4499
		4500	/**************** Bit definition for RCC_AHBENR register ****************/
		4501	#define RCC_AHBENR_GPIOAEN_Pos (0U)
		4502	#define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /!< 0x00000001 /
		4503	#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /!< GPIO port A clock enable /
		4504	#define RCC_AHBENR_GPIOBEN_Pos (1U)
		4505	#define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /!< 0x00000002 /
		4506	#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /!< GPIO port B clock enable /
		4507	#define RCC_AHBENR_GPIOCEN_Pos (2U)
		4508	#define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /!< 0x00000004 /
		4509	#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /!< GPIO port C clock enable /
		4510	#define RCC_AHBENR_GPIODEN_Pos (3U)
		4511	#define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /!< 0x00000008 /
		4512	#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /!< GPIO port D clock enable /
		4513	#define RCC_AHBENR_GPIOEEN_Pos (4U)
		4514	#define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /!< 0x00000010 /
		4515	#define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /!< GPIO port E clock enable /
		4516	#define RCC_AHBENR_GPIOHEN_Pos (5U)
		4517	#define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /!< 0x00000020 /
		4518	#define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /!< GPIO port H clock enable /
		4519	#define RCC_AHBENR_GPIOFEN_Pos (6U)
		4520	#define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /!< 0x00000040 /
		4521	#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /!< GPIO port F clock enable /
		4522	#define RCC_AHBENR_GPIOGEN_Pos (7U)
		4523	#define RCC_AHBENR_GPIOGEN_Msk (0x1U << RCC_AHBENR_GPIOGEN_Pos) /!< 0x00000080 /
		4524	#define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /!< GPIO port G clock enable /
		4525	#define RCC_AHBENR_CRCEN_Pos (12U)
		4526	#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /!< 0x00001000 /
		4527	#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /!< CRC clock enable /
		4528	#define RCC_AHBENR_FLITFEN_Pos (15U)
		4529	#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /!< 0x00008000 /
		4530	#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when
		4531	the Flash memory is in power down mode) */
		4532	#define RCC_AHBENR_DMA1EN_Pos (24U)
		4533	#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /!< 0x01000000 /
		4534	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /!< DMA1 clock enable /
		4535	#define RCC_AHBENR_DMA2EN_Pos (25U)
		4536	#define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /!< 0x02000000 /
		4537	#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /!< DMA2 clock enable /
		4538
		4539	/**************** Bit definition for RCC_APB2ENR register ***************/
		4540	#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
		4541	#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /!< 0x00000001 /
		4542	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /!< System Configuration SYSCFG clock enable /
		4543	#define RCC_APB2ENR_TIM9EN_Pos (2U)
		4544	#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /!< 0x00000004 /
		4545	#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /!< TIM9 interface clock enable /
		4546	#define RCC_APB2ENR_TIM10EN_Pos (3U)
		4547	#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /!< 0x00000008 /
		4548	#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /!< TIM10 interface clock enable /
		4549	#define RCC_APB2ENR_TIM11EN_Pos (4U)
		4550	#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /!< 0x00000010 /
		4551	#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /!< TIM11 Timer clock enable /
		4552	#define RCC_APB2ENR_ADC1EN_Pos (9U)
		4553	#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /!< 0x00000200 /
		4554	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /!< ADC1 clock enable /
		4555	#define RCC_APB2ENR_SPI1EN_Pos (12U)
		4556	#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /!< 0x00001000 /
		4557	#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /!< SPI1 clock enable /
		4558	#define RCC_APB2ENR_USART1EN_Pos (14U)
		4559	#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /!< 0x00004000 /
		4560	#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /!< USART1 clock enable /
		4561
		4562	/*************** Bit definition for RCC_APB1ENR register ****************/
		4563	#define RCC_APB1ENR_TIM2EN_Pos (0U)
		4564	#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /!< 0x00000001 /
		4565	#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /!< Timer 2 clock enabled/
		4566	#define RCC_APB1ENR_TIM3EN_Pos (1U)
		4567	#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /!< 0x00000002 /
		4568	#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /!< Timer 3 clock enable /
		4569	#define RCC_APB1ENR_TIM4EN_Pos (2U)
		4570	#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /!< 0x00000004 /
		4571	#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /!< Timer 4 clock enable /
		4572	#define RCC_APB1ENR_TIM5EN_Pos (3U)
		4573	#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /!< 0x00000008 /
		4574	#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /!< Timer 5 clock enable /
		4575	#define RCC_APB1ENR_TIM6EN_Pos (4U)
		4576	#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /!< 0x00000010 /
		4577	#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /!< Timer 6 clock enable /
		4578	#define RCC_APB1ENR_TIM7EN_Pos (5U)
		4579	#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /!< 0x00000020 /
		4580	#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /!< Timer 7 clock enable /
		4581	#define RCC_APB1ENR_WWDGEN_Pos (11U)
		4582	#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /!< 0x00000800 /
		4583	#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /!< Window Watchdog clock enable /
		4584	#define RCC_APB1ENR_SPI2EN_Pos (14U)
		4585	#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /!< 0x00004000 /
		4586	#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /!< SPI 2 clock enable /
		4587	#define RCC_APB1ENR_SPI3EN_Pos (15U)
		4588	#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /!< 0x00008000 /
		4589	#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /!< SPI 3 clock enable /
		4590	#define RCC_APB1ENR_USART2EN_Pos (17U)
		4591	#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /!< 0x00020000 /
		4592	#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /!< USART 2 clock enable /
		4593	#define RCC_APB1ENR_USART3EN_Pos (18U)
		4594	#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /!< 0x00040000 /
		4595	#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /!< USART 3 clock enable /
		4596	#define RCC_APB1ENR_UART4EN_Pos (19U)
		4597	#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /!< 0x00080000 /
		4598	#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /!< UART 4 clock enable /
		4599	#define RCC_APB1ENR_UART5EN_Pos (20U)
		4600	#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /!< 0x00100000 /
		4601	#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /!< UART 5 clock enable /
		4602	#define RCC_APB1ENR_I2C1EN_Pos (21U)
		4603	#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /!< 0x00200000 /
		4604	#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /!< I2C 1 clock enable /
		4605	#define RCC_APB1ENR_I2C2EN_Pos (22U)
		4606	#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /!< 0x00400000 /
		4607	#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /!< I2C 2 clock enable /
		4608	#define RCC_APB1ENR_USBEN_Pos (23U)
		4609	#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /!< 0x00800000 /
		4610	#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /!< USB clock enable /
		4611	#define RCC_APB1ENR_PWREN_Pos (28U)
		4612	#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /!< 0x10000000 /
		4613	#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /!< Power interface clock enable /
		4614	#define RCC_APB1ENR_DACEN_Pos (29U)
		4615	#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /!< 0x20000000 /
		4616	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /!< DAC interface clock enable /
		4617	#define RCC_APB1ENR_COMPEN_Pos (31U)
		4618	#define RCC_APB1ENR_COMPEN_Msk (0x1U << RCC_APB1ENR_COMPEN_Pos) /!< 0x80000000 /
		4619	#define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /!< Comparator interface clock enable /
		4620
		4621	/**************** Bit definition for RCC_AHBLPENR register **************/
		4622	#define RCC_AHBLPENR_GPIOALPEN_Pos (0U)
		4623	#define RCC_AHBLPENR_GPIOALPEN_Msk (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /!< 0x00000001 /
		4624	#define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /!< GPIO port A clock enabled in sleep mode /
		4625	#define RCC_AHBLPENR_GPIOBLPEN_Pos (1U)
		4626	#define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /!< 0x00000002 /
		4627	#define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /!< GPIO port B clock enabled in sleep mode /
		4628	#define RCC_AHBLPENR_GPIOCLPEN_Pos (2U)
		4629	#define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /!< 0x00000004 /
		4630	#define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /!< GPIO port C clock enabled in sleep mode /
		4631	#define RCC_AHBLPENR_GPIODLPEN_Pos (3U)
		4632	#define RCC_AHBLPENR_GPIODLPEN_Msk (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /!< 0x00000008 /
		4633	#define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /!< GPIO port D clock enabled in sleep mode /
		4634	#define RCC_AHBLPENR_GPIOELPEN_Pos (4U)
		4635	#define RCC_AHBLPENR_GPIOELPEN_Msk (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /!< 0x00000010 /
		4636	#define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /!< GPIO port E clock enabled in sleep mode /
		4637	#define RCC_AHBLPENR_GPIOHLPEN_Pos (5U)
		4638	#define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /!< 0x00000020 /
		4639	#define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /!< GPIO port H clock enabled in sleep mode /
		4640	#define RCC_AHBLPENR_GPIOFLPEN_Pos (6U)
		4641	#define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOFLPEN_Pos) /!< 0x00000040 /
		4642	#define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /!< GPIO port F clock enabled in sleep mode /
		4643	#define RCC_AHBLPENR_GPIOGLPEN_Pos (7U)
		4644	#define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOGLPEN_Pos) /!< 0x00000080 /
		4645	#define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /!< GPIO port G clock enabled in sleep mode /
		4646	#define RCC_AHBLPENR_CRCLPEN_Pos (12U)
		4647	#define RCC_AHBLPENR_CRCLPEN_Msk (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /!< 0x00001000 /
		4648	#define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /!< CRC clock enabled in sleep mode /
		4649	#define RCC_AHBLPENR_FLITFLPEN_Pos (15U)
		4650	#define RCC_AHBLPENR_FLITFLPEN_Msk (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /!< 0x00008000 /
		4651	#define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode
		4652	(has effect only when the Flash memory is
		4653	in power down mode) */
		4654	#define RCC_AHBLPENR_SRAMLPEN_Pos (16U)
		4655	#define RCC_AHBLPENR_SRAMLPEN_Msk (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /!< 0x00010000 /
		4656	#define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /!< SRAM clock enabled in sleep mode /
		4657	#define RCC_AHBLPENR_DMA1LPEN_Pos (24U)
		4658	#define RCC_AHBLPENR_DMA1LPEN_Msk (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /!< 0x01000000 /
		4659	#define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /!< DMA1 clock enabled in sleep mode /
		4660	#define RCC_AHBLPENR_DMA2LPEN_Pos (25U)
		4661	#define RCC_AHBLPENR_DMA2LPEN_Msk (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /!< 0x02000000 /
		4662	#define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /!< DMA2 clock enabled in sleep mode /
		4663
		4664	/**************** Bit definition for RCC_APB2LPENR register *************/
		4665	#define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U)
		4666	#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /!< 0x00000001 /
		4667	#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /!< System Configuration SYSCFG clock enabled in sleep mode /
		4668	#define RCC_APB2LPENR_TIM9LPEN_Pos (2U)
		4669	#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /!< 0x00000004 /
		4670	#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /!< TIM9 interface clock enabled in sleep mode /
		4671	#define RCC_APB2LPENR_TIM10LPEN_Pos (3U)
		4672	#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /!< 0x00000008 /
		4673	#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /!< TIM10 interface clock enabled in sleep mode /
		4674	#define RCC_APB2LPENR_TIM11LPEN_Pos (4U)
		4675	#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /!< 0x00000010 /
		4676	#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /!< TIM11 Timer clock enabled in sleep mode /
		4677	#define RCC_APB2LPENR_ADC1LPEN_Pos (9U)
		4678	#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /!< 0x00000200 /
		4679	#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /!< ADC1 clock enabled in sleep mode /
		4680	#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
		4681	#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /!< 0x00001000 /
		4682	#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /!< SPI1 clock enabled in sleep mode /
		4683	#define RCC_APB2LPENR_USART1LPEN_Pos (14U)
		4684	#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /!< 0x00004000 /
		4685	#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /!< USART1 clock enabled in sleep mode /
		4686
		4687	/*************** Bit definition for RCC_APB1LPENR register **************/
		4688	#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
		4689	#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /!< 0x00000001 /
		4690	#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /!< Timer 2 clock enabled in sleep mode /
		4691	#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
		4692	#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /!< 0x00000002 /
		4693	#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /!< Timer 3 clock enabled in sleep mode /
		4694	#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
		4695	#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /!< 0x00000004 /
		4696	#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /!< Timer 4 clock enabled in sleep mode /
		4697	#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
		4698	#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /!< 0x00000008 /
		4699	#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /!< Timer 5 clock enabled in sleep mode /
		4700	#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
		4701	#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /!< 0x00000010 /
		4702	#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /!< Timer 6 clock enabled in sleep mode /
		4703	#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
		4704	#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /!< 0x00000020 /
		4705	#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /!< Timer 7 clock enabled in sleep mode /
		4706	#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
		4707	#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /!< 0x00000800 /
		4708	#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /!< Window Watchdog clock enabled in sleep mode /
		4709	#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
		4710	#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /!< 0x00004000 /
		4711	#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /!< SPI 2 clock enabled in sleep mode /
		4712	#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
		4713	#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /!< 0x00008000 /
		4714	#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /!< SPI 3 clock enabled in sleep mode /
		4715	#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
		4716	#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /!< 0x00020000 /
		4717	#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /!< USART 2 clock enabled in sleep mode /
		4718	#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
		4719	#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /!< 0x00040000 /
		4720	#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /!< USART 3 clock enabled in sleep mode /
		4721	#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
		4722	#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /!< 0x00080000 /
		4723	#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /!< UART 4 clock enabled in sleep mode /
		4724	#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
		4725	#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /!< 0x00100000 /
		4726	#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /!< UART 5 clock enabled in sleep mode /
		4727	#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
		4728	#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /!< 0x00200000 /
		4729	#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /!< I2C 1 clock enabled in sleep mode /
		4730	#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
		4731	#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /!< 0x00400000 /
		4732	#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /!< I2C 2 clock enabled in sleep mode /
		4733	#define RCC_APB1LPENR_USBLPEN_Pos (23U)
		4734	#define RCC_APB1LPENR_USBLPEN_Msk (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /!< 0x00800000 /
		4735	#define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /!< USB clock enabled in sleep mode /
		4736	#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
		4737	#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /!< 0x10000000 /
		4738	#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /!< Power interface clock enabled in sleep mode /
		4739	#define RCC_APB1LPENR_DACLPEN_Pos (29U)
		4740	#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /!< 0x20000000 /
		4741	#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /!< DAC interface clock enabled in sleep mode /
		4742	#define RCC_APB1LPENR_COMPLPEN_Pos (31U)
		4743	#define RCC_APB1LPENR_COMPLPEN_Msk (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /!< 0x80000000 /
		4744	#define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /!< Comparator interface clock enabled in sleep mode/
		4745
		4746	/***************** Bit definition for RCC_CSR register ******************/
		4747	#define RCC_CSR_LSION_Pos (0U)
		4748	#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /!< 0x00000001 /
		4749	#define RCC_CSR_LSION RCC_CSR_LSION_Msk /!< Internal Low Speed oscillator enable /
		4750	#define RCC_CSR_LSIRDY_Pos (1U)
		4751	#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /!< 0x00000002 /
		4752	#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /!< Internal Low Speed oscillator Ready /
		4753
		4754	#define RCC_CSR_LSEON_Pos (8U)
		4755	#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /!< 0x00000100 /
		4756	#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /!< External Low Speed oscillator enable /
		4757	#define RCC_CSR_LSERDY_Pos (9U)
		4758	#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /!< 0x00000200 /
		4759	#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /!< External Low Speed oscillator Ready /
		4760	#define RCC_CSR_LSEBYP_Pos (10U)
		4761	#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /!< 0x00000400 /
		4762	#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /!< External Low Speed oscillator Bypass /
		4763
		4764	#define RCC_CSR_LSECSSON_Pos (11U)
		4765	#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /!< 0x00000800 /
		4766	#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /!< External Low Speed oscillator CSS Enable /
		4767	#define RCC_CSR_LSECSSD_Pos (12U)
		4768	#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /!< 0x00001000 /
		4769	#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /!< External Low Speed oscillator CSS Detected /
		4770
		4771	#define RCC_CSR_RTCSEL_Pos (16U)
		4772	#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /!< 0x00030000 /
		4773	#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /!< RTCSEL[1:0] bits (RTC clock source selection) /
		4774	#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /!< 0x00010000 /
		4775	#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /!< 0x00020000 /
		4776
		4777	/!< RTC congiguration /
		4778	#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /!< No clock /
		4779	#define RCC_CSR_RTCSEL_LSE_Pos (16U)
		4780	#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /!< 0x00010000 /
		4781	#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /!< LSE oscillator clock used as RTC clock /
		4782	#define RCC_CSR_RTCSEL_LSI_Pos (17U)
		4783	#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /!< 0x00020000 /
		4784	#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /!< LSI oscillator clock used as RTC clock /
		4785	#define RCC_CSR_RTCSEL_HSE_Pos (16U)
		4786	#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /!< 0x00030000 /
		4787	#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock /
		4788
		4789	#define RCC_CSR_RTCEN_Pos (22U)
		4790	#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /!< 0x00400000 /
		4791	#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /!< RTC clock enable /
		4792	#define RCC_CSR_RTCRST_Pos (23U)
		4793	#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /!< 0x00800000 /
		4794	#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /!< RTC reset /
		4795
		4796	#define RCC_CSR_RMVF_Pos (24U)
		4797	#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /!< 0x01000000 /
		4798	#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /!< Remove reset flag /
		4799	#define RCC_CSR_OBLRSTF_Pos (25U)
		4800	#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /!< 0x02000000 /
		4801	#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /!< Option Bytes Loader reset flag /
		4802	#define RCC_CSR_PINRSTF_Pos (26U)
		4803	#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /!< 0x04000000 /
		4804	#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /!< PIN reset flag /
		4805	#define RCC_CSR_PORRSTF_Pos (27U)
		4806	#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /!< 0x08000000 /
		4807	#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /!< POR/PDR reset flag /
		4808	#define RCC_CSR_SFTRSTF_Pos (28U)
		4809	#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /!< 0x10000000 /
		4810	#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /!< Software Reset flag /
		4811	#define RCC_CSR_IWDGRSTF_Pos (29U)
		4812	#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /!< 0x20000000 /
		4813	#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /!< Independent Watchdog reset flag /
		4814	#define RCC_CSR_WWDGRSTF_Pos (30U)
		4815	#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /!< 0x40000000 /
		4816	#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /!< Window watchdog reset flag /
		4817	#define RCC_CSR_LPWRRSTF_Pos (31U)
		4818	#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /!< 0x80000000 /
		4819	#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /!< Low-Power reset flag /
		4820
		4821	/******************************************************************************/
		4822	/* */
		4823	/* Real-Time Clock (RTC) */
		4824	/* */
		4825	/******************************************************************************/
		4826	/*
		4827	* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
		4828	*/
		4829	#define RTC_TAMPER1_SUPPORT /!< TAMPER 1 feature support /
		4830	#define RTC_TAMPER2_SUPPORT /!< TAMPER 2 feature support /
		4831	#define RTC_TAMPER3_SUPPORT /!< TAMPER 3 feature support /
		4832	#define RTC_BACKUP_SUPPORT /!< BACKUP register feature support /
		4833	#define RTC_WAKEUP_SUPPORT /!< WAKEUP feature support /
		4834	#define RTC_SMOOTHCALIB_SUPPORT /!< Smooth digital calibration feature support /
		4835	#define RTC_SUBSECOND_SUPPORT /!< Sub-second feature support /
		4836
		4837	/****************** Bits definition for RTC_TR register *****************/
		4838	#define RTC_TR_PM_Pos (22U)
		4839	#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /!< 0x00400000 /
		4840	#define RTC_TR_PM RTC_TR_PM_Msk
		4841	#define RTC_TR_HT_Pos (20U)
		4842	#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /!< 0x00300000 /
		4843	#define RTC_TR_HT RTC_TR_HT_Msk
		4844	#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /!< 0x00100000 /
		4845	#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /!< 0x00200000 /
		4846	#define RTC_TR_HU_Pos (16U)
		4847	#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /!< 0x000F0000 /
		4848	#define RTC_TR_HU RTC_TR_HU_Msk
		4849	#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /!< 0x00010000 /
		4850	#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /!< 0x00020000 /
		4851	#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /!< 0x00040000 /
		4852	#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /!< 0x00080000 /
		4853	#define RTC_TR_MNT_Pos (12U)
		4854	#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /!< 0x00007000 /
		4855	#define RTC_TR_MNT RTC_TR_MNT_Msk
		4856	#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /!< 0x00001000 /
		4857	#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /!< 0x00002000 /
		4858	#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /!< 0x00004000 /
		4859	#define RTC_TR_MNU_Pos (8U)
		4860	#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /!< 0x00000F00 /
		4861	#define RTC_TR_MNU RTC_TR_MNU_Msk
		4862	#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /!< 0x00000100 /
		4863	#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /!< 0x00000200 /
		4864	#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /!< 0x00000400 /
		4865	#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /!< 0x00000800 /
		4866	#define RTC_TR_ST_Pos (4U)
		4867	#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /!< 0x00000070 /
		4868	#define RTC_TR_ST RTC_TR_ST_Msk
		4869	#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /!< 0x00000010 /
		4870	#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /!< 0x00000020 /
		4871	#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /!< 0x00000040 /
		4872	#define RTC_TR_SU_Pos (0U)
		4873	#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /!< 0x0000000F /
		4874	#define RTC_TR_SU RTC_TR_SU_Msk
		4875	#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /!< 0x00000001 /
		4876	#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /!< 0x00000002 /
		4877	#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /!< 0x00000004 /
		4878	#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /!< 0x00000008 /
		4879
		4880	/****************** Bits definition for RTC_DR register *****************/
		4881	#define RTC_DR_YT_Pos (20U)
		4882	#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /!< 0x00F00000 /
		4883	#define RTC_DR_YT RTC_DR_YT_Msk
		4884	#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /!< 0x00100000 /
		4885	#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /!< 0x00200000 /
		4886	#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /!< 0x00400000 /
		4887	#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /!< 0x00800000 /
		4888	#define RTC_DR_YU_Pos (16U)
		4889	#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /!< 0x000F0000 /
		4890	#define RTC_DR_YU RTC_DR_YU_Msk
		4891	#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /!< 0x00010000 /
		4892	#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /!< 0x00020000 /
		4893	#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /!< 0x00040000 /
		4894	#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /!< 0x00080000 /
		4895	#define RTC_DR_WDU_Pos (13U)
		4896	#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /!< 0x0000E000 /
		4897	#define RTC_DR_WDU RTC_DR_WDU_Msk
		4898	#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /!< 0x00002000 /
		4899	#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /!< 0x00004000 /
		4900	#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /!< 0x00008000 /
		4901	#define RTC_DR_MT_Pos (12U)
		4902	#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /!< 0x00001000 /
		4903	#define RTC_DR_MT RTC_DR_MT_Msk
		4904	#define RTC_DR_MU_Pos (8U)
		4905	#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /!< 0x00000F00 /
		4906	#define RTC_DR_MU RTC_DR_MU_Msk
		4907	#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /!< 0x00000100 /
		4908	#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /!< 0x00000200 /
		4909	#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /!< 0x00000400 /
		4910	#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /!< 0x00000800 /
		4911	#define RTC_DR_DT_Pos (4U)
		4912	#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /!< 0x00000030 /
		4913	#define RTC_DR_DT RTC_DR_DT_Msk
		4914	#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /!< 0x00000010 /
		4915	#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /!< 0x00000020 /
		4916	#define RTC_DR_DU_Pos (0U)
		4917	#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /!< 0x0000000F /
		4918	#define RTC_DR_DU RTC_DR_DU_Msk
		4919	#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /!< 0x00000001 /
		4920	#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /!< 0x00000002 /
		4921	#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /!< 0x00000004 /
		4922	#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /!< 0x00000008 /
		4923
		4924	/****************** Bits definition for RTC_CR register *****************/
		4925	#define RTC_CR_COE_Pos (23U)
		4926	#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /!< 0x00800000 /
		4927	#define RTC_CR_COE RTC_CR_COE_Msk
		4928	#define RTC_CR_OSEL_Pos (21U)
		4929	#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /!< 0x00600000 /
		4930	#define RTC_CR_OSEL RTC_CR_OSEL_Msk
		4931	#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /!< 0x00200000 /
		4932	#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /!< 0x00400000 /
		4933	#define RTC_CR_POL_Pos (20U)
		4934	#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /!< 0x00100000 /
		4935	#define RTC_CR_POL RTC_CR_POL_Msk
		4936	#define RTC_CR_COSEL_Pos (19U)
		4937	#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /!< 0x00080000 /
		4938	#define RTC_CR_COSEL RTC_CR_COSEL_Msk
		4939	#define RTC_CR_BCK_Pos (18U)
		4940	#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /!< 0x00040000 /
		4941	#define RTC_CR_BCK RTC_CR_BCK_Msk
		4942	#define RTC_CR_SUB1H_Pos (17U)
		4943	#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /!< 0x00020000 /
		4944	#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
		4945	#define RTC_CR_ADD1H_Pos (16U)
		4946	#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /!< 0x00010000 /
		4947	#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
		4948	#define RTC_CR_TSIE_Pos (15U)
		4949	#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /!< 0x00008000 /
		4950	#define RTC_CR_TSIE RTC_CR_TSIE_Msk
		4951	#define RTC_CR_WUTIE_Pos (14U)
		4952	#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /!< 0x00004000 /
		4953	#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
		4954	#define RTC_CR_ALRBIE_Pos (13U)
		4955	#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /!< 0x00002000 /
		4956	#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
		4957	#define RTC_CR_ALRAIE_Pos (12U)
		4958	#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /!< 0x00001000 /
		4959	#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
		4960	#define RTC_CR_TSE_Pos (11U)
		4961	#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /!< 0x00000800 /
		4962	#define RTC_CR_TSE RTC_CR_TSE_Msk
		4963	#define RTC_CR_WUTE_Pos (10U)
		4964	#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /!< 0x00000400 /
		4965	#define RTC_CR_WUTE RTC_CR_WUTE_Msk
		4966	#define RTC_CR_ALRBE_Pos (9U)
		4967	#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /!< 0x00000200 /
		4968	#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
		4969	#define RTC_CR_ALRAE_Pos (8U)
		4970	#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /!< 0x00000100 /
		4971	#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
		4972	#define RTC_CR_DCE_Pos (7U)
		4973	#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /!< 0x00000080 /
		4974	#define RTC_CR_DCE RTC_CR_DCE_Msk
		4975	#define RTC_CR_FMT_Pos (6U)
		4976	#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /!< 0x00000040 /
		4977	#define RTC_CR_FMT RTC_CR_FMT_Msk
		4978	#define RTC_CR_BYPSHAD_Pos (5U)
		4979	#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /!< 0x00000020 /
		4980	#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
		4981	#define RTC_CR_REFCKON_Pos (4U)
		4982	#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /!< 0x00000010 /
		4983	#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
		4984	#define RTC_CR_TSEDGE_Pos (3U)
		4985	#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /!< 0x00000008 /
		4986	#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
		4987	#define RTC_CR_WUCKSEL_Pos (0U)
		4988	#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /!< 0x00000007 /
		4989	#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
		4990	#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /!< 0x00000001 /
		4991	#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /!< 0x00000002 /
		4992	#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /!< 0x00000004 /
		4993
		4994	/****************** Bits definition for RTC_ISR register ****************/
		4995	#define RTC_ISR_RECALPF_Pos (16U)
		4996	#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /!< 0x00010000 /
		4997	#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
		4998	#define RTC_ISR_TAMP3F_Pos (15U)
		4999	#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /!< 0x00008000 /
		5000	#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
		5001	#define RTC_ISR_TAMP2F_Pos (14U)
		5002	#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /!< 0x00004000 /
		5003	#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
		5004	#define RTC_ISR_TAMP1F_Pos (13U)
		5005	#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /!< 0x00002000 /
		5006	#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
		5007	#define RTC_ISR_TSOVF_Pos (12U)
		5008	#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /!< 0x00001000 /
		5009	#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
		5010	#define RTC_ISR_TSF_Pos (11U)
		5011	#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /!< 0x00000800 /
		5012	#define RTC_ISR_TSF RTC_ISR_TSF_Msk
		5013	#define RTC_ISR_WUTF_Pos (10U)
		5014	#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /!< 0x00000400 /
		5015	#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
		5016	#define RTC_ISR_ALRBF_Pos (9U)
		5017	#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /!< 0x00000200 /
		5018	#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
		5019	#define RTC_ISR_ALRAF_Pos (8U)
		5020	#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /!< 0x00000100 /
		5021	#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
		5022	#define RTC_ISR_INIT_Pos (7U)
		5023	#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /!< 0x00000080 /
		5024	#define RTC_ISR_INIT RTC_ISR_INIT_Msk
		5025	#define RTC_ISR_INITF_Pos (6U)
		5026	#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /!< 0x00000040 /
		5027	#define RTC_ISR_INITF RTC_ISR_INITF_Msk
		5028	#define RTC_ISR_RSF_Pos (5U)
		5029	#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /!< 0x00000020 /
		5030	#define RTC_ISR_RSF RTC_ISR_RSF_Msk
		5031	#define RTC_ISR_INITS_Pos (4U)
		5032	#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /!< 0x00000010 /
		5033	#define RTC_ISR_INITS RTC_ISR_INITS_Msk
		5034	#define RTC_ISR_SHPF_Pos (3U)
		5035	#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /!< 0x00000008 /
		5036	#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
		5037	#define RTC_ISR_WUTWF_Pos (2U)
		5038	#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /!< 0x00000004 /
		5039	#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
		5040	#define RTC_ISR_ALRBWF_Pos (1U)
		5041	#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /!< 0x00000002 /
		5042	#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
		5043	#define RTC_ISR_ALRAWF_Pos (0U)
		5044	#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /!< 0x00000001 /
		5045	#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
		5046
		5047	/****************** Bits definition for RTC_PRER register ***************/
		5048	#define RTC_PRER_PREDIV_A_Pos (16U)
		5049	#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /!< 0x007F0000 /
		5050	#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
		5051	#define RTC_PRER_PREDIV_S_Pos (0U)
		5052	#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /!< 0x00007FFF /
		5053	#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
		5054
		5055	/****************** Bits definition for RTC_WUTR register ***************/
		5056	#define RTC_WUTR_WUT_Pos (0U)
		5057	#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /!< 0x0000FFFF /
		5058	#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
		5059
		5060	/****************** Bits definition for RTC_CALIBR register *************/
		5061	#define RTC_CALIBR_DCS_Pos (7U)
		5062	#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /!< 0x00000080 /
		5063	#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
		5064	#define RTC_CALIBR_DC_Pos (0U)
		5065	#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /!< 0x0000001F /
		5066	#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
		5067
		5068	/****************** Bits definition for RTC_ALRMAR register *************/
		5069	#define RTC_ALRMAR_MSK4_Pos (31U)
		5070	#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /!< 0x80000000 /
		5071	#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
		5072	#define RTC_ALRMAR_WDSEL_Pos (30U)
		5073	#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /!< 0x40000000 /
		5074	#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
		5075	#define RTC_ALRMAR_DT_Pos (28U)
		5076	#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /!< 0x30000000 /
		5077	#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
		5078	#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /!< 0x10000000 /
		5079	#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /!< 0x20000000 /
		5080	#define RTC_ALRMAR_DU_Pos (24U)
		5081	#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /!< 0x0F000000 /
		5082	#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
		5083	#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /!< 0x01000000 /
		5084	#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /!< 0x02000000 /
		5085	#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /!< 0x04000000 /
		5086	#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /!< 0x08000000 /
		5087	#define RTC_ALRMAR_MSK3_Pos (23U)
		5088	#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /!< 0x00800000 /
		5089	#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
		5090	#define RTC_ALRMAR_PM_Pos (22U)
		5091	#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /!< 0x00400000 /
		5092	#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
		5093	#define RTC_ALRMAR_HT_Pos (20U)
		5094	#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /!< 0x00300000 /
		5095	#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
		5096	#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /!< 0x00100000 /
		5097	#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /!< 0x00200000 /
		5098	#define RTC_ALRMAR_HU_Pos (16U)
		5099	#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /!< 0x000F0000 /
		5100	#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
		5101	#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /!< 0x00010000 /
		5102	#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /!< 0x00020000 /
		5103	#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /!< 0x00040000 /
		5104	#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /!< 0x00080000 /
		5105	#define RTC_ALRMAR_MSK2_Pos (15U)
		5106	#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /!< 0x00008000 /
		5107	#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
		5108	#define RTC_ALRMAR_MNT_Pos (12U)
		5109	#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /!< 0x00007000 /
		5110	#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
		5111	#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /!< 0x00001000 /
		5112	#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /!< 0x00002000 /
		5113	#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /!< 0x00004000 /
		5114	#define RTC_ALRMAR_MNU_Pos (8U)
		5115	#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /!< 0x00000F00 /
		5116	#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
		5117	#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /!< 0x00000100 /
		5118	#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /!< 0x00000200 /
		5119	#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /!< 0x00000400 /
		5120	#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /!< 0x00000800 /
		5121	#define RTC_ALRMAR_MSK1_Pos (7U)
		5122	#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /!< 0x00000080 /
		5123	#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
		5124	#define RTC_ALRMAR_ST_Pos (4U)
		5125	#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /!< 0x00000070 /
		5126	#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
		5127	#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /!< 0x00000010 /
		5128	#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /!< 0x00000020 /
		5129	#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /!< 0x00000040 /
		5130	#define RTC_ALRMAR_SU_Pos (0U)
		5131	#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /!< 0x0000000F /
		5132	#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
		5133	#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /!< 0x00000001 /
		5134	#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /!< 0x00000002 /
		5135	#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /!< 0x00000004 /
		5136	#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /!< 0x00000008 /
		5137
		5138	/****************** Bits definition for RTC_ALRMBR register *************/
		5139	#define RTC_ALRMBR_MSK4_Pos (31U)
		5140	#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /!< 0x80000000 /
		5141	#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
		5142	#define RTC_ALRMBR_WDSEL_Pos (30U)
		5143	#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /!< 0x40000000 /
		5144	#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
		5145	#define RTC_ALRMBR_DT_Pos (28U)
		5146	#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /!< 0x30000000 /
		5147	#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
		5148	#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /!< 0x10000000 /
		5149	#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /!< 0x20000000 /
		5150	#define RTC_ALRMBR_DU_Pos (24U)
		5151	#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /!< 0x0F000000 /
		5152	#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
		5153	#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /!< 0x01000000 /
		5154	#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /!< 0x02000000 /
		5155	#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /!< 0x04000000 /
		5156	#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /!< 0x08000000 /
		5157	#define RTC_ALRMBR_MSK3_Pos (23U)
		5158	#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /!< 0x00800000 /
		5159	#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
		5160	#define RTC_ALRMBR_PM_Pos (22U)
		5161	#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /!< 0x00400000 /
		5162	#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
		5163	#define RTC_ALRMBR_HT_Pos (20U)
		5164	#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /!< 0x00300000 /
		5165	#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
		5166	#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /!< 0x00100000 /
		5167	#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /!< 0x00200000 /
		5168	#define RTC_ALRMBR_HU_Pos (16U)
		5169	#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /!< 0x000F0000 /
		5170	#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
		5171	#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /!< 0x00010000 /
		5172	#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /!< 0x00020000 /
		5173	#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /!< 0x00040000 /
		5174	#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /!< 0x00080000 /
		5175	#define RTC_ALRMBR_MSK2_Pos (15U)
		5176	#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /!< 0x00008000 /
		5177	#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
		5178	#define RTC_ALRMBR_MNT_Pos (12U)
		5179	#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /!< 0x00007000 /
		5180	#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
		5181	#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /!< 0x00001000 /
		5182	#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /!< 0x00002000 /
		5183	#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /!< 0x00004000 /
		5184	#define RTC_ALRMBR_MNU_Pos (8U)
		5185	#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /!< 0x00000F00 /
		5186	#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
		5187	#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /!< 0x00000100 /
		5188	#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /!< 0x00000200 /
		5189	#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /!< 0x00000400 /
		5190	#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /!< 0x00000800 /
		5191	#define RTC_ALRMBR_MSK1_Pos (7U)
		5192	#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /!< 0x00000080 /
		5193	#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
		5194	#define RTC_ALRMBR_ST_Pos (4U)
		5195	#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /!< 0x00000070 /
		5196	#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
		5197	#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /!< 0x00000010 /
		5198	#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /!< 0x00000020 /
		5199	#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /!< 0x00000040 /
		5200	#define RTC_ALRMBR_SU_Pos (0U)
		5201	#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /!< 0x0000000F /
		5202	#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
		5203	#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /!< 0x00000001 /
		5204	#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /!< 0x00000002 /
		5205	#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /!< 0x00000004 /
		5206	#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /!< 0x00000008 /
		5207
		5208	/****************** Bits definition for RTC_WPR register ****************/
		5209	#define RTC_WPR_KEY_Pos (0U)
		5210	#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /!< 0x000000FF /
		5211	#define RTC_WPR_KEY RTC_WPR_KEY_Msk
		5212
		5213	/****************** Bits definition for RTC_SSR register ****************/
		5214	#define RTC_SSR_SS_Pos (0U)
		5215	#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /!< 0x0000FFFF /
		5216	#define RTC_SSR_SS RTC_SSR_SS_Msk
		5217
		5218	/****************** Bits definition for RTC_SHIFTR register *************/
		5219	#define RTC_SHIFTR_SUBFS_Pos (0U)
		5220	#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /!< 0x00007FFF /
		5221	#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
		5222	#define RTC_SHIFTR_ADD1S_Pos (31U)
		5223	#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /!< 0x80000000 /
		5224	#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
		5225
		5226	/****************** Bits definition for RTC_TSTR register ***************/
		5227	#define RTC_TSTR_PM_Pos (22U)
		5228	#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /!< 0x00400000 /
		5229	#define RTC_TSTR_PM RTC_TSTR_PM_Msk
		5230	#define RTC_TSTR_HT_Pos (20U)
		5231	#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /!< 0x00300000 /
		5232	#define RTC_TSTR_HT RTC_TSTR_HT_Msk
		5233	#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /!< 0x00100000 /
		5234	#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /!< 0x00200000 /
		5235	#define RTC_TSTR_HU_Pos (16U)
		5236	#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /!< 0x000F0000 /
		5237	#define RTC_TSTR_HU RTC_TSTR_HU_Msk
		5238	#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /!< 0x00010000 /
		5239	#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /!< 0x00020000 /
		5240	#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /!< 0x00040000 /
		5241	#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /!< 0x00080000 /
		5242	#define RTC_TSTR_MNT_Pos (12U)
		5243	#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /!< 0x00007000 /
		5244	#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
		5245	#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /!< 0x00001000 /
		5246	#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /!< 0x00002000 /
		5247	#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /!< 0x00004000 /
		5248	#define RTC_TSTR_MNU_Pos (8U)
		5249	#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /!< 0x00000F00 /
		5250	#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
		5251	#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /!< 0x00000100 /
		5252	#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /!< 0x00000200 /
		5253	#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /!< 0x00000400 /
		5254	#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /!< 0x00000800 /
		5255	#define RTC_TSTR_ST_Pos (4U)
		5256	#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /!< 0x00000070 /
		5257	#define RTC_TSTR_ST RTC_TSTR_ST_Msk
		5258	#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /!< 0x00000010 /
		5259	#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /!< 0x00000020 /
		5260	#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /!< 0x00000040 /
		5261	#define RTC_TSTR_SU_Pos (0U)
		5262	#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /!< 0x0000000F /
		5263	#define RTC_TSTR_SU RTC_TSTR_SU_Msk
		5264	#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /!< 0x00000001 /
		5265	#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /!< 0x00000002 /
		5266	#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /!< 0x00000004 /
		5267	#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /!< 0x00000008 /
		5268
		5269	/****************** Bits definition for RTC_TSDR register ***************/
		5270	#define RTC_TSDR_WDU_Pos (13U)
		5271	#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /!< 0x0000E000 /
		5272	#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
		5273	#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /!< 0x00002000 /
		5274	#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /!< 0x00004000 /
		5275	#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /!< 0x00008000 /
		5276	#define RTC_TSDR_MT_Pos (12U)
		5277	#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /!< 0x00001000 /
		5278	#define RTC_TSDR_MT RTC_TSDR_MT_Msk
		5279	#define RTC_TSDR_MU_Pos (8U)
		5280	#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /!< 0x00000F00 /
		5281	#define RTC_TSDR_MU RTC_TSDR_MU_Msk
		5282	#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /!< 0x00000100 /
		5283	#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /!< 0x00000200 /
		5284	#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /!< 0x00000400 /
		5285	#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /!< 0x00000800 /
		5286	#define RTC_TSDR_DT_Pos (4U)
		5287	#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /!< 0x00000030 /
		5288	#define RTC_TSDR_DT RTC_TSDR_DT_Msk
		5289	#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /!< 0x00000010 /
		5290	#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /!< 0x00000020 /
		5291	#define RTC_TSDR_DU_Pos (0U)
		5292	#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /!< 0x0000000F /
		5293	#define RTC_TSDR_DU RTC_TSDR_DU_Msk
		5294	#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /!< 0x00000001 /
		5295	#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /!< 0x00000002 /
		5296	#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /!< 0x00000004 /
		5297	#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /!< 0x00000008 /
		5298
		5299	/****************** Bits definition for RTC_TSSSR register **************/
		5300	#define RTC_TSSSR_SS_Pos (0U)
		5301	#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /!< 0x0000FFFF /
		5302	#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
		5303
		5304	/****************** Bits definition for RTC_CAL register ***************/
		5305	#define RTC_CALR_CALP_Pos (15U)
		5306	#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /!< 0x00008000 /
		5307	#define RTC_CALR_CALP RTC_CALR_CALP_Msk
		5308	#define RTC_CALR_CALW8_Pos (14U)
		5309	#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /!< 0x00004000 /
		5310	#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
		5311	#define RTC_CALR_CALW16_Pos (13U)
		5312	#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /!< 0x00002000 /
		5313	#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
		5314	#define RTC_CALR_CALM_Pos (0U)
		5315	#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /!< 0x000001FF /
		5316	#define RTC_CALR_CALM RTC_CALR_CALM_Msk
		5317	#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /!< 0x00000001 /
		5318	#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /!< 0x00000002 /
		5319	#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /!< 0x00000004 /
		5320	#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /!< 0x00000008 /
		5321	#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /!< 0x00000010 /
		5322	#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /!< 0x00000020 /
		5323	#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /!< 0x00000040 /
		5324	#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /!< 0x00000080 /
		5325	#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /!< 0x00000100 /
		5326
		5327	/****************** Bits definition for RTC_TAFCR register **************/
		5328	#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
		5329	#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /!< 0x00040000 /
		5330	#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
		5331	#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
		5332	#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /!< 0x00008000 /
		5333	#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
		5334	#define RTC_TAFCR_TAMPPRCH_Pos (13U)
		5335	#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /!< 0x00006000 /
		5336	#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
		5337	#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /!< 0x00002000 /
		5338	#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /!< 0x00004000 /
		5339	#define RTC_TAFCR_TAMPFLT_Pos (11U)
		5340	#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /!< 0x00001800 /
		5341	#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
		5342	#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /!< 0x00000800 /
		5343	#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /!< 0x00001000 /
		5344	#define RTC_TAFCR_TAMPFREQ_Pos (8U)
		5345	#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000700 /
		5346	#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
		5347	#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000100 /
		5348	#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000200 /
		5349	#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /!< 0x00000400 /
		5350	#define RTC_TAFCR_TAMPTS_Pos (7U)
		5351	#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /!< 0x00000080 /
		5352	#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
		5353	#define RTC_TAFCR_TAMP3TRG_Pos (6U)
		5354	#define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /!< 0x00000040 /
		5355	#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
		5356	#define RTC_TAFCR_TAMP3E_Pos (5U)
		5357	#define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /!< 0x00000020 /
		5358	#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
		5359	#define RTC_TAFCR_TAMP2TRG_Pos (4U)
		5360	#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /!< 0x00000010 /
		5361	#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
		5362	#define RTC_TAFCR_TAMP2E_Pos (3U)
		5363	#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /!< 0x00000008 /
		5364	#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
		5365	#define RTC_TAFCR_TAMPIE_Pos (2U)
		5366	#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /!< 0x00000004 /
		5367	#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
		5368	#define RTC_TAFCR_TAMP1TRG_Pos (1U)
		5369	#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /!< 0x00000002 /
		5370	#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
		5371	#define RTC_TAFCR_TAMP1E_Pos (0U)
		5372	#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /!< 0x00000001 /
		5373	#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
		5374
		5375	/****************** Bits definition for RTC_ALRMASSR register ***********/
		5376	#define RTC_ALRMASSR_MASKSS_Pos (24U)
		5377	#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /!< 0x0F000000 /
		5378	#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
		5379	#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x01000000 /
		5380	#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x02000000 /
		5381	#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x04000000 /
		5382	#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /!< 0x08000000 /
		5383	#define RTC_ALRMASSR_SS_Pos (0U)
		5384	#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /!< 0x00007FFF /
		5385	#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
		5386
		5387	/****************** Bits definition for RTC_ALRMBSSR register ***********/
		5388	#define RTC_ALRMBSSR_MASKSS_Pos (24U)
		5389	#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /!< 0x0F000000 /
		5390	#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
		5391	#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /!< 0x01000000 /
		5392	#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /!< 0x02000000 /
		5393	#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /!< 0x04000000 /
		5394	#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /!< 0x08000000 /
		5395	#define RTC_ALRMBSSR_SS_Pos (0U)
		5396	#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /!< 0x00007FFF /
		5397	#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
		5398
		5399	/****************** Bits definition for RTC_BKP0R register **************/
		5400	#define RTC_BKP0R_Pos (0U)
		5401	#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /!< 0xFFFFFFFF /
		5402	#define RTC_BKP0R RTC_BKP0R_Msk
		5403
		5404	/****************** Bits definition for RTC_BKP1R register **************/
		5405	#define RTC_BKP1R_Pos (0U)
		5406	#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /!< 0xFFFFFFFF /
		5407	#define RTC_BKP1R RTC_BKP1R_Msk
		5408
		5409	/****************** Bits definition for RTC_BKP2R register **************/
		5410	#define RTC_BKP2R_Pos (0U)
		5411	#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /!< 0xFFFFFFFF /
		5412	#define RTC_BKP2R RTC_BKP2R_Msk
		5413
		5414	/****************** Bits definition for RTC_BKP3R register **************/
		5415	#define RTC_BKP3R_Pos (0U)
		5416	#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /!< 0xFFFFFFFF /
		5417	#define RTC_BKP3R RTC_BKP3R_Msk
		5418
		5419	/****************** Bits definition for RTC_BKP4R register **************/
		5420	#define RTC_BKP4R_Pos (0U)
		5421	#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /!< 0xFFFFFFFF /
		5422	#define RTC_BKP4R RTC_BKP4R_Msk
		5423
		5424	/****************** Bits definition for RTC_BKP5R register **************/
		5425	#define RTC_BKP5R_Pos (0U)
		5426	#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /!< 0xFFFFFFFF /
		5427	#define RTC_BKP5R RTC_BKP5R_Msk
		5428
		5429	/****************** Bits definition for RTC_BKP6R register **************/
		5430	#define RTC_BKP6R_Pos (0U)
		5431	#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /!< 0xFFFFFFFF /
		5432	#define RTC_BKP6R RTC_BKP6R_Msk
		5433
		5434	/****************** Bits definition for RTC_BKP7R register **************/
		5435	#define RTC_BKP7R_Pos (0U)
		5436	#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /!< 0xFFFFFFFF /
		5437	#define RTC_BKP7R RTC_BKP7R_Msk
		5438
		5439	/****************** Bits definition for RTC_BKP8R register **************/
		5440	#define RTC_BKP8R_Pos (0U)
		5441	#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /!< 0xFFFFFFFF /
		5442	#define RTC_BKP8R RTC_BKP8R_Msk
		5443
		5444	/****************** Bits definition for RTC_BKP9R register **************/
		5445	#define RTC_BKP9R_Pos (0U)
		5446	#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /!< 0xFFFFFFFF /
		5447	#define RTC_BKP9R RTC_BKP9R_Msk
		5448
		5449	/****************** Bits definition for RTC_BKP10R register *************/
		5450	#define RTC_BKP10R_Pos (0U)
		5451	#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /!< 0xFFFFFFFF /
		5452	#define RTC_BKP10R RTC_BKP10R_Msk
		5453
		5454	/****************** Bits definition for RTC_BKP11R register *************/
		5455	#define RTC_BKP11R_Pos (0U)
		5456	#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /!< 0xFFFFFFFF /
		5457	#define RTC_BKP11R RTC_BKP11R_Msk
		5458
		5459	/****************** Bits definition for RTC_BKP12R register *************/
		5460	#define RTC_BKP12R_Pos (0U)
		5461	#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /!< 0xFFFFFFFF /
		5462	#define RTC_BKP12R RTC_BKP12R_Msk
		5463
		5464	/****************** Bits definition for RTC_BKP13R register *************/
		5465	#define RTC_BKP13R_Pos (0U)
		5466	#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /!< 0xFFFFFFFF /
		5467	#define RTC_BKP13R RTC_BKP13R_Msk
		5468
		5469	/****************** Bits definition for RTC_BKP14R register *************/
		5470	#define RTC_BKP14R_Pos (0U)
		5471	#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /!< 0xFFFFFFFF /
		5472	#define RTC_BKP14R RTC_BKP14R_Msk
		5473
		5474	/****************** Bits definition for RTC_BKP15R register *************/
		5475	#define RTC_BKP15R_Pos (0U)
		5476	#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /!< 0xFFFFFFFF /
		5477	#define RTC_BKP15R RTC_BKP15R_Msk
		5478
		5479	/****************** Bits definition for RTC_BKP16R register *************/
		5480	#define RTC_BKP16R_Pos (0U)
		5481	#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /!< 0xFFFFFFFF /
		5482	#define RTC_BKP16R RTC_BKP16R_Msk
		5483
		5484	/****************** Bits definition for RTC_BKP17R register *************/
		5485	#define RTC_BKP17R_Pos (0U)
		5486	#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /!< 0xFFFFFFFF /
		5487	#define RTC_BKP17R RTC_BKP17R_Msk
		5488
		5489	/****************** Bits definition for RTC_BKP18R register *************/
		5490	#define RTC_BKP18R_Pos (0U)
		5491	#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /!< 0xFFFFFFFF /
		5492	#define RTC_BKP18R RTC_BKP18R_Msk
		5493
		5494	/****************** Bits definition for RTC_BKP19R register *************/
		5495	#define RTC_BKP19R_Pos (0U)
		5496	#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /!< 0xFFFFFFFF /
		5497	#define RTC_BKP19R RTC_BKP19R_Msk
		5498
		5499	/****************** Bits definition for RTC_BKP20R register *************/
		5500	#define RTC_BKP20R_Pos (0U)
		5501	#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /!< 0xFFFFFFFF /
		5502	#define RTC_BKP20R RTC_BKP20R_Msk
		5503
		5504	/****************** Bits definition for RTC_BKP21R register *************/
		5505	#define RTC_BKP21R_Pos (0U)
		5506	#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /!< 0xFFFFFFFF /
		5507	#define RTC_BKP21R RTC_BKP21R_Msk
		5508
		5509	/****************** Bits definition for RTC_BKP22R register *************/
		5510	#define RTC_BKP22R_Pos (0U)
		5511	#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /!< 0xFFFFFFFF /
		5512	#define RTC_BKP22R RTC_BKP22R_Msk
		5513
		5514	/****************** Bits definition for RTC_BKP23R register *************/
		5515	#define RTC_BKP23R_Pos (0U)
		5516	#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /!< 0xFFFFFFFF /
		5517	#define RTC_BKP23R RTC_BKP23R_Msk
		5518
		5519	/****************** Bits definition for RTC_BKP24R register *************/
		5520	#define RTC_BKP24R_Pos (0U)
		5521	#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /!< 0xFFFFFFFF /
		5522	#define RTC_BKP24R RTC_BKP24R_Msk
		5523
		5524	/****************** Bits definition for RTC_BKP25R register *************/
		5525	#define RTC_BKP25R_Pos (0U)
		5526	#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /!< 0xFFFFFFFF /
		5527	#define RTC_BKP25R RTC_BKP25R_Msk
		5528
		5529	/****************** Bits definition for RTC_BKP26R register *************/
		5530	#define RTC_BKP26R_Pos (0U)
		5531	#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /!< 0xFFFFFFFF /
		5532	#define RTC_BKP26R RTC_BKP26R_Msk
		5533
		5534	/****************** Bits definition for RTC_BKP27R register *************/
		5535	#define RTC_BKP27R_Pos (0U)
		5536	#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /!< 0xFFFFFFFF /
		5537	#define RTC_BKP27R RTC_BKP27R_Msk
		5538
		5539	/****************** Bits definition for RTC_BKP28R register *************/
		5540	#define RTC_BKP28R_Pos (0U)
		5541	#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /!< 0xFFFFFFFF /
		5542	#define RTC_BKP28R RTC_BKP28R_Msk
		5543
		5544	/****************** Bits definition for RTC_BKP29R register *************/
		5545	#define RTC_BKP29R_Pos (0U)
		5546	#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /!< 0xFFFFFFFF /
		5547	#define RTC_BKP29R RTC_BKP29R_Msk
		5548
		5549	/****************** Bits definition for RTC_BKP30R register *************/
		5550	#define RTC_BKP30R_Pos (0U)
		5551	#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /!< 0xFFFFFFFF /
		5552	#define RTC_BKP30R RTC_BKP30R_Msk
		5553
		5554	/****************** Bits definition for RTC_BKP31R register *************/
		5555	#define RTC_BKP31R_Pos (0U)
		5556	#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /!< 0xFFFFFFFF /
		5557	#define RTC_BKP31R RTC_BKP31R_Msk
		5558
		5559	/****************** Number of backup registers ****************************/
		5560	#define RTC_BKP_NUMBER 32
		5561
		5562	/******************************************************************************/
		5563	/* */
		5564	/* Serial Peripheral Interface (SPI) */
		5565	/* */
		5566	/******************************************************************************/
		5567
		5568	/*
		5569	* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
		5570	*/
		5571	#define SPI_I2S_SUPPORT
		5572
		5573	/***************** Bit definition for SPI_CR1 register ******************/
		5574	#define SPI_CR1_CPHA_Pos (0U)
		5575	#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /!< 0x00000001 /
		5576	#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /!< Clock Phase /
		5577	#define SPI_CR1_CPOL_Pos (1U)
		5578	#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /!< 0x00000002 /
		5579	#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /!< Clock Polarity /
		5580	#define SPI_CR1_MSTR_Pos (2U)
		5581	#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /!< 0x00000004 /
		5582	#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /!< Master Selection /
		5583
		5584	#define SPI_CR1_BR_Pos (3U)
		5585	#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /!< 0x00000038 /
		5586	#define SPI_CR1_BR SPI_CR1_BR_Msk /!< BR[2:0] bits (Baud Rate Control) /
		5587	#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /!< 0x00000008 /
		5588	#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /!< 0x00000010 /
		5589	#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /!< 0x00000020 /
		5590
		5591	#define SPI_CR1_SPE_Pos (6U)
		5592	#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /!< 0x00000040 /
		5593	#define SPI_CR1_SPE SPI_CR1_SPE_Msk /!< SPI Enable /
		5594	#define SPI_CR1_LSBFIRST_Pos (7U)
		5595	#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /!< 0x00000080 /
		5596	#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /!< Frame Format /
		5597	#define SPI_CR1_SSI_Pos (8U)
		5598	#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /!< 0x00000100 /
		5599	#define SPI_CR1_SSI SPI_CR1_SSI_Msk /!< Internal slave select /
		5600	#define SPI_CR1_SSM_Pos (9U)
		5601	#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /!< 0x00000200 /
		5602	#define SPI_CR1_SSM SPI_CR1_SSM_Msk /!< Software slave management /
		5603	#define SPI_CR1_RXONLY_Pos (10U)
		5604	#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /!< 0x00000400 /
		5605	#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /!< Receive only /
		5606	#define SPI_CR1_DFF_Pos (11U)
		5607	#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /!< 0x00000800 /
		5608	#define SPI_CR1_DFF SPI_CR1_DFF_Msk /!< Data Frame Format /
		5609	#define SPI_CR1_CRCNEXT_Pos (12U)
		5610	#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /!< 0x00001000 /
		5611	#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /!< Transmit CRC next /
		5612	#define SPI_CR1_CRCEN_Pos (13U)
		5613	#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /!< 0x00002000 /
		5614	#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /!< Hardware CRC calculation enable /
		5615	#define SPI_CR1_BIDIOE_Pos (14U)
		5616	#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /!< 0x00004000 /
		5617	#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /!< Output enable in bidirectional mode /
		5618	#define SPI_CR1_BIDIMODE_Pos (15U)
		5619	#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /!< 0x00008000 /
		5620	#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /!< Bidirectional data mode enable /
		5621
		5622	/***************** Bit definition for SPI_CR2 register ******************/
		5623	#define SPI_CR2_RXDMAEN_Pos (0U)
		5624	#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /!< 0x00000001 /
		5625	#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /!< Rx Buffer DMA Enable /
		5626	#define SPI_CR2_TXDMAEN_Pos (1U)
		5627	#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /!< 0x00000002 /
		5628	#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /!< Tx Buffer DMA Enable /
		5629	#define SPI_CR2_SSOE_Pos (2U)
		5630	#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /!< 0x00000004 /
		5631	#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /!< SS Output Enable /
		5632	#define SPI_CR2_FRF_Pos (4U)
		5633	#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /!< 0x00000010 /
		5634	#define SPI_CR2_FRF SPI_CR2_FRF_Msk /!< Frame format /
		5635	#define SPI_CR2_ERRIE_Pos (5U)
		5636	#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /!< 0x00000020 /
		5637	#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /!< Error Interrupt Enable /
		5638	#define SPI_CR2_RXNEIE_Pos (6U)
		5639	#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /!< 0x00000040 /
		5640	#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /!< RX buffer Not Empty Interrupt Enable /
		5641	#define SPI_CR2_TXEIE_Pos (7U)
		5642	#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /!< 0x00000080 /
		5643	#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /!< Tx buffer Empty Interrupt Enable /
		5644
		5645	/****************** Bit definition for SPI_SR register ******************/
		5646	#define SPI_SR_RXNE_Pos (0U)
		5647	#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /!< 0x00000001 /
		5648	#define SPI_SR_RXNE SPI_SR_RXNE_Msk /!< Receive buffer Not Empty /
		5649	#define SPI_SR_TXE_Pos (1U)
		5650	#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /!< 0x00000002 /
		5651	#define SPI_SR_TXE SPI_SR_TXE_Msk /!< Transmit buffer Empty /
		5652	#define SPI_SR_CHSIDE_Pos (2U)
		5653	#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /!< 0x00000004 /
		5654	#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /!< Channel side /
		5655	#define SPI_SR_UDR_Pos (3U)
		5656	#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /!< 0x00000008 /
		5657	#define SPI_SR_UDR SPI_SR_UDR_Msk /!< Underrun flag /
		5658	#define SPI_SR_CRCERR_Pos (4U)
		5659	#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /!< 0x00000010 /
		5660	#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /!< CRC Error flag /
		5661	#define SPI_SR_MODF_Pos (5U)
		5662	#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /!< 0x00000020 /
		5663	#define SPI_SR_MODF SPI_SR_MODF_Msk /!< Mode fault /
		5664	#define SPI_SR_OVR_Pos (6U)
		5665	#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /!< 0x00000040 /
		5666	#define SPI_SR_OVR SPI_SR_OVR_Msk /!< Overrun flag /
		5667	#define SPI_SR_BSY_Pos (7U)
		5668	#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /!< 0x00000080 /
		5669	#define SPI_SR_BSY SPI_SR_BSY_Msk /!< Busy flag /
		5670	#define SPI_SR_FRE_Pos (8U)
		5671	#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /!< 0x00000100 /
		5672	#define SPI_SR_FRE SPI_SR_FRE_Msk /!<Frame format error flag /
		5673
		5674	/****************** Bit definition for SPI_DR register ******************/
		5675	#define SPI_DR_DR_Pos (0U)
		5676	#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /!< 0x0000FFFF /
		5677	#define SPI_DR_DR SPI_DR_DR_Msk /!< Data Register /
		5678
		5679	/***************** Bit definition for SPI_CRCPR register ****************/
		5680	#define SPI_CRCPR_CRCPOLY_Pos (0U)
		5681	#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /!< 0x0000FFFF /
		5682	#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /!< CRC polynomial register /
		5683
		5684	/**************** Bit definition for SPI_RXCRCR register ****************/
		5685	#define SPI_RXCRCR_RXCRC_Pos (0U)
		5686	#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /!< 0x0000FFFF /
		5687	#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /!< Rx CRC Register /
		5688
		5689	/**************** Bit definition for SPI_TXCRCR register ****************/
		5690	#define SPI_TXCRCR_TXCRC_Pos (0U)
		5691	#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /!< 0x0000FFFF /
		5692	#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /!< Tx CRC Register /
		5693
		5694	/**************** Bit definition for SPI_I2SCFGR register ***************/
		5695	#define SPI_I2SCFGR_CHLEN_Pos (0U)
		5696	#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /!< 0x00000001 /
		5697	#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /!<Channel length (number of bits per audio channel) /
		5698
		5699	#define SPI_I2SCFGR_DATLEN_Pos (1U)
		5700	#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000006 /
		5701	#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /!<DATLEN[1:0] bits (Data length to be transferred) /
		5702	#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000002 /
		5703	#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /!< 0x00000004 /
		5704
		5705	#define SPI_I2SCFGR_CKPOL_Pos (3U)
		5706	#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /!< 0x00000008 /
		5707	#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /!<steady state clock polarity /
		5708
		5709	#define SPI_I2SCFGR_I2SSTD_Pos (4U)
		5710	#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000030 /
		5711	#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /!<I2SSTD[1:0] bits (I2S standard selection) /
		5712	#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000010 /
		5713	#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /!< 0x00000020 /
		5714
		5715	#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
		5716	#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /!< 0x00000080 /
		5717	#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /!<PCM frame synchronization /
		5718
		5719	#define SPI_I2SCFGR_I2SCFG_Pos (8U)
		5720	#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000300 /
		5721	#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /!<I2SCFG[1:0] bits (I2S configuration mode) /
		5722	#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000100 /
		5723	#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /!< 0x00000200 /
		5724
		5725	#define SPI_I2SCFGR_I2SE_Pos (10U)
		5726	#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /!< 0x00000400 /
		5727	#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /!<I2S Enable /
		5728	#define SPI_I2SCFGR_I2SMOD_Pos (11U)
		5729	#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /!< 0x00000800 /
		5730	#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /!<I2S mode selection /
		5731
		5732	/**************** Bit definition for SPI_I2SPR register *****************/
		5733	#define SPI_I2SPR_I2SDIV_Pos (0U)
		5734	#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /!< 0x000000FF /
		5735	#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /!<I2S Linear prescaler /
		5736	#define SPI_I2SPR_ODD_Pos (8U)
		5737	#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /!< 0x00000100 /
		5738	#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /!<Odd factor for the prescaler /
		5739	#define SPI_I2SPR_MCKOE_Pos (9U)
		5740	#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /!< 0x00000200 /
		5741	#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /!<Master Clock Output Enable /
		5742
		5743	/******************************************************************************/
		5744	/* */
		5745	/* System Configuration (SYSCFG) */
		5746	/* */
		5747	/******************************************************************************/
		5748	/*************** Bit definition for SYSCFG_MEMRMP register **************/
		5749	#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
		5750	#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /!< 0x00000003 /
		5751	#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /!< SYSCFG_Memory Remap Config /
		5752	#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /!< 0x00000001 /
		5753	#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /!< 0x00000002 /
		5754	#define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U)
		5755	#define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /!< 0x00000300 /
		5756	#define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /!< Boot mode Config /
		5757	#define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /!< 0x00000100 /
		5758	#define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /!< 0x00000200 /
		5759
		5760	/*************** Bit definition for SYSCFG_PMC register *****************/
		5761	#define SYSCFG_PMC_USB_PU_Pos (0U)
		5762	#define SYSCFG_PMC_USB_PU_Msk (0x1U << SYSCFG_PMC_USB_PU_Pos) /!< 0x00000001 /
		5763	#define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /!< SYSCFG PMC /
		5764
		5765	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
		5766	#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
		5767	#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /!< 0x0000000F /
		5768	#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /!< EXTI 0 configuration /
		5769	#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
		5770	#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /!< 0x000000F0 /
		5771	#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /!< EXTI 1 configuration /
		5772	#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
		5773	#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /!< 0x00000F00 /
		5774	#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /!< EXTI 2 configuration /
		5775	#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
		5776	#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /!< 0x0000F000 /
		5777	#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /!< EXTI 3 configuration /
		5778
		5779	/**
		5780	* @brief EXTI0 configuration
		5781	*/
		5782	#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /!< PA[0] pin /
		5783	#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /!< PB[0] pin /
		5784	#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /!< PC[0] pin /
		5785	#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /!< PD[0] pin /
		5786	#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /!< PE[0] pin /
		5787	#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /!< PH[0] pin /
		5788	#define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /!< PF[0] pin /
		5789	#define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /!< PG[0] pin /
		5790
		5791	/**
		5792	* @brief EXTI1 configuration
		5793	*/
		5794	#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /!< PA[1] pin /
		5795	#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /!< PB[1] pin /
		5796	#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /!< PC[1] pin /
		5797	#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /!< PD[1] pin /
		5798	#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /!< PE[1] pin /
		5799	#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /!< PH[1] pin /
		5800	#define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /!< PF[1] pin /
		5801	#define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /!< PG[1] pin /
		5802
		5803	/**
		5804	* @brief EXTI2 configuration
		5805	*/
		5806	#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /!< PA[2] pin /
		5807	#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /!< PB[2] pin /
		5808	#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /!< PC[2] pin /
		5809	#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /!< PD[2] pin /
		5810	#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /!< PE[2] pin /
		5811	#define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /!< PH[2] pin /
		5812	#define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /!< PF[2] pin /
		5813	#define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /!< PG[2] pin /
		5814
		5815	/**
		5816	* @brief EXTI3 configuration
		5817	*/
		5818	#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /!< PA[3] pin /
		5819	#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /!< PB[3] pin /
		5820	#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /!< PC[3] pin /
		5821	#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /!< PD[3] pin /
		5822	#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /!< PE[3] pin /
		5823	#define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /!< PF[3] pin /
		5824	#define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /!< PG[3] pin /
		5825
		5826	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
		5827	#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
		5828	#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /!< 0x0000000F /
		5829	#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /!< EXTI 4 configuration /
		5830	#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
		5831	#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /!< 0x000000F0 /
		5832	#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /!< EXTI 5 configuration /
		5833	#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
		5834	#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /!< 0x00000F00 /
		5835	#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /!< EXTI 6 configuration /
		5836	#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
		5837	#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /!< 0x0000F000 /
		5838	#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /!< EXTI 7 configuration /
		5839
		5840	/**
		5841	* @brief EXTI4 configuration
		5842	*/
		5843	#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /!< PA[4] pin /
		5844	#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /!< PB[4] pin /
		5845	#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /!< PC[4] pin /
		5846	#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /!< PD[4] pin /
		5847	#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /!< PE[4] pin /
		5848	#define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /!< PF[4] pin /
		5849	#define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /!< PG[4] pin /
		5850
		5851	/**
		5852	* @brief EXTI5 configuration
		5853	*/
		5854	#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /!< PA[5] pin /
		5855	#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /!< PB[5] pin /
		5856	#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /!< PC[5] pin /
		5857	#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /!< PD[5] pin /
		5858	#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /!< PE[5] pin /
		5859	#define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /!< PF[5] pin /
		5860	#define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /!< PG[5] pin /
		5861
		5862	/**
		5863	* @brief EXTI6 configuration
		5864	*/
		5865	#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /!< PA[6] pin /
		5866	#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /!< PB[6] pin /
		5867	#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /!< PC[6] pin /
		5868	#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /!< PD[6] pin /
		5869	#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /!< PE[6] pin /
		5870	#define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /!< PF[6] pin /
		5871	#define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /!< PG[6] pin /
		5872
		5873	/**
		5874	* @brief EXTI7 configuration
		5875	*/
		5876	#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /!< PA[7] pin /
		5877	#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /!< PB[7] pin /
		5878	#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /!< PC[7] pin /
		5879	#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /!< PD[7] pin /
		5880	#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /!< PE[7] pin /
		5881	#define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /!< PF[7] pin /
		5882	#define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /!< PG[7] pin /
		5883
		5884	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
		5885	#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
		5886	#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /!< 0x0000000F /
		5887	#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /!< EXTI 8 configuration /
		5888	#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
		5889	#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /!< 0x000000F0 /
		5890	#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /!< EXTI 9 configuration /
		5891	#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
		5892	#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /!< 0x00000F00 /
		5893	#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /!< EXTI 10 configuration /
		5894	#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
		5895	#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /!< 0x0000F000 /
		5896	#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /!< EXTI 11 configuration /
		5897
		5898	/**
		5899	* @brief EXTI8 configuration
		5900	*/
		5901	#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /!< PA[8] pin /
		5902	#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /!< PB[8] pin /
		5903	#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /!< PC[8] pin /
		5904	#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /!< PD[8] pin /
		5905	#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /!< PE[8] pin /
		5906	#define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /!< PF[8] pin /
		5907	#define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /!< PG[8] pin /
		5908
		5909	/**
		5910	* @brief EXTI9 configuration
		5911	*/
		5912	#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /!< PA[9] pin /
		5913	#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /!< PB[9] pin /
		5914	#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /!< PC[9] pin /
		5915	#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /!< PD[9] pin /
		5916	#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /!< PE[9] pin /
		5917	#define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /!< PF[9] pin /
		5918	#define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /!< PG[9] pin /
		5919
		5920	/**
		5921	* @brief EXTI10 configuration
		5922	*/
		5923	#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /!< PA[10] pin /
		5924	#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /!< PB[10] pin /
		5925	#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /!< PC[10] pin /
		5926	#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /!< PD[10] pin /
		5927	#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /!< PE[10] pin /
		5928	#define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /!< PF[10] pin /
		5929	#define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /!< PG[10] pin /
		5930
		5931	/**
		5932	* @brief EXTI11 configuration
		5933	*/
		5934	#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /!< PA[11] pin /
		5935	#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /!< PB[11] pin /
		5936	#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /!< PC[11] pin /
		5937	#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /!< PD[11] pin /
		5938	#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /!< PE[11] pin /
		5939	#define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /!< PF[11] pin /
		5940	#define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /!< PG[11] pin /
		5941
		5942	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
		5943	#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
		5944	#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /!< 0x0000000F /
		5945	#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /!< EXTI 12 configuration /
		5946	#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
		5947	#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /!< 0x000000F0 /
		5948	#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /!< EXTI 13 configuration /
		5949	#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
		5950	#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /!< 0x00000F00 /
		5951	#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /!< EXTI 14 configuration /
		5952	#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
		5953	#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /!< 0x0000F000 /
		5954	#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /!< EXTI 15 configuration /
		5955
		5956	/**
		5957	* @brief EXTI12 configuration
		5958	*/
		5959	#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /!< PA[12] pin /
		5960	#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /!< PB[12] pin /
		5961	#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /!< PC[12] pin /
		5962	#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /!< PD[12] pin /
		5963	#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /!< PE[12] pin /
		5964	#define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /!< PF[12] pin /
		5965	#define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /!< PG[12] pin /
		5966
		5967	/**
		5968	* @brief EXTI13 configuration
		5969	*/
		5970	#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /!< PA[13] pin /
		5971	#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /!< PB[13] pin /
		5972	#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /!< PC[13] pin /
		5973	#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /!< PD[13] pin /
		5974	#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /!< PE[13] pin /
		5975	#define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /!< PF[13] pin /
		5976	#define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /!< PG[13] pin /
		5977
		5978	/**
		5979	* @brief EXTI14 configuration
		5980	*/
		5981	#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /!< PA[14] pin /
		5982	#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /!< PB[14] pin /
		5983	#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /!< PC[14] pin /
		5984	#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /!< PD[14] pin /
		5985	#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /!< PE[14] pin /
		5986	#define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /!< PF[14] pin /
		5987	#define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /!< PG[14] pin /
		5988
		5989	/**
		5990	* @brief EXTI15 configuration
		5991	*/
		5992	#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /!< PA[15] pin /
		5993	#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /!< PB[15] pin /
		5994	#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /!< PC[15] pin /
		5995	#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /!< PD[15] pin /
		5996	#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /!< PE[15] pin /
		5997	#define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /!< PF[15] pin /
		5998	#define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /!< PG[15] pin /
		5999
		6000	/******************************************************************************/
		6001	/* */
		6002	/* Routing Interface (RI) */
		6003	/* */
		6004	/******************************************************************************/
		6005
		6006	/****************** Bit definition for RI_ICR register ******************/
		6007	#define RI_ICR_IC1OS_Pos (0U)
		6008	#define RI_ICR_IC1OS_Msk (0xFU << RI_ICR_IC1OS_Pos) /!< 0x0000000F /
		6009	#define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /!< IC1OS[3:0] bits (Input Capture 1 select bits) /
		6010	#define RI_ICR_IC1OS_0 (0x1U << RI_ICR_IC1OS_Pos) /!< 0x00000001 /
		6011	#define RI_ICR_IC1OS_1 (0x2U << RI_ICR_IC1OS_Pos) /!< 0x00000002 /
		6012	#define RI_ICR_IC1OS_2 (0x4U << RI_ICR_IC1OS_Pos) /!< 0x00000004 /
		6013	#define RI_ICR_IC1OS_3 (0x8U << RI_ICR_IC1OS_Pos) /!< 0x00000008 /
		6014
		6015	#define RI_ICR_IC2OS_Pos (4U)
		6016	#define RI_ICR_IC2OS_Msk (0xFU << RI_ICR_IC2OS_Pos) /!< 0x000000F0 /
		6017	#define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /!< IC2OS[3:0] bits (Input Capture 2 select bits) /
		6018	#define RI_ICR_IC2OS_0 (0x1U << RI_ICR_IC2OS_Pos) /!< 0x00000010 /
		6019	#define RI_ICR_IC2OS_1 (0x2U << RI_ICR_IC2OS_Pos) /!< 0x00000020 /
		6020	#define RI_ICR_IC2OS_2 (0x4U << RI_ICR_IC2OS_Pos) /!< 0x00000040 /
		6021	#define RI_ICR_IC2OS_3 (0x8U << RI_ICR_IC2OS_Pos) /!< 0x00000080 /
		6022
		6023	#define RI_ICR_IC3OS_Pos (8U)
		6024	#define RI_ICR_IC3OS_Msk (0xFU << RI_ICR_IC3OS_Pos) /!< 0x00000F00 /
		6025	#define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /!< IC3OS[3:0] bits (Input Capture 3 select bits) /
		6026	#define RI_ICR_IC3OS_0 (0x1U << RI_ICR_IC3OS_Pos) /!< 0x00000100 /
		6027	#define RI_ICR_IC3OS_1 (0x2U << RI_ICR_IC3OS_Pos) /!< 0x00000200 /
		6028	#define RI_ICR_IC3OS_2 (0x4U << RI_ICR_IC3OS_Pos) /!< 0x00000400 /
		6029	#define RI_ICR_IC3OS_3 (0x8U << RI_ICR_IC3OS_Pos) /!< 0x00000800 /
		6030
		6031	#define RI_ICR_IC4OS_Pos (12U)
		6032	#define RI_ICR_IC4OS_Msk (0xFU << RI_ICR_IC4OS_Pos) /!< 0x0000F000 /
		6033	#define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /!< IC4OS[3:0] bits (Input Capture 4 select bits) /
		6034	#define RI_ICR_IC4OS_0 (0x1U << RI_ICR_IC4OS_Pos) /!< 0x00001000 /
		6035	#define RI_ICR_IC4OS_1 (0x2U << RI_ICR_IC4OS_Pos) /!< 0x00002000 /
		6036	#define RI_ICR_IC4OS_2 (0x4U << RI_ICR_IC4OS_Pos) /!< 0x00004000 /
		6037	#define RI_ICR_IC4OS_3 (0x8U << RI_ICR_IC4OS_Pos) /!< 0x00008000 /
		6038
		6039	#define RI_ICR_TIM_Pos (16U)
		6040	#define RI_ICR_TIM_Msk (0x3U << RI_ICR_TIM_Pos) /!< 0x00030000 /
		6041	#define RI_ICR_TIM RI_ICR_TIM_Msk /!< TIM[3:0] bits (Timers select bits) /
		6042	#define RI_ICR_TIM_0 (0x1U << RI_ICR_TIM_Pos) /!< 0x00010000 /
		6043	#define RI_ICR_TIM_1 (0x2U << RI_ICR_TIM_Pos) /!< 0x00020000 /
		6044
		6045	#define RI_ICR_IC1_Pos (18U)
		6046	#define RI_ICR_IC1_Msk (0x1U << RI_ICR_IC1_Pos) /!< 0x00040000 /
		6047	#define RI_ICR_IC1 RI_ICR_IC1_Msk /!< Input capture 1 /
		6048	#define RI_ICR_IC2_Pos (19U)
		6049	#define RI_ICR_IC2_Msk (0x1U << RI_ICR_IC2_Pos) /!< 0x00080000 /
		6050	#define RI_ICR_IC2 RI_ICR_IC2_Msk /!< Input capture 2 /
		6051	#define RI_ICR_IC3_Pos (20U)
		6052	#define RI_ICR_IC3_Msk (0x1U << RI_ICR_IC3_Pos) /!< 0x00100000 /
		6053	#define RI_ICR_IC3 RI_ICR_IC3_Msk /!< Input capture 3 /
		6054	#define RI_ICR_IC4_Pos (21U)
		6055	#define RI_ICR_IC4_Msk (0x1U << RI_ICR_IC4_Pos) /!< 0x00200000 /
		6056	#define RI_ICR_IC4 RI_ICR_IC4_Msk /!< Input capture 4 /
		6057
		6058	/****************** Bit definition for RI_ASCR1 register ******************/
		6059	#define RI_ASCR1_CH_Pos (0U)
		6060	#define RI_ASCR1_CH_Msk (0x7BFDFFFFU << RI_ASCR1_CH_Pos) /!< 0x7BFDFFFF /
		6061	#define RI_ASCR1_CH RI_ASCR1_CH_Msk /!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) /
		6062	#define RI_ASCR1_CH_0 (0x00000001U) /!< Bit 0 /
		6063	#define RI_ASCR1_CH_1 (0x00000002U) /!< Bit 1 /
		6064	#define RI_ASCR1_CH_2 (0x00000004U) /!< Bit 2 /
		6065	#define RI_ASCR1_CH_3 (0x00000008U) /!< Bit 3 /
		6066	#define RI_ASCR1_CH_4 (0x00000010U) /!< Bit 4 /
		6067	#define RI_ASCR1_CH_5 (0x00000020U) /!< Bit 5 /
		6068	#define RI_ASCR1_CH_6 (0x00000040U) /!< Bit 6 /
		6069	#define RI_ASCR1_CH_7 (0x00000080U) /!< Bit 7 /
		6070	#define RI_ASCR1_CH_8 (0x00000100U) /!< Bit 8 /
		6071	#define RI_ASCR1_CH_9 (0x00000200U) /!< Bit 9 /
		6072	#define RI_ASCR1_CH_10 (0x00000400U) /!< Bit 10 /
		6073	#define RI_ASCR1_CH_11 (0x00000800U) /!< Bit 11 /
		6074	#define RI_ASCR1_CH_12 (0x00001000U) /!< Bit 12 /
		6075	#define RI_ASCR1_CH_13 (0x00002000U) /!< Bit 13 /
		6076	#define RI_ASCR1_CH_14 (0x00004000U) /!< Bit 14 /
		6077	#define RI_ASCR1_CH_15 (0x00008000U) /!< Bit 15 /
		6078	#define RI_ASCR1_CH_31 (0x00010000U) /!< Bit 16 /
		6079	#define RI_ASCR1_CH_18 (0x00040000U) /!< Bit 18 /
		6080	#define RI_ASCR1_CH_19 (0x00080000U) /!< Bit 19 /
		6081	#define RI_ASCR1_CH_20 (0x00100000U) /!< Bit 20 /
		6082	#define RI_ASCR1_CH_21 (0x00200000U) /!< Bit 21 /
		6083	#define RI_ASCR1_CH_22 (0x00400000U) /!< Bit 22 /
		6084	#define RI_ASCR1_CH_23 (0x00800000U) /!< Bit 23 /
		6085	#define RI_ASCR1_CH_24 (0x01000000U) /!< Bit 24 /
		6086	#define RI_ASCR1_CH_25 (0x02000000U) /!< Bit 25 /
		6087	#define RI_ASCR1_VCOMP_Pos (26U)
		6088	#define RI_ASCR1_VCOMP_Msk (0x1U << RI_ASCR1_VCOMP_Pos) /!< 0x04000000 /
		6089	#define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /!< ADC analog switch selection for internal node to COMP1 /
		6090	#define RI_ASCR1_CH_27 (0x08000000U) /!< Bit 27 /
		6091	#define RI_ASCR1_CH_28 (0x10000000U) /!< Bit 28 /
		6092	#define RI_ASCR1_CH_29 (0x20000000U) /!< Bit 29 /
		6093	#define RI_ASCR1_CH_30 (0x40000000U) /!< Bit 30 /
		6094	#define RI_ASCR1_SCM_Pos (31U)
		6095	#define RI_ASCR1_SCM_Msk (0x1U << RI_ASCR1_SCM_Pos) /!< 0x80000000 /
		6096	#define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /!< I/O Switch control mode /
		6097
		6098	/****************** Bit definition for RI_ASCR2 register ******************/
		6099	#define RI_ASCR2_GR10_1 (0x00000001U) /!< GR10-1 selection bit /
		6100	#define RI_ASCR2_GR10_2 (0x00000002U) /!< GR10-2 selection bit /
		6101	#define RI_ASCR2_GR10_3 (0x00000004U) /!< GR10-3 selection bit /
		6102	#define RI_ASCR2_GR10_4 (0x00000008U) /!< GR10-4 selection bit /
		6103	#define RI_ASCR2_GR6_Pos (4U)
		6104	#define RI_ASCR2_GR6_Msk (0x1800003U << RI_ASCR2_GR6_Pos) /!< 0x18000030 /
		6105	#define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /!< GR6 selection bits /
		6106	#define RI_ASCR2_GR6_1 (0x0000001U << RI_ASCR2_GR6_Pos) /!< 0x00000010 /
		6107	#define RI_ASCR2_GR6_2 (0x0000002U << RI_ASCR2_GR6_Pos) /!< 0x00000020 /
		6108	#define RI_ASCR2_GR6_3 (0x0800000U << RI_ASCR2_GR6_Pos) /!< 0x08000000 /
		6109	#define RI_ASCR2_GR6_4 (0x1000000U << RI_ASCR2_GR6_Pos) /!< 0x10000000 /
		6110	#define RI_ASCR2_GR5_1 (0x00000040U) /!< GR5-1 selection bit /
		6111	#define RI_ASCR2_GR5_2 (0x00000080U) /!< GR5-2 selection bit /
		6112	#define RI_ASCR2_GR5_3 (0x00000100U) /!< GR5-3 selection bit /
		6113	#define RI_ASCR2_GR4_1 (0x00000200U) /!< GR4-1 selection bit /
		6114	#define RI_ASCR2_GR4_2 (0x00000400U) /!< GR4-2 selection bit /
		6115	#define RI_ASCR2_GR4_3 (0x00000800U) /!< GR4-3 selection bit /
		6116	#define RI_ASCR2_GR4_4 (0x00008000U) /!< GR4-4 selection bit /
		6117	#define RI_ASCR2_CH0b_Pos (16U)
		6118	#define RI_ASCR2_CH0b_Msk (0x1U << RI_ASCR2_CH0b_Pos) /!< 0x00010000 /
		6119	#define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /!< CH0b selection bit /
		6120	#define RI_ASCR2_CH1b_Pos (17U)
		6121	#define RI_ASCR2_CH1b_Msk (0x1U << RI_ASCR2_CH1b_Pos) /!< 0x00020000 /
		6122	#define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /!< CH1b selection bit /
		6123	#define RI_ASCR2_CH2b_Pos (18U)
		6124	#define RI_ASCR2_CH2b_Msk (0x1U << RI_ASCR2_CH2b_Pos) /!< 0x00040000 /
		6125	#define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /!< CH2b selection bit /
		6126	#define RI_ASCR2_CH3b_Pos (19U)
		6127	#define RI_ASCR2_CH3b_Msk (0x1U << RI_ASCR2_CH3b_Pos) /!< 0x00080000 /
		6128	#define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /!< CH3b selection bit /
		6129	#define RI_ASCR2_CH6b_Pos (20U)
		6130	#define RI_ASCR2_CH6b_Msk (0x1U << RI_ASCR2_CH6b_Pos) /!< 0x00100000 /
		6131	#define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /!< CH6b selection bit /
		6132	#define RI_ASCR2_CH7b_Pos (21U)
		6133	#define RI_ASCR2_CH7b_Msk (0x1U << RI_ASCR2_CH7b_Pos) /!< 0x00200000 /
		6134	#define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /!< CH7b selection bit /
		6135	#define RI_ASCR2_CH8b_Pos (22U)
		6136	#define RI_ASCR2_CH8b_Msk (0x1U << RI_ASCR2_CH8b_Pos) /!< 0x00400000 /
		6137	#define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /!< CH8b selection bit /
		6138	#define RI_ASCR2_CH9b_Pos (23U)
		6139	#define RI_ASCR2_CH9b_Msk (0x1U << RI_ASCR2_CH9b_Pos) /!< 0x00800000 /
		6140	#define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /!< CH9b selection bit /
		6141	#define RI_ASCR2_CH10b_Pos (24U)
		6142	#define RI_ASCR2_CH10b_Msk (0x1U << RI_ASCR2_CH10b_Pos) /!< 0x01000000 /
		6143	#define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /!< CH10b selection bit /
		6144	#define RI_ASCR2_CH11b_Pos (25U)
		6145	#define RI_ASCR2_CH11b_Msk (0x1U << RI_ASCR2_CH11b_Pos) /!< 0x02000000 /
		6146	#define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /!< CH11b selection bit /
		6147	#define RI_ASCR2_CH12b_Pos (26U)
		6148	#define RI_ASCR2_CH12b_Msk (0x1U << RI_ASCR2_CH12b_Pos) /!< 0x04000000 /
		6149	#define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /!< CH12b selection bit /
		6150
		6151	/****************** Bit definition for RI_HYSCR1 register ******************/
		6152	#define RI_HYSCR1_PA_Pos (0U)
		6153	#define RI_HYSCR1_PA_Msk (0xFFFFU << RI_HYSCR1_PA_Pos) /!< 0x0000FFFF /
		6154	#define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /!< PA[15:0] Port A Hysteresis selection /
		6155	#define RI_HYSCR1_PA_0 (0x0001U << RI_HYSCR1_PA_Pos) /!< 0x00000001 /
		6156	#define RI_HYSCR1_PA_1 (0x0002U << RI_HYSCR1_PA_Pos) /!< 0x00000002 /
		6157	#define RI_HYSCR1_PA_2 (0x0004U << RI_HYSCR1_PA_Pos) /!< 0x00000004 /
		6158	#define RI_HYSCR1_PA_3 (0x0008U << RI_HYSCR1_PA_Pos) /!< 0x00000008 /
		6159	#define RI_HYSCR1_PA_4 (0x0010U << RI_HYSCR1_PA_Pos) /!< 0x00000010 /
		6160	#define RI_HYSCR1_PA_5 (0x0020U << RI_HYSCR1_PA_Pos) /!< 0x00000020 /
		6161	#define RI_HYSCR1_PA_6 (0x0040U << RI_HYSCR1_PA_Pos) /!< 0x00000040 /
		6162	#define RI_HYSCR1_PA_7 (0x0080U << RI_HYSCR1_PA_Pos) /!< 0x00000080 /
		6163	#define RI_HYSCR1_PA_8 (0x0100U << RI_HYSCR1_PA_Pos) /!< 0x00000100 /
		6164	#define RI_HYSCR1_PA_9 (0x0200U << RI_HYSCR1_PA_Pos) /!< 0x00000200 /
		6165	#define RI_HYSCR1_PA_10 (0x0400U << RI_HYSCR1_PA_Pos) /!< 0x00000400 /
		6166	#define RI_HYSCR1_PA_11 (0x0800U << RI_HYSCR1_PA_Pos) /!< 0x00000800 /
		6167	#define RI_HYSCR1_PA_12 (0x1000U << RI_HYSCR1_PA_Pos) /!< 0x00001000 /
		6168	#define RI_HYSCR1_PA_13 (0x2000U << RI_HYSCR1_PA_Pos) /!< 0x00002000 /
		6169	#define RI_HYSCR1_PA_14 (0x4000U << RI_HYSCR1_PA_Pos) /!< 0x00004000 /
		6170	#define RI_HYSCR1_PA_15 (0x8000U << RI_HYSCR1_PA_Pos) /!< 0x00008000 /
		6171
		6172	#define RI_HYSCR1_PB_Pos (16U)
		6173	#define RI_HYSCR1_PB_Msk (0xFFFFU << RI_HYSCR1_PB_Pos) /!< 0xFFFF0000 /
		6174	#define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /!< PB[15:0] Port B Hysteresis selection /
		6175	#define RI_HYSCR1_PB_0 (0x0001U << RI_HYSCR1_PB_Pos) /!< 0x00010000 /
		6176	#define RI_HYSCR1_PB_1 (0x0002U << RI_HYSCR1_PB_Pos) /!< 0x00020000 /
		6177	#define RI_HYSCR1_PB_2 (0x0004U << RI_HYSCR1_PB_Pos) /!< 0x00040000 /
		6178	#define RI_HYSCR1_PB_3 (0x0008U << RI_HYSCR1_PB_Pos) /!< 0x00080000 /
		6179	#define RI_HYSCR1_PB_4 (0x0010U << RI_HYSCR1_PB_Pos) /!< 0x00100000 /
		6180	#define RI_HYSCR1_PB_5 (0x0020U << RI_HYSCR1_PB_Pos) /!< 0x00200000 /
		6181	#define RI_HYSCR1_PB_6 (0x0040U << RI_HYSCR1_PB_Pos) /!< 0x00400000 /
		6182	#define RI_HYSCR1_PB_7 (0x0080U << RI_HYSCR1_PB_Pos) /!< 0x00800000 /
		6183	#define RI_HYSCR1_PB_8 (0x0100U << RI_HYSCR1_PB_Pos) /!< 0x01000000 /
		6184	#define RI_HYSCR1_PB_9 (0x0200U << RI_HYSCR1_PB_Pos) /!< 0x02000000 /
		6185	#define RI_HYSCR1_PB_10 (0x0400U << RI_HYSCR1_PB_Pos) /!< 0x04000000 /
		6186	#define RI_HYSCR1_PB_11 (0x0800U << RI_HYSCR1_PB_Pos) /!< 0x08000000 /
		6187	#define RI_HYSCR1_PB_12 (0x1000U << RI_HYSCR1_PB_Pos) /!< 0x10000000 /
		6188	#define RI_HYSCR1_PB_13 (0x2000U << RI_HYSCR1_PB_Pos) /!< 0x20000000 /
		6189	#define RI_HYSCR1_PB_14 (0x4000U << RI_HYSCR1_PB_Pos) /!< 0x40000000 /
		6190	#define RI_HYSCR1_PB_15 (0x8000U << RI_HYSCR1_PB_Pos) /!< 0x80000000 /
		6191
		6192	/****************** Bit definition for RI_HYSCR2 register ******************/
		6193	#define RI_HYSCR2_PC_Pos (0U)
		6194	#define RI_HYSCR2_PC_Msk (0xFFFFU << RI_HYSCR2_PC_Pos) /!< 0x0000FFFF /
		6195	#define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /!< PC[15:0] Port C Hysteresis selection /
		6196	#define RI_HYSCR2_PC_0 (0x0001U << RI_HYSCR2_PC_Pos) /!< 0x00000001 /
		6197	#define RI_HYSCR2_PC_1 (0x0002U << RI_HYSCR2_PC_Pos) /!< 0x00000002 /
		6198	#define RI_HYSCR2_PC_2 (0x0004U << RI_HYSCR2_PC_Pos) /!< 0x00000004 /
		6199	#define RI_HYSCR2_PC_3 (0x0008U << RI_HYSCR2_PC_Pos) /!< 0x00000008 /
		6200	#define RI_HYSCR2_PC_4 (0x0010U << RI_HYSCR2_PC_Pos) /!< 0x00000010 /
		6201	#define RI_HYSCR2_PC_5 (0x0020U << RI_HYSCR2_PC_Pos) /!< 0x00000020 /
		6202	#define RI_HYSCR2_PC_6 (0x0040U << RI_HYSCR2_PC_Pos) /!< 0x00000040 /
		6203	#define RI_HYSCR2_PC_7 (0x0080U << RI_HYSCR2_PC_Pos) /!< 0x00000080 /
		6204	#define RI_HYSCR2_PC_8 (0x0100U << RI_HYSCR2_PC_Pos) /!< 0x00000100 /
		6205	#define RI_HYSCR2_PC_9 (0x0200U << RI_HYSCR2_PC_Pos) /!< 0x00000200 /
		6206	#define RI_HYSCR2_PC_10 (0x0400U << RI_HYSCR2_PC_Pos) /!< 0x00000400 /
		6207	#define RI_HYSCR2_PC_11 (0x0800U << RI_HYSCR2_PC_Pos) /!< 0x00000800 /
		6208	#define RI_HYSCR2_PC_12 (0x1000U << RI_HYSCR2_PC_Pos) /!< 0x00001000 /
		6209	#define RI_HYSCR2_PC_13 (0x2000U << RI_HYSCR2_PC_Pos) /!< 0x00002000 /
		6210	#define RI_HYSCR2_PC_14 (0x4000U << RI_HYSCR2_PC_Pos) /!< 0x00004000 /
		6211	#define RI_HYSCR2_PC_15 (0x8000U << RI_HYSCR2_PC_Pos) /!< 0x00008000 /
		6212
		6213	#define RI_HYSCR2_PD_Pos (16U)
		6214	#define RI_HYSCR2_PD_Msk (0xFFFFU << RI_HYSCR2_PD_Pos) /!< 0xFFFF0000 /
		6215	#define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /!< PD[15:0] Port D Hysteresis selection /
		6216	#define RI_HYSCR2_PD_0 (0x0001U << RI_HYSCR2_PD_Pos) /!< 0x00010000 /
		6217	#define RI_HYSCR2_PD_1 (0x0002U << RI_HYSCR2_PD_Pos) /!< 0x00020000 /
		6218	#define RI_HYSCR2_PD_2 (0x0004U << RI_HYSCR2_PD_Pos) /!< 0x00040000 /
		6219	#define RI_HYSCR2_PD_3 (0x0008U << RI_HYSCR2_PD_Pos) /!< 0x00080000 /
		6220	#define RI_HYSCR2_PD_4 (0x0010U << RI_HYSCR2_PD_Pos) /!< 0x00100000 /
		6221	#define RI_HYSCR2_PD_5 (0x0020U << RI_HYSCR2_PD_Pos) /!< 0x00200000 /
		6222	#define RI_HYSCR2_PD_6 (0x0040U << RI_HYSCR2_PD_Pos) /!< 0x00400000 /
		6223	#define RI_HYSCR2_PD_7 (0x0080U << RI_HYSCR2_PD_Pos) /!< 0x00800000 /
		6224	#define RI_HYSCR2_PD_8 (0x0100U << RI_HYSCR2_PD_Pos) /!< 0x01000000 /
		6225	#define RI_HYSCR2_PD_9 (0x0200U << RI_HYSCR2_PD_Pos) /!< 0x02000000 /
		6226	#define RI_HYSCR2_PD_10 (0x0400U << RI_HYSCR2_PD_Pos) /!< 0x04000000 /
		6227	#define RI_HYSCR2_PD_11 (0x0800U << RI_HYSCR2_PD_Pos) /!< 0x08000000 /
		6228	#define RI_HYSCR2_PD_12 (0x1000U << RI_HYSCR2_PD_Pos) /!< 0x10000000 /
		6229	#define RI_HYSCR2_PD_13 (0x2000U << RI_HYSCR2_PD_Pos) /!< 0x20000000 /
		6230	#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /!< 0x40000000 /
		6231	#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /!< 0x80000000 /
		6232
		6233	/****************** Bit definition for RI_HYSCR3 register ******************/
		6234	#define RI_HYSCR3_PE_Pos (0U)
		6235	#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /!< 0x0000FFFF /
		6236	#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /!< PE[15:0] Port E Hysteresis selection /
		6237	#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /!< 0x00000001 /
		6238	#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /!< 0x00000002 /
		6239	#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /!< 0x00000004 /
		6240	#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /!< 0x00000008 /
		6241	#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /!< 0x00000010 /
		6242	#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /!< 0x00000020 /
		6243	#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /!< 0x00000040 /
		6244	#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /!< 0x00000080 /
		6245	#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /!< 0x00000100 /
		6246	#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /!< 0x00000200 /
		6247	#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /!< 0x00000400 /
		6248	#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /!< 0x00000800 /
		6249	#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /!< 0x00001000 /
		6250	#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /!< 0x00002000 /
		6251	#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /!< 0x00004000 /
		6252	#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /!< 0x00008000 /
		6253	#define RI_HYSCR3_PF_Pos (16U)
		6254	#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /!< 0xFFFF0000 /
		6255	#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /!< PF[15:0] Port F Hysteresis selection /
		6256	#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /!< 0x00010000 /
		6257	#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /!< 0x00020000 /
		6258	#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /!< 0x00040000 /
		6259	#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /!< 0x00080000 /
		6260	#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /!< 0x00100000 /
		6261	#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /!< 0x00200000 /
		6262	#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /!< 0x00400000 /
		6263	#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /!< 0x00800000 /
		6264	#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /!< 0x01000000 /
		6265	#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /!< 0x02000000 /
		6266	#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /!< 0x04000000 /
		6267	#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /!< 0x08000000 /
		6268	#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /!< 0x10000000 /
		6269	#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /!< 0x20000000 /
		6270	#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /!< 0x40000000 /
		6271	#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /!< 0x80000000 /
		6272
		6273	/****************** Bit definition for RI_HYSCR4 register ******************/
		6274	#define RI_HYSCR4_PG_Pos (0U)
		6275	#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /!< 0x0000FFFF /
		6276	#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /!< PG[15:0] Port G Hysteresis selection /
		6277	#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /!< 0x00000001 /
		6278	#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /!< 0x00000002 /
		6279	#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /!< 0x00000004 /
		6280	#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /!< 0x00000008 /
		6281	#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /!< 0x00000010 /
		6282	#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /!< 0x00000020 /
		6283	#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /!< 0x00000040 /
		6284	#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /!< 0x00000080 /
		6285	#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /!< 0x00000100 /
		6286	#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /!< 0x00000200 /
		6287	#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /!< 0x00000400 /
		6288	#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /!< 0x00000800 /
		6289	#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /!< 0x00001000 /
		6290	#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /!< 0x00002000 /
		6291	#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /!< 0x00004000 /
		6292	#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /!< 0x00008000 /
		6293
		6294	/****************** Bit definition for RI_ASMR1 register ******************/
		6295	#define RI_ASMR1_PA_Pos (0U)
		6296	#define RI_ASMR1_PA_Msk (0xFFFFU << RI_ASMR1_PA_Pos) /!< 0x0000FFFF /
		6297	#define RI_ASMR1_PA RI_ASMR1_PA_Msk /!< PA[15:0] Port A selection/
		6298	#define RI_ASMR1_PA_0 (0x0001U << RI_ASMR1_PA_Pos) /!< 0x00000001 /
		6299	#define RI_ASMR1_PA_1 (0x0002U << RI_ASMR1_PA_Pos) /!< 0x00000002 /
		6300	#define RI_ASMR1_PA_2 (0x0004U << RI_ASMR1_PA_Pos) /!< 0x00000004 /
		6301	#define RI_ASMR1_PA_3 (0x0008U << RI_ASMR1_PA_Pos) /!< 0x00000008 /
		6302	#define RI_ASMR1_PA_4 (0x0010U << RI_ASMR1_PA_Pos) /!< 0x00000010 /
		6303	#define RI_ASMR1_PA_5 (0x0020U << RI_ASMR1_PA_Pos) /!< 0x00000020 /
		6304	#define RI_ASMR1_PA_6 (0x0040U << RI_ASMR1_PA_Pos) /!< 0x00000040 /
		6305	#define RI_ASMR1_PA_7 (0x0080U << RI_ASMR1_PA_Pos) /!< 0x00000080 /
		6306	#define RI_ASMR1_PA_8 (0x0100U << RI_ASMR1_PA_Pos) /!< 0x00000100 /
		6307	#define RI_ASMR1_PA_9 (0x0200U << RI_ASMR1_PA_Pos) /!< 0x00000200 /
		6308	#define RI_ASMR1_PA_10 (0x0400U << RI_ASMR1_PA_Pos) /!< 0x00000400 /
		6309	#define RI_ASMR1_PA_11 (0x0800U << RI_ASMR1_PA_Pos) /!< 0x00000800 /
		6310	#define RI_ASMR1_PA_12 (0x1000U << RI_ASMR1_PA_Pos) /!< 0x00001000 /
		6311	#define RI_ASMR1_PA_13 (0x2000U << RI_ASMR1_PA_Pos) /!< 0x00002000 /
		6312	#define RI_ASMR1_PA_14 (0x4000U << RI_ASMR1_PA_Pos) /!< 0x00004000 /
		6313	#define RI_ASMR1_PA_15 (0x8000U << RI_ASMR1_PA_Pos) /!< 0x00008000 /
		6314
		6315	/****************** Bit definition for RI_CMR1 register ******************/
		6316	#define RI_CMR1_PA_Pos (0U)
		6317	#define RI_CMR1_PA_Msk (0xFFFFU << RI_CMR1_PA_Pos) /!< 0x0000FFFF /
		6318	#define RI_CMR1_PA RI_CMR1_PA_Msk /!< PA[15:0] Port A selection/
		6319	#define RI_CMR1_PA_0 (0x0001U << RI_CMR1_PA_Pos) /!< 0x00000001 /
		6320	#define RI_CMR1_PA_1 (0x0002U << RI_CMR1_PA_Pos) /!< 0x00000002 /
		6321	#define RI_CMR1_PA_2 (0x0004U << RI_CMR1_PA_Pos) /!< 0x00000004 /
		6322	#define RI_CMR1_PA_3 (0x0008U << RI_CMR1_PA_Pos) /!< 0x00000008 /
		6323	#define RI_CMR1_PA_4 (0x0010U << RI_CMR1_PA_Pos) /!< 0x00000010 /
		6324	#define RI_CMR1_PA_5 (0x0020U << RI_CMR1_PA_Pos) /!< 0x00000020 /
		6325	#define RI_CMR1_PA_6 (0x0040U << RI_CMR1_PA_Pos) /!< 0x00000040 /
		6326	#define RI_CMR1_PA_7 (0x0080U << RI_CMR1_PA_Pos) /!< 0x00000080 /
		6327	#define RI_CMR1_PA_8 (0x0100U << RI_CMR1_PA_Pos) /!< 0x00000100 /
		6328	#define RI_CMR1_PA_9 (0x0200U << RI_CMR1_PA_Pos) /!< 0x00000200 /
		6329	#define RI_CMR1_PA_10 (0x0400U << RI_CMR1_PA_Pos) /!< 0x00000400 /
		6330	#define RI_CMR1_PA_11 (0x0800U << RI_CMR1_PA_Pos) /!< 0x00000800 /
		6331	#define RI_CMR1_PA_12 (0x1000U << RI_CMR1_PA_Pos) /!< 0x00001000 /
		6332	#define RI_CMR1_PA_13 (0x2000U << RI_CMR1_PA_Pos) /!< 0x00002000 /
		6333	#define RI_CMR1_PA_14 (0x4000U << RI_CMR1_PA_Pos) /!< 0x00004000 /
		6334	#define RI_CMR1_PA_15 (0x8000U << RI_CMR1_PA_Pos) /!< 0x00008000 /
		6335
		6336	/****************** Bit definition for RI_CICR1 register ******************/
		6337	#define RI_CICR1_PA_Pos (0U)
		6338	#define RI_CICR1_PA_Msk (0xFFFFU << RI_CICR1_PA_Pos) /!< 0x0000FFFF /
		6339	#define RI_CICR1_PA RI_CICR1_PA_Msk /!< PA[15:0] Port A selection/
		6340	#define RI_CICR1_PA_0 (0x0001U << RI_CICR1_PA_Pos) /!< 0x00000001 /
		6341	#define RI_CICR1_PA_1 (0x0002U << RI_CICR1_PA_Pos) /!< 0x00000002 /
		6342	#define RI_CICR1_PA_2 (0x0004U << RI_CICR1_PA_Pos) /!< 0x00000004 /
		6343	#define RI_CICR1_PA_3 (0x0008U << RI_CICR1_PA_Pos) /!< 0x00000008 /
		6344	#define RI_CICR1_PA_4 (0x0010U << RI_CICR1_PA_Pos) /!< 0x00000010 /
		6345	#define RI_CICR1_PA_5 (0x0020U << RI_CICR1_PA_Pos) /!< 0x00000020 /
		6346	#define RI_CICR1_PA_6 (0x0040U << RI_CICR1_PA_Pos) /!< 0x00000040 /
		6347	#define RI_CICR1_PA_7 (0x0080U << RI_CICR1_PA_Pos) /!< 0x00000080 /
		6348	#define RI_CICR1_PA_8 (0x0100U << RI_CICR1_PA_Pos) /!< 0x00000100 /
		6349	#define RI_CICR1_PA_9 (0x0200U << RI_CICR1_PA_Pos) /!< 0x00000200 /
		6350	#define RI_CICR1_PA_10 (0x0400U << RI_CICR1_PA_Pos) /!< 0x00000400 /
		6351	#define RI_CICR1_PA_11 (0x0800U << RI_CICR1_PA_Pos) /!< 0x00000800 /
		6352	#define RI_CICR1_PA_12 (0x1000U << RI_CICR1_PA_Pos) /!< 0x00001000 /
		6353	#define RI_CICR1_PA_13 (0x2000U << RI_CICR1_PA_Pos) /!< 0x00002000 /
		6354	#define RI_CICR1_PA_14 (0x4000U << RI_CICR1_PA_Pos) /!< 0x00004000 /
		6355	#define RI_CICR1_PA_15 (0x8000U << RI_CICR1_PA_Pos) /!< 0x00008000 /
		6356
		6357	/****************** Bit definition for RI_ASMR2 register ******************/
		6358	#define RI_ASMR2_PB_Pos (0U)
		6359	#define RI_ASMR2_PB_Msk (0xFFFFU << RI_ASMR2_PB_Pos) /!< 0x0000FFFF /
		6360	#define RI_ASMR2_PB RI_ASMR2_PB_Msk /!< PB[15:0] Port B selection /
		6361	#define RI_ASMR2_PB_0 (0x0001U << RI_ASMR2_PB_Pos) /!< 0x00000001 /
		6362	#define RI_ASMR2_PB_1 (0x0002U << RI_ASMR2_PB_Pos) /!< 0x00000002 /
		6363	#define RI_ASMR2_PB_2 (0x0004U << RI_ASMR2_PB_Pos) /!< 0x00000004 /
		6364	#define RI_ASMR2_PB_3 (0x0008U << RI_ASMR2_PB_Pos) /!< 0x00000008 /
		6365	#define RI_ASMR2_PB_4 (0x0010U << RI_ASMR2_PB_Pos) /!< 0x00000010 /
		6366	#define RI_ASMR2_PB_5 (0x0020U << RI_ASMR2_PB_Pos) /!< 0x00000020 /
		6367	#define RI_ASMR2_PB_6 (0x0040U << RI_ASMR2_PB_Pos) /!< 0x00000040 /
		6368	#define RI_ASMR2_PB_7 (0x0080U << RI_ASMR2_PB_Pos) /!< 0x00000080 /
		6369	#define RI_ASMR2_PB_8 (0x0100U << RI_ASMR2_PB_Pos) /!< 0x00000100 /
		6370	#define RI_ASMR2_PB_9 (0x0200U << RI_ASMR2_PB_Pos) /!< 0x00000200 /
		6371	#define RI_ASMR2_PB_10 (0x0400U << RI_ASMR2_PB_Pos) /!< 0x00000400 /
		6372	#define RI_ASMR2_PB_11 (0x0800U << RI_ASMR2_PB_Pos) /!< 0x00000800 /
		6373	#define RI_ASMR2_PB_12 (0x1000U << RI_ASMR2_PB_Pos) /!< 0x00001000 /
		6374	#define RI_ASMR2_PB_13 (0x2000U << RI_ASMR2_PB_Pos) /!< 0x00002000 /
		6375	#define RI_ASMR2_PB_14 (0x4000U << RI_ASMR2_PB_Pos) /!< 0x00004000 /
		6376	#define RI_ASMR2_PB_15 (0x8000U << RI_ASMR2_PB_Pos) /!< 0x00008000 /
		6377
		6378	/****************** Bit definition for RI_CMR2 register ******************/
		6379	#define RI_CMR2_PB_Pos (0U)
		6380	#define RI_CMR2_PB_Msk (0xFFFFU << RI_CMR2_PB_Pos) /!< 0x0000FFFF /
		6381	#define RI_CMR2_PB RI_CMR2_PB_Msk /!< PB[15:0] Port B selection /
		6382	#define RI_CMR2_PB_0 (0x0001U << RI_CMR2_PB_Pos) /!< 0x00000001 /
		6383	#define RI_CMR2_PB_1 (0x0002U << RI_CMR2_PB_Pos) /!< 0x00000002 /
		6384	#define RI_CMR2_PB_2 (0x0004U << RI_CMR2_PB_Pos) /!< 0x00000004 /
		6385	#define RI_CMR2_PB_3 (0x0008U << RI_CMR2_PB_Pos) /!< 0x00000008 /
		6386	#define RI_CMR2_PB_4 (0x0010U << RI_CMR2_PB_Pos) /!< 0x00000010 /
		6387	#define RI_CMR2_PB_5 (0x0020U << RI_CMR2_PB_Pos) /!< 0x00000020 /
		6388	#define RI_CMR2_PB_6 (0x0040U << RI_CMR2_PB_Pos) /!< 0x00000040 /
		6389	#define RI_CMR2_PB_7 (0x0080U << RI_CMR2_PB_Pos) /!< 0x00000080 /
		6390	#define RI_CMR2_PB_8 (0x0100U << RI_CMR2_PB_Pos) /!< 0x00000100 /
		6391	#define RI_CMR2_PB_9 (0x0200U << RI_CMR2_PB_Pos) /!< 0x00000200 /
		6392	#define RI_CMR2_PB_10 (0x0400U << RI_CMR2_PB_Pos) /!< 0x00000400 /
		6393	#define RI_CMR2_PB_11 (0x0800U << RI_CMR2_PB_Pos) /!< 0x00000800 /
		6394	#define RI_CMR2_PB_12 (0x1000U << RI_CMR2_PB_Pos) /!< 0x00001000 /
		6395	#define RI_CMR2_PB_13 (0x2000U << RI_CMR2_PB_Pos) /!< 0x00002000 /
		6396	#define RI_CMR2_PB_14 (0x4000U << RI_CMR2_PB_Pos) /!< 0x00004000 /
		6397	#define RI_CMR2_PB_15 (0x8000U << RI_CMR2_PB_Pos) /!< 0x00008000 /
		6398
		6399	/****************** Bit definition for RI_CICR2 register ******************/
		6400	#define RI_CICR2_PB_Pos (0U)
		6401	#define RI_CICR2_PB_Msk (0xFFFFU << RI_CICR2_PB_Pos) /!< 0x0000FFFF /
		6402	#define RI_CICR2_PB RI_CICR2_PB_Msk /!< PB[15:0] Port B selection /
		6403	#define RI_CICR2_PB_0 (0x0001U << RI_CICR2_PB_Pos) /!< 0x00000001 /
		6404	#define RI_CICR2_PB_1 (0x0002U << RI_CICR2_PB_Pos) /!< 0x00000002 /
		6405	#define RI_CICR2_PB_2 (0x0004U << RI_CICR2_PB_Pos) /!< 0x00000004 /
		6406	#define RI_CICR2_PB_3 (0x0008U << RI_CICR2_PB_Pos) /!< 0x00000008 /
		6407	#define RI_CICR2_PB_4 (0x0010U << RI_CICR2_PB_Pos) /!< 0x00000010 /
		6408	#define RI_CICR2_PB_5 (0x0020U << RI_CICR2_PB_Pos) /!< 0x00000020 /
		6409	#define RI_CICR2_PB_6 (0x0040U << RI_CICR2_PB_Pos) /!< 0x00000040 /
		6410	#define RI_CICR2_PB_7 (0x0080U << RI_CICR2_PB_Pos) /!< 0x00000080 /
		6411	#define RI_CICR2_PB_8 (0x0100U << RI_CICR2_PB_Pos) /!< 0x00000100 /
		6412	#define RI_CICR2_PB_9 (0x0200U << RI_CICR2_PB_Pos) /!< 0x00000200 /
		6413	#define RI_CICR2_PB_10 (0x0400U << RI_CICR2_PB_Pos) /!< 0x00000400 /
		6414	#define RI_CICR2_PB_11 (0x0800U << RI_CICR2_PB_Pos) /!< 0x00000800 /
		6415	#define RI_CICR2_PB_12 (0x1000U << RI_CICR2_PB_Pos) /!< 0x00001000 /
		6416	#define RI_CICR2_PB_13 (0x2000U << RI_CICR2_PB_Pos) /!< 0x00002000 /
		6417	#define RI_CICR2_PB_14 (0x4000U << RI_CICR2_PB_Pos) /!< 0x00004000 /
		6418	#define RI_CICR2_PB_15 (0x8000U << RI_CICR2_PB_Pos) /!< 0x00008000 /
		6419
		6420	/****************** Bit definition for RI_ASMR3 register ******************/
		6421	#define RI_ASMR3_PC_Pos (0U)
		6422	#define RI_ASMR3_PC_Msk (0xFFFFU << RI_ASMR3_PC_Pos) /!< 0x0000FFFF /
		6423	#define RI_ASMR3_PC RI_ASMR3_PC_Msk /!< PC[15:0] Port C selection /
		6424	#define RI_ASMR3_PC_0 (0x0001U << RI_ASMR3_PC_Pos) /!< 0x00000001 /
		6425	#define RI_ASMR3_PC_1 (0x0002U << RI_ASMR3_PC_Pos) /!< 0x00000002 /
		6426	#define RI_ASMR3_PC_2 (0x0004U << RI_ASMR3_PC_Pos) /!< 0x00000004 /
		6427	#define RI_ASMR3_PC_3 (0x0008U << RI_ASMR3_PC_Pos) /!< 0x00000008 /
		6428	#define RI_ASMR3_PC_4 (0x0010U << RI_ASMR3_PC_Pos) /!< 0x00000010 /
		6429	#define RI_ASMR3_PC_5 (0x0020U << RI_ASMR3_PC_Pos) /!< 0x00000020 /
		6430	#define RI_ASMR3_PC_6 (0x0040U << RI_ASMR3_PC_Pos) /!< 0x00000040 /
		6431	#define RI_ASMR3_PC_7 (0x0080U << RI_ASMR3_PC_Pos) /!< 0x00000080 /
		6432	#define RI_ASMR3_PC_8 (0x0100U << RI_ASMR3_PC_Pos) /!< 0x00000100 /
		6433	#define RI_ASMR3_PC_9 (0x0200U << RI_ASMR3_PC_Pos) /!< 0x00000200 /
		6434	#define RI_ASMR3_PC_10 (0x0400U << RI_ASMR3_PC_Pos) /!< 0x00000400 /
		6435	#define RI_ASMR3_PC_11 (0x0800U << RI_ASMR3_PC_Pos) /!< 0x00000800 /
		6436	#define RI_ASMR3_PC_12 (0x1000U << RI_ASMR3_PC_Pos) /!< 0x00001000 /
		6437	#define RI_ASMR3_PC_13 (0x2000U << RI_ASMR3_PC_Pos) /!< 0x00002000 /
		6438	#define RI_ASMR3_PC_14 (0x4000U << RI_ASMR3_PC_Pos) /!< 0x00004000 /
		6439	#define RI_ASMR3_PC_15 (0x8000U << RI_ASMR3_PC_Pos) /!< 0x00008000 /
		6440
		6441	/****************** Bit definition for RI_CMR3 register ******************/
		6442	#define RI_CMR3_PC_Pos (0U)
		6443	#define RI_CMR3_PC_Msk (0xFFFFU << RI_CMR3_PC_Pos) /!< 0x0000FFFF /
		6444	#define RI_CMR3_PC RI_CMR3_PC_Msk /!< PC[15:0] Port C selection /
		6445	#define RI_CMR3_PC_0 (0x0001U << RI_CMR3_PC_Pos) /!< 0x00000001 /
		6446	#define RI_CMR3_PC_1 (0x0002U << RI_CMR3_PC_Pos) /!< 0x00000002 /
		6447	#define RI_CMR3_PC_2 (0x0004U << RI_CMR3_PC_Pos) /!< 0x00000004 /
		6448	#define RI_CMR3_PC_3 (0x0008U << RI_CMR3_PC_Pos) /!< 0x00000008 /
		6449	#define RI_CMR3_PC_4 (0x0010U << RI_CMR3_PC_Pos) /!< 0x00000010 /
		6450	#define RI_CMR3_PC_5 (0x0020U << RI_CMR3_PC_Pos) /!< 0x00000020 /
		6451	#define RI_CMR3_PC_6 (0x0040U << RI_CMR3_PC_Pos) /!< 0x00000040 /
		6452	#define RI_CMR3_PC_7 (0x0080U << RI_CMR3_PC_Pos) /!< 0x00000080 /
		6453	#define RI_CMR3_PC_8 (0x0100U << RI_CMR3_PC_Pos) /!< 0x00000100 /
		6454	#define RI_CMR3_PC_9 (0x0200U << RI_CMR3_PC_Pos) /!< 0x00000200 /
		6455	#define RI_CMR3_PC_10 (0x0400U << RI_CMR3_PC_Pos) /!< 0x00000400 /
		6456	#define RI_CMR3_PC_11 (0x0800U << RI_CMR3_PC_Pos) /!< 0x00000800 /
		6457	#define RI_CMR3_PC_12 (0x1000U << RI_CMR3_PC_Pos) /!< 0x00001000 /
		6458	#define RI_CMR3_PC_13 (0x2000U << RI_CMR3_PC_Pos) /!< 0x00002000 /
		6459	#define RI_CMR3_PC_14 (0x4000U << RI_CMR3_PC_Pos) /!< 0x00004000 /
		6460	#define RI_CMR3_PC_15 (0x8000U << RI_CMR3_PC_Pos) /!< 0x00008000 /
		6461
		6462	/****************** Bit definition for RI_CICR3 register ******************/
		6463	#define RI_CICR3_PC_Pos (0U)
		6464	#define RI_CICR3_PC_Msk (0xFFFFU << RI_CICR3_PC_Pos) /!< 0x0000FFFF /
		6465	#define RI_CICR3_PC RI_CICR3_PC_Msk /!< PC[15:0] Port C selection /
		6466	#define RI_CICR3_PC_0 (0x0001U << RI_CICR3_PC_Pos) /!< 0x00000001 /
		6467	#define RI_CICR3_PC_1 (0x0002U << RI_CICR3_PC_Pos) /!< 0x00000002 /
		6468	#define RI_CICR3_PC_2 (0x0004U << RI_CICR3_PC_Pos) /!< 0x00000004 /
		6469	#define RI_CICR3_PC_3 (0x0008U << RI_CICR3_PC_Pos) /!< 0x00000008 /
		6470	#define RI_CICR3_PC_4 (0x0010U << RI_CICR3_PC_Pos) /!< 0x00000010 /
		6471	#define RI_CICR3_PC_5 (0x0020U << RI_CICR3_PC_Pos) /!< 0x00000020 /
		6472	#define RI_CICR3_PC_6 (0x0040U << RI_CICR3_PC_Pos) /!< 0x00000040 /
		6473	#define RI_CICR3_PC_7 (0x0080U << RI_CICR3_PC_Pos) /!< 0x00000080 /
		6474	#define RI_CICR3_PC_8 (0x0100U << RI_CICR3_PC_Pos) /!< 0x00000100 /
		6475	#define RI_CICR3_PC_9 (0x0200U << RI_CICR3_PC_Pos) /!< 0x00000200 /
		6476	#define RI_CICR3_PC_10 (0x0400U << RI_CICR3_PC_Pos) /!< 0x00000400 /
		6477	#define RI_CICR3_PC_11 (0x0800U << RI_CICR3_PC_Pos) /!< 0x00000800 /
		6478	#define RI_CICR3_PC_12 (0x1000U << RI_CICR3_PC_Pos) /!< 0x00001000 /
		6479	#define RI_CICR3_PC_13 (0x2000U << RI_CICR3_PC_Pos) /!< 0x00002000 /
		6480	#define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /!< 0x00004000 /
		6481	#define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /!< 0x00008000 /
		6482
		6483	/****************** Bit definition for RI_ASMR4 register ******************/
		6484	#define RI_ASMR4_PF_Pos (0U)
		6485	#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /!< 0x0000FFFF /
		6486	#define RI_ASMR4_PF RI_ASMR4_PF_Msk /!< PF[15:0] Port F selection /
		6487	#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /!< 0x00000001 /
		6488	#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /!< 0x00000002 /
		6489	#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /!< 0x00000004 /
		6490	#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /!< 0x00000008 /
		6491	#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /!< 0x00000010 /
		6492	#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /!< 0x00000020 /
		6493	#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /!< 0x00000040 /
		6494	#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /!< 0x00000080 /
		6495	#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /!< 0x00000100 /
		6496	#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /!< 0x00000200 /
		6497	#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /!< 0x00000400 /
		6498	#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /!< 0x00000800 /
		6499	#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /!< 0x00001000 /
		6500	#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /!< 0x00002000 /
		6501	#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /!< 0x00004000 /
		6502	#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /!< 0x00008000 /
		6503
		6504	/****************** Bit definition for RI_CMR4 register ******************/
		6505	#define RI_CMR4_PF_Pos (0U)
		6506	#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /!< 0x0000FFFF /
		6507	#define RI_CMR4_PF RI_CMR4_PF_Msk /!< PF[15:0] Port F selection /
		6508	#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /!< 0x00000001 /
		6509	#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /!< 0x00000002 /
		6510	#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /!< 0x00000004 /
		6511	#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /!< 0x00000008 /
		6512	#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /!< 0x00000010 /
		6513	#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /!< 0x00000020 /
		6514	#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /!< 0x00000040 /
		6515	#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /!< 0x00000080 /
		6516	#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /!< 0x00000100 /
		6517	#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /!< 0x00000200 /
		6518	#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /!< 0x00000400 /
		6519	#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /!< 0x00000800 /
		6520	#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /!< 0x00001000 /
		6521	#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /!< 0x00002000 /
		6522	#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /!< 0x00004000 /
		6523	#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /!< 0x00008000 /
		6524
		6525	/****************** Bit definition for RI_CICR4 register ******************/
		6526	#define RI_CICR4_PF_Pos (0U)
		6527	#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /!< 0x0000FFFF /
		6528	#define RI_CICR4_PF RI_CICR4_PF_Msk /!< PF[15:0] Port F selection /
		6529	#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /!< 0x00000001 /
		6530	#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /!< 0x00000002 /
		6531	#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /!< 0x00000004 /
		6532	#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /!< 0x00000008 /
		6533	#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /!< 0x00000010 /
		6534	#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /!< 0x00000020 /
		6535	#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /!< 0x00000040 /
		6536	#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /!< 0x00000080 /
		6537	#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /!< 0x00000100 /
		6538	#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /!< 0x00000200 /
		6539	#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /!< 0x00000400 /
		6540	#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /!< 0x00000800 /
		6541	#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /!< 0x00001000 /
		6542	#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /!< 0x00002000 /
		6543	#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /!< 0x00004000 /
		6544	#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /!< 0x00008000 /
		6545
		6546	/****************** Bit definition for RI_ASMR5 register ******************/
		6547	#define RI_ASMR5_PG_Pos (0U)
		6548	#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /!< 0x0000FFFF /
		6549	#define RI_ASMR5_PG RI_ASMR5_PG_Msk /!< PG[15:0] Port G selection /
		6550	#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /!< 0x00000001 /
		6551	#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /!< 0x00000002 /
		6552	#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /!< 0x00000004 /
		6553	#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /!< 0x00000008 /
		6554	#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /!< 0x00000010 /
		6555	#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /!< 0x00000020 /
		6556	#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /!< 0x00000040 /
		6557	#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /!< 0x00000080 /
		6558	#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /!< 0x00000100 /
		6559	#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /!< 0x00000200 /
		6560	#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /!< 0x00000400 /
		6561	#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /!< 0x00000800 /
		6562	#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /!< 0x00001000 /
		6563	#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /!< 0x00002000 /
		6564	#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /!< 0x00004000 /
		6565	#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /!< 0x00008000 /
		6566
		6567	/****************** Bit definition for RI_CMR5 register ******************/
		6568	#define RI_CMR5_PG_Pos (0U)
		6569	#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /!< 0x0000FFFF /
		6570	#define RI_CMR5_PG RI_CMR5_PG_Msk /!< PG[15:0] Port G selection /
		6571	#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /!< 0x00000001 /
		6572	#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /!< 0x00000002 /
		6573	#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /!< 0x00000004 /
		6574	#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /!< 0x00000008 /
		6575	#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /!< 0x00000010 /
		6576	#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /!< 0x00000020 /
		6577	#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /!< 0x00000040 /
		6578	#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /!< 0x00000080 /
		6579	#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /!< 0x00000100 /
		6580	#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /!< 0x00000200 /
		6581	#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /!< 0x00000400 /
		6582	#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /!< 0x00000800 /
		6583	#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /!< 0x00001000 /
		6584	#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /!< 0x00002000 /
		6585	#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /!< 0x00004000 /
		6586	#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /!< 0x00008000 /
		6587
		6588	/****************** Bit definition for RI_CICR5 register ******************/
		6589	#define RI_CICR5_PG_Pos (0U)
		6590	#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /!< 0x0000FFFF /
		6591	#define RI_CICR5_PG RI_CICR5_PG_Msk /!< PG[15:0] Port G selection /
		6592	#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /!< 0x00000001 /
		6593	#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /!< 0x00000002 /
		6594	#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /!< 0x00000004 /
		6595	#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /!< 0x00000008 /
		6596	#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /!< 0x00000010 /
		6597	#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /!< 0x00000020 /
		6598	#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /!< 0x00000040 /
		6599	#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /!< 0x00000080 /
		6600	#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /!< 0x00000100 /
		6601	#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /!< 0x00000200 /
		6602	#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /!< 0x00000400 /
		6603	#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /!< 0x00000800 /
		6604	#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /!< 0x00001000 /
		6605	#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /!< 0x00002000 /
		6606	#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /!< 0x00004000 /
		6607	#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /!< 0x00008000 /
		6608
		6609	/******************************************************************************/
		6610	/* */
		6611	/* Timers (TIM) */
		6612	/* */
		6613	/******************************************************************************/
		6614
		6615	/***************** Bit definition for TIM_CR1 register ******************/
		6616	#define TIM_CR1_CEN_Pos (0U)
		6617	#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /!< 0x00000001 /
		6618	#define TIM_CR1_CEN TIM_CR1_CEN_Msk /!<Counter enable /
		6619	#define TIM_CR1_UDIS_Pos (1U)
		6620	#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /!< 0x00000002 /
		6621	#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /!<Update disable /
		6622	#define TIM_CR1_URS_Pos (2U)
		6623	#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /!< 0x00000004 /
		6624	#define TIM_CR1_URS TIM_CR1_URS_Msk /!<Update request source /
		6625	#define TIM_CR1_OPM_Pos (3U)
		6626	#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /!< 0x00000008 /
		6627	#define TIM_CR1_OPM TIM_CR1_OPM_Msk /!<One pulse mode /
		6628	#define TIM_CR1_DIR_Pos (4U)
		6629	#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /!< 0x00000010 /
		6630	#define TIM_CR1_DIR TIM_CR1_DIR_Msk /!<Direction /
		6631
		6632	#define TIM_CR1_CMS_Pos (5U)
		6633	#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /!< 0x00000060 /
		6634	#define TIM_CR1_CMS TIM_CR1_CMS_Msk /!<CMS[1:0] bits (Center-aligned mode selection) /
		6635	#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /!< 0x00000020 /
		6636	#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /!< 0x00000040 /
		6637
		6638	#define TIM_CR1_ARPE_Pos (7U)
		6639	#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /!< 0x00000080 /
		6640	#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /!<Auto-reload preload enable /
		6641
		6642	#define TIM_CR1_CKD_Pos (8U)
		6643	#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /!< 0x00000300 /
		6644	#define TIM_CR1_CKD TIM_CR1_CKD_Msk /!<CKD[1:0] bits (clock division) /
		6645	#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /!< 0x00000100 /
		6646	#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /!< 0x00000200 /
		6647
		6648	/***************** Bit definition for TIM_CR2 register ******************/
		6649	#define TIM_CR2_CCDS_Pos (3U)
		6650	#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /!< 0x00000008 /
		6651	#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /!<Capture/Compare DMA Selection /
		6652
		6653	#define TIM_CR2_MMS_Pos (4U)
		6654	#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /!< 0x00000070 /
		6655	#define TIM_CR2_MMS TIM_CR2_MMS_Msk /!<MMS[2:0] bits (Master Mode Selection) /
		6656	#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /!< 0x00000010 /
		6657	#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /!< 0x00000020 /
		6658	#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /!< 0x00000040 /
		6659
		6660	#define TIM_CR2_TI1S_Pos (7U)
		6661	#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /!< 0x00000080 /
		6662	#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /!<TI1 Selection /
		6663
		6664	/***************** Bit definition for TIM_SMCR register *****************/
		6665	#define TIM_SMCR_SMS_Pos (0U)
		6666	#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /!< 0x00000007 /
		6667	#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /!<SMS[2:0] bits (Slave mode selection) /
		6668	#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /!< 0x00000001 /
		6669	#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /!< 0x00000002 /
		6670	#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /!< 0x00000004 /
		6671
		6672	#define TIM_SMCR_OCCS_Pos (3U)
		6673	#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /!< 0x00000008 /
		6674	#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /!< OCREF clear selection /
		6675
		6676	#define TIM_SMCR_TS_Pos (4U)
		6677	#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /!< 0x00000070 /
		6678	#define TIM_SMCR_TS TIM_SMCR_TS_Msk /!<TS[2:0] bits (Trigger selection) /
		6679	#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /!< 0x00000010 /
		6680	#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /!< 0x00000020 /
		6681	#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /!< 0x00000040 /
		6682
		6683	#define TIM_SMCR_MSM_Pos (7U)
		6684	#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /!< 0x00000080 /
		6685	#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /!<Master/slave mode /
		6686
		6687	#define TIM_SMCR_ETF_Pos (8U)
		6688	#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /!< 0x00000F00 /
		6689	#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /!<ETF[3:0] bits (External trigger filter) /
		6690	#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /!< 0x00000100 /
		6691	#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /!< 0x00000200 /
		6692	#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /!< 0x00000400 /
		6693	#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /!< 0x00000800 /
		6694
		6695	#define TIM_SMCR_ETPS_Pos (12U)
		6696	#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /!< 0x00003000 /
		6697	#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /!<ETPS[1:0] bits (External trigger prescaler) /
		6698	#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /!< 0x00001000 /
		6699	#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /!< 0x00002000 /
		6700
		6701	#define TIM_SMCR_ECE_Pos (14U)
		6702	#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /!< 0x00004000 /
		6703	#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /!<External clock enable /
		6704	#define TIM_SMCR_ETP_Pos (15U)
		6705	#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /!< 0x00008000 /
		6706	#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /!<External trigger polarity /
		6707
		6708	/***************** Bit definition for TIM_DIER register *****************/
		6709	#define TIM_DIER_UIE_Pos (0U)
		6710	#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /!< 0x00000001 /
		6711	#define TIM_DIER_UIE TIM_DIER_UIE_Msk /!<Update interrupt enable /
		6712	#define TIM_DIER_CC1IE_Pos (1U)
		6713	#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /!< 0x00000002 /
		6714	#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /!<Capture/Compare 1 interrupt enable /
		6715	#define TIM_DIER_CC2IE_Pos (2U)
		6716	#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /!< 0x00000004 /
		6717	#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /!<Capture/Compare 2 interrupt enable /
		6718	#define TIM_DIER_CC3IE_Pos (3U)
		6719	#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /!< 0x00000008 /
		6720	#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /!<Capture/Compare 3 interrupt enable /
		6721	#define TIM_DIER_CC4IE_Pos (4U)
		6722	#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /!< 0x00000010 /
		6723	#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /!<Capture/Compare 4 interrupt enable /
		6724	#define TIM_DIER_TIE_Pos (6U)
		6725	#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /!< 0x00000040 /
		6726	#define TIM_DIER_TIE TIM_DIER_TIE_Msk /!<Trigger interrupt enable /
		6727	#define TIM_DIER_UDE_Pos (8U)
		6728	#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /!< 0x00000100 /
		6729	#define TIM_DIER_UDE TIM_DIER_UDE_Msk /!<Update DMA request enable /
		6730	#define TIM_DIER_CC1DE_Pos (9U)
		6731	#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /!< 0x00000200 /
		6732	#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /!<Capture/Compare 1 DMA request enable /
		6733	#define TIM_DIER_CC2DE_Pos (10U)
		6734	#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /!< 0x00000400 /
		6735	#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /!<Capture/Compare 2 DMA request enable /
		6736	#define TIM_DIER_CC3DE_Pos (11U)
		6737	#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /!< 0x00000800 /
		6738	#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /!<Capture/Compare 3 DMA request enable /
		6739	#define TIM_DIER_CC4DE_Pos (12U)
		6740	#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /!< 0x00001000 /
		6741	#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /!<Capture/Compare 4 DMA request enable /
		6742	#define TIM_DIER_COMDE ((uint16_t)0x2000U) /!<COM DMA request enable /
		6743	#define TIM_DIER_TDE_Pos (14U)
		6744	#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /!< 0x00004000 /
		6745	#define TIM_DIER_TDE TIM_DIER_TDE_Msk /!<Trigger DMA request enable /
		6746
		6747	/****************** Bit definition for TIM_SR register ******************/
		6748	#define TIM_SR_UIF_Pos (0U)
		6749	#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /!< 0x00000001 /
		6750	#define TIM_SR_UIF TIM_SR_UIF_Msk /!<Update interrupt Flag /
		6751	#define TIM_SR_CC1IF_Pos (1U)
		6752	#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /!< 0x00000002 /
		6753	#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /!<Capture/Compare 1 interrupt Flag /
		6754	#define TIM_SR_CC2IF_Pos (2U)
		6755	#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /!< 0x00000004 /
		6756	#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /!<Capture/Compare 2 interrupt Flag /
		6757	#define TIM_SR_CC3IF_Pos (3U)
		6758	#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /!< 0x00000008 /
		6759	#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /!<Capture/Compare 3 interrupt Flag /
		6760	#define TIM_SR_CC4IF_Pos (4U)
		6761	#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /!< 0x00000010 /
		6762	#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /!<Capture/Compare 4 interrupt Flag /
		6763	#define TIM_SR_TIF_Pos (6U)
		6764	#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /!< 0x00000040 /
		6765	#define TIM_SR_TIF TIM_SR_TIF_Msk /!<Trigger interrupt Flag /
		6766	#define TIM_SR_CC1OF_Pos (9U)
		6767	#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /!< 0x00000200 /
		6768	#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /!<Capture/Compare 1 Overcapture Flag /
		6769	#define TIM_SR_CC2OF_Pos (10U)
		6770	#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /!< 0x00000400 /
		6771	#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /!<Capture/Compare 2 Overcapture Flag /
		6772	#define TIM_SR_CC3OF_Pos (11U)
		6773	#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /!< 0x00000800 /
		6774	#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /!<Capture/Compare 3 Overcapture Flag /
		6775	#define TIM_SR_CC4OF_Pos (12U)
		6776	#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /!< 0x00001000 /
		6777	#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /!<Capture/Compare 4 Overcapture Flag /
		6778
		6779	/***************** Bit definition for TIM_EGR register ******************/
		6780	#define TIM_EGR_UG_Pos (0U)
		6781	#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /!< 0x00000001 /
		6782	#define TIM_EGR_UG TIM_EGR_UG_Msk /!<Update Generation /
		6783	#define TIM_EGR_CC1G_Pos (1U)
		6784	#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /!< 0x00000002 /
		6785	#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /!<Capture/Compare 1 Generation /
		6786	#define TIM_EGR_CC2G_Pos (2U)
		6787	#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /!< 0x00000004 /
		6788	#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /!<Capture/Compare 2 Generation /
		6789	#define TIM_EGR_CC3G_Pos (3U)
		6790	#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /!< 0x00000008 /
		6791	#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /!<Capture/Compare 3 Generation /
		6792	#define TIM_EGR_CC4G_Pos (4U)
		6793	#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /!< 0x00000010 /
		6794	#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /!<Capture/Compare 4 Generation /
		6795	#define TIM_EGR_TG_Pos (6U)
		6796	#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /!< 0x00000040 /
		6797	#define TIM_EGR_TG TIM_EGR_TG_Msk /!<Trigger Generation /
		6798
		6799	/**************** Bit definition for TIM_CCMR1 register *****************/
		6800	#define TIM_CCMR1_CC1S_Pos (0U)
		6801	#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /!< 0x00000003 /
		6802	#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
		6803	#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /!< 0x00000001 /
		6804	#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /!< 0x00000002 /
		6805
		6806	#define TIM_CCMR1_OC1FE_Pos (2U)
		6807	#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /!< 0x00000004 /
		6808	#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /!<Output Compare 1 Fast enable /
		6809	#define TIM_CCMR1_OC1PE_Pos (3U)
		6810	#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /!< 0x00000008 /
		6811	#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /!<Output Compare 1 Preload enable /
		6812
		6813	#define TIM_CCMR1_OC1M_Pos (4U)
		6814	#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /!< 0x00000070 /
		6815	#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /!<OC1M[2:0] bits (Output Compare 1 Mode) /
		6816	#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /!< 0x00000010 /
		6817	#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /!< 0x00000020 /
		6818	#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /!< 0x00000040 /
		6819
		6820	#define TIM_CCMR1_OC1CE_Pos (7U)
		6821	#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /!< 0x00000080 /
		6822	#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /!<Output Compare 1Clear Enable /
		6823
		6824	#define TIM_CCMR1_CC2S_Pos (8U)
		6825	#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /!< 0x00000300 /
		6826	#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
		6827	#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /!< 0x00000100 /
		6828	#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /!< 0x00000200 /
		6829
		6830	#define TIM_CCMR1_OC2FE_Pos (10U)
		6831	#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /!< 0x00000400 /
		6832	#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /!<Output Compare 2 Fast enable /
		6833	#define TIM_CCMR1_OC2PE_Pos (11U)
		6834	#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /!< 0x00000800 /
		6835	#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /!<Output Compare 2 Preload enable /
		6836
		6837	#define TIM_CCMR1_OC2M_Pos (12U)
		6838	#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /!< 0x00007000 /
		6839	#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /!<OC2M[2:0] bits (Output Compare 2 Mode) /
		6840	#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /!< 0x00001000 /
		6841	#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /!< 0x00002000 /
		6842	#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /!< 0x00004000 /
		6843
		6844	#define TIM_CCMR1_OC2CE_Pos (15U)
		6845	#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /!< 0x00008000 /
		6846	#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /!<Output Compare 2 Clear Enable /
		6847
		6848	/----------------------------------------------------------------------------/
		6849
		6850	#define TIM_CCMR1_IC1PSC_Pos (2U)
		6851	#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /!< 0x0000000C /
		6852	#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
		6853	#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000004 /
		6854	#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /!< 0x00000008 /
		6855
		6856	#define TIM_CCMR1_IC1F_Pos (4U)
		6857	#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /!< 0x000000F0 /
		6858	#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /!<IC1F[3:0] bits (Input Capture 1 Filter) /
		6859	#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /!< 0x00000010 /
		6860	#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /!< 0x00000020 /
		6861	#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /!< 0x00000040 /
		6862	#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /!< 0x00000080 /
		6863
		6864	#define TIM_CCMR1_IC2PSC_Pos (10U)
		6865	#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000C00 /
		6866	#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
		6867	#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000400 /
		6868	#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /!< 0x00000800 /
		6869
		6870	#define TIM_CCMR1_IC2F_Pos (12U)
		6871	#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /!< 0x0000F000 /
		6872	#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /!<IC2F[3:0] bits (Input Capture 2 Filter) /
		6873	#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /!< 0x00001000 /
		6874	#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /!< 0x00002000 /
		6875	#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /!< 0x00004000 /
		6876	#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /!< 0x00008000 /
		6877
		6878	/**************** Bit definition for TIM_CCMR2 register *****************/
		6879	#define TIM_CCMR2_CC3S_Pos (0U)
		6880	#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /!< 0x00000003 /
		6881	#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
		6882	#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /!< 0x00000001 /
		6883	#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /!< 0x00000002 /
		6884
		6885	#define TIM_CCMR2_OC3FE_Pos (2U)
		6886	#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /!< 0x00000004 /
		6887	#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /!<Output Compare 3 Fast enable /
		6888	#define TIM_CCMR2_OC3PE_Pos (3U)
		6889	#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /!< 0x00000008 /
		6890	#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /!<Output Compare 3 Preload enable /
		6891
		6892	#define TIM_CCMR2_OC3M_Pos (4U)
		6893	#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /!< 0x00000070 /
		6894	#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /!<OC3M[2:0] bits (Output Compare 3 Mode) /
		6895	#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /!< 0x00000010 /
		6896	#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /!< 0x00000020 /
		6897	#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /!< 0x00000040 /
		6898
		6899	#define TIM_CCMR2_OC3CE_Pos (7U)
		6900	#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /!< 0x00000080 /
		6901	#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /!<Output Compare 3 Clear Enable /
		6902
		6903	#define TIM_CCMR2_CC4S_Pos (8U)
		6904	#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /!< 0x00000300 /
		6905	#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
		6906	#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /!< 0x00000100 /
		6907	#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /!< 0x00000200 /
		6908
		6909	#define TIM_CCMR2_OC4FE_Pos (10U)
		6910	#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /!< 0x00000400 /
		6911	#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /!<Output Compare 4 Fast enable /
		6912	#define TIM_CCMR2_OC4PE_Pos (11U)
		6913	#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /!< 0x00000800 /
		6914	#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /!<Output Compare 4 Preload enable /
		6915
		6916	#define TIM_CCMR2_OC4M_Pos (12U)
		6917	#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /!< 0x00007000 /
		6918	#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /!<OC4M[2:0] bits (Output Compare 4 Mode) /
		6919	#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /!< 0x00001000 /
		6920	#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /!< 0x00002000 /
		6921	#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /!< 0x00004000 /
		6922
		6923	#define TIM_CCMR2_OC4CE_Pos (15U)
		6924	#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /!< 0x00008000 /
		6925	#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /!<Output Compare 4 Clear Enable /
		6926
		6927	/----------------------------------------------------------------------------/
		6928
		6929	#define TIM_CCMR2_IC3PSC_Pos (2U)
		6930	#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /!< 0x0000000C /
		6931	#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
		6932	#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000004 /
		6933	#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /!< 0x00000008 /
		6934
		6935	#define TIM_CCMR2_IC3F_Pos (4U)
		6936	#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /!< 0x000000F0 /
		6937	#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /!<IC3F[3:0] bits (Input Capture 3 Filter) /
		6938	#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /!< 0x00000010 /
		6939	#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /!< 0x00000020 /
		6940	#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /!< 0x00000040 /
		6941	#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /!< 0x00000080 /
		6942
		6943	#define TIM_CCMR2_IC4PSC_Pos (10U)
		6944	#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000C00 /
		6945	#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
		6946	#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000400 /
		6947	#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /!< 0x00000800 /
		6948
		6949	#define TIM_CCMR2_IC4F_Pos (12U)
		6950	#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /!< 0x0000F000 /
		6951	#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /!<IC4F[3:0] bits (Input Capture 4 Filter) /
		6952	#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /!< 0x00001000 /
		6953	#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /!< 0x00002000 /
		6954	#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /!< 0x00004000 /
		6955	#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /!< 0x00008000 /
		6956
		6957	/***************** Bit definition for TIM_CCER register *****************/
		6958	#define TIM_CCER_CC1E_Pos (0U)
		6959	#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /!< 0x00000001 /
		6960	#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /!<Capture/Compare 1 output enable /
		6961	#define TIM_CCER_CC1P_Pos (1U)
		6962	#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /!< 0x00000002 /
		6963	#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /!<Capture/Compare 1 output Polarity /
		6964	#define TIM_CCER_CC1NP_Pos (3U)
		6965	#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /!< 0x00000008 /
		6966	#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /!<Capture/Compare 1 Complementary output Polarity /
		6967	#define TIM_CCER_CC2E_Pos (4U)
		6968	#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /!< 0x00000010 /
		6969	#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /!<Capture/Compare 2 output enable /
		6970	#define TIM_CCER_CC2P_Pos (5U)
		6971	#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /!< 0x00000020 /
		6972	#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /!<Capture/Compare 2 output Polarity /
		6973	#define TIM_CCER_CC2NP_Pos (7U)
		6974	#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /!< 0x00000080 /
		6975	#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /!<Capture/Compare 2 Complementary output Polarity /
		6976	#define TIM_CCER_CC3E_Pos (8U)
		6977	#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /!< 0x00000100 /
		6978	#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /!<Capture/Compare 3 output enable /
		6979	#define TIM_CCER_CC3P_Pos (9U)
		6980	#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /!< 0x00000200 /
		6981	#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /!<Capture/Compare 3 output Polarity /
		6982	#define TIM_CCER_CC3NP_Pos (11U)
		6983	#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /!< 0x00000800 /
		6984	#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /!<Capture/Compare 3 Complementary output Polarity /
		6985	#define TIM_CCER_CC4E_Pos (12U)
		6986	#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /!< 0x00001000 /
		6987	#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /!<Capture/Compare 4 output enable /
		6988	#define TIM_CCER_CC4P_Pos (13U)
		6989	#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /!< 0x00002000 /
		6990	#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /!<Capture/Compare 4 output Polarity /
		6991	#define TIM_CCER_CC4NP_Pos (15U)
		6992	#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /!< 0x00008000 /
		6993	#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /!<Capture/Compare 4 Complementary output Polarity /
		6994
		6995	/***************** Bit definition for TIM_CNT register ******************/
		6996	#define TIM_CNT_CNT_Pos (0U)
		6997	#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /!< 0xFFFFFFFF /
		6998	#define TIM_CNT_CNT TIM_CNT_CNT_Msk /!<Counter Value /
		6999
		7000	/***************** Bit definition for TIM_PSC register ******************/
		7001	#define TIM_PSC_PSC_Pos (0U)
		7002	#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /!< 0x0000FFFF /
		7003	#define TIM_PSC_PSC TIM_PSC_PSC_Msk /!<Prescaler Value /
		7004
		7005	/***************** Bit definition for TIM_ARR register ******************/
		7006	#define TIM_ARR_ARR_Pos (0U)
		7007	#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /!< 0xFFFFFFFF /
		7008	#define TIM_ARR_ARR TIM_ARR_ARR_Msk /!<actual auto-reload Value /
		7009
		7010	/***************** Bit definition for TIM_CCR1 register *****************/
		7011	#define TIM_CCR1_CCR1_Pos (0U)
		7012	#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /!< 0x0000FFFF /
		7013	#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /!<Capture/Compare 1 Value /
		7014
		7015	/***************** Bit definition for TIM_CCR2 register *****************/
		7016	#define TIM_CCR2_CCR2_Pos (0U)
		7017	#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /!< 0x0000FFFF /
		7018	#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /!<Capture/Compare 2 Value /
		7019
		7020	/***************** Bit definition for TIM_CCR3 register *****************/
		7021	#define TIM_CCR3_CCR3_Pos (0U)
		7022	#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /!< 0x0000FFFF /
		7023	#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /!<Capture/Compare 3 Value /
		7024
		7025	/***************** Bit definition for TIM_CCR4 register *****************/
		7026	#define TIM_CCR4_CCR4_Pos (0U)
		7027	#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /!< 0x0000FFFF /
		7028	#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /!<Capture/Compare 4 Value /
		7029
		7030	/***************** Bit definition for TIM_DCR register ******************/
		7031	#define TIM_DCR_DBA_Pos (0U)
		7032	#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /!< 0x0000001F /
		7033	#define TIM_DCR_DBA TIM_DCR_DBA_Msk /!<DBA[4:0] bits (DMA Base Address) /
		7034	#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /!< 0x00000001 /
		7035	#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /!< 0x00000002 /
		7036	#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /!< 0x00000004 /
		7037	#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /!< 0x00000008 /
		7038	#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /!< 0x00000010 /
		7039
		7040	#define TIM_DCR_DBL_Pos (8U)
		7041	#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /!< 0x00001F00 /
		7042	#define TIM_DCR_DBL TIM_DCR_DBL_Msk /!<DBL[4:0] bits (DMA Burst Length) /
		7043	#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /!< 0x00000100 /
		7044	#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /!< 0x00000200 /
		7045	#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /!< 0x00000400 /
		7046	#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /!< 0x00000800 /
		7047	#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /!< 0x00001000 /
		7048
		7049	/***************** Bit definition for TIM_DMAR register *****************/
		7050	#define TIM_DMAR_DMAB_Pos (0U)
		7051	#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /!< 0x0000FFFF /
		7052	#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /!<DMA register for burst accesses /
		7053
		7054	/***************** Bit definition for TIM_OR register *******************/
		7055	#define TIM_OR_TI1RMP_Pos (0U)
		7056	#define TIM_OR_TI1RMP_Msk (0x3U << TIM_OR_TI1RMP_Pos) /!< 0x00000003 /
		7057	#define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /!<TI1_RMP[1:0] bits (TIM Input 1 remap) /
		7058	#define TIM_OR_TI1RMP_0 (0x1U << TIM_OR_TI1RMP_Pos) /!< 0x00000001 /
		7059	#define TIM_OR_TI1RMP_1 (0x2U << TIM_OR_TI1RMP_Pos) /!< 0x00000002 /
		7060
		7061	#define TIM_OR_ETR_RMP_Pos (2U)
		7062	#define TIM_OR_ETR_RMP_Msk (0x1U << TIM_OR_ETR_RMP_Pos) /!< 0x00000004 /
		7063	#define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /!<ETR_RMP bit (TIM10/11 ETR remap)/
		7064	#define TIM_OR_TI1_RMP_RI_Pos (3U)
		7065	#define TIM_OR_TI1_RMP_RI_Msk (0x1U << TIM_OR_TI1_RMP_RI_Pos) /!< 0x00000008 /
		7066	#define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) /
		7067
		7068	/----------------------------------------------------------------------------/
		7069	#define TIM9_OR_ITR1_RMP_Pos (2U)
		7070	#define TIM9_OR_ITR1_RMP_Msk (0x1U << TIM9_OR_ITR1_RMP_Pos) /!< 0x00000004 /
		7071	#define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) /
		7072
		7073	/----------------------------------------------------------------------------/
		7074	#define TIM2_OR_ITR1_RMP_Pos (0U)
		7075	#define TIM2_OR_ITR1_RMP_Msk (0x1U << TIM2_OR_ITR1_RMP_Pos) /!< 0x00000001 /
		7076	#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) /
		7077
		7078	/----------------------------------------------------------------------------/
		7079	#define TIM3_OR_ITR2_RMP_Pos (0U)
		7080	#define TIM3_OR_ITR2_RMP_Msk (0x1U << TIM3_OR_ITR2_RMP_Pos) /!< 0x00000001 /
		7081	#define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) /
		7082
		7083	/----------------------------------------------------------------------------/
		7084
		7085	/******************************************************************************/
		7086	/* */
		7087	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
		7088	/* */
		7089	/******************************************************************************/
		7090
		7091	/***************** Bit definition for USART_SR register *****************/
		7092	#define USART_SR_PE_Pos (0U)
		7093	#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /!< 0x00000001 /
		7094	#define USART_SR_PE USART_SR_PE_Msk /!< Parity Error /
		7095	#define USART_SR_FE_Pos (1U)
		7096	#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /!< 0x00000002 /
		7097	#define USART_SR_FE USART_SR_FE_Msk /!< Framing Error /
		7098	#define USART_SR_NE_Pos (2U)
		7099	#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /!< 0x00000004 /
		7100	#define USART_SR_NE USART_SR_NE_Msk /!< Noise Error Flag /
		7101	#define USART_SR_ORE_Pos (3U)
		7102	#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /!< 0x00000008 /
		7103	#define USART_SR_ORE USART_SR_ORE_Msk /!< OverRun Error /
		7104	#define USART_SR_IDLE_Pos (4U)
		7105	#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /!< 0x00000010 /
		7106	#define USART_SR_IDLE USART_SR_IDLE_Msk /!< IDLE line detected /
		7107	#define USART_SR_RXNE_Pos (5U)
		7108	#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /!< 0x00000020 /
		7109	#define USART_SR_RXNE USART_SR_RXNE_Msk /!< Read Data Register Not Empty /
		7110	#define USART_SR_TC_Pos (6U)
		7111	#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /!< 0x00000040 /
		7112	#define USART_SR_TC USART_SR_TC_Msk /!< Transmission Complete /
		7113	#define USART_SR_TXE_Pos (7U)
		7114	#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /!< 0x00000080 /
		7115	#define USART_SR_TXE USART_SR_TXE_Msk /!< Transmit Data Register Empty /
		7116	#define USART_SR_LBD_Pos (8U)
		7117	#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /!< 0x00000100 /
		7118	#define USART_SR_LBD USART_SR_LBD_Msk /!< LIN Break Detection Flag /
		7119	#define USART_SR_CTS_Pos (9U)
		7120	#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /!< 0x00000200 /
		7121	#define USART_SR_CTS USART_SR_CTS_Msk /!< CTS Flag /
		7122
		7123	/***************** Bit definition for USART_DR register *****************/
		7124	#define USART_DR_DR_Pos (0U)
		7125	#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /!< 0x000001FF /
		7126	#define USART_DR_DR USART_DR_DR_Msk /!< Data value /
		7127
		7128	/**************** Bit definition for USART_BRR register *****************/
		7129	#define USART_BRR_DIV_FRACTION_Pos (0U)
		7130	#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /!< 0x0000000F /
		7131	#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /!< Fraction of USARTDIV /
		7132	#define USART_BRR_DIV_MANTISSA_Pos (4U)
		7133	#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /!< 0x0000FFF0 /
		7134	#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /!< Mantissa of USARTDIV /
		7135
		7136	/**************** Bit definition for USART_CR1 register *****************/
		7137	#define USART_CR1_SBK_Pos (0U)
		7138	#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /!< 0x00000001 /
		7139	#define USART_CR1_SBK USART_CR1_SBK_Msk /!< Send Break /
		7140	#define USART_CR1_RWU_Pos (1U)
		7141	#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /!< 0x00000002 /
		7142	#define USART_CR1_RWU USART_CR1_RWU_Msk /!< Receiver wakeup /
		7143	#define USART_CR1_RE_Pos (2U)
		7144	#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /!< 0x00000004 /
		7145	#define USART_CR1_RE USART_CR1_RE_Msk /!< Receiver Enable /
		7146	#define USART_CR1_TE_Pos (3U)
		7147	#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /!< 0x00000008 /
		7148	#define USART_CR1_TE USART_CR1_TE_Msk /!< Transmitter Enable /
		7149	#define USART_CR1_IDLEIE_Pos (4U)
		7150	#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /!< 0x00000010 /
		7151	#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /!< IDLE Interrupt Enable /
		7152	#define USART_CR1_RXNEIE_Pos (5U)
		7153	#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /!< 0x00000020 /
		7154	#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /!< RXNE Interrupt Enable /
		7155	#define USART_CR1_TCIE_Pos (6U)
		7156	#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /!< 0x00000040 /
		7157	#define USART_CR1_TCIE USART_CR1_TCIE_Msk /!< Transmission Complete Interrupt Enable /
		7158	#define USART_CR1_TXEIE_Pos (7U)
		7159	#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /!< 0x00000080 /
		7160	#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /!< PE Interrupt Enable /
		7161	#define USART_CR1_PEIE_Pos (8U)
		7162	#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /!< 0x00000100 /
		7163	#define USART_CR1_PEIE USART_CR1_PEIE_Msk /!< PE Interrupt Enable /
		7164	#define USART_CR1_PS_Pos (9U)
		7165	#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /!< 0x00000200 /
		7166	#define USART_CR1_PS USART_CR1_PS_Msk /!< Parity Selection /
		7167	#define USART_CR1_PCE_Pos (10U)
		7168	#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /!< 0x00000400 /
		7169	#define USART_CR1_PCE USART_CR1_PCE_Msk /!< Parity Control Enable /
		7170	#define USART_CR1_WAKE_Pos (11U)
		7171	#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /!< 0x00000800 /
		7172	#define USART_CR1_WAKE USART_CR1_WAKE_Msk /!< Wakeup method /
		7173	#define USART_CR1_M_Pos (12U)
		7174	#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /!< 0x00001000 /
		7175	#define USART_CR1_M USART_CR1_M_Msk /!< Word length /
		7176	#define USART_CR1_UE_Pos (13U)
		7177	#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /!< 0x00002000 /
		7178	#define USART_CR1_UE USART_CR1_UE_Msk /!< USART Enable /
		7179	#define USART_CR1_OVER8_Pos (15U)
		7180	#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /!< 0x00008000 /
		7181	#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /!< Oversampling by 8-bit mode /
		7182
		7183	/**************** Bit definition for USART_CR2 register *****************/
		7184	#define USART_CR2_ADD_Pos (0U)
		7185	#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /!< 0x0000000F /
		7186	#define USART_CR2_ADD USART_CR2_ADD_Msk /!< Address of the USART node /
		7187	#define USART_CR2_LBDL_Pos (5U)
		7188	#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /!< 0x00000020 /
		7189	#define USART_CR2_LBDL USART_CR2_LBDL_Msk /!< LIN Break Detection Length /
		7190	#define USART_CR2_LBDIE_Pos (6U)
		7191	#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /!< 0x00000040 /
		7192	#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /!< LIN Break Detection Interrupt Enable /
		7193	#define USART_CR2_LBCL_Pos (8U)
		7194	#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /!< 0x00000100 /
		7195	#define USART_CR2_LBCL USART_CR2_LBCL_Msk /!< Last Bit Clock pulse /
		7196	#define USART_CR2_CPHA_Pos (9U)
		7197	#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /!< 0x00000200 /
		7198	#define USART_CR2_CPHA USART_CR2_CPHA_Msk /!< Clock Phase /
		7199	#define USART_CR2_CPOL_Pos (10U)
		7200	#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /!< 0x00000400 /
		7201	#define USART_CR2_CPOL USART_CR2_CPOL_Msk /!< Clock Polarity /
		7202	#define USART_CR2_CLKEN_Pos (11U)
		7203	#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /!< 0x00000800 /
		7204	#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /!< Clock Enable /
		7205
		7206	#define USART_CR2_STOP_Pos (12U)
		7207	#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /!< 0x00003000 /
		7208	#define USART_CR2_STOP USART_CR2_STOP_Msk /!< STOP[1:0] bits (STOP bits) /
		7209	#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /!< 0x00001000 /
		7210	#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /!< 0x00002000 /
		7211
		7212	#define USART_CR2_LINEN_Pos (14U)
		7213	#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /!< 0x00004000 /
		7214	#define USART_CR2_LINEN USART_CR2_LINEN_Msk /!< LIN mode enable /
		7215
		7216	/**************** Bit definition for USART_CR3 register *****************/
		7217	#define USART_CR3_EIE_Pos (0U)
		7218	#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /!< 0x00000001 /
		7219	#define USART_CR3_EIE USART_CR3_EIE_Msk /!< Error Interrupt Enable /
		7220	#define USART_CR3_IREN_Pos (1U)
		7221	#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /!< 0x00000002 /
		7222	#define USART_CR3_IREN USART_CR3_IREN_Msk /!< IrDA mode Enable /
		7223	#define USART_CR3_IRLP_Pos (2U)
		7224	#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /!< 0x00000004 /
		7225	#define USART_CR3_IRLP USART_CR3_IRLP_Msk /!< IrDA Low-Power /
		7226	#define USART_CR3_HDSEL_Pos (3U)
		7227	#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /!< 0x00000008 /
		7228	#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /!< Half-Duplex Selection /
		7229	#define USART_CR3_NACK_Pos (4U)
		7230	#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /!< 0x00000010 /
		7231	#define USART_CR3_NACK USART_CR3_NACK_Msk /!< Smartcard NACK enable /
		7232	#define USART_CR3_SCEN_Pos (5U)
		7233	#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /!< 0x00000020 /
		7234	#define USART_CR3_SCEN USART_CR3_SCEN_Msk /!< Smartcard mode enable /
		7235	#define USART_CR3_DMAR_Pos (6U)
		7236	#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /!< 0x00000040 /
		7237	#define USART_CR3_DMAR USART_CR3_DMAR_Msk /!< DMA Enable Receiver /
		7238	#define USART_CR3_DMAT_Pos (7U)
		7239	#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /!< 0x00000080 /
		7240	#define USART_CR3_DMAT USART_CR3_DMAT_Msk /!< DMA Enable Transmitter /
		7241	#define USART_CR3_RTSE_Pos (8U)
		7242	#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /!< 0x00000100 /
		7243	#define USART_CR3_RTSE USART_CR3_RTSE_Msk /!< RTS Enable /
		7244	#define USART_CR3_CTSE_Pos (9U)
		7245	#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /!< 0x00000200 /
		7246	#define USART_CR3_CTSE USART_CR3_CTSE_Msk /!< CTS Enable /
		7247	#define USART_CR3_CTSIE_Pos (10U)
		7248	#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /!< 0x00000400 /
		7249	#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /!< CTS Interrupt Enable /
		7250	#define USART_CR3_ONEBIT_Pos (11U)
		7251	#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /!< 0x00000800 /
		7252	#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /!< One sample bit method enable /
		7253
		7254	/**************** Bit definition for USART_GTPR register ****************/
		7255	#define USART_GTPR_PSC_Pos (0U)
		7256	#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /!< 0x000000FF /
		7257	#define USART_GTPR_PSC USART_GTPR_PSC_Msk /!< PSC[7:0] bits (Prescaler value) /
		7258	#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /!< 0x00000001 /
		7259	#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /!< 0x00000002 /
		7260	#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /!< 0x00000004 /
		7261	#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /!< 0x00000008 /
		7262	#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /!< 0x00000010 /
		7263	#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /!< 0x00000020 /
		7264	#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /!< 0x00000040 /
		7265	#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /!< 0x00000080 /
		7266
		7267	#define USART_GTPR_GT_Pos (8U)
		7268	#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /!< 0x0000FF00 /
		7269	#define USART_GTPR_GT USART_GTPR_GT_Msk /!< Guard time value /
		7270
		7271	/******************************************************************************/
		7272	/* */
		7273	/* Universal Serial Bus (USB) */
		7274	/* */
		7275	/******************************************************************************/
		7276
		7277	/!<Endpoint-specific registers /
		7278
		7279	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
		7280	#define USB_EP1R (USB_BASE + 0x00000004U) /!< endpoint 1 register address /
		7281	#define USB_EP2R (USB_BASE + 0x00000008U) /!< endpoint 2 register address /
		7282	#define USB_EP3R (USB_BASE + 0x0000000CU) /!< endpoint 3 register address /
		7283	#define USB_EP4R (USB_BASE + 0x00000010U) /!< endpoint 4 register address /
		7284	#define USB_EP5R (USB_BASE + 0x00000014U) /!< endpoint 5 register address /
		7285	#define USB_EP6R (USB_BASE + 0x00000018U) /!< endpoint 6 register address /
		7286	#define USB_EP7R (USB_BASE + 0x0000001CU) /!< endpoint 7 register address /
		7287
		7288	/* bit positions */
		7289	#define USB_EP_CTR_RX_Pos (15U)
		7290	#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /!< 0x00008000 /
		7291	#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /!< EndPoint Correct TRansfer RX /
		7292	#define USB_EP_DTOG_RX_Pos (14U)
		7293	#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /!< 0x00004000 /
		7294	#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /!< EndPoint Data TOGGLE RX /
		7295	#define USB_EPRX_STAT_Pos (12U)
		7296	#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /!< 0x00003000 /
		7297	#define USB_EPRX_STAT USB_EPRX_STAT_Msk /!< EndPoint RX STATus bit field /
		7298	#define USB_EP_SETUP_Pos (11U)
		7299	#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /!< 0x00000800 /
		7300	#define USB_EP_SETUP USB_EP_SETUP_Msk /!< EndPoint SETUP /
		7301	#define USB_EP_T_FIELD_Pos (9U)
		7302	#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /!< 0x00000600 /
		7303	#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /!< EndPoint TYPE /
		7304	#define USB_EP_KIND_Pos (8U)
		7305	#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /!< 0x00000100 /
		7306	#define USB_EP_KIND USB_EP_KIND_Msk /!< EndPoint KIND /
		7307	#define USB_EP_CTR_TX_Pos (7U)
		7308	#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /!< 0x00000080 /
		7309	#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /!< EndPoint Correct TRansfer TX /
		7310	#define USB_EP_DTOG_TX_Pos (6U)
		7311	#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /!< 0x00000040 /
		7312	#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /!< EndPoint Data TOGGLE TX /
		7313	#define USB_EPTX_STAT_Pos (4U)
		7314	#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /!< 0x00000030 /
		7315	#define USB_EPTX_STAT USB_EPTX_STAT_Msk /!< EndPoint TX STATus bit field /
		7316	#define USB_EPADDR_FIELD_Pos (0U)
		7317	#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /!< 0x0000000F /
		7318	#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /!< EndPoint ADDRess FIELD /
		7319
		7320	/* EndPoint REGister MASK (no toggle fields) */
		7321	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
		7322	/!< EP_TYPE[1:0] EndPoint TYPE /
		7323	#define USB_EP_TYPE_MASK_Pos (9U)
		7324	#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /!< 0x00000600 /
		7325	#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /!< EndPoint TYPE Mask /
		7326	#define USB_EP_BULK (0x00000000U) /!< EndPoint BULK /
		7327	#define USB_EP_CONTROL (0x00000200U) /!< EndPoint CONTROL /
		7328	#define USB_EP_ISOCHRONOUS (0x00000400U) /!< EndPoint ISOCHRONOUS /
		7329	#define USB_EP_INTERRUPT (0x00000600U) /!< EndPoint INTERRUPT /
		7330	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
		7331
		7332	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
		7333	/!< STAT_TX[1:0] STATus for TX transfer /
		7334	#define USB_EP_TX_DIS (0x00000000U) /!< EndPoint TX DISabled /
		7335	#define USB_EP_TX_STALL (0x00000010U) /!< EndPoint TX STALLed /
		7336	#define USB_EP_TX_NAK (0x00000020U) /!< EndPoint TX NAKed /
		7337	#define USB_EP_TX_VALID (0x00000030U) /!< EndPoint TX VALID /
		7338	#define USB_EPTX_DTOG1 (0x00000010U) /!< EndPoint TX Data TOGgle bit1 /
		7339	#define USB_EPTX_DTOG2 (0x00000020U) /!< EndPoint TX Data TOGgle bit2 /
		7340	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
		7341	/!< STAT_RX[1:0] STATus for RX transfer /
		7342	#define USB_EP_RX_DIS (0x00000000U) /!< EndPoint RX DISabled /
		7343	#define USB_EP_RX_STALL (0x00001000U) /!< EndPoint RX STALLed /
		7344	#define USB_EP_RX_NAK (0x00002000U) /!< EndPoint RX NAKed /
		7345	#define USB_EP_RX_VALID (0x00003000U) /!< EndPoint RX VALID /
		7346	#define USB_EPRX_DTOG1 (0x00001000U) /!< EndPoint RX Data TOGgle bit1 /
		7347	#define USB_EPRX_DTOG2 (0x00002000U) /!< EndPoint RX Data TOGgle bit1 /
		7348	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
		7349
		7350	/***************** Bit definition for USB_EP0R register *****************/
		7351	#define USB_EP0R_EA_Pos (0U)
		7352	#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /!< 0x0000000F /
		7353	#define USB_EP0R_EA USB_EP0R_EA_Msk /!<Endpoint Address /
		7354
		7355	#define USB_EP0R_STAT_TX_Pos (4U)
		7356	#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /!< 0x00000030 /
		7357	#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7358	#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /!< 0x00000010 /
		7359	#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /!< 0x00000020 /
		7360
		7361	#define USB_EP0R_DTOG_TX_Pos (6U)
		7362	#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /!< 0x00000040 /
		7363	#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7364	#define USB_EP0R_CTR_TX_Pos (7U)
		7365	#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /!< 0x00000080 /
		7366	#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7367	#define USB_EP0R_EP_KIND_Pos (8U)
		7368	#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /!< 0x00000100 /
		7369	#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /!<Endpoint Kind /
		7370
		7371	#define USB_EP0R_EP_TYPE_Pos (9U)
		7372	#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /!< 0x00000600 /
		7373	#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7374	#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /!< 0x00000200 /
		7375	#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /!< 0x00000400 /
		7376
		7377	#define USB_EP0R_SETUP_Pos (11U)
		7378	#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /!< 0x00000800 /
		7379	#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /!<Setup transaction completed /
		7380
		7381	#define USB_EP0R_STAT_RX_Pos (12U)
		7382	#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /!< 0x00003000 /
		7383	#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7384	#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /!< 0x00001000 /
		7385	#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /!< 0x00002000 /
		7386
		7387	#define USB_EP0R_DTOG_RX_Pos (14U)
		7388	#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /!< 0x00004000 /
		7389	#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7390	#define USB_EP0R_CTR_RX_Pos (15U)
		7391	#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /!< 0x00008000 /
		7392	#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /!<Correct Transfer for reception /
		7393
		7394	/***************** Bit definition for USB_EP1R register *****************/
		7395	#define USB_EP1R_EA_Pos (0U)
		7396	#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /!< 0x0000000F /
		7397	#define USB_EP1R_EA USB_EP1R_EA_Msk /!<Endpoint Address /
		7398
		7399	#define USB_EP1R_STAT_TX_Pos (4U)
		7400	#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /!< 0x00000030 /
		7401	#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7402	#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /!< 0x00000010 /
		7403	#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /!< 0x00000020 /
		7404
		7405	#define USB_EP1R_DTOG_TX_Pos (6U)
		7406	#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /!< 0x00000040 /
		7407	#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7408	#define USB_EP1R_CTR_TX_Pos (7U)
		7409	#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /!< 0x00000080 /
		7410	#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7411	#define USB_EP1R_EP_KIND_Pos (8U)
		7412	#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /!< 0x00000100 /
		7413	#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /!<Endpoint Kind /
		7414
		7415	#define USB_EP1R_EP_TYPE_Pos (9U)
		7416	#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /!< 0x00000600 /
		7417	#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7418	#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /!< 0x00000200 /
		7419	#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /!< 0x00000400 /
		7420
		7421	#define USB_EP1R_SETUP_Pos (11U)
		7422	#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /!< 0x00000800 /
		7423	#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /!<Setup transaction completed /
		7424
		7425	#define USB_EP1R_STAT_RX_Pos (12U)
		7426	#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /!< 0x00003000 /
		7427	#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7428	#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /!< 0x00001000 /
		7429	#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /!< 0x00002000 /
		7430
		7431	#define USB_EP1R_DTOG_RX_Pos (14U)
		7432	#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /!< 0x00004000 /
		7433	#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7434	#define USB_EP1R_CTR_RX_Pos (15U)
		7435	#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /!< 0x00008000 /
		7436	#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /!<Correct Transfer for reception /
		7437
		7438	/***************** Bit definition for USB_EP2R register *****************/
		7439	#define USB_EP2R_EA_Pos (0U)
		7440	#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /!< 0x0000000F /
		7441	#define USB_EP2R_EA USB_EP2R_EA_Msk /!<Endpoint Address /
		7442
		7443	#define USB_EP2R_STAT_TX_Pos (4U)
		7444	#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /!< 0x00000030 /
		7445	#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7446	#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /!< 0x00000010 /
		7447	#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /!< 0x00000020 /
		7448
		7449	#define USB_EP2R_DTOG_TX_Pos (6U)
		7450	#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /!< 0x00000040 /
		7451	#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7452	#define USB_EP2R_CTR_TX_Pos (7U)
		7453	#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /!< 0x00000080 /
		7454	#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7455	#define USB_EP2R_EP_KIND_Pos (8U)
		7456	#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /!< 0x00000100 /
		7457	#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /!<Endpoint Kind /
		7458
		7459	#define USB_EP2R_EP_TYPE_Pos (9U)
		7460	#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /!< 0x00000600 /
		7461	#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7462	#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /!< 0x00000200 /
		7463	#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /!< 0x00000400 /
		7464
		7465	#define USB_EP2R_SETUP_Pos (11U)
		7466	#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /!< 0x00000800 /
		7467	#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /!<Setup transaction completed /
		7468
		7469	#define USB_EP2R_STAT_RX_Pos (12U)
		7470	#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /!< 0x00003000 /
		7471	#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7472	#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /!< 0x00001000 /
		7473	#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /!< 0x00002000 /
		7474
		7475	#define USB_EP2R_DTOG_RX_Pos (14U)
		7476	#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /!< 0x00004000 /
		7477	#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7478	#define USB_EP2R_CTR_RX_Pos (15U)
		7479	#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /!< 0x00008000 /
		7480	#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /!<Correct Transfer for reception /
		7481
		7482	/***************** Bit definition for USB_EP3R register *****************/
		7483	#define USB_EP3R_EA_Pos (0U)
		7484	#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /!< 0x0000000F /
		7485	#define USB_EP3R_EA USB_EP3R_EA_Msk /!<Endpoint Address /
		7486
		7487	#define USB_EP3R_STAT_TX_Pos (4U)
		7488	#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /!< 0x00000030 /
		7489	#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7490	#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /!< 0x00000010 /
		7491	#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /!< 0x00000020 /
		7492
		7493	#define USB_EP3R_DTOG_TX_Pos (6U)
		7494	#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /!< 0x00000040 /
		7495	#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7496	#define USB_EP3R_CTR_TX_Pos (7U)
		7497	#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /!< 0x00000080 /
		7498	#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7499	#define USB_EP3R_EP_KIND_Pos (8U)
		7500	#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /!< 0x00000100 /
		7501	#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /!<Endpoint Kind /
		7502
		7503	#define USB_EP3R_EP_TYPE_Pos (9U)
		7504	#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /!< 0x00000600 /
		7505	#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7506	#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /!< 0x00000200 /
		7507	#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /!< 0x00000400 /
		7508
		7509	#define USB_EP3R_SETUP_Pos (11U)
		7510	#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /!< 0x00000800 /
		7511	#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /!<Setup transaction completed /
		7512
		7513	#define USB_EP3R_STAT_RX_Pos (12U)
		7514	#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /!< 0x00003000 /
		7515	#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7516	#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /!< 0x00001000 /
		7517	#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /!< 0x00002000 /
		7518
		7519	#define USB_EP3R_DTOG_RX_Pos (14U)
		7520	#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /!< 0x00004000 /
		7521	#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7522	#define USB_EP3R_CTR_RX_Pos (15U)
		7523	#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /!< 0x00008000 /
		7524	#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /!<Correct Transfer for reception /
		7525
		7526	/***************** Bit definition for USB_EP4R register *****************/
		7527	#define USB_EP4R_EA_Pos (0U)
		7528	#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /!< 0x0000000F /
		7529	#define USB_EP4R_EA USB_EP4R_EA_Msk /!<Endpoint Address /
		7530
		7531	#define USB_EP4R_STAT_TX_Pos (4U)
		7532	#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /!< 0x00000030 /
		7533	#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7534	#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /!< 0x00000010 /
		7535	#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /!< 0x00000020 /
		7536
		7537	#define USB_EP4R_DTOG_TX_Pos (6U)
		7538	#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /!< 0x00000040 /
		7539	#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7540	#define USB_EP4R_CTR_TX_Pos (7U)
		7541	#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /!< 0x00000080 /
		7542	#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7543	#define USB_EP4R_EP_KIND_Pos (8U)
		7544	#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /!< 0x00000100 /
		7545	#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /!<Endpoint Kind /
		7546
		7547	#define USB_EP4R_EP_TYPE_Pos (9U)
		7548	#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /!< 0x00000600 /
		7549	#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7550	#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /!< 0x00000200 /
		7551	#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /!< 0x00000400 /
		7552
		7553	#define USB_EP4R_SETUP_Pos (11U)
		7554	#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /!< 0x00000800 /
		7555	#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /!<Setup transaction completed /
		7556
		7557	#define USB_EP4R_STAT_RX_Pos (12U)
		7558	#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /!< 0x00003000 /
		7559	#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7560	#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /!< 0x00001000 /
		7561	#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /!< 0x00002000 /
		7562
		7563	#define USB_EP4R_DTOG_RX_Pos (14U)
		7564	#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /!< 0x00004000 /
		7565	#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7566	#define USB_EP4R_CTR_RX_Pos (15U)
		7567	#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /!< 0x00008000 /
		7568	#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /!<Correct Transfer for reception /
		7569
		7570	/***************** Bit definition for USB_EP5R register *****************/
		7571	#define USB_EP5R_EA_Pos (0U)
		7572	#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /!< 0x0000000F /
		7573	#define USB_EP5R_EA USB_EP5R_EA_Msk /!<Endpoint Address /
		7574
		7575	#define USB_EP5R_STAT_TX_Pos (4U)
		7576	#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /!< 0x00000030 /
		7577	#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7578	#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /!< 0x00000010 /
		7579	#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /!< 0x00000020 /
		7580
		7581	#define USB_EP5R_DTOG_TX_Pos (6U)
		7582	#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /!< 0x00000040 /
		7583	#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7584	#define USB_EP5R_CTR_TX_Pos (7U)
		7585	#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /!< 0x00000080 /
		7586	#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7587	#define USB_EP5R_EP_KIND_Pos (8U)
		7588	#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /!< 0x00000100 /
		7589	#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /!<Endpoint Kind /
		7590
		7591	#define USB_EP5R_EP_TYPE_Pos (9U)
		7592	#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /!< 0x00000600 /
		7593	#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7594	#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /!< 0x00000200 /
		7595	#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /!< 0x00000400 /
		7596
		7597	#define USB_EP5R_SETUP_Pos (11U)
		7598	#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /!< 0x00000800 /
		7599	#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /!<Setup transaction completed /
		7600
		7601	#define USB_EP5R_STAT_RX_Pos (12U)
		7602	#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /!< 0x00003000 /
		7603	#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7604	#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /!< 0x00001000 /
		7605	#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /!< 0x00002000 /
		7606
		7607	#define USB_EP5R_DTOG_RX_Pos (14U)
		7608	#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /!< 0x00004000 /
		7609	#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7610	#define USB_EP5R_CTR_RX_Pos (15U)
		7611	#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /!< 0x00008000 /
		7612	#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /!<Correct Transfer for reception /
		7613
		7614	/***************** Bit definition for USB_EP6R register *****************/
		7615	#define USB_EP6R_EA_Pos (0U)
		7616	#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /!< 0x0000000F /
		7617	#define USB_EP6R_EA USB_EP6R_EA_Msk /!<Endpoint Address /
		7618
		7619	#define USB_EP6R_STAT_TX_Pos (4U)
		7620	#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /!< 0x00000030 /
		7621	#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7622	#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /!< 0x00000010 /
		7623	#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /!< 0x00000020 /
		7624
		7625	#define USB_EP6R_DTOG_TX_Pos (6U)
		7626	#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /!< 0x00000040 /
		7627	#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7628	#define USB_EP6R_CTR_TX_Pos (7U)
		7629	#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /!< 0x00000080 /
		7630	#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7631	#define USB_EP6R_EP_KIND_Pos (8U)
		7632	#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /!< 0x00000100 /
		7633	#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /!<Endpoint Kind /
		7634
		7635	#define USB_EP6R_EP_TYPE_Pos (9U)
		7636	#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /!< 0x00000600 /
		7637	#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7638	#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /!< 0x00000200 /
		7639	#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /!< 0x00000400 /
		7640
		7641	#define USB_EP6R_SETUP_Pos (11U)
		7642	#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /!< 0x00000800 /
		7643	#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /!<Setup transaction completed /
		7644
		7645	#define USB_EP6R_STAT_RX_Pos (12U)
		7646	#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /!< 0x00003000 /
		7647	#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7648	#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /!< 0x00001000 /
		7649	#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /!< 0x00002000 /
		7650
		7651	#define USB_EP6R_DTOG_RX_Pos (14U)
		7652	#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /!< 0x00004000 /
		7653	#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7654	#define USB_EP6R_CTR_RX_Pos (15U)
		7655	#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /!< 0x00008000 /
		7656	#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /!<Correct Transfer for reception /
		7657
		7658	/***************** Bit definition for USB_EP7R register *****************/
		7659	#define USB_EP7R_EA_Pos (0U)
		7660	#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /!< 0x0000000F /
		7661	#define USB_EP7R_EA USB_EP7R_EA_Msk /!<Endpoint Address /
		7662
		7663	#define USB_EP7R_STAT_TX_Pos (4U)
		7664	#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /!< 0x00000030 /
		7665	#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /!<STAT_TX[1:0] bits (Status bits, for transmission transfers) /
		7666	#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /!< 0x00000010 /
		7667	#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /!< 0x00000020 /
		7668
		7669	#define USB_EP7R_DTOG_TX_Pos (6U)
		7670	#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /!< 0x00000040 /
		7671	#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /!<Data Toggle, for transmission transfers /
		7672	#define USB_EP7R_CTR_TX_Pos (7U)
		7673	#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /!< 0x00000080 /
		7674	#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /!<Correct Transfer for transmission /
		7675	#define USB_EP7R_EP_KIND_Pos (8U)
		7676	#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /!< 0x00000100 /
		7677	#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /!<Endpoint Kind /
		7678
		7679	#define USB_EP7R_EP_TYPE_Pos (9U)
		7680	#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /!< 0x00000600 /
		7681	#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /!<EP_TYPE[1:0] bits (Endpoint type) /
		7682	#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /!< 0x00000200 /
		7683	#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /!< 0x00000400 /
		7684
		7685	#define USB_EP7R_SETUP_Pos (11U)
		7686	#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /!< 0x00000800 /
		7687	#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /!<Setup transaction completed /
		7688
		7689	#define USB_EP7R_STAT_RX_Pos (12U)
		7690	#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /!< 0x00003000 /
		7691	#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /!<STAT_RX[1:0] bits (Status bits, for reception transfers) /
		7692	#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /!< 0x00001000 /
		7693	#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /!< 0x00002000 /
		7694
		7695	#define USB_EP7R_DTOG_RX_Pos (14U)
		7696	#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /!< 0x00004000 /
		7697	#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /!<Data Toggle, for reception transfers /
		7698	#define USB_EP7R_CTR_RX_Pos (15U)
		7699	#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /!< 0x00008000 /
		7700	#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /!<Correct Transfer for reception /
		7701
		7702	/!<Common registers /
		7703
		7704	#define USB_CNTR (USB_BASE + 0x00000040U) /!< Control register /
		7705	#define USB_ISTR (USB_BASE + 0x00000044U) /!< Interrupt status register /
		7706	#define USB_FNR (USB_BASE + 0x00000048U) /!< Frame number register /
		7707	#define USB_DADDR (USB_BASE + 0x0000004CU) /!< Device address register /
		7708	#define USB_BTABLE (USB_BASE + 0x00000050U) /!< Buffer Table address register /
		7709
		7710
		7711
		7712	/***************** Bit definition for USB_CNTR register *****************/
		7713	#define USB_CNTR_FRES_Pos (0U)
		7714	#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /!< 0x00000001 /
		7715	#define USB_CNTR_FRES USB_CNTR_FRES_Msk /!<Force USB Reset /
		7716	#define USB_CNTR_PDWN_Pos (1U)
		7717	#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /!< 0x00000002 /
		7718	#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /!<Power down /
		7719	#define USB_CNTR_LPMODE_Pos (2U)
		7720	#define USB_CNTR_LPMODE_Msk (0x1U << USB_CNTR_LPMODE_Pos) /!< 0x00000004 /
		7721	#define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /!<Low-power mode /
		7722	#define USB_CNTR_FSUSP_Pos (3U)
		7723	#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /!< 0x00000008 /
		7724	#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /!<Force suspend /
		7725	#define USB_CNTR_RESUME_Pos (4U)
		7726	#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /!< 0x00000010 /
		7727	#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /!<Resume request /
		7728	#define USB_CNTR_ESOFM_Pos (8U)
		7729	#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /!< 0x00000100 /
		7730	#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /!<Expected Start Of Frame Interrupt Mask /
		7731	#define USB_CNTR_SOFM_Pos (9U)
		7732	#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /!< 0x00000200 /
		7733	#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /!<Start Of Frame Interrupt Mask /
		7734	#define USB_CNTR_RESETM_Pos (10U)
		7735	#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /!< 0x00000400 /
		7736	#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /!<RESET Interrupt Mask /
		7737	#define USB_CNTR_SUSPM_Pos (11U)
		7738	#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /!< 0x00000800 /
		7739	#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /!<Suspend mode Interrupt Mask /
		7740	#define USB_CNTR_WKUPM_Pos (12U)
		7741	#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /!< 0x00001000 /
		7742	#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /!<Wakeup Interrupt Mask /
		7743	#define USB_CNTR_ERRM_Pos (13U)
		7744	#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /!< 0x00002000 /
		7745	#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /!<Error Interrupt Mask /
		7746	#define USB_CNTR_PMAOVRM_Pos (14U)
		7747	#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /!< 0x00004000 /
		7748	#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /!<Packet Memory Area Over / Underrun Interrupt Mask /
		7749	#define USB_CNTR_CTRM_Pos (15U)
		7750	#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /!< 0x00008000 /
		7751	#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /!<Correct Transfer Interrupt Mask /
		7752
		7753	/***************** Bit definition for USB_ISTR register *****************/
		7754	#define USB_ISTR_EP_ID_Pos (0U)
		7755	#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /!< 0x0000000F /
		7756	#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /!<Endpoint Identifier /
		7757	#define USB_ISTR_DIR_Pos (4U)
		7758	#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /!< 0x00000010 /
		7759	#define USB_ISTR_DIR USB_ISTR_DIR_Msk /!<Direction of transaction /
		7760	#define USB_ISTR_ESOF_Pos (8U)
		7761	#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /!< 0x00000100 /
		7762	#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /!<Expected Start Of Frame /
		7763	#define USB_ISTR_SOF_Pos (9U)
		7764	#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /!< 0x00000200 /
		7765	#define USB_ISTR_SOF USB_ISTR_SOF_Msk /!<Start Of Frame /
		7766	#define USB_ISTR_RESET_Pos (10U)
		7767	#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /!< 0x00000400 /
		7768	#define USB_ISTR_RESET USB_ISTR_RESET_Msk /!<USB RESET request /
		7769	#define USB_ISTR_SUSP_Pos (11U)
		7770	#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /!< 0x00000800 /
		7771	#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /!<Suspend mode request /
		7772	#define USB_ISTR_WKUP_Pos (12U)
		7773	#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /!< 0x00001000 /
		7774	#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /!<Wake up /
		7775	#define USB_ISTR_ERR_Pos (13U)
		7776	#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /!< 0x00002000 /
		7777	#define USB_ISTR_ERR USB_ISTR_ERR_Msk /!<Error /
		7778	#define USB_ISTR_PMAOVR_Pos (14U)
		7779	#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /!< 0x00004000 /
		7780	#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /!<Packet Memory Area Over / Underrun /
		7781	#define USB_ISTR_CTR_Pos (15U)
		7782	#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /!< 0x00008000 /
		7783	#define USB_ISTR_CTR USB_ISTR_CTR_Msk /!<Correct Transfer /
		7784
		7785	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
		7786	#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
		7787	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
		7788	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
		7789	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
		7790	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
		7791	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
		7792	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
		7793
		7794
		7795	/***************** Bit definition for USB_FNR register ******************/
		7796	#define USB_FNR_FN_Pos (0U)
		7797	#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /!< 0x000007FF /
		7798	#define USB_FNR_FN USB_FNR_FN_Msk /!<Frame Number /
		7799	#define USB_FNR_LSOF_Pos (11U)
		7800	#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /!< 0x00001800 /
		7801	#define USB_FNR_LSOF USB_FNR_LSOF_Msk /!<Lost SOF /
		7802	#define USB_FNR_LCK_Pos (13U)
		7803	#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /!< 0x00002000 /
		7804	#define USB_FNR_LCK USB_FNR_LCK_Msk /!<Locked /
		7805	#define USB_FNR_RXDM_Pos (14U)
		7806	#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /!< 0x00004000 /
		7807	#define USB_FNR_RXDM USB_FNR_RXDM_Msk /!<Receive Data - Line Status /
		7808	#define USB_FNR_RXDP_Pos (15U)
		7809	#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /!< 0x00008000 /
		7810	#define USB_FNR_RXDP USB_FNR_RXDP_Msk /!<Receive Data + Line Status /
		7811
		7812	/**************** Bit definition for USB_DADDR register *****************/
		7813	#define USB_DADDR_ADD_Pos (0U)
		7814	#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /!< 0x0000007F /
		7815	#define USB_DADDR_ADD USB_DADDR_ADD_Msk /!<ADD[6:0] bits (Device Address) /
		7816	#define USB_DADDR_ADD0_Pos (0U)
		7817	#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /!< 0x00000001 /
		7818	#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /!<Bit 0 /
		7819	#define USB_DADDR_ADD1_Pos (1U)
		7820	#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /!< 0x00000002 /
		7821	#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /!<Bit 1 /
		7822	#define USB_DADDR_ADD2_Pos (2U)
		7823	#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /!< 0x00000004 /
		7824	#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /!<Bit 2 /
		7825	#define USB_DADDR_ADD3_Pos (3U)
		7826	#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /!< 0x00000008 /
		7827	#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /!<Bit 3 /
		7828	#define USB_DADDR_ADD4_Pos (4U)
		7829	#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /!< 0x00000010 /
		7830	#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /!<Bit 4 /
		7831	#define USB_DADDR_ADD5_Pos (5U)
		7832	#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /!< 0x00000020 /
		7833	#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /!<Bit 5 /
		7834	#define USB_DADDR_ADD6_Pos (6U)
		7835	#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /!< 0x00000040 /
		7836	#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /!<Bit 6 /
		7837
		7838	#define USB_DADDR_EF_Pos (7U)
		7839	#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /!< 0x00000080 /
		7840	#define USB_DADDR_EF USB_DADDR_EF_Msk /!<Enable Function /
		7841
		7842	/**************** Bit definition for USB_BTABLE register ****************/
		7843	#define USB_BTABLE_BTABLE_Pos (3U)
		7844	#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /!< 0x0000FFF8 /
		7845	#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /!<Buffer Table /
		7846
		7847	/!< Buffer descriptor table /
		7848	/*************** Bit definition for USB_ADDR0_TX register ***************/
		7849	#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
		7850	#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /!< 0x0000FFFE /
		7851	#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /!< Transmission Buffer Address 0 /
		7852
		7853	/*************** Bit definition for USB_ADDR1_TX register ***************/
		7854	#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
		7855	#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /!< 0x0000FFFE /
		7856	#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /!< Transmission Buffer Address 1 /
		7857
		7858	/*************** Bit definition for USB_ADDR2_TX register ***************/
		7859	#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
		7860	#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /!< 0x0000FFFE /
		7861	#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /!< Transmission Buffer Address 2 /
		7862
		7863	/*************** Bit definition for USB_ADDR3_TX register ***************/
		7864	#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
		7865	#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /!< 0x0000FFFE /
		7866	#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /!< Transmission Buffer Address 3 /
		7867
		7868	/*************** Bit definition for USB_ADDR4_TX register ***************/
		7869	#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
		7870	#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /!< 0x0000FFFE /
		7871	#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /!< Transmission Buffer Address 4 /
		7872
		7873	/*************** Bit definition for USB_ADDR5_TX register ***************/
		7874	#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
		7875	#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /!< 0x0000FFFE /
		7876	#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /!< Transmission Buffer Address 5 /
		7877
		7878	/*************** Bit definition for USB_ADDR6_TX register ***************/
		7879	#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
		7880	#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /!< 0x0000FFFE /
		7881	#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /!< Transmission Buffer Address 6 /
		7882
		7883	/*************** Bit definition for USB_ADDR7_TX register ***************/
		7884	#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
		7885	#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /!< 0x0000FFFE /
		7886	#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /!< Transmission Buffer Address 7 /
		7887
		7888	/----------------------------------------------------------------------------/
		7889
		7890	/*************** Bit definition for USB_COUNT0_TX register **************/
		7891	#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
		7892	#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /!< 0x000003FF /
		7893	#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /!< Transmission Byte Count 0 /
		7894
		7895	/*************** Bit definition for USB_COUNT1_TX register **************/
		7896	#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
		7897	#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /!< 0x000003FF /
		7898	#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /!< Transmission Byte Count 1 /
		7899
		7900	/*************** Bit definition for USB_COUNT2_TX register **************/
		7901	#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
		7902	#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /!< 0x000003FF /
		7903	#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /!< Transmission Byte Count 2 /
		7904
		7905	/*************** Bit definition for USB_COUNT3_TX register **************/
		7906	#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
		7907	#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /!< 0x000003FF /
		7908	#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /!< Transmission Byte Count 3 /
		7909
		7910	/*************** Bit definition for USB_COUNT4_TX register **************/
		7911	#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
		7912	#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /!< 0x000003FF /
		7913	#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /!< Transmission Byte Count 4 /
		7914
		7915	/*************** Bit definition for USB_COUNT5_TX register **************/
		7916	#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
		7917	#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /!< 0x000003FF /
		7918	#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /!< Transmission Byte Count 5 /
		7919
		7920	/*************** Bit definition for USB_COUNT6_TX register **************/
		7921	#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
		7922	#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /!< 0x000003FF /
		7923	#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /!< Transmission Byte Count 6 /
		7924
		7925	/*************** Bit definition for USB_COUNT7_TX register **************/
		7926	#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
		7927	#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /!< 0x000003FF /
		7928	#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /!< Transmission Byte Count 7 /
		7929
		7930	/----------------------------------------------------------------------------/
		7931
		7932	/************** Bit definition for USB_COUNT0_TX_0 register *************/
		7933	#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /!< Transmission Byte Count 0 (low) /
		7934
		7935	/************** Bit definition for USB_COUNT0_TX_1 register *************/
		7936	#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /!< Transmission Byte Count 0 (high) /
		7937
		7938	/************** Bit definition for USB_COUNT1_TX_0 register *************/
		7939	#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /!< Transmission Byte Count 1 (low) /
		7940
		7941	/************** Bit definition for USB_COUNT1_TX_1 register *************/
		7942	#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /!< Transmission Byte Count 1 (high) /
		7943
		7944	/************** Bit definition for USB_COUNT2_TX_0 register *************/
		7945	#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /!< Transmission Byte Count 2 (low) /
		7946
		7947	/************** Bit definition for USB_COUNT2_TX_1 register *************/
		7948	#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /!< Transmission Byte Count 2 (high) /
		7949
		7950	/************** Bit definition for USB_COUNT3_TX_0 register *************/
		7951	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /!< Transmission Byte Count 3 (low) /
		7952
		7953	/************** Bit definition for USB_COUNT3_TX_1 register *************/
		7954	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /!< Transmission Byte Count 3 (high) /
		7955
		7956	/************** Bit definition for USB_COUNT4_TX_0 register *************/
		7957	#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /!< Transmission Byte Count 4 (low) /
		7958
		7959	/************** Bit definition for USB_COUNT4_TX_1 register *************/
		7960	#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /!< Transmission Byte Count 4 (high) /
		7961
		7962	/************** Bit definition for USB_COUNT5_TX_0 register *************/
		7963	#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /!< Transmission Byte Count 5 (low) /
		7964
		7965	/************** Bit definition for USB_COUNT5_TX_1 register *************/
		7966	#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /!< Transmission Byte Count 5 (high) /
		7967
		7968	/************** Bit definition for USB_COUNT6_TX_0 register *************/
		7969	#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /!< Transmission Byte Count 6 (low) /
		7970
		7971	/************** Bit definition for USB_COUNT6_TX_1 register *************/
		7972	#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /!< Transmission Byte Count 6 (high) /
		7973
		7974	/************** Bit definition for USB_COUNT7_TX_0 register *************/
		7975	#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /!< Transmission Byte Count 7 (low) /
		7976
		7977	/************** Bit definition for USB_COUNT7_TX_1 register *************/
		7978	#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /!< Transmission Byte Count 7 (high) /
		7979
		7980	/----------------------------------------------------------------------------/
		7981
		7982	/*************** Bit definition for USB_ADDR0_RX register ***************/
		7983	#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
		7984	#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /!< 0x0000FFFE /
		7985	#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /!< Reception Buffer Address 0 /
		7986
		7987	/*************** Bit definition for USB_ADDR1_RX register ***************/
		7988	#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
		7989	#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /!< 0x0000FFFE /
		7990	#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /!< Reception Buffer Address 1 /
		7991
		7992	/*************** Bit definition for USB_ADDR2_RX register ***************/
		7993	#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
		7994	#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /!< 0x0000FFFE /
		7995	#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /!< Reception Buffer Address 2 /
		7996
		7997	/*************** Bit definition for USB_ADDR3_RX register ***************/
		7998	#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
		7999	#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /!< 0x0000FFFE /
		8000	#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /!< Reception Buffer Address 3 /
		8001
		8002	/*************** Bit definition for USB_ADDR4_RX register ***************/
		8003	#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
		8004	#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /!< 0x0000FFFE /
		8005	#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /!< Reception Buffer Address 4 /
		8006
		8007	/*************** Bit definition for USB_ADDR5_RX register ***************/
		8008	#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
		8009	#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /!< 0x0000FFFE /
		8010	#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /!< Reception Buffer Address 5 /
		8011
		8012	/*************** Bit definition for USB_ADDR6_RX register ***************/
		8013	#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
		8014	#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /!< 0x0000FFFE /
		8015	#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /!< Reception Buffer Address 6 /
		8016
		8017	/*************** Bit definition for USB_ADDR7_RX register ***************/
		8018	#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
		8019	#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /!< 0x0000FFFE /
		8020	#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /!< Reception Buffer Address 7 /
		8021
		8022	/----------------------------------------------------------------------------/
		8023
		8024	/*************** Bit definition for USB_COUNT0_RX register **************/
		8025	#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
		8026	#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /!< 0x000003FF /
		8027	#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /!< Reception Byte Count /
		8028
		8029	#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
		8030	#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8031	#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8032	#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8033	#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8034	#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8035	#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8036	#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8037
		8038	#define USB_COUNT0_RX_BLSIZE_Pos (15U)
		8039	#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /!< 0x00008000 /
		8040	#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /!< BLock SIZE /
		8041
		8042	/*************** Bit definition for USB_COUNT1_RX register **************/
		8043	#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
		8044	#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /!< 0x000003FF /
		8045	#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /!< Reception Byte Count /
		8046
		8047	#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
		8048	#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8049	#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8050	#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8051	#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8052	#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8053	#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8054	#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8055
		8056	#define USB_COUNT1_RX_BLSIZE_Pos (15U)
		8057	#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /!< 0x00008000 /
		8058	#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /!< BLock SIZE /
		8059
		8060	/*************** Bit definition for USB_COUNT2_RX register **************/
		8061	#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
		8062	#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /!< 0x000003FF /
		8063	#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /!< Reception Byte Count /
		8064
		8065	#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
		8066	#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8067	#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8068	#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8069	#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8070	#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8071	#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8072	#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8073
		8074	#define USB_COUNT2_RX_BLSIZE_Pos (15U)
		8075	#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /!< 0x00008000 /
		8076	#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /!< BLock SIZE /
		8077
		8078	/*************** Bit definition for USB_COUNT3_RX register **************/
		8079	#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
		8080	#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /!< 0x000003FF /
		8081	#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /!< Reception Byte Count /
		8082
		8083	#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
		8084	#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8085	#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8086	#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8087	#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8088	#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8089	#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8090	#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8091
		8092	#define USB_COUNT3_RX_BLSIZE_Pos (15U)
		8093	#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /!< 0x00008000 /
		8094	#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /!< BLock SIZE /
		8095
		8096	/*************** Bit definition for USB_COUNT4_RX register **************/
		8097	#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
		8098	#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /!< 0x000003FF /
		8099	#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /!< Reception Byte Count /
		8100
		8101	#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
		8102	#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8103	#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8104	#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8105	#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8106	#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8107	#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8108	#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8109
		8110	#define USB_COUNT4_RX_BLSIZE_Pos (15U)
		8111	#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /!< 0x00008000 /
		8112	#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /!< BLock SIZE /
		8113
		8114	/*************** Bit definition for USB_COUNT5_RX register **************/
		8115	#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
		8116	#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /!< 0x000003FF /
		8117	#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /!< Reception Byte Count /
		8118
		8119	#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
		8120	#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8121	#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8122	#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8123	#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8124	#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8125	#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8126	#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8127
		8128	#define USB_COUNT5_RX_BLSIZE_Pos (15U)
		8129	#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /!< 0x00008000 /
		8130	#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /!< BLock SIZE /
		8131
		8132	/*************** Bit definition for USB_COUNT6_RX register **************/
		8133	#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
		8134	#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /!< 0x000003FF /
		8135	#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /!< Reception Byte Count /
		8136
		8137	#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
		8138	#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8139	#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8140	#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8141	#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8142	#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8143	#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8144	#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8145
		8146	#define USB_COUNT6_RX_BLSIZE_Pos (15U)
		8147	#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /!< 0x00008000 /
		8148	#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /!< BLock SIZE /
		8149
		8150	/*************** Bit definition for USB_COUNT7_RX register **************/
		8151	#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
		8152	#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /!< 0x000003FF /
		8153	#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /!< Reception Byte Count /
		8154
		8155	#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
		8156	#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00007C00 /
		8157	#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /!< NUM_BLOCK[4:0] bits (Number of blocks) /
		8158	#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00000400 /
		8159	#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00000800 /
		8160	#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00001000 /
		8161	#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00002000 /
		8162	#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /!< 0x00004000 /
		8163
		8164	#define USB_COUNT7_RX_BLSIZE_Pos (15U)
		8165	#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /!< 0x00008000 /
		8166	#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /!< BLock SIZE /
		8167
		8168	/----------------------------------------------------------------------------/
		8169
		8170	/************** Bit definition for USB_COUNT0_RX_0 register *************/
		8171	#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8172
		8173	#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8174	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8175	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8176	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8177	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8178	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8179
		8180	#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8181
		8182	/************** Bit definition for USB_COUNT0_RX_1 register *************/
		8183	#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8184
		8185	#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8186	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 1 /
		8187	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8188	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8189	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8190	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8191
		8192	#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8193
		8194	/************** Bit definition for USB_COUNT1_RX_0 register *************/
		8195	#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8196
		8197	#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8198	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8199	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8200	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8201	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8202	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8203
		8204	#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8205
		8206	/************** Bit definition for USB_COUNT1_RX_1 register *************/
		8207	#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8208
		8209	#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8210	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8211	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8212	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8213	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8214	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8215
		8216	#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8217
		8218	/************** Bit definition for USB_COUNT2_RX_0 register *************/
		8219	#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8220
		8221	#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8222	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8223	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8224	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8225	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8226	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8227
		8228	#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8229
		8230	/************** Bit definition for USB_COUNT2_RX_1 register *************/
		8231	#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8232
		8233	#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8234	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8235	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8236	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8237	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8238	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8239
		8240	#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8241
		8242	/************** Bit definition for USB_COUNT3_RX_0 register *************/
		8243	#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8244
		8245	#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8246	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8247	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8248	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8249	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8250	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8251
		8252	#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8253
		8254	/************** Bit definition for USB_COUNT3_RX_1 register *************/
		8255	#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8256
		8257	#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8258	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8259	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8260	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8261	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8262	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8263
		8264	#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8265
		8266	/************** Bit definition for USB_COUNT4_RX_0 register *************/
		8267	#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8268
		8269	#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8270	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8271	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8272	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8273	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8274	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8275
		8276	#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8277
		8278	/************** Bit definition for USB_COUNT4_RX_1 register *************/
		8279	#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8280
		8281	#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8282	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8283	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8284	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8285	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8286	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8287
		8288	#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8289
		8290	/************** Bit definition for USB_COUNT5_RX_0 register *************/
		8291	#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8292
		8293	#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8294	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8295	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8296	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8297	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8298	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8299
		8300	#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8301
		8302	/************** Bit definition for USB_COUNT5_RX_1 register *************/
		8303	#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8304
		8305	#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8306	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8307	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8308	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8309	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8310	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8311
		8312	#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8313
		8314	/************* Bit definition for USB_COUNT6_RX_0 register *************/
		8315	#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8316
		8317	#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8318	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8319	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8320	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8321	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8322	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8323
		8324	#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8325
		8326	/************** Bit definition for USB_COUNT6_RX_1 register *************/
		8327	#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8328
		8329	#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8330	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8331	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8332	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8333	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8334	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8335
		8336	#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8337
		8338	/************* Bit definition for USB_COUNT7_RX_0 register **************/
		8339	#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /!< Reception Byte Count (low) /
		8340
		8341	#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
		8342	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /!< Bit 0 /
		8343	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /!< Bit 1 /
		8344	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /!< Bit 2 /
		8345	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /!< Bit 3 /
		8346	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /!< Bit 4 /
		8347
		8348	#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /!< BLock SIZE (low) /
		8349
		8350	/************* Bit definition for USB_COUNT7_RX_1 register **************/
		8351	#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /!< Reception Byte Count (high) /
		8352
		8353	#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
		8354	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /!< Bit 0 /
		8355	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /!< Bit 1 /
		8356	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /!< Bit 2 /
		8357	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /!< Bit 3 /
		8358	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /!< Bit 4 /
		8359
		8360	#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /!< BLock SIZE (high) /
		8361
		8362	/******************************************************************************/
		8363	/* */
		8364	/* Window WATCHDOG (WWDG) */
		8365	/* */
		8366	/******************************************************************************/
		8367
		8368	/***************** Bit definition for WWDG_CR register ******************/
		8369	#define WWDG_CR_T_Pos (0U)
		8370	#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /!< 0x0000007F /
		8371	#define WWDG_CR_T WWDG_CR_T_Msk /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
		8372	#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /!< 0x00000001 /
		8373	#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /!< 0x00000002 /
		8374	#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /!< 0x00000004 /
		8375	#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /!< 0x00000008 /
		8376	#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /!< 0x00000010 /
		8377	#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /!< 0x00000020 /
		8378	#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /!< 0x00000040 /
		8379
		8380	/* Legacy defines */
		8381	#define WWDG_CR_T0 WWDG_CR_T_0
		8382	#define WWDG_CR_T1 WWDG_CR_T_1
		8383	#define WWDG_CR_T2 WWDG_CR_T_2
		8384	#define WWDG_CR_T3 WWDG_CR_T_3
		8385	#define WWDG_CR_T4 WWDG_CR_T_4
		8386	#define WWDG_CR_T5 WWDG_CR_T_5
		8387	#define WWDG_CR_T6 WWDG_CR_T_6
		8388
		8389	#define WWDG_CR_WDGA_Pos (7U)
		8390	#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /!< 0x00000080 /
		8391	#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /!< Activation bit /
		8392
		8393	/***************** Bit definition for WWDG_CFR register *****************/
		8394	#define WWDG_CFR_W_Pos (0U)
		8395	#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /!< 0x0000007F /
		8396	#define WWDG_CFR_W WWDG_CFR_W_Msk /!< W[6:0] bits (7-bit window value) /
		8397	#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /!< 0x00000001 /
		8398	#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /!< 0x00000002 /
		8399	#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /!< 0x00000004 /
		8400	#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /!< 0x00000008 /
		8401	#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /!< 0x00000010 /
		8402	#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /!< 0x00000020 /
		8403	#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /!< 0x00000040 /
		8404
		8405	/* Legacy defines */
		8406	#define WWDG_CFR_W0 WWDG_CFR_W_0
		8407	#define WWDG_CFR_W1 WWDG_CFR_W_1
		8408	#define WWDG_CFR_W2 WWDG_CFR_W_2
		8409	#define WWDG_CFR_W3 WWDG_CFR_W_3
		8410	#define WWDG_CFR_W4 WWDG_CFR_W_4
		8411	#define WWDG_CFR_W5 WWDG_CFR_W_5
		8412	#define WWDG_CFR_W6 WWDG_CFR_W_6
		8413
		8414	#define WWDG_CFR_WDGTB_Pos (7U)
		8415	#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /!< 0x00000180 /
		8416	#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /!< WDGTB[1:0] bits (Timer Base) /
		8417	#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /!< 0x00000080 /
		8418	#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /!< 0x00000100 /
		8419
		8420	/* Legacy defines */
		8421	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
		8422	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
		8423
		8424	#define WWDG_CFR_EWI_Pos (9U)
		8425	#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /!< 0x00000200 /
		8426	#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /!< Early Wakeup Interrupt /
		8427
		8428	/***************** Bit definition for WWDG_SR register ******************/
		8429	#define WWDG_SR_EWIF_Pos (0U)
		8430	#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /!< 0x00000001 /
		8431	#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /!< Early Wakeup Interrupt Flag /
		8432
		8433	/******************************************************************************/
		8434	/* */
		8435	/* SystemTick (SysTick) */
		8436	/* */
		8437	/******************************************************************************/
		8438
		8439	/*************** Bit definition for SysTick_CTRL register ***************/
		8440	#define SysTick_CTRL_ENABLE (0x00000001U) /!< Counter enable /
		8441	#define SysTick_CTRL_TICKINT (0x00000002U) /!< Counting down to 0 pends the SysTick handler /
		8442	#define SysTick_CTRL_CLKSOURCE (0x00000004U) /!< Clock source /
		8443	#define SysTick_CTRL_COUNTFLAG (0x00010000U) /!< Count Flag /
		8444
		8445	/*************** Bit definition for SysTick_LOAD register ***************/
		8446	#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
		8447
		8448	/*************** Bit definition for SysTick_VAL register ****************/
		8449	#define SysTick_VAL_CURRENT (0x00FFFFFFU) /!< Current value at the time the register is accessed /
		8450
		8451	/*************** Bit definition for SysTick_CALIB register **************/
		8452	#define SysTick_CALIB_TENMS (0x00FFFFFFU) /!< Reload value to use for 10ms timing /
		8453	#define SysTick_CALIB_SKEW (0x40000000U) /!< Calibration value is not exactly 10 ms /
		8454	#define SysTick_CALIB_NOREF (0x80000000U) /!< The reference clock is not provided /
		8455
		8456	/******************************************************************************/
		8457	/* */
		8458	/* Nested Vectored Interrupt Controller (NVIC) */
		8459	/* */
		8460	/******************************************************************************/
		8461
		8462	/**************** Bit definition for NVIC_ISER register *****************/
		8463	#define NVIC_ISER_SETENA_Pos (0U)
		8464	#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /!< 0xFFFFFFFF /
		8465	#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /!< Interrupt set enable bits /
		8466	#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /!< 0x00000001 /
		8467	#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /!< 0x00000002 /
		8468	#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /!< 0x00000004 /
		8469	#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /!< 0x00000008 /
		8470	#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /!< 0x00000010 /
		8471	#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /!< 0x00000020 /
		8472	#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /!< 0x00000040 /
		8473	#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /!< 0x00000080 /
		8474	#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /!< 0x00000100 /
		8475	#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /!< 0x00000200 /
		8476	#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /!< 0x00000400 /
		8477	#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /!< 0x00000800 /
		8478	#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /!< 0x00001000 /
		8479	#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /!< 0x00002000 /
		8480	#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /!< 0x00004000 /
		8481	#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /!< 0x00008000 /
		8482	#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /!< 0x00010000 /
		8483	#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /!< 0x00020000 /
		8484	#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /!< 0x00040000 /
		8485	#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /!< 0x00080000 /
		8486	#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /!< 0x00100000 /
		8487	#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /!< 0x00200000 /
		8488	#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /!< 0x00400000 /
		8489	#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /!< 0x00800000 /
		8490	#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /!< 0x01000000 /
		8491	#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /!< 0x02000000 /
		8492	#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /!< 0x04000000 /
		8493	#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /!< 0x08000000 /
		8494	#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /!< 0x10000000 /
		8495	#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /!< 0x20000000 /
		8496	#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /!< 0x40000000 /
		8497	#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /!< 0x80000000 /
		8498
		8499	/**************** Bit definition for NVIC_ICER register *****************/
		8500	#define NVIC_ICER_CLRENA_Pos (0U)
		8501	#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /!< 0xFFFFFFFF /
		8502	#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /!< Interrupt clear-enable bits /
		8503	#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /!< 0x00000001 /
		8504	#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /!< 0x00000002 /
		8505	#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /!< 0x00000004 /
		8506	#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /!< 0x00000008 /
		8507	#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /!< 0x00000010 /
		8508	#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /!< 0x00000020 /
		8509	#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /!< 0x00000040 /
		8510	#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /!< 0x00000080 /
		8511	#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /!< 0x00000100 /
		8512	#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /!< 0x00000200 /
		8513	#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /!< 0x00000400 /
		8514	#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /!< 0x00000800 /
		8515	#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /!< 0x00001000 /
		8516	#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /!< 0x00002000 /
		8517	#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /!< 0x00004000 /
		8518	#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /!< 0x00008000 /
		8519	#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /!< 0x00010000 /
		8520	#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /!< 0x00020000 /
		8521	#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /!< 0x00040000 /
		8522	#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /!< 0x00080000 /
		8523	#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /!< 0x00100000 /
		8524	#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /!< 0x00200000 /
		8525	#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /!< 0x00400000 /
		8526	#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /!< 0x00800000 /
		8527	#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /!< 0x01000000 /
		8528	#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /!< 0x02000000 /
		8529	#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /!< 0x04000000 /
		8530	#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /!< 0x08000000 /
		8531	#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /!< 0x10000000 /
		8532	#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /!< 0x20000000 /
		8533	#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /!< 0x40000000 /
		8534	#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /!< 0x80000000 /
		8535
		8536	/**************** Bit definition for NVIC_ISPR register *****************/
		8537	#define NVIC_ISPR_SETPEND_Pos (0U)
		8538	#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /!< 0xFFFFFFFF /
		8539	#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /!< Interrupt set-pending bits /
		8540	#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000001 /
		8541	#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000002 /
		8542	#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000004 /
		8543	#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000008 /
		8544	#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000010 /
		8545	#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000020 /
		8546	#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000040 /
		8547	#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000080 /
		8548	#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000100 /
		8549	#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000200 /
		8550	#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000400 /
		8551	#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /!< 0x00000800 /
		8552	#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00001000 /
		8553	#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00002000 /
		8554	#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00004000 /
		8555	#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00008000 /
		8556	#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00010000 /
		8557	#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00020000 /
		8558	#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00040000 /
		8559	#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00080000 /
		8560	#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00100000 /
		8561	#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00200000 /
		8562	#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00400000 /
		8563	#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /!< 0x00800000 /
		8564	#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x01000000 /
		8565	#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x02000000 /
		8566	#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x04000000 /
		8567	#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x08000000 /
		8568	#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x10000000 /
		8569	#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x20000000 /
		8570	#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x40000000 /
		8571	#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /!< 0x80000000 /
		8572
		8573	/**************** Bit definition for NVIC_ICPR register *****************/
		8574	#define NVIC_ICPR_CLRPEND_Pos (0U)
		8575	#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /!< 0xFFFFFFFF /
		8576	#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /!< Interrupt clear-pending bits /
		8577	#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000001 /
		8578	#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000002 /
		8579	#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000004 /
		8580	#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000008 /
		8581	#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000010 /
		8582	#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000020 /
		8583	#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000040 /
		8584	#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000080 /
		8585	#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000100 /
		8586	#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000200 /
		8587	#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000400 /
		8588	#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00000800 /
		8589	#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00001000 /
		8590	#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00002000 /
		8591	#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00004000 /
		8592	#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00008000 /
		8593	#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00010000 /
		8594	#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00020000 /
		8595	#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00040000 /
		8596	#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00080000 /
		8597	#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00100000 /
		8598	#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00200000 /
		8599	#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00400000 /
		8600	#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x00800000 /
		8601	#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x01000000 /
		8602	#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x02000000 /
		8603	#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x04000000 /
		8604	#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x08000000 /
		8605	#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x10000000 /
		8606	#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x20000000 /
		8607	#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x40000000 /
		8608	#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /!< 0x80000000 /
		8609
		8610	/**************** Bit definition for NVIC_IABR register *****************/
		8611	#define NVIC_IABR_ACTIVE_Pos (0U)
		8612	#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /!< 0xFFFFFFFF /
		8613	#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /!< Interrupt active flags /
		8614	#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000001 /
		8615	#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000002 /
		8616	#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000004 /
		8617	#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000008 /
		8618	#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000010 /
		8619	#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000020 /
		8620	#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000040 /
		8621	#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000080 /
		8622	#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000100 /
		8623	#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000200 /
		8624	#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000400 /
		8625	#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /!< 0x00000800 /
		8626	#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00001000 /
		8627	#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00002000 /
		8628	#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00004000 /
		8629	#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00008000 /
		8630	#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00010000 /
		8631	#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00020000 /
		8632	#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00040000 /
		8633	#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00080000 /
		8634	#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00100000 /
		8635	#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00200000 /
		8636	#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00400000 /
		8637	#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /!< 0x00800000 /
		8638	#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x01000000 /
		8639	#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x02000000 /
		8640	#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x04000000 /
		8641	#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x08000000 /
		8642	#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x10000000 /
		8643	#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x20000000 /
		8644	#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x40000000 /
		8645	#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /!< 0x80000000 /
		8646
		8647	/**************** Bit definition for NVIC_PRI0 register *****************/
		8648	#define NVIC_IPR0_PRI_0 (0x000000FFU) /!< Priority of interrupt 0 /
		8649	#define NVIC_IPR0_PRI_1 (0x0000FF00U) /!< Priority of interrupt 1 /
		8650	#define NVIC_IPR0_PRI_2 (0x00FF0000U) /!< Priority of interrupt 2 /
		8651	#define NVIC_IPR0_PRI_3 (0xFF000000U) /!< Priority of interrupt 3 /
		8652
		8653	/**************** Bit definition for NVIC_PRI1 register *****************/
		8654	#define NVIC_IPR1_PRI_4 (0x000000FFU) /!< Priority of interrupt 4 /
		8655	#define NVIC_IPR1_PRI_5 (0x0000FF00U) /!< Priority of interrupt 5 /
		8656	#define NVIC_IPR1_PRI_6 (0x00FF0000U) /!< Priority of interrupt 6 /
		8657	#define NVIC_IPR1_PRI_7 (0xFF000000U) /!< Priority of interrupt 7 /
		8658
		8659	/**************** Bit definition for NVIC_PRI2 register *****************/
		8660	#define NVIC_IPR2_PRI_8 (0x000000FFU) /!< Priority of interrupt 8 /
		8661	#define NVIC_IPR2_PRI_9 (0x0000FF00U) /!< Priority of interrupt 9 /
		8662	#define NVIC_IPR2_PRI_10 (0x00FF0000U) /!< Priority of interrupt 10 /
		8663	#define NVIC_IPR2_PRI_11 (0xFF000000U) /!< Priority of interrupt 11 /
		8664
		8665	/**************** Bit definition for NVIC_PRI3 register *****************/
		8666	#define NVIC_IPR3_PRI_12 (0x000000FFU) /!< Priority of interrupt 12 /
		8667	#define NVIC_IPR3_PRI_13 (0x0000FF00U) /!< Priority of interrupt 13 /
		8668	#define NVIC_IPR3_PRI_14 (0x00FF0000U) /!< Priority of interrupt 14 /
		8669	#define NVIC_IPR3_PRI_15 (0xFF000000U) /!< Priority of interrupt 15 /
		8670
		8671	/**************** Bit definition for NVIC_PRI4 register *****************/
		8672	#define NVIC_IPR4_PRI_16 (0x000000FFU) /!< Priority of interrupt 16 /
		8673	#define NVIC_IPR4_PRI_17 (0x0000FF00U) /!< Priority of interrupt 17 /
		8674	#define NVIC_IPR4_PRI_18 (0x00FF0000U) /!< Priority of interrupt 18 /
		8675	#define NVIC_IPR4_PRI_19 (0xFF000000U) /!< Priority of interrupt 19 /
		8676
		8677	/**************** Bit definition for NVIC_PRI5 register *****************/
		8678	#define NVIC_IPR5_PRI_20 (0x000000FFU) /!< Priority of interrupt 20 /
		8679	#define NVIC_IPR5_PRI_21 (0x0000FF00U) /!< Priority of interrupt 21 /
		8680	#define NVIC_IPR5_PRI_22 (0x00FF0000U) /!< Priority of interrupt 22 /
		8681	#define NVIC_IPR5_PRI_23 (0xFF000000U) /!< Priority of interrupt 23 /
		8682
		8683	/**************** Bit definition for NVIC_PRI6 register *****************/
		8684	#define NVIC_IPR6_PRI_24 (0x000000FFU) /!< Priority of interrupt 24 /
		8685	#define NVIC_IPR6_PRI_25 (0x0000FF00U) /!< Priority of interrupt 25 /
		8686	#define NVIC_IPR6_PRI_26 (0x00FF0000U) /!< Priority of interrupt 26 /
		8687	#define NVIC_IPR6_PRI_27 (0xFF000000U) /!< Priority of interrupt 27 /
		8688
		8689	/**************** Bit definition for NVIC_PRI7 register *****************/
		8690	#define NVIC_IPR7_PRI_28 (0x000000FFU) /!< Priority of interrupt 28 /
		8691	#define NVIC_IPR7_PRI_29 (0x0000FF00U) /!< Priority of interrupt 29 /
		8692	#define NVIC_IPR7_PRI_30 (0x00FF0000U) /!< Priority of interrupt 30 /
		8693	#define NVIC_IPR7_PRI_31 (0xFF000000U) /!< Priority of interrupt 31 /
		8694
		8695	/**************** Bit definition for SCB_CPUID register *****************/
		8696	#define SCB_CPUID_REVISION (0x0000000FU) /!< Implementation defined revision number /
		8697	#define SCB_CPUID_PARTNO (0x0000FFF0U) /!< Number of processor within serie /
		8698	#define SCB_CPUID_Constant (0x000F0000U) /!< Reads as 0x0F /
		8699	#define SCB_CPUID_VARIANT (0x00F00000U) /!< Implementation defined variant number /
		8700	#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /!< Implementer code. ARM is 0x41 /
		8701
		8702	/***************** Bit definition for SCB_ICSR register *****************/
		8703	#define SCB_ICSR_VECTACTIVE (0x000001FFU) /!< Active ISR number field /
		8704	#define SCB_ICSR_RETTOBASE (0x00000800U) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
		8705	#define SCB_ICSR_VECTPENDING (0x003FF000U) /!< Pending ISR number field /
		8706	#define SCB_ICSR_ISRPENDING (0x00400000U) /!< Interrupt pending flag /
		8707	#define SCB_ICSR_ISRPREEMPT (0x00800000U) /!< It indicates that a pending interrupt becomes active in the next running cycle /
		8708	#define SCB_ICSR_PENDSTCLR (0x02000000U) /!< Clear pending SysTick bit /
		8709	#define SCB_ICSR_PENDSTSET (0x04000000U) /!< Set pending SysTick bit /
		8710	#define SCB_ICSR_PENDSVCLR (0x08000000U) /!< Clear pending pendSV bit /
		8711	#define SCB_ICSR_PENDSVSET (0x10000000U) /!< Set pending pendSV bit /
		8712	#define SCB_ICSR_NMIPENDSET (0x80000000U) /!< Set pending NMI bit /
		8713
		8714	/***************** Bit definition for SCB_VTOR register *****************/
		8715	#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /!< Vector table base offset field /
		8716	#define SCB_VTOR_TBLBASE (0x20000000U) /!< Table base in code(0) or RAM(1) /
		8717
		8718	/!<************** Bit definition for SCB_AIRCR register *****************/
		8719	#define SCB_AIRCR_VECTRESET (0x00000001U) /!< System Reset bit /
		8720	#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /!< Clear active vector bit /
		8721	#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /!< Requests chip control logic to generate a reset /
		8722
		8723	#define SCB_AIRCR_PRIGROUP (0x00000700U) /!< PRIGROUP[2:0] bits (Priority group) /
		8724	#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /!< Bit 0 /
		8725	#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /!< Bit 1 /
		8726	#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /!< Bit 2 /
		8727
		8728	/* prority group configuration */
		8729	#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
		8730	#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
		8731	#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
		8732	#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
		8733	#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
		8734	#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
		8735	#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
		8736	#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
		8737
		8738	#define SCB_AIRCR_ENDIANESS (0x00008000U) /!< Data endianness bit /
		8739	#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
		8740
		8741	/***************** Bit definition for SCB_SCR register ******************/
		8742	#define SCB_SCR_SLEEPONEXIT (0x00000002U) /!< Sleep on exit bit /
		8743	#define SCB_SCR_SLEEPDEEP (0x00000004U) /!< Sleep deep bit /
		8744	#define SCB_SCR_SEVONPEND (0x00000010U) /!< Wake up from WFE /
		8745
		8746	/****************** Bit definition for SCB_CCR register *****************/
		8747	#define SCB_CCR_NONBASETHRDENA (0x00000001U) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
		8748	#define SCB_CCR_USERSETMPEND (0x00000002U) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
		8749	#define SCB_CCR_UNALIGN_TRP (0x00000008U) /!< Trap for unaligned access /
		8750	#define SCB_CCR_DIV_0_TRP (0x00000010U) /!< Trap on Divide by 0 /
		8751	#define SCB_CCR_BFHFNMIGN (0x00000100U) /!< Handlers running at priority -1 and -2 /
		8752	#define SCB_CCR_STKALIGN (0x00000200U) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
		8753
		8754	/***************** Bit definition for SCB_SHPR register ******************/
		8755	#define SCB_SHPR_PRI_N_Pos (0U)
		8756	#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /!< 0x000000FF /
		8757	#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
		8758	#define SCB_SHPR_PRI_N1_Pos (8U)
		8759	#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /!< 0x0000FF00 /
		8760	#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
		8761	#define SCB_SHPR_PRI_N2_Pos (16U)
		8762	#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /!< 0x00FF0000 /
		8763	#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
		8764	#define SCB_SHPR_PRI_N3_Pos (24U)
		8765	#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /!< 0xFF000000 /
		8766	#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
		8767
		8768	/**************** Bit definition for SCB_SHCSR register *****************/
		8769	#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /!< MemManage is active /
		8770	#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /!< BusFault is active /
		8771	#define SCB_SHCSR_USGFAULTACT (0x00000008U) /!< UsageFault is active /
		8772	#define SCB_SHCSR_SVCALLACT (0x00000080U) /!< SVCall is active /
		8773	#define SCB_SHCSR_MONITORACT (0x00000100U) /!< Monitor is active /
		8774	#define SCB_SHCSR_PENDSVACT (0x00000400U) /!< PendSV is active /
		8775	#define SCB_SHCSR_SYSTICKACT (0x00000800U) /!< SysTick is active /
		8776	#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /!< Usage Fault is pended /
		8777	#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /!< MemManage is pended /
		8778	#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /!< Bus Fault is pended /
		8779	#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /!< SVCall is pended /
		8780	#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /!< MemManage enable /
		8781	#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /!< Bus Fault enable /
		8782	#define SCB_SHCSR_USGFAULTENA (0x00040000U) /!< UsageFault enable /
		8783
		8784	/***************** Bit definition for SCB_CFSR register *****************/
		8785	/!< MFSR /
		8786	#define SCB_CFSR_IACCVIOL_Pos (0U)
		8787	#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /!< 0x00000001 /
		8788	#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /!< Instruction access violation /
		8789	#define SCB_CFSR_DACCVIOL_Pos (1U)
		8790	#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /!< 0x00000002 /
		8791	#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /!< Data access violation /
		8792	#define SCB_CFSR_MUNSTKERR_Pos (3U)
		8793	#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /!< 0x00000008 /
		8794	#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /!< Unstacking error /
		8795	#define SCB_CFSR_MSTKERR_Pos (4U)
		8796	#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /!< 0x00000010 /
		8797	#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /!< Stacking error /
		8798	#define SCB_CFSR_MMARVALID_Pos (7U)
		8799	#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /!< 0x00000080 /
		8800	#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /!< Memory Manage Address Register address valid flag /
		8801	/!< BFSR /
		8802	#define SCB_CFSR_IBUSERR_Pos (8U)
		8803	#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /!< 0x00000100 /
		8804	#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /!< Instruction bus error flag /
		8805	#define SCB_CFSR_PRECISERR_Pos (9U)
		8806	#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /!< 0x00000200 /
		8807	#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /!< Precise data bus error /
		8808	#define SCB_CFSR_IMPRECISERR_Pos (10U)
		8809	#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /!< 0x00000400 /
		8810	#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /!< Imprecise data bus error /
		8811	#define SCB_CFSR_UNSTKERR_Pos (11U)
		8812	#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /!< 0x00000800 /
		8813	#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /!< Unstacking error /
		8814	#define SCB_CFSR_STKERR_Pos (12U)
		8815	#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /!< 0x00001000 /
		8816	#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /!< Stacking error /
		8817	#define SCB_CFSR_BFARVALID_Pos (15U)
		8818	#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /!< 0x00008000 /
		8819	#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /!< Bus Fault Address Register address valid flag /
		8820	/!< UFSR /
		8821	#define SCB_CFSR_UNDEFINSTR_Pos (16U)
		8822	#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /!< 0x00010000 /
		8823	#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /!< The processor attempt to excecute an undefined instruction /
		8824	#define SCB_CFSR_INVSTATE_Pos (17U)
		8825	#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /!< 0x00020000 /
		8826	#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /!< Invalid combination of EPSR and instruction /
		8827	#define SCB_CFSR_INVPC_Pos (18U)
		8828	#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /!< 0x00040000 /
		8829	#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /!< Attempt to load EXC_RETURN into pc illegally /
		8830	#define SCB_CFSR_NOCP_Pos (19U)
		8831	#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /!< 0x00080000 /
		8832	#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /!< Attempt to use a coprocessor instruction /
		8833	#define SCB_CFSR_UNALIGNED_Pos (24U)
		8834	#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /!< 0x01000000 /
		8835	#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /!< Fault occurs when there is an attempt to make an unaligned memory access /
		8836	#define SCB_CFSR_DIVBYZERO_Pos (25U)
		8837	#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /!< 0x02000000 /
		8838	#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
		8839
		8840	/***************** Bit definition for SCB_HFSR register *****************/
		8841	#define SCB_HFSR_VECTTBL (0x00000002U) /!< Fault occures because of vector table read on exception processing /
		8842	#define SCB_HFSR_FORCED (0x40000000U) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
		8843	#define SCB_HFSR_DEBUGEVT (0x80000000U) /!< Fault related to debug /
		8844
		8845	/***************** Bit definition for SCB_DFSR register *****************/
		8846	#define SCB_DFSR_HALTED (0x00000001U) /!< Halt request flag /
		8847	#define SCB_DFSR_BKPT (0x00000002U) /!< BKPT flag /
		8848	#define SCB_DFSR_DWTTRAP (0x00000004U) /!< Data Watchpoint and Trace (DWT) flag /
		8849	#define SCB_DFSR_VCATCH (0x00000008U) /!< Vector catch flag /
		8850	#define SCB_DFSR_EXTERNAL (0x00000010U) /!< External debug request flag /
		8851
		8852	/***************** Bit definition for SCB_MMFAR register ****************/
		8853	#define SCB_MMFAR_ADDRESS_Pos (0U)
		8854	#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /!< 0xFFFFFFFF /
		8855	#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /!< Mem Manage fault address field /
		8856
		8857	/***************** Bit definition for SCB_BFAR register *****************/
		8858	#define SCB_BFAR_ADDRESS_Pos (0U)
		8859	#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /!< 0xFFFFFFFF /
		8860	#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /!< Bus fault address field /
		8861
		8862	/***************** Bit definition for SCB_afsr register *****************/
		8863	#define SCB_AFSR_IMPDEF_Pos (0U)
		8864	#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /!< 0xFFFFFFFF /
		8865	#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /!< Implementation defined /
		8866	/**
		8867	* @}
		8868	*/
		8869
		8870	/**
		8871	* @}
		8872	*/
		8873	/** @addtogroup Exported_macro
		8874	* @{
		8875	*/
		8876
		8877	/**************************** ADC Instances *******************************/
		8878	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
		8879
		8880	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
		8881
		8882	/****************************** COMP Instances ****************************/
		8883	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
		8884	((INSTANCE) == COMP2))
		8885
		8886	#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
		8887
		8888	/**************************** CRC Instances *******************************/
		8889	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
		8890
		8891	/**************************** DAC Instances *******************************/
		8892	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
		8893
		8894	/**************************** DMA Instances *******************************/
		8895	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
		8896	((INSTANCE) == DMA1_Channel2) \|\| \
		8897	((INSTANCE) == DMA1_Channel3) \|\| \
		8898	((INSTANCE) == DMA1_Channel4) \|\| \
		8899	((INSTANCE) == DMA1_Channel5) \|\| \
		8900	((INSTANCE) == DMA1_Channel6) \|\| \
		8901	((INSTANCE) == DMA1_Channel7) \|\| \
		8902	((INSTANCE) == DMA2_Channel1) \|\| \
		8903	((INSTANCE) == DMA2_Channel2) \|\| \
		8904	((INSTANCE) == DMA2_Channel3) \|\| \
		8905	((INSTANCE) == DMA2_Channel4) \|\| \
		8906	((INSTANCE) == DMA2_Channel5))
		8907
		8908	/***************************** GPIO Instances *****************************/
		8909	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
		8910	((INSTANCE) == GPIOB) \|\| \
		8911	((INSTANCE) == GPIOC) \|\| \
		8912	((INSTANCE) == GPIOD) \|\| \
		8913	((INSTANCE) == GPIOE) \|\| \
		8914	((INSTANCE) == GPIOF) \|\| \
		8915	((INSTANCE) == GPIOG) \|\| \
		8916	((INSTANCE) == GPIOH))
		8917
		8918	/************************** GPIO Alternate Function Instances *************/
		8919	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		8920
		8921	/************************** GPIO Lock Instances ***************************/
		8922	/* On L1, all GPIO Bank support the Lock mechanism */
		8923	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
		8924
		8925	/****************************** I2C Instances *****************************/
		8926	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
		8927	((INSTANCE) == I2C2))
		8928
		8929	/**************************** SMBUS Instances *****************************/
		8930	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
		8931
		8932	/****************************** I2S Instances *****************************/
		8933	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) \|\| \
		8934	((INSTANCE) == SPI3))
		8935	/**************************** IWDG Instances ******************************/
		8936	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
		8937
		8938	/**************************** OPAMP Instances *****************************/
		8939	#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) \|\| \
		8940	((INSTANCE) == OPAMP2))
		8941
		8942	#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
		8943
		8944	/**************************** RTC Instances *******************************/
		8945	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
		8946
		8947	/****************************** SPI Instances *****************************/
		8948	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
		8949	((INSTANCE) == SPI2) \|\| \
		8950	((INSTANCE) == SPI3))
		8951
		8952	/**************************** TIM Instances *******************************/
		8953	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8954	((INSTANCE) == TIM3) \|\| \
		8955	((INSTANCE) == TIM4) \|\| \
		8956	((INSTANCE) == TIM5) \|\| \
		8957	((INSTANCE) == TIM6) \|\| \
		8958	((INSTANCE) == TIM7) \|\| \
		8959	((INSTANCE) == TIM9) \|\| \
		8960	((INSTANCE) == TIM10) \|\| \
		8961	((INSTANCE) == TIM11))
		8962
		8963	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8964	((INSTANCE) == TIM3) \|\| \
		8965	((INSTANCE) == TIM4) \|\| \
		8966	((INSTANCE) == TIM5) \|\| \
		8967	((INSTANCE) == TIM9) \|\| \
		8968	((INSTANCE) == TIM10) \|\| \
		8969	((INSTANCE) == TIM11))
		8970
		8971	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8972	((INSTANCE) == TIM3) \|\| \
		8973	((INSTANCE) == TIM4) \|\| \
		8974	((INSTANCE) == TIM5) \|\| \
		8975	((INSTANCE) == TIM9))
		8976
		8977	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8978	((INSTANCE) == TIM3) \|\| \
		8979	((INSTANCE) == TIM4) \|\| \
		8980	((INSTANCE) == TIM5))
		8981
		8982	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8983	((INSTANCE) == TIM3) \|\| \
		8984	((INSTANCE) == TIM4) \|\| \
		8985	((INSTANCE) == TIM5))
		8986
		8987	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8988	((INSTANCE) == TIM3) \|\| \
		8989	((INSTANCE) == TIM4) \|\| \
		8990	((INSTANCE) == TIM5) \|\| \
		8991	((INSTANCE) == TIM9))
		8992
		8993	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		8994	((INSTANCE) == TIM3) \|\| \
		8995	((INSTANCE) == TIM4) \|\| \
		8996	((INSTANCE) == TIM5) \|\| \
		8997	((INSTANCE) == TIM9) \|\| \
		8998	((INSTANCE) == TIM10) \|\| \
		8999	((INSTANCE) == TIM11))
		9000
		9001	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9002	((INSTANCE) == TIM3) \|\| \
		9003	((INSTANCE) == TIM4) \|\| \
		9004	((INSTANCE) == TIM5) \|\| \
		9005	((INSTANCE) == TIM9))
		9006
		9007	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9008	((INSTANCE) == TIM3) \|\| \
		9009	((INSTANCE) == TIM4) \|\| \
		9010	((INSTANCE) == TIM5) \|\| \
		9011	((INSTANCE) == TIM9))
		9012
		9013	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9014	((INSTANCE) == TIM3) \|\| \
		9015	((INSTANCE) == TIM4))
		9016
		9017	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9018	((INSTANCE) == TIM3) \|\| \
		9019	((INSTANCE) == TIM4) \|\| \
		9020	((INSTANCE) == TIM5))
		9021
		9022	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9023	((INSTANCE) == TIM3) \|\| \
		9024	((INSTANCE) == TIM4) \|\| \
		9025	((INSTANCE) == TIM5))
		9026
		9027
		9028	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9029	((INSTANCE) == TIM3) \|\| \
		9030	((INSTANCE) == TIM4) \|\| \
		9031	((INSTANCE) == TIM5) \|\| \
		9032	((INSTANCE) == TIM6) \|\| \
		9033	((INSTANCE) == TIM7) \|\| \
		9034	((INSTANCE) == TIM9))
		9035
		9036	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9037	((INSTANCE) == TIM3) \|\| \
		9038	((INSTANCE) == TIM4) \|\| \
		9039	((INSTANCE) == TIM5) \|\| \
		9040	((INSTANCE) == TIM9))
		9041
		9042	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
		9043
		9044	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9045	((INSTANCE) == TIM3) \|\| \
		9046	((INSTANCE) == TIM4) \|\| \
		9047	((INSTANCE) == TIM5))
		9048
		9049	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
		9050	((((INSTANCE) == TIM2) && \
		9051	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		9052	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		9053	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		9054	((CHANNEL) == TIM_CHANNEL_4))) \
		9055	\|\| \
		9056	(((INSTANCE) == TIM3) && \
		9057	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		9058	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		9059	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		9060	((CHANNEL) == TIM_CHANNEL_4))) \
		9061	\|\| \
		9062	(((INSTANCE) == TIM4) && \
		9063	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		9064	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		9065	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		9066	((CHANNEL) == TIM_CHANNEL_4))) \
		9067	\|\| \
		9068	(((INSTANCE) == TIM5) && \
		9069	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		9070	((CHANNEL) == TIM_CHANNEL_2) \|\| \
		9071	((CHANNEL) == TIM_CHANNEL_3) \|\| \
		9072	((CHANNEL) == TIM_CHANNEL_4))) \
		9073	\|\| \
		9074	(((INSTANCE) == TIM9) && \
		9075	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
		9076	((CHANNEL) == TIM_CHANNEL_2))) \
		9077	\|\| \
		9078	(((INSTANCE) == TIM10) && \
		9079	(((CHANNEL) == TIM_CHANNEL_1))) \
		9080	\|\| \
		9081	(((INSTANCE) == TIM11) && \
		9082	(((CHANNEL) == TIM_CHANNEL_1))))
		9083
		9084	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9085	((INSTANCE) == TIM3) \|\| \
		9086	((INSTANCE) == TIM4) \|\| \
		9087	((INSTANCE) == TIM5) \|\| \
		9088	((INSTANCE) == TIM9) \|\| \
		9089	((INSTANCE) == TIM10) \|\| \
		9090	((INSTANCE) == TIM11))
		9091
		9092	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9093	((INSTANCE) == TIM3) \|\| \
		9094	((INSTANCE) == TIM4) \|\| \
		9095	((INSTANCE) == TIM5) \|\| \
		9096	((INSTANCE) == TIM6) \|\| \
		9097	((INSTANCE) == TIM7))
		9098
		9099	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9100	((INSTANCE) == TIM3) \|\| \
		9101	((INSTANCE) == TIM4) \|\| \
		9102	((INSTANCE) == TIM5))
		9103
		9104	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9105	((INSTANCE) == TIM3) \|\| \
		9106	((INSTANCE) == TIM4) \|\| \
		9107	((INSTANCE) == TIM5) \|\| \
		9108	((INSTANCE) == TIM9))
		9109
		9110	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9111	((INSTANCE) == TIM3) \|\| \
		9112	((INSTANCE) == TIM4) \|\| \
		9113	((INSTANCE) == TIM5) \|\| \
		9114	((INSTANCE) == TIM9))
		9115
		9116	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
		9117	((INSTANCE) == TIM3) \|\| \
		9118	((INSTANCE) == TIM9) \|\| \
		9119	((INSTANCE) == TIM10) \|\| \
		9120	((INSTANCE) == TIM11))
		9121
		9122	/****************** USART Instances : Synchronous mode ********************/
		9123	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9124	((INSTANCE) == USART2) \|\| \
		9125	((INSTANCE) == USART3))
		9126
		9127	/****************** UART Instances : Asynchronous mode ********************/
		9128	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9129	((INSTANCE) == USART2) \|\| \
		9130	((INSTANCE) == USART3) \|\| \
		9131	((INSTANCE) == UART4) \|\| \
		9132	((INSTANCE) == UART5))
		9133
		9134	/****************** UART Instances : Half-Duplex mode ********************/
		9135	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9136	((INSTANCE) == USART2) \|\| \
		9137	((INSTANCE) == USART3) \|\| \
		9138	((INSTANCE) == UART4) \|\| \
		9139	((INSTANCE) == UART5))
		9140
		9141	/****************** UART Instances : LIN mode ********************/
		9142	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9143	((INSTANCE) == USART2) \|\| \
		9144	((INSTANCE) == USART3) \|\| \
		9145	((INSTANCE) == UART4) \|\| \
		9146	((INSTANCE) == UART5))
		9147
		9148	/**************** UART Instances : Hardware Flow control ******************/
		9149	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9150	((INSTANCE) == USART2) \|\| \
		9151	((INSTANCE) == USART3))
		9152
		9153	/******************* UART Instances : Smard card mode *********************/
		9154	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9155	((INSTANCE) == USART2) \|\| \
		9156	((INSTANCE) == USART3))
		9157
		9158	/********************* UART Instances : IRDA mode *************************/
		9159	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9160	((INSTANCE) == USART2) \|\| \
		9161	((INSTANCE) == USART3) \|\| \
		9162	((INSTANCE) == UART4) \|\| \
		9163	((INSTANCE) == UART5))
		9164
		9165	/*************** UART Instances : Multi-Processor mode ********************/
		9166	#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
		9167	((INSTANCE) == USART2) \|\| \
		9168	((INSTANCE) == USART3) \|\| \
		9169	((INSTANCE) == UART4) \|\| \
		9170	((INSTANCE) == UART5))
		9171
		9172	/**************************** WWDG Instances ******************************/
		9173	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
		9174
		9175	/**************************** USB Instances ******************************/
		9176	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
		9177
		9178	/**
		9179	* @}
		9180	*/
		9181
		9182	/******************************************************************************/
		9183	/* For a painless codes migration between the STM32L1xx device product */
		9184	/* lines, the aliases defined below are put in place to overcome the */
		9185	/* differences in the interrupt handlers and IRQn definitions. */
		9186	/* No need to update developed interrupt code when moving across */
		9187	/* product lines within the same STM32L1 Family */
		9188	/******************************************************************************/
		9189
		9190	/* Aliases for __IRQn */
		9191
		9192	/* Aliases for __IRQHandler */
		9193
		9194	/**
		9195	* @}
		9196	*/
		9197
		9198	/**
		9199	* @}
		9200	*/
		9201
		9202	#ifdef __cplusplus
		9203	}
		9204	#endif /* __cplusplus */
		9205
		9206	#endif /* __STM32L151xDX_H */
		9207
		9208
		9209
		9210	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Subversion Repositories EngineBay2

(root)/trunk/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l151xdx.h – Rev 2