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Rev	Author	Line No.	Line
2	mjames	1	;****************** (C) COPYRIGHT 2015 STMicroelectronics ******************
		2	; File Name : startup_stm32f100xe.s*
		3	; Author : MCD Application Team*
		4	; Version : V4.0.1*
		5	; Date : 31-July-2015*
		6	; Description : STM32F100xE Value Line Devices vector table*
		7	; for EWARM toolchain.*
		8	; This module performs:*
		9	; - Set the initial SP*
		10	; - Set the initial PC == __iar_program_start,*
		11	; - Set the vector table entries with the exceptions ISR*
		12	; address.*
		13	; After Reset the Cortex-M3 processor is in Thread mode,*
		14	; priority is Privileged, and the Stack is set to Main.*
		15	;********************************************************************************
		16	;*
		17	; <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>*
		18	;*
		19	; Redistribution and use in source and binary forms, with or without modification,*
		20	; are permitted provided that the following conditions are met:*
		21	; 1. Redistributions of source code must retain the above copyright notice,*
		22	; this list of conditions and the following disclaimer.*
		23	; 2. Redistributions in binary form must reproduce the above copyright notice,*
		24	; this list of conditions and the following disclaimer in the documentation*
		25	; and/or other materials provided with the distribution.*
		26	; 3. Neither the name of STMicroelectronics nor the names of its contributors*
		27	; may be used to endorse or promote products derived from this software*
		28	; without specific prior written permission.*
		29	;*
		30	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"*
		31	; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE*
		32	; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE*
		33	; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE*
		34	; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL*
		35	; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR*
		36	; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER*
		37	; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,*
		38	; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE*
		39	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
		40	;*
		41	;*******************************************************************************
		42	;
		43	;
		44	; The modules in this file are included in the libraries, and may be replaced
		45	; by any user-defined modules that define the PUBLIC symbol _program_start or
		46	; a user defined start symbol.
		47	; To override the cstartup defined in the library, simply add your modified
		48	; version to the workbench project.
		49	;
		50	; The vector table is normally located at address 0.
		51	; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
		52	; The name "__vector_table" has special meaning for C-SPY:
		53	; it is where the SP start value is found, and the NVIC vector
		54	; table register (VTOR) is initialized to this address if != 0.
		55	;
		56	; Cortex-M version
		57	;
		58
		59	MODULE ?cstartup
		60
		61	;; Forward declaration of sections.
		62	SECTION CSTACK:DATA:NOROOT(3)
		63
		64	SECTION .intvec:CODE:NOROOT(2)
		65
		66	EXTERN __iar_program_start
		67	EXTERN SystemInit
		68	PUBLIC __vector_table
		69
		70	DATA
		71	__vector_table
		72	DCD sfe(CSTACK)
		73	DCD Reset_Handler ; Reset Handler
		74	DCD NMI_Handler ; NMI Handler
		75	DCD HardFault_Handler ; Hard Fault Handler
		76	DCD MemManage_Handler ; MPU Fault Handler
		77	DCD BusFault_Handler ; Bus Fault Handler
		78	DCD UsageFault_Handler ; Usage Fault Handler
		79	DCD 0 ; Reserved
		80	DCD 0 ; Reserved
		81	DCD 0 ; Reserved
		82	DCD 0 ; Reserved
		83	DCD SVC_Handler ; SVCall Handler
		84	DCD DebugMon_Handler ; Debug Monitor Handler
		85	DCD 0 ; Reserved
		86	DCD PendSV_Handler ; PendSV Handler
		87	DCD SysTick_Handler ; SysTick Handler
		88
		89	; External Interrupts
		90	DCD WWDG_IRQHandler ; Window Watchdog
		91	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		92	DCD TAMPER_IRQHandler ; Tamper
		93	DCD RTC_IRQHandler ; RTC
		94	DCD FLASH_IRQHandler ; Flash
		95	DCD RCC_IRQHandler ; RCC
		96	DCD EXTI0_IRQHandler ; EXTI Line 0
		97	DCD EXTI1_IRQHandler ; EXTI Line 1
		98	DCD EXTI2_IRQHandler ; EXTI Line 2
		99	DCD EXTI3_IRQHandler ; EXTI Line 3
		100	DCD EXTI4_IRQHandler ; EXTI Line 4
		101	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		102	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		103	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		104	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		105	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		106	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		107	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		108	DCD ADC1_IRQHandler ; ADC1
		109	DCD 0 ; Reserved
		110	DCD 0 ; Reserved
		111	DCD 0 ; Reserved
		112	DCD 0 ; Reserved
		113	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		114	DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
		115	DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
		116	DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
		117	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		118	DCD TIM2_IRQHandler ; TIM2
		119	DCD TIM3_IRQHandler ; TIM3
		120	DCD TIM4_IRQHandler ; TIM4
		121	DCD I2C1_EV_IRQHandler ; I2C1 Event
		122	DCD I2C1_ER_IRQHandler ; I2C1 Error
		123	DCD I2C2_EV_IRQHandler ; I2C2 Event
		124	DCD I2C2_ER_IRQHandler ; I2C2 Error
		125	DCD SPI1_IRQHandler ; SPI1
		126	DCD SPI2_IRQHandler ; SPI2
		127	DCD USART1_IRQHandler ; USART1
		128	DCD USART2_IRQHandler ; USART2
		129	DCD USART3_IRQHandler ; USART3
		130	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		131	DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
		132	DCD CEC_IRQHandler ; HDMI CEC
		133	DCD TIM12_IRQHandler ; TIM12
		134	DCD TIM13_IRQHandler ; TIM13
		135	DCD TIM14_IRQHandler ; TIM14
		136	DCD 0 ; Reserved
		137	DCD 0 ; Reserved
		138	DCD 0 ; Reserved
		139	DCD 0 ; Reserved
		140	DCD TIM5_IRQHandler ; TIM5
		141	DCD SPI3_IRQHandler ; SPI3
		142	DCD UART4_IRQHandler ; UART4
		143	DCD UART5_IRQHandler ; UART5
		144	DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
		145	DCD TIM7_IRQHandler ; TIM7
		146	DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
		147	DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
		148	DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
		149	DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 if MISC_REMAP is not set
		150	; or DMA2 Channel4 if MISC_REMAP is set
		151	DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 if MISC_REMAP is set
		152
		153	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		154	;;
		155	;; Default interrupt handlers.
		156	;;
		157	THUMB
		158
		159	PUBWEAK Reset_Handler
		160	SECTION .text:CODE:REORDER:NOROOT(2)
		161	Reset_Handler
		162	LDR R0, =SystemInit
		163	BLX R0
		164	LDR R0, =__iar_program_start
		165	BX R0
		166
		167	PUBWEAK NMI_Handler
		168	SECTION .text:CODE:REORDER:NOROOT(1)
		169	NMI_Handler
		170	B NMI_Handler
		171
		172	PUBWEAK HardFault_Handler
		173	SECTION .text:CODE:REORDER:NOROOT(1)
		174	HardFault_Handler
		175	B HardFault_Handler
		176
		177	PUBWEAK MemManage_Handler
		178	SECTION .text:CODE:REORDER:NOROOT(1)
		179	MemManage_Handler
		180	B MemManage_Handler
		181
		182	PUBWEAK BusFault_Handler
		183	SECTION .text:CODE:REORDER:NOROOT(1)
		184	BusFault_Handler
		185	B BusFault_Handler
		186
		187	PUBWEAK UsageFault_Handler
		188	SECTION .text:CODE:REORDER:NOROOT(1)
		189	UsageFault_Handler
		190	B UsageFault_Handler
		191
		192	PUBWEAK SVC_Handler
		193	SECTION .text:CODE:REORDER:NOROOT(1)
		194	SVC_Handler
		195	B SVC_Handler
		196
		197	PUBWEAK DebugMon_Handler
		198	SECTION .text:CODE:REORDER:NOROOT(1)
		199	DebugMon_Handler
		200	B DebugMon_Handler
		201
		202	PUBWEAK PendSV_Handler
		203	SECTION .text:CODE:REORDER:NOROOT(1)
		204	PendSV_Handler
		205	B PendSV_Handler
		206
		207	PUBWEAK SysTick_Handler
		208	SECTION .text:CODE:REORDER:NOROOT(1)
		209	SysTick_Handler
		210	B SysTick_Handler
		211
		212	PUBWEAK WWDG_IRQHandler
		213	SECTION .text:CODE:REORDER:NOROOT(1)
		214	WWDG_IRQHandler
		215	B WWDG_IRQHandler
		216
		217	PUBWEAK PVD_IRQHandler
		218	SECTION .text:CODE:REORDER:NOROOT(1)
		219	PVD_IRQHandler
		220	B PVD_IRQHandler
		221
		222	PUBWEAK TAMPER_IRQHandler
		223	SECTION .text:CODE:REORDER:NOROOT(1)
		224	TAMPER_IRQHandler
		225	B TAMPER_IRQHandler
		226
		227	PUBWEAK RTC_IRQHandler
		228	SECTION .text:CODE:REORDER:NOROOT(1)
		229	RTC_IRQHandler
		230	B RTC_IRQHandler
		231
		232	PUBWEAK FLASH_IRQHandler
		233	SECTION .text:CODE:REORDER:NOROOT(1)
		234	FLASH_IRQHandler
		235	B FLASH_IRQHandler
		236
		237	PUBWEAK RCC_IRQHandler
		238	SECTION .text:CODE:REORDER:NOROOT(1)
		239	RCC_IRQHandler
		240	B RCC_IRQHandler
		241
		242	PUBWEAK EXTI0_IRQHandler
		243	SECTION .text:CODE:REORDER:NOROOT(1)
		244	EXTI0_IRQHandler
		245	B EXTI0_IRQHandler
		246
		247	PUBWEAK EXTI1_IRQHandler
		248	SECTION .text:CODE:REORDER:NOROOT(1)
		249	EXTI1_IRQHandler
		250	B EXTI1_IRQHandler
		251
		252	PUBWEAK EXTI2_IRQHandler
		253	SECTION .text:CODE:REORDER:NOROOT(1)
		254	EXTI2_IRQHandler
		255	B EXTI2_IRQHandler
		256
		257	PUBWEAK EXTI3_IRQHandler
		258	SECTION .text:CODE:REORDER:NOROOT(1)
		259	EXTI3_IRQHandler
		260	B EXTI3_IRQHandler
		261
		262	PUBWEAK EXTI4_IRQHandler
		263	SECTION .text:CODE:REORDER:NOROOT(1)
		264	EXTI4_IRQHandler
		265	B EXTI4_IRQHandler
		266
		267	PUBWEAK DMA1_Channel1_IRQHandler
		268	SECTION .text:CODE:REORDER:NOROOT(1)
		269	DMA1_Channel1_IRQHandler
		270	B DMA1_Channel1_IRQHandler
		271
		272	PUBWEAK DMA1_Channel2_IRQHandler
		273	SECTION .text:CODE:REORDER:NOROOT(1)
		274	DMA1_Channel2_IRQHandler
		275	B DMA1_Channel2_IRQHandler
		276
		277	PUBWEAK DMA1_Channel3_IRQHandler
		278	SECTION .text:CODE:REORDER:NOROOT(1)
		279	DMA1_Channel3_IRQHandler
		280	B DMA1_Channel3_IRQHandler
		281
		282	PUBWEAK DMA1_Channel4_IRQHandler
		283	SECTION .text:CODE:REORDER:NOROOT(1)
		284	DMA1_Channel4_IRQHandler
		285	B DMA1_Channel4_IRQHandler
		286
		287	PUBWEAK DMA1_Channel5_IRQHandler
		288	SECTION .text:CODE:REORDER:NOROOT(1)
		289	DMA1_Channel5_IRQHandler
		290	B DMA1_Channel5_IRQHandler
		291
		292	PUBWEAK DMA1_Channel6_IRQHandler
		293	SECTION .text:CODE:REORDER:NOROOT(1)
		294	DMA1_Channel6_IRQHandler
		295	B DMA1_Channel6_IRQHandler
		296
		297	PUBWEAK DMA1_Channel7_IRQHandler
		298	SECTION .text:CODE:REORDER:NOROOT(1)
		299	DMA1_Channel7_IRQHandler
		300	B DMA1_Channel7_IRQHandler
		301
		302	PUBWEAK ADC1_IRQHandler
		303	SECTION .text:CODE:REORDER:NOROOT(1)
		304	ADC1_IRQHandler
		305	B ADC1_IRQHandler
		306
		307	PUBWEAK EXTI9_5_IRQHandler
		308	SECTION .text:CODE:REORDER:NOROOT(1)
		309	EXTI9_5_IRQHandler
		310	B EXTI9_5_IRQHandler
		311
		312	PUBWEAK TIM1_BRK_TIM15_IRQHandler
		313	SECTION .text:CODE:REORDER:NOROOT(1)
		314	TIM1_BRK_TIM15_IRQHandler
		315	B TIM1_BRK_TIM15_IRQHandler
		316
		317	PUBWEAK TIM1_UP_TIM16_IRQHandler
		318	SECTION .text:CODE:REORDER:NOROOT(1)
		319	TIM1_UP_TIM16_IRQHandler
		320	B TIM1_UP_TIM16_IRQHandler
		321
		322	PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
		323	SECTION .text:CODE:REORDER:NOROOT(1)
		324	TIM1_TRG_COM_TIM17_IRQHandler
		325	B TIM1_TRG_COM_TIM17_IRQHandler
		326
		327	PUBWEAK TIM1_CC_IRQHandler
		328	SECTION .text:CODE:REORDER:NOROOT(1)
		329	TIM1_CC_IRQHandler
		330	B TIM1_CC_IRQHandler
		331
		332	PUBWEAK TIM2_IRQHandler
		333	SECTION .text:CODE:REORDER:NOROOT(1)
		334	TIM2_IRQHandler
		335	B TIM2_IRQHandler
		336
		337	PUBWEAK TIM3_IRQHandler
		338	SECTION .text:CODE:REORDER:NOROOT(1)
		339	TIM3_IRQHandler
		340	B TIM3_IRQHandler
		341
		342	PUBWEAK TIM4_IRQHandler
		343	SECTION .text:CODE:REORDER:NOROOT(1)
		344	TIM4_IRQHandler
		345	B TIM4_IRQHandler
		346
		347	PUBWEAK I2C1_EV_IRQHandler
		348	SECTION .text:CODE:REORDER:NOROOT(1)
		349	I2C1_EV_IRQHandler
		350	B I2C1_EV_IRQHandler
		351
		352	PUBWEAK I2C1_ER_IRQHandler
		353	SECTION .text:CODE:REORDER:NOROOT(1)
		354	I2C1_ER_IRQHandler
		355	B I2C1_ER_IRQHandler
		356
		357	PUBWEAK I2C2_EV_IRQHandler
		358	SECTION .text:CODE:REORDER:NOROOT(1)
		359	I2C2_EV_IRQHandler
		360	B I2C2_EV_IRQHandler
		361
		362	PUBWEAK I2C2_ER_IRQHandler
		363	SECTION .text:CODE:REORDER:NOROOT(1)
		364	I2C2_ER_IRQHandler
		365	B I2C2_ER_IRQHandler
		366
		367	PUBWEAK SPI1_IRQHandler
		368	SECTION .text:CODE:REORDER:NOROOT(1)
		369	SPI1_IRQHandler
		370	B SPI1_IRQHandler
		371
		372	PUBWEAK SPI2_IRQHandler
		373	SECTION .text:CODE:REORDER:NOROOT(1)
		374	SPI2_IRQHandler
		375	B SPI2_IRQHandler
		376
		377	PUBWEAK USART1_IRQHandler
		378	SECTION .text:CODE:REORDER:NOROOT(1)
		379	USART1_IRQHandler
		380	B USART1_IRQHandler
		381
		382	PUBWEAK USART2_IRQHandler
		383	SECTION .text:CODE:REORDER:NOROOT(1)
		384	USART2_IRQHandler
		385	B USART2_IRQHandler
		386
		387	PUBWEAK USART3_IRQHandler
		388	SECTION .text:CODE:REORDER:NOROOT(1)
		389	USART3_IRQHandler
		390	B USART3_IRQHandler
		391
		392	PUBWEAK EXTI15_10_IRQHandler
		393	SECTION .text:CODE:REORDER:NOROOT(1)
		394	EXTI15_10_IRQHandler
		395	B EXTI15_10_IRQHandler
		396
		397	PUBWEAK RTC_Alarm_IRQHandler
		398	SECTION .text:CODE:REORDER:NOROOT(1)
		399	RTC_Alarm_IRQHandler
		400	B RTC_Alarm_IRQHandler
		401
		402
		403	PUBWEAK CEC_IRQHandler
		404	SECTION .text:CODE:REORDER:NOROOT(1)
		405	CEC_IRQHandler
		406	B CEC_IRQHandler
		407
		408	PUBWEAK TIM12_IRQHandler
		409	SECTION .text:CODE:REORDER:NOROOT(1)
		410	TIM12_IRQHandler
		411	B TIM12_IRQHandler
		412
		413	PUBWEAK TIM13_IRQHandler
		414	SECTION .text:CODE:REORDER:NOROOT(1)
		415	TIM13_IRQHandler
		416	B TIM13_IRQHandler
		417
		418	PUBWEAK TIM14_IRQHandler
		419	SECTION .text:CODE:REORDER:NOROOT(1)
		420	TIM14_IRQHandler
		421	B TIM14_IRQHandler
		422
		423	PUBWEAK TIM5_IRQHandler
		424	SECTION .text:CODE:REORDER:NOROOT(1)
		425	TIM5_IRQHandler
		426	B TIM5_IRQHandler
		427
		428	PUBWEAK SPI3_IRQHandler
		429	SECTION .text:CODE:REORDER:NOROOT(1)
		430	SPI3_IRQHandler
		431	B SPI3_IRQHandler
		432
		433	PUBWEAK UART4_IRQHandler
		434	SECTION .text:CODE:REORDER:NOROOT(1)
		435	UART4_IRQHandler
		436	B UART4_IRQHandler
		437
		438	PUBWEAK UART5_IRQHandler
		439	SECTION .text:CODE:REORDER:NOROOT(1)
		440	UART5_IRQHandler
		441	B UART5_IRQHandler
		442
		443	PUBWEAK TIM6_DAC_IRQHandler
		444	SECTION .text:CODE:REORDER:NOROOT(1)
		445	TIM6_DAC_IRQHandler
		446	B TIM6_DAC_IRQHandler
		447
		448	PUBWEAK TIM7_IRQHandler
		449	SECTION .text:CODE:REORDER:NOROOT(1)
		450	TIM7_IRQHandler
		451	B TIM7_IRQHandler
		452
		453	PUBWEAK DMA2_Channel1_IRQHandler
		454	SECTION .text:CODE:REORDER:NOROOT(1)
		455	DMA2_Channel1_IRQHandler
		456	B DMA2_Channel1_IRQHandler
		457
		458	PUBWEAK DMA2_Channel2_IRQHandler
		459	SECTION .text:CODE:REORDER:NOROOT(1)
		460	DMA2_Channel2_IRQHandler
		461	B DMA2_Channel2_IRQHandler
		462
		463	PUBWEAK DMA2_Channel3_IRQHandler
		464	SECTION .text:CODE:REORDER:NOROOT(1)
		465	DMA2_Channel3_IRQHandler
		466	B DMA2_Channel3_IRQHandler
		467
		468	PUBWEAK DMA2_Channel4_5_IRQHandler
		469	SECTION .text:CODE:REORDER:NOROOT(1)
		470	DMA2_Channel4_5_IRQHandler
		471	B DMA2_Channel4_5_IRQHandler
		472
		473	PUBWEAK DMA2_Channel5_IRQHandler
		474	SECTION .text:CODE:REORDER:NOROOT(1)
		475	DMA2_Channel5_IRQHandler
		476	B DMA2_Channel5_IRQHandler
		477
		478	END
		479	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f100xe.s – Rev 2