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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | mjames | 1 | /** |
| 5 | mjames | 2 | *************** (C) COPYRIGHT 2016 STMicroelectronics ************************ |
| 2 | mjames | 3 | * @file startup_stm32f105xc.s |
| 4 | * @author MCD Application Team |
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| 5 | mjames | 5 | * @version V4.1.0 |
| 6 | * @date 29-April-2016 |
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| 2 | mjames | 7 | * @brief STM32F105xC Devices vector table for Atollic toolchain. |
| 8 | * This module performs: |
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| 9 | * - Set the initial SP |
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| 10 | * - Set the initial PC == Reset_Handler, |
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| 11 | * - Set the vector table entries with the exceptions ISR address |
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| 12 | * - Configure the clock system |
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| 13 | * - Branches to main in the C library (which eventually |
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| 14 | * calls main()). |
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| 15 | * After Reset the Cortex-M3 processor is in Thread mode, |
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| 16 | * priority is Privileged, and the Stack is set to Main. |
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| 17 | ****************************************************************************** |
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| 18 | * |
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| 5 | mjames | 19 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 2 | mjames | 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without modification, |
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| 22 | * are permitted provided that the following conditions are met: |
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| 23 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 24 | * this list of conditions and the following disclaimer. |
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| 25 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 26 | * this list of conditions and the following disclaimer in the documentation |
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| 27 | * and/or other materials provided with the distribution. |
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| 28 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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| 29 | * may be used to endorse or promote products derived from this software |
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| 30 | * without specific prior written permission. |
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| 31 | * |
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| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 33 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 34 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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| 35 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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| 36 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 38 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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| 39 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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| 40 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 41 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 42 | * |
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| 43 | ****************************************************************************** |
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| 44 | */ |
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| 45 | |||
| 46 | .syntax unified |
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| 47 | .cpu cortex-m3 |
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| 48 | .fpu softvfp |
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| 49 | .thumb |
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| 50 | |||
| 51 | .global g_pfnVectors |
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| 52 | .global Default_Handler |
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| 53 | |||
| 54 | /* start address for the initialization values of the .data section. |
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| 55 | defined in linker script */ |
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| 56 | .word _sidata |
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| 57 | /* start address for the .data section. defined in linker script */ |
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| 58 | .word _sdata |
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| 59 | /* end address for the .data section. defined in linker script */ |
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| 60 | .word _edata |
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| 61 | /* start address for the .bss section. defined in linker script */ |
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| 62 | .word _sbss |
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| 63 | /* end address for the .bss section. defined in linker script */ |
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| 64 | .word _ebss |
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| 65 | |||
| 66 | .equ BootRAM, 0xF1E0F85F |
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| 67 | /** |
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| 68 | * @brief This is the code that gets called when the processor first |
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| 69 | * starts execution following a reset event. Only the absolutely |
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| 70 | * necessary set is performed, after which the application |
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| 71 | * supplied main() routine is called. |
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| 72 | * @param None |
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| 73 | * @retval : None |
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| 74 | */ |
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| 75 | |||
| 76 | .section .text.Reset_Handler |
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| 77 | .weak Reset_Handler |
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| 78 | .type Reset_Handler, %function |
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| 79 | Reset_Handler: |
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| 80 | |||
| 81 | /* Copy the data segment initializers from flash to SRAM */ |
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| 82 | movs r1, #0 |
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| 83 | b LoopCopyDataInit |
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| 84 | |||
| 85 | CopyDataInit: |
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| 86 | ldr r3, =_sidata |
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| 87 | ldr r3, [r3, r1] |
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| 88 | str r3, [r0, r1] |
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| 89 | adds r1, r1, #4 |
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| 90 | |||
| 91 | LoopCopyDataInit: |
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| 92 | ldr r0, =_sdata |
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| 93 | ldr r3, =_edata |
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| 94 | adds r2, r0, r1 |
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| 95 | cmp r2, r3 |
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| 96 | bcc CopyDataInit |
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| 97 | ldr r2, =_sbss |
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| 98 | b LoopFillZerobss |
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| 99 | |||
| 100 | /* Zero fill the bss segment. */ |
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| 101 | FillZerobss: |
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| 102 | movs r3, #0 |
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| 103 | str r3, [r2], #4 |
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| 104 | |||
| 105 | LoopFillZerobss: |
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| 106 | ldr r3, = _ebss |
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| 107 | cmp r2, r3 |
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| 108 | bcc FillZerobss |
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| 109 | /* Call the clock system intitialization function.*/ |
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| 110 | bl SystemInit |
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| 111 | /* Call the application's entry point.*/ |
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| 112 | bl main |
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| 113 | bx lr |
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| 114 | .size Reset_Handler, .-Reset_Handler |
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| 115 | |||
| 116 | /** |
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| 117 | * @brief This is the code that gets called when the processor receives an |
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| 118 | * unexpected interrupt. This simply enters an infinite loop, preserving |
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| 119 | * the system state for examination by a debugger. |
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| 120 | * @param None |
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| 121 | * @retval None |
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| 122 | */ |
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| 123 | .section .text.Default_Handler,"ax",%progbits |
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| 124 | Default_Handler: |
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| 125 | Infinite_Loop: |
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| 126 | b Infinite_Loop |
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| 127 | .size Default_Handler, .-Default_Handler |
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| 128 | /****************************************************************************** |
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| 129 | * |
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| 130 | * The minimal vector table for a Cortex M3. Note that the proper constructs |
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| 131 | * must be placed on this to ensure that it ends up at physical address |
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| 132 | * 0x0000.0000. |
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| 133 | * |
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| 134 | ******************************************************************************/ |
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| 135 | .section .isr_vector,"a",%progbits |
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| 136 | .type g_pfnVectors, %object |
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| 137 | .size g_pfnVectors, .-g_pfnVectors |
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| 138 | |||
| 139 | |||
| 140 | g_pfnVectors: |
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| 141 | |||
| 142 | .word _estack |
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| 143 | .word Reset_Handler |
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| 144 | .word NMI_Handler |
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| 145 | .word HardFault_Handler |
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| 146 | .word MemManage_Handler |
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| 147 | .word BusFault_Handler |
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| 148 | .word UsageFault_Handler |
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| 149 | .word 0 |
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| 150 | .word 0 |
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| 151 | .word 0 |
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| 152 | .word 0 |
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| 153 | .word SVC_Handler |
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| 154 | .word DebugMon_Handler |
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| 155 | .word 0 |
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| 156 | .word PendSV_Handler |
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| 157 | .word SysTick_Handler |
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| 158 | .word WWDG_IRQHandler |
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| 159 | .word PVD_IRQHandler |
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| 160 | .word TAMPER_IRQHandler |
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| 161 | .word RTC_IRQHandler |
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| 162 | .word FLASH_IRQHandler |
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| 163 | .word RCC_IRQHandler |
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| 164 | .word EXTI0_IRQHandler |
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| 165 | .word EXTI1_IRQHandler |
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| 166 | .word EXTI2_IRQHandler |
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| 167 | .word EXTI3_IRQHandler |
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| 168 | .word EXTI4_IRQHandler |
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| 169 | .word DMA1_Channel1_IRQHandler |
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| 170 | .word DMA1_Channel2_IRQHandler |
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| 171 | .word DMA1_Channel3_IRQHandler |
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| 172 | .word DMA1_Channel4_IRQHandler |
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| 173 | .word DMA1_Channel5_IRQHandler |
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| 174 | .word DMA1_Channel6_IRQHandler |
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| 175 | .word DMA1_Channel7_IRQHandler |
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| 176 | .word ADC1_2_IRQHandler |
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| 177 | .word CAN1_TX_IRQHandler |
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| 178 | .word CAN1_RX0_IRQHandler |
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| 179 | .word CAN1_RX1_IRQHandler |
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| 180 | .word CAN1_SCE_IRQHandler |
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| 181 | .word EXTI9_5_IRQHandler |
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| 182 | .word TIM1_BRK_IRQHandler |
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| 183 | .word TIM1_UP_IRQHandler |
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| 184 | .word TIM1_TRG_COM_IRQHandler |
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| 185 | .word TIM1_CC_IRQHandler |
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| 186 | .word TIM2_IRQHandler |
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| 187 | .word TIM3_IRQHandler |
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| 188 | .word TIM4_IRQHandler |
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| 189 | .word I2C1_EV_IRQHandler |
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| 190 | .word I2C1_ER_IRQHandler |
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| 191 | .word I2C2_EV_IRQHandler |
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| 192 | .word I2C2_ER_IRQHandler |
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| 193 | .word SPI1_IRQHandler |
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| 194 | .word SPI2_IRQHandler |
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| 195 | .word USART1_IRQHandler |
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| 196 | .word USART2_IRQHandler |
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| 197 | .word USART3_IRQHandler |
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| 198 | .word EXTI15_10_IRQHandler |
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| 199 | .word RTC_Alarm_IRQHandler |
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| 200 | .word OTG_FS_WKUP_IRQHandler |
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| 201 | .word 0 |
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| 202 | .word 0 |
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| 203 | .word 0 |
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| 204 | .word 0 |
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| 205 | .word 0 |
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| 206 | .word 0 |
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| 207 | .word 0 |
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| 208 | .word TIM5_IRQHandler |
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| 209 | .word SPI3_IRQHandler |
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| 210 | .word UART4_IRQHandler |
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| 211 | .word UART5_IRQHandler |
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| 212 | .word TIM6_IRQHandler |
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| 213 | .word TIM7_IRQHandler |
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| 214 | .word DMA2_Channel1_IRQHandler |
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| 215 | .word DMA2_Channel2_IRQHandler |
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| 216 | .word DMA2_Channel3_IRQHandler |
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| 217 | .word DMA2_Channel4_IRQHandler |
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| 218 | .word DMA2_Channel5_IRQHandler |
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| 219 | .word 0 |
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| 220 | .word 0 |
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| 221 | .word CAN2_TX_IRQHandler |
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| 222 | .word CAN2_RX0_IRQHandler |
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| 223 | .word CAN2_RX1_IRQHandler |
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| 224 | .word CAN2_SCE_IRQHandler |
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| 225 | .word OTG_FS_IRQHandler |
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| 226 | .word 0 |
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| 227 | .word 0 |
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| 228 | .word 0 |
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| 229 | .word 0 |
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| 230 | .word 0 |
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| 231 | .word 0 |
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| 232 | .word 0 |
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| 233 | .word 0 |
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| 234 | .word 0 |
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| 235 | .word 0 |
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| 236 | .word 0 |
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| 237 | .word 0 |
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| 238 | .word 0 |
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| 239 | .word 0 |
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| 240 | .word 0 |
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| 241 | .word 0 |
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| 242 | .word 0 |
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| 243 | .word 0 |
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| 244 | .word 0 |
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| 245 | .word 0 |
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| 246 | .word 0 |
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| 247 | .word 0 |
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| 248 | .word 0 |
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| 249 | .word 0 |
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| 250 | .word 0 |
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| 251 | .word 0 |
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| 252 | .word 0 |
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| 253 | .word 0 |
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| 254 | .word 0 |
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| 255 | .word 0 |
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| 256 | .word 0 |
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| 257 | .word 0 |
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| 258 | .word 0 |
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| 259 | .word 0 |
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| 260 | .word 0 |
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| 261 | .word 0 |
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| 262 | .word BootRAM /* @0x1E0. This is for boot in RAM mode for |
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| 263 | STM32F10x Connectivity line Devices. */ |
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| 264 | |||
| 265 | /******************************************************************************* |
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| 266 | * |
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| 267 | * Provide weak aliases for each Exception handler to the Default_Handler. |
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| 268 | * As they are weak aliases, any function with the same name will override |
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| 269 | * this definition. |
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| 270 | * |
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| 271 | *******************************************************************************/ |
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| 272 | .weak NMI_Handler |
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| 273 | .thumb_set NMI_Handler,Default_Handler |
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| 274 | |||
| 275 | .weak HardFault_Handler |
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| 276 | .thumb_set HardFault_Handler,Default_Handler |
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| 277 | |||
| 278 | .weak MemManage_Handler |
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| 279 | .thumb_set MemManage_Handler,Default_Handler |
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| 280 | |||
| 281 | .weak BusFault_Handler |
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| 282 | .thumb_set BusFault_Handler,Default_Handler |
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| 283 | |||
| 284 | .weak UsageFault_Handler |
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| 285 | .thumb_set UsageFault_Handler,Default_Handler |
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| 286 | |||
| 287 | .weak SVC_Handler |
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| 288 | .thumb_set SVC_Handler,Default_Handler |
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| 289 | |||
| 290 | .weak DebugMon_Handler |
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| 291 | .thumb_set DebugMon_Handler,Default_Handler |
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| 292 | |||
| 293 | .weak PendSV_Handler |
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| 294 | .thumb_set PendSV_Handler,Default_Handler |
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| 295 | |||
| 296 | .weak SysTick_Handler |
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| 297 | .thumb_set SysTick_Handler,Default_Handler |
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| 298 | |||
| 299 | .weak WWDG_IRQHandler |
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| 300 | .thumb_set WWDG_IRQHandler,Default_Handler |
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| 301 | |||
| 302 | .weak PVD_IRQHandler |
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| 303 | .thumb_set PVD_IRQHandler,Default_Handler |
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| 304 | |||
| 305 | .weak TAMPER_IRQHandler |
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| 306 | .thumb_set TAMPER_IRQHandler,Default_Handler |
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| 307 | |||
| 308 | .weak RTC_IRQHandler |
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| 309 | .thumb_set RTC_IRQHandler,Default_Handler |
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| 310 | |||
| 311 | .weak FLASH_IRQHandler |
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| 312 | .thumb_set FLASH_IRQHandler,Default_Handler |
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| 313 | |||
| 314 | .weak RCC_IRQHandler |
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| 315 | .thumb_set RCC_IRQHandler,Default_Handler |
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| 316 | |||
| 317 | .weak EXTI0_IRQHandler |
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| 318 | .thumb_set EXTI0_IRQHandler,Default_Handler |
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| 319 | |||
| 320 | .weak EXTI1_IRQHandler |
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| 321 | .thumb_set EXTI1_IRQHandler,Default_Handler |
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| 322 | |||
| 323 | .weak EXTI2_IRQHandler |
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| 324 | .thumb_set EXTI2_IRQHandler,Default_Handler |
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| 325 | |||
| 326 | .weak EXTI3_IRQHandler |
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| 327 | .thumb_set EXTI3_IRQHandler,Default_Handler |
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| 328 | |||
| 329 | .weak EXTI4_IRQHandler |
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| 330 | .thumb_set EXTI4_IRQHandler,Default_Handler |
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| 331 | |||
| 332 | .weak DMA1_Channel1_IRQHandler |
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| 333 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
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| 334 | |||
| 335 | .weak DMA1_Channel2_IRQHandler |
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| 336 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler |
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| 337 | |||
| 338 | .weak DMA1_Channel3_IRQHandler |
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| 339 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler |
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| 340 | |||
| 341 | .weak DMA1_Channel4_IRQHandler |
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| 342 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler |
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| 343 | |||
| 344 | .weak DMA1_Channel5_IRQHandler |
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| 345 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler |
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| 346 | |||
| 347 | .weak DMA1_Channel6_IRQHandler |
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| 348 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler |
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| 349 | |||
| 350 | .weak DMA1_Channel7_IRQHandler |
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| 351 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler |
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| 352 | |||
| 353 | .weak ADC1_2_IRQHandler |
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| 354 | .thumb_set ADC1_2_IRQHandler,Default_Handler |
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| 355 | |||
| 356 | .weak CAN1_TX_IRQHandler |
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| 357 | .thumb_set CAN1_TX_IRQHandler,Default_Handler |
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| 358 | |||
| 359 | .weak CAN1_RX0_IRQHandler |
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| 360 | .thumb_set CAN1_RX0_IRQHandler,Default_Handler |
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| 361 | |||
| 362 | .weak CAN1_RX1_IRQHandler |
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| 363 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler |
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| 364 | |||
| 365 | .weak CAN1_SCE_IRQHandler |
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| 366 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler |
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| 367 | |||
| 368 | .weak EXTI9_5_IRQHandler |
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| 369 | .thumb_set EXTI9_5_IRQHandler,Default_Handler |
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| 370 | |||
| 371 | .weak TIM1_BRK_IRQHandler |
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| 372 | .thumb_set TIM1_BRK_IRQHandler,Default_Handler |
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| 373 | |||
| 374 | .weak TIM1_UP_IRQHandler |
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| 375 | .thumb_set TIM1_UP_IRQHandler,Default_Handler |
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| 376 | |||
| 377 | .weak TIM1_TRG_COM_IRQHandler |
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| 378 | .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler |
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| 379 | |||
| 380 | .weak TIM1_CC_IRQHandler |
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| 381 | .thumb_set TIM1_CC_IRQHandler,Default_Handler |
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| 382 | |||
| 383 | .weak TIM2_IRQHandler |
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| 384 | .thumb_set TIM2_IRQHandler,Default_Handler |
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| 385 | |||
| 386 | .weak TIM3_IRQHandler |
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| 387 | .thumb_set TIM3_IRQHandler,Default_Handler |
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| 388 | |||
| 389 | .weak TIM4_IRQHandler |
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| 390 | .thumb_set TIM4_IRQHandler,Default_Handler |
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| 391 | |||
| 392 | .weak I2C1_EV_IRQHandler |
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| 393 | .thumb_set I2C1_EV_IRQHandler,Default_Handler |
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| 394 | |||
| 395 | .weak I2C1_ER_IRQHandler |
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| 396 | .thumb_set I2C1_ER_IRQHandler,Default_Handler |
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| 397 | |||
| 398 | .weak I2C2_EV_IRQHandler |
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| 399 | .thumb_set I2C2_EV_IRQHandler,Default_Handler |
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| 400 | |||
| 401 | .weak I2C2_ER_IRQHandler |
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| 402 | .thumb_set I2C2_ER_IRQHandler,Default_Handler |
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| 403 | |||
| 404 | .weak SPI1_IRQHandler |
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| 405 | .thumb_set SPI1_IRQHandler,Default_Handler |
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| 406 | |||
| 407 | .weak SPI2_IRQHandler |
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| 408 | .thumb_set SPI2_IRQHandler,Default_Handler |
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| 409 | |||
| 410 | .weak USART1_IRQHandler |
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| 411 | .thumb_set USART1_IRQHandler,Default_Handler |
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| 412 | |||
| 413 | .weak USART2_IRQHandler |
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| 414 | .thumb_set USART2_IRQHandler,Default_Handler |
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| 415 | |||
| 416 | .weak USART3_IRQHandler |
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| 417 | .thumb_set USART3_IRQHandler,Default_Handler |
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| 418 | |||
| 419 | .weak EXTI15_10_IRQHandler |
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| 420 | .thumb_set EXTI15_10_IRQHandler,Default_Handler |
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| 421 | |||
| 422 | .weak RTC_Alarm_IRQHandler |
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| 423 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler |
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| 424 | |||
| 425 | .weak OTG_FS_WKUP_IRQHandler |
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| 426 | .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler |
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| 427 | |||
| 428 | .weak TIM5_IRQHandler |
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| 429 | .thumb_set TIM5_IRQHandler,Default_Handler |
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| 430 | |||
| 431 | .weak SPI3_IRQHandler |
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| 432 | .thumb_set SPI3_IRQHandler,Default_Handler |
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| 433 | |||
| 434 | .weak UART4_IRQHandler |
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| 435 | .thumb_set UART4_IRQHandler,Default_Handler |
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| 436 | |||
| 437 | .weak UART5_IRQHandler |
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| 438 | .thumb_set UART5_IRQHandler,Default_Handler |
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| 439 | |||
| 440 | .weak TIM6_IRQHandler |
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| 441 | .thumb_set TIM6_IRQHandler,Default_Handler |
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| 442 | |||
| 443 | .weak TIM7_IRQHandler |
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| 444 | .thumb_set TIM7_IRQHandler,Default_Handler |
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| 445 | |||
| 446 | .weak DMA2_Channel1_IRQHandler |
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| 447 | .thumb_set DMA2_Channel1_IRQHandler,Default_Handler |
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| 448 | |||
| 449 | .weak DMA2_Channel2_IRQHandler |
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| 450 | .thumb_set DMA2_Channel2_IRQHandler,Default_Handler |
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| 451 | |||
| 452 | .weak DMA2_Channel3_IRQHandler |
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| 453 | .thumb_set DMA2_Channel3_IRQHandler,Default_Handler |
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| 454 | |||
| 455 | .weak DMA2_Channel4_IRQHandler |
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| 456 | .thumb_set DMA2_Channel4_IRQHandler,Default_Handler |
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| 457 | |||
| 458 | .weak DMA2_Channel5_IRQHandler |
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| 459 | .thumb_set DMA2_Channel5_IRQHandler,Default_Handler |
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| 460 | |||
| 461 | .weak CAN2_TX_IRQHandler |
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| 462 | .thumb_set CAN2_TX_IRQHandler,Default_Handler |
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| 463 | |||
| 464 | .weak CAN2_RX0_IRQHandler |
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| 465 | .thumb_set CAN2_RX0_IRQHandler,Default_Handler |
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| 466 | |||
| 467 | .weak CAN2_RX1_IRQHandler |
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| 468 | .thumb_set CAN2_RX1_IRQHandler,Default_Handler |
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| 469 | |||
| 470 | .weak CAN2_SCE_IRQHandler |
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| 471 | .thumb_set CAN2_SCE_IRQHandler,Default_Handler |
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| 472 | |||
| 473 | .weak OTG_FS_IRQHandler |
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| 474 | .thumb_set OTG_FS_IRQHandler ,Default_Handler |
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| 475 | |||
| 476 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |