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2 mjames 1 
/**
5 mjames 2 
  *************** (C) COPYRIGHT 2016 STMicroelectronics ************************
2 mjames 3 
  * @file      startup_stm32f103xb.s
4 
  * @author    MCD Application Team
5 mjames 5 
  * @version   V4.1.0
6 
  * @date      29-April-2016
2 mjames 7 
  * @brief     STM32F103xB Devices vector table for Atollic toolchain.
8 
  *            This module performs:
9 
  *                - Set the initial SP
10 
  *                - Set the initial PC == Reset_Handler,
11 
  *                - Set the vector table entries with the exceptions ISR address
12 
  *                - Configure the clock system
13 
  *                - Branches to main in the C library (which eventually
14 
  *                  calls main()).
15 
  *            After Reset the Cortex-M3 processor is in Thread mode,
16 
  *            priority is Privileged, and the Stack is set to Main.
17 
  ******************************************************************************
18 
  *
5 mjames 19 
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2 mjames 20 
  *
21 
  * Redistribution and use in source and binary forms, with or without modification,
22 
  * are permitted provided that the following conditions are met:
23 
  *   1. Redistributions of source code must retain the above copyright notice,
24 
  *      this list of conditions and the following disclaimer.
25 
  *   2. Redistributions in binary form must reproduce the above copyright notice,
26 
  *      this list of conditions and the following disclaimer in the documentation
27 
  *      and/or other materials provided with the distribution.
28 
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
29 
  *      may be used to endorse or promote products derived from this software
30 
  *      without specific prior written permission.
31 
  *
32 
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
36 
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
38 
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
39 
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
40 
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 
  *
43 
  ******************************************************************************
44 
  */
45 
 
46 
  .syntax unified
47 
  .cpu cortex-m3
48 
  .fpu softvfp
49 
  .thumb
50 
 
51 
.global g_pfnVectors
52 
.global Default_Handler
53 
 
54 
/* start address for the initialization values of the .data section.
55 
defined in linker script */
56 
.word _sidata
57 
/* start address for the .data section. defined in linker script */
58 
.word _sdata
59 
/* end address for the .data section. defined in linker script */
60 
.word _edata
61 
/* start address for the .bss section. defined in linker script */
62 
.word _sbss
63 
/* end address for the .bss section. defined in linker script */
64 
.word _ebss
65 
 
66 
.equ  BootRAM,        0xF1E0F85F
67 
/**
68 
 * @brief  This is the code that gets called when the processor first
69 
 *          starts execution following a reset event. Only the absolutely
70 
 *          necessary set is performed, after which the application
71 
 *          supplied main() routine is called.
72 
 * @param  None
73 
 * @retval : None
74 
*/
75 
 
76 
  .section .text.Reset_Handler
77 
  .weak Reset_Handler
78 
  .type Reset_Handler, %function
79 
Reset_Handler:
80 
 
81 
/* Copy the data segment initializers from flash to SRAM */
82 
  movs r1, #0
83 
  b LoopCopyDataInit
84 
 
85 
CopyDataInit:
86 
  ldr r3, =_sidata
87 
  ldr r3, [r3, r1]
88 
  str r3, [r0, r1]
89 
  adds r1, r1, #4
90 
 
91 
LoopCopyDataInit:
92 
  ldr r0, =_sdata
93 
  ldr r3, =_edata
94 
  adds r2, r0, r1
95 
  cmp r2, r3
96 
  bcc CopyDataInit
97 
  ldr r2, =_sbss
98 
  b LoopFillZerobss
99 
 
100 
/* Zero fill the bss segment. */
101 
FillZerobss:
102 
  movs r3, #0
103 
  str r3, [r2], #4
104 
 
105 
LoopFillZerobss:
106 
  ldr r3, = _ebss
107 
  cmp r2, r3
108 
  bcc FillZerobss
109 
 
110 
/* Call the clock system intitialization function.*/
111 
    bl  SystemInit
112 
/* Call static constructors */
113 
    bl __libc_init_array
114 
/* Call the application's entry point.*/
115 
  bl main
116 
  bx lr
117 
.size Reset_Handler, .-Reset_Handler
118 
 
119 
/**
120 
 * @brief  This is the code that gets called when the processor receives an
121 
 *         unexpected interrupt.  This simply enters an infinite loop, preserving
122 
 *         the system state for examination by a debugger.
123 
 * @param  None
124 
 * @retval None
125 
*/
126 
    .section .text.Default_Handler,"ax",%progbits
127 
Default_Handler:
128 
Infinite_Loop:
129 
  b Infinite_Loop
130 
  .size Default_Handler, .-Default_Handler
131 
/******************************************************************************
132 
*
133 
* The minimal vector table for a Cortex M3.  Note that the proper constructs
134 
* must be placed on this to ensure that it ends up at physical address
135 
* 0x0000.0000.
136 
*
137 
*******************************************************************************/
138 
  .section .isr_vector,"a",%progbits
139 
  .type g_pfnVectors, %object
140 
  .size g_pfnVectors, .-g_pfnVectors
141 
 
142 
 
143 
g_pfnVectors:
144 
 
145 
  .word  _estack
146 
  .word  Reset_Handler
147 
  .word  NMI_Handler
148 
  .word  HardFault_Handler
149 
  .word  MemManage_Handler
150 
  .word  BusFault_Handler
151 
  .word  UsageFault_Handler
152 
  .word  0
153 
  .word  0
154 
  .word  0
155 
  .word  0
156 
  .word  SVC_Handler
157 
  .word  DebugMon_Handler
158 
  .word  0
159 
  .word  PendSV_Handler
160 
  .word  SysTick_Handler
161 
  .word  WWDG_IRQHandler
162 
  .word  PVD_IRQHandler
163 
  .word  TAMPER_IRQHandler
164 
  .word  RTC_IRQHandler
165 
  .word  FLASH_IRQHandler
166 
  .word  RCC_IRQHandler
167 
  .word  EXTI0_IRQHandler
168 
  .word  EXTI1_IRQHandler
169 
  .word  EXTI2_IRQHandler
170 
  .word  EXTI3_IRQHandler
171 
  .word  EXTI4_IRQHandler
172 
  .word  DMA1_Channel1_IRQHandler
173 
  .word  DMA1_Channel2_IRQHandler
174 
  .word  DMA1_Channel3_IRQHandler
175 
  .word  DMA1_Channel4_IRQHandler
176 
  .word  DMA1_Channel5_IRQHandler
177 
  .word  DMA1_Channel6_IRQHandler
178 
  .word  DMA1_Channel7_IRQHandler
179 
  .word  ADC1_2_IRQHandler
180 
  .word  USB_HP_CAN1_TX_IRQHandler
181 
  .word  USB_LP_CAN1_RX0_IRQHandler
182 
  .word  CAN1_RX1_IRQHandler
183 
  .word  CAN1_SCE_IRQHandler
184 
  .word  EXTI9_5_IRQHandler
185 
  .word  TIM1_BRK_TIM9_IRQHandler
186 
  .word  TIM1_UP_TIM10_IRQHandler
187 
  .word  TIM1_TRG_COM_TIM11_IRQHandler
188 
  .word  TIM1_CC_IRQHandler
189 
  .word  TIM2_IRQHandler
190 
  .word  TIM3_IRQHandler
191 
  .word  TIM4_IRQHandler
192 
  .word  I2C1_EV_IRQHandler
193 
  .word  I2C1_ER_IRQHandler
194 
  .word  I2C2_EV_IRQHandler
195 
  .word  I2C2_ER_IRQHandler
196 
  .word  SPI1_IRQHandler
197 
  .word  SPI2_IRQHandler
198 
  .word  USART1_IRQHandler
199 
  .word  USART2_IRQHandler
200 
  .word  USART3_IRQHandler
201 
  .word  EXTI15_10_IRQHandler
202 
  .word  RTC_Alarm_IRQHandler
203 
  .word  USBWakeUp_IRQHandler
204 
  .word  TIM8_BRK_TIM12_IRQHandler
205 
  .word  TIM8_UP_TIM13_IRQHandler
206 
  .word  TIM8_TRG_COM_TIM14_IRQHandler
207 
  .word  TIM8_CC_IRQHandler
208 
  .word  ADC3_IRQHandler
209 
  .word  FSMC_IRQHandler
210 
  .word  SDIO_IRQHandler
211 
  .word  TIM5_IRQHandler
212 
  .word  SPI3_IRQHandler
213 
  .word  UART4_IRQHandler
214 
  .word  UART5_IRQHandler
215 
  .word  TIM6_IRQHandler
216 
  .word  TIM7_IRQHandler
217 
  .word  DMA2_Channel1_IRQHandler
218 
  .word  DMA2_Channel2_IRQHandler
219 
  .word  DMA2_Channel3_IRQHandler
220 
  .word  DMA2_Channel4_5_IRQHandler
221 
  .word  0
222 
  .word  0
223 
  .word  0
224 
  .word  0
225 
  .word  0
226 
  .word  0
227 
  .word  0
228 
  .word  0
229 
  .word  0
230 
  .word  0
231 
  .word  0
232 
  .word  0
233 
  .word  0
234 
  .word  0
235 
  .word  0
236 
  .word  0
237 
  .word  0
238 
  .word  0
239 
  .word  0
240 
  .word  0
241 
  .word  0
242 
  .word  0
243 
  .word  0
244 
  .word  0
245 
  .word  0
246 
  .word  0
247 
  .word  0
248 
  .word  0
249 
  .word  0
250 
  .word  0
251 
  .word  0
252 
  .word  0
253 
  .word  0
254 
  .word  0
255 
  .word  0
256 
  .word  0
257 
  .word  0
258 
  .word  0
259 
  .word  0
260 
  .word  0
261 
  .word  0
262 
  .word  0
263 
  .word  0
264 
  .word  0
265 
  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for
266 
                         STM32F10x XL-Density devices. */
267 
/*******************************************************************************
268 
*
269 
* Provide weak aliases for each Exception handler to the Default_Handler.
270 
* As they are weak aliases, any function with the same name will override
271 
* this definition.
272 
*
273 
*******************************************************************************/
274 
 
275 
  .weak  NMI_Handler
276 
  .thumb_set NMI_Handler,Default_Handler
277 
 
278 
  .weak  HardFault_Handler
279 
  .thumb_set HardFault_Handler,Default_Handler
280 
 
281 
  .weak  MemManage_Handler
282 
  .thumb_set MemManage_Handler,Default_Handler
283 
 
284 
  .weak  BusFault_Handler
285 
  .thumb_set BusFault_Handler,Default_Handler
286 
 
287 
  .weak  UsageFault_Handler
288 
  .thumb_set UsageFault_Handler,Default_Handler
289 
 
290 
  .weak  SVC_Handler
291 
  .thumb_set SVC_Handler,Default_Handler
292 
 
293 
  .weak  DebugMon_Handler
294 
  .thumb_set DebugMon_Handler,Default_Handler
295 
 
296 
  .weak  PendSV_Handler
297 
  .thumb_set PendSV_Handler,Default_Handler
298 
 
299 
  .weak  SysTick_Handler
300 
  .thumb_set SysTick_Handler,Default_Handler
301 
 
302 
  .weak  WWDG_IRQHandler
303 
  .thumb_set WWDG_IRQHandler,Default_Handler
304 
 
305 
  .weak  PVD_IRQHandler
306 
  .thumb_set PVD_IRQHandler,Default_Handler
307 
 
308 
  .weak  TAMPER_IRQHandler
309 
  .thumb_set TAMPER_IRQHandler,Default_Handler
310 
 
311 
  .weak  RTC_IRQHandler
312 
  .thumb_set RTC_IRQHandler,Default_Handler
313 
 
314 
  .weak  FLASH_IRQHandler
315 
  .thumb_set FLASH_IRQHandler,Default_Handler
316 
 
317 
  .weak  RCC_IRQHandler
318 
  .thumb_set RCC_IRQHandler,Default_Handler
319 
 
320 
  .weak  EXTI0_IRQHandler
321 
  .thumb_set EXTI0_IRQHandler,Default_Handler
322 
 
323 
  .weak  EXTI1_IRQHandler
324 
  .thumb_set EXTI1_IRQHandler,Default_Handler
325 
 
326 
  .weak  EXTI2_IRQHandler
327 
  .thumb_set EXTI2_IRQHandler,Default_Handler
328 
 
329 
  .weak  EXTI3_IRQHandler
330 
  .thumb_set EXTI3_IRQHandler,Default_Handler
331 
 
332 
  .weak  EXTI4_IRQHandler
333 
  .thumb_set EXTI4_IRQHandler,Default_Handler
334 
 
335 
  .weak  DMA1_Channel1_IRQHandler
336 
  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
337 
 
338 
  .weak  DMA1_Channel2_IRQHandler
339 
  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
340 
 
341 
  .weak  DMA1_Channel3_IRQHandler
342 
  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
343 
 
344 
  .weak  DMA1_Channel4_IRQHandler
345 
  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
346 
 
347 
  .weak  DMA1_Channel5_IRQHandler
348 
  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
349 
 
350 
  .weak  DMA1_Channel6_IRQHandler
351 
  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
352 
 
353 
  .weak  DMA1_Channel7_IRQHandler
354 
  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
355 
 
356 
  .weak  ADC1_2_IRQHandler
357 
  .thumb_set ADC1_2_IRQHandler,Default_Handler
358 
 
359 
  .weak  USB_HP_CAN1_TX_IRQHandler
360 
  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
361 
 
362 
  .weak  USB_LP_CAN1_RX0_IRQHandler
363 
  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
364 
 
365 
  .weak  CAN1_RX1_IRQHandler
366 
  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
367 
 
368 
  .weak  CAN1_SCE_IRQHandler
369 
  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
370 
 
371 
  .weak  EXTI9_5_IRQHandler
372 
  .thumb_set EXTI9_5_IRQHandler,Default_Handler
373 
 
374 
  .weak  TIM1_BRK_TIM9_IRQHandler
375 
  .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
376 
 
377 
  .weak  TIM1_UP_TIM10_IRQHandler
378 
  .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
379 
 
380 
  .weak  TIM1_TRG_COM_TIM11_IRQHandler
381 
  .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
382 
 
383 
  .weak  TIM1_CC_IRQHandler
384 
  .thumb_set TIM1_CC_IRQHandler,Default_Handler
385 
 
386 
  .weak  TIM2_IRQHandler
387 
  .thumb_set TIM2_IRQHandler,Default_Handler
388 
 
389 
  .weak  TIM3_IRQHandler
390 
  .thumb_set TIM3_IRQHandler,Default_Handler
391 
 
392 
  .weak  TIM4_IRQHandler
393 
  .thumb_set TIM4_IRQHandler,Default_Handler
394 
 
395 
  .weak  I2C1_EV_IRQHandler
396 
  .thumb_set I2C1_EV_IRQHandler,Default_Handler
397 
 
398 
  .weak  I2C1_ER_IRQHandler
399 
  .thumb_set I2C1_ER_IRQHandler,Default_Handler
400 
 
401 
  .weak  I2C2_EV_IRQHandler
402 
  .thumb_set I2C2_EV_IRQHandler,Default_Handler
403 
 
404 
  .weak  I2C2_ER_IRQHandler
405 
  .thumb_set I2C2_ER_IRQHandler,Default_Handler
406 
 
407 
  .weak  SPI1_IRQHandler
408 
  .thumb_set SPI1_IRQHandler,Default_Handler
409 
 
410 
  .weak  SPI2_IRQHandler
411 
  .thumb_set SPI2_IRQHandler,Default_Handler
412 
 
413 
  .weak  USART1_IRQHandler
414 
  .thumb_set USART1_IRQHandler,Default_Handler
415 
 
416 
  .weak  USART2_IRQHandler
417 
  .thumb_set USART2_IRQHandler,Default_Handler
418 
 
419 
  .weak  USART3_IRQHandler
420 
  .thumb_set USART3_IRQHandler,Default_Handler
421 
 
422 
  .weak  EXTI15_10_IRQHandler
423 
  .thumb_set EXTI15_10_IRQHandler,Default_Handler
424 
 
425 
  .weak  RTC_Alarm_IRQHandler
426 
  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
427 
 
428 
  .weak  USBWakeUp_IRQHandler
429 
  .thumb_set USBWakeUp_IRQHandler,Default_Handler
430 
 
431 
  .weak  TIM8_BRK_TIM12_IRQHandler
432 
  .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
433 
 
434 
  .weak  TIM8_UP_TIM13_IRQHandler
435 
  .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
436 
 
437 
  .weak  TIM8_TRG_COM_TIM14_IRQHandler
438 
  .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
439 
 
440 
  .weak  TIM8_CC_IRQHandler
441 
  .thumb_set TIM8_CC_IRQHandler,Default_Handler
442 
 
443 
  .weak  ADC3_IRQHandler
444 
  .thumb_set ADC3_IRQHandler,Default_Handler
445 
 
446 
  .weak  FSMC_IRQHandler
447 
  .thumb_set FSMC_IRQHandler,Default_Handler
448 
 
449 
  .weak  SDIO_IRQHandler
450 
  .thumb_set SDIO_IRQHandler,Default_Handler
451 
 
452 
  .weak  TIM5_IRQHandler
453 
  .thumb_set TIM5_IRQHandler,Default_Handler
454 
 
455 
  .weak  SPI3_IRQHandler
456 
  .thumb_set SPI3_IRQHandler,Default_Handler
457 
 
458 
  .weak  UART4_IRQHandler
459 
  .thumb_set UART4_IRQHandler,Default_Handler
460 
 
461 
  .weak  UART5_IRQHandler
462 
  .thumb_set UART5_IRQHandler,Default_Handler
463 
 
464 
  .weak  TIM6_IRQHandler
465 
  .thumb_set TIM6_IRQHandler,Default_Handler
466 
 
467 
  .weak  TIM7_IRQHandler
468 
  .thumb_set TIM7_IRQHandler,Default_Handler
469 
 
470 
  .weak  DMA2_Channel1_IRQHandler
471 
  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
472 
 
473 
  .weak  DMA2_Channel2_IRQHandler
474 
  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
475 
 
476 
  .weak  DMA2_Channel3_IRQHandler
477 
  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
478 
 
479 
  .weak  DMA2_Channel4_5_IRQHandler
480 
  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
481 
 
482 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/