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2 mjames 1
/**
2
  *************** (C) COPYRIGHT 2015 STMicroelectronics ************************
3
  * @file      startup_stm32f103xe.s
4
  * @author    MCD Application Team
5
  * @version   V4.0.1
6
  * @date      31-July-2015
7
  * @brief     STM32F103xE Devices vector table for Atollic toolchain.
8
  *            This module performs:
9
  *                - Set the initial SP
10
  *                - Set the initial PC == Reset_Handler,
11
  *                - Set the vector table entries with the exceptions ISR address
12
  *                - Configure the clock system   
13
  *                - Configure external SRAM mounted on STM3210E-EVAL board
14
  *                  to be used as data memory (optional, to be enabled by user)
15
  *                - Branches to main in the C library (which eventually
16
  *                  calls main()).
17
  *            After Reset the Cortex-M3 processor is in Thread mode,
18
  *            priority is Privileged, and the Stack is set to Main.
19
  ******************************************************************************
20
  *
21
  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
22
  *
23
  * Redistribution and use in source and binary forms, with or without modification,
24
  * are permitted provided that the following conditions are met:
25
  *   1. Redistributions of source code must retain the above copyright notice,
26
  *      this list of conditions and the following disclaimer.
27
  *   2. Redistributions in binary form must reproduce the above copyright notice,
28
  *      this list of conditions and the following disclaimer in the documentation
29
  *      and/or other materials provided with the distribution.
30
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
31
  *      may be used to endorse or promote products derived from this software
32
  *      without specific prior written permission.
33
  *
34
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
35
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
38
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
40
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
42
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44
  *
45
  ******************************************************************************
46
  */
47
 
48
  .syntax unified
49
  .cpu cortex-m3
50
  .fpu softvfp
51
  .thumb
52
 
53
.global g_pfnVectors
54
.global Default_Handler
55
 
56
/* start address for the initialization values of the .data section.
57
defined in linker script */
58
.word _sidata
59
/* start address for the .data section. defined in linker script */
60
.word _sdata
61
/* end address for the .data section. defined in linker script */
62
.word _edata
63
/* start address for the .bss section. defined in linker script */
64
.word _sbss
65
/* end address for the .bss section. defined in linker script */
66
.word _ebss
67
 
68
.equ  BootRAM,        0xF1E0F85F
69
/**
70
 * @brief  This is the code that gets called when the processor first
71
 *          starts execution following a reset event. Only the absolutely
72
 *          necessary set is performed, after which the application
73
 *          supplied main() routine is called.
74
 * @param  None
75
 * @retval : None
76
*/
77
 
78
  .section .text.Reset_Handler
79
  .weak Reset_Handler
80
  .type Reset_Handler, %function
81
Reset_Handler:
82
 
83
/* Copy the data segment initializers from flash to SRAM */
84
  movs r1, #0
85
  b LoopCopyDataInit
86
 
87
CopyDataInit:
88
  ldr r3, =_sidata
89
  ldr r3, [r3, r1]
90
  str r3, [r0, r1]
91
  adds r1, r1, #4
92
 
93
LoopCopyDataInit:
94
  ldr r0, =_sdata
95
  ldr r3, =_edata
96
  adds r2, r0, r1
97
  cmp r2, r3
98
  bcc CopyDataInit
99
  ldr r2, =_sbss
100
  b LoopFillZerobss
101
/* Zero fill the bss segment. */
102
FillZerobss:
103
  movs r3, #0
104
  str r3, [r2], #4
105
 
106
LoopFillZerobss:
107
  ldr r3, = _ebss
108
  cmp r2, r3
109
  bcc FillZerobss
110
 
111
/* Call the clock system intitialization function.*/
112
    bl  SystemInit
113
/* Call static constructors */
114
    bl __libc_init_array
115
/* Call the application's entry point.*/
116
  bl main
117
  bx lr
118
.size Reset_Handler, .-Reset_Handler
119
 
120
/**
121
 * @brief  This is the code that gets called when the processor receives an
122
 *         unexpected interrupt.  This simply enters an infinite loop, preserving
123
 *         the system state for examination by a debugger.
124
 *
125
 * @param  None
126
 * @retval : None
127
*/
128
    .section .text.Default_Handler,"ax",%progbits
129
Default_Handler:
130
Infinite_Loop:
131
  b Infinite_Loop
132
  .size Default_Handler, .-Default_Handler
133
/******************************************************************************
134
*
135
* The minimal vector table for a Cortex M3.  Note that the proper constructs
136
* must be placed on this to ensure that it ends up at physical address
137
* 0x0000.0000.
138
*
139
******************************************************************************/
140
  .section .isr_vector,"a",%progbits
141
  .type g_pfnVectors, %object
142
  .size g_pfnVectors, .-g_pfnVectors
143
 
144
 
145
g_pfnVectors:
146
 
147
  .word _estack
148
  .word Reset_Handler
149
  .word NMI_Handler
150
  .word HardFault_Handler
151
  .word MemManage_Handler
152
  .word BusFault_Handler
153
  .word UsageFault_Handler
154
  .word 0
155
  .word 0
156
  .word 0
157
  .word 0
158
  .word SVC_Handler
159
  .word DebugMon_Handler
160
  .word 0
161
  .word PendSV_Handler
162
  .word SysTick_Handler
163
  .word WWDG_IRQHandler
164
  .word PVD_IRQHandler
165
  .word TAMPER_IRQHandler
166
  .word RTC_IRQHandler
167
  .word FLASH_IRQHandler
168
  .word RCC_IRQHandler
169
  .word EXTI0_IRQHandler
170
  .word EXTI1_IRQHandler
171
  .word EXTI2_IRQHandler
172
  .word EXTI3_IRQHandler
173
  .word EXTI4_IRQHandler
174
  .word DMA1_Channel1_IRQHandler
175
  .word DMA1_Channel2_IRQHandler
176
  .word DMA1_Channel3_IRQHandler
177
  .word DMA1_Channel4_IRQHandler
178
  .word DMA1_Channel5_IRQHandler
179
  .word DMA1_Channel6_IRQHandler
180
  .word DMA1_Channel7_IRQHandler
181
  .word ADC1_2_IRQHandler
182
  .word USB_HP_CAN1_TX_IRQHandler
183
  .word USB_LP_CAN1_RX0_IRQHandler
184
  .word CAN1_RX1_IRQHandler
185
  .word CAN1_SCE_IRQHandler
186
  .word EXTI9_5_IRQHandler
187
  .word TIM1_BRK_IRQHandler
188
  .word TIM1_UP_IRQHandler
189
  .word TIM1_TRG_COM_IRQHandler
190
  .word TIM1_CC_IRQHandler
191
  .word TIM2_IRQHandler
192
  .word TIM3_IRQHandler
193
  .word TIM4_IRQHandler
194
  .word I2C1_EV_IRQHandler
195
  .word I2C1_ER_IRQHandler
196
  .word I2C2_EV_IRQHandler
197
  .word I2C2_ER_IRQHandler
198
  .word SPI1_IRQHandler
199
  .word SPI2_IRQHandler
200
  .word USART1_IRQHandler
201
  .word USART2_IRQHandler
202
  .word USART3_IRQHandler
203
  .word EXTI15_10_IRQHandler
204
  .word RTC_Alarm_IRQHandler
205
  .word USBWakeUp_IRQHandler
206
  .word TIM8_BRK_IRQHandler
207
  .word TIM8_UP_IRQHandler
208
  .word TIM8_TRG_COM_IRQHandler
209
  .word TIM8_CC_IRQHandler
210
  .word ADC3_IRQHandler
211
  .word FSMC_IRQHandler
212
  .word SDIO_IRQHandler
213
  .word TIM5_IRQHandler
214
  .word SPI3_IRQHandler
215
  .word UART4_IRQHandler
216
  .word UART5_IRQHandler
217
  .word TIM6_IRQHandler
218
  .word TIM7_IRQHandler
219
  .word DMA2_Channel1_IRQHandler
220
  .word DMA2_Channel2_IRQHandler
221
  .word DMA2_Channel3_IRQHandler
222
  .word DMA2_Channel4_5_IRQHandler
223
  .word 0
224
  .word 0
225
  .word 0
226
  .word 0
227
  .word 0
228
  .word 0
229
  .word 0
230
  .word 0
231
  .word 0
232
  .word 0
233
  .word 0
234
  .word 0
235
  .word 0
236
  .word 0
237
  .word 0
238
  .word 0
239
  .word 0
240
  .word 0
241
  .word 0
242
  .word 0
243
  .word 0
244
  .word 0
245
  .word 0
246
  .word 0
247
  .word 0
248
  .word 0
249
  .word 0
250
  .word 0
251
  .word 0
252
  .word 0
253
  .word 0
254
  .word 0
255
  .word 0
256
  .word 0
257
  .word 0
258
  .word 0
259
  .word 0
260
  .word 0
261
  .word 0
262
  .word 0
263
  .word 0
264
  .word 0
265
  .word 0
266
  .word 0
267
  .word BootRAM       /* @0x1E0. This is for boot in RAM mode for
268
                         STM32F10x High Density devices. */
269
 
270
/*******************************************************************************
271
*
272
* Provide weak aliases for each Exception handler to the Default_Handler.
273
* As they are weak aliases, any function with the same name will override
274
* this definition.
275
*
276
*******************************************************************************/
277
 
278
  .weak NMI_Handler
279
  .thumb_set NMI_Handler,Default_Handler
280
 
281
  .weak HardFault_Handler
282
  .thumb_set HardFault_Handler,Default_Handler
283
 
284
  .weak MemManage_Handler
285
  .thumb_set MemManage_Handler,Default_Handler
286
 
287
  .weak BusFault_Handler
288
  .thumb_set BusFault_Handler,Default_Handler
289
 
290
  .weak UsageFault_Handler
291
  .thumb_set UsageFault_Handler,Default_Handler
292
 
293
  .weak SVC_Handler
294
  .thumb_set SVC_Handler,Default_Handler
295
 
296
  .weak DebugMon_Handler
297
  .thumb_set DebugMon_Handler,Default_Handler
298
 
299
  .weak PendSV_Handler
300
  .thumb_set PendSV_Handler,Default_Handler
301
 
302
  .weak SysTick_Handler
303
  .thumb_set SysTick_Handler,Default_Handler
304
 
305
  .weak WWDG_IRQHandler
306
  .thumb_set WWDG_IRQHandler,Default_Handler
307
 
308
  .weak PVD_IRQHandler
309
  .thumb_set PVD_IRQHandler,Default_Handler
310
 
311
  .weak TAMPER_IRQHandler
312
  .thumb_set TAMPER_IRQHandler,Default_Handler
313
 
314
  .weak RTC_IRQHandler
315
  .thumb_set RTC_IRQHandler,Default_Handler
316
 
317
  .weak FLASH_IRQHandler
318
  .thumb_set FLASH_IRQHandler,Default_Handler
319
 
320
  .weak RCC_IRQHandler
321
  .thumb_set RCC_IRQHandler,Default_Handler
322
 
323
  .weak EXTI0_IRQHandler
324
  .thumb_set EXTI0_IRQHandler,Default_Handler
325
 
326
  .weak EXTI1_IRQHandler
327
  .thumb_set EXTI1_IRQHandler,Default_Handler
328
 
329
  .weak EXTI2_IRQHandler
330
  .thumb_set EXTI2_IRQHandler,Default_Handler
331
 
332
  .weak EXTI3_IRQHandler
333
  .thumb_set EXTI3_IRQHandler,Default_Handler
334
 
335
  .weak EXTI4_IRQHandler
336
  .thumb_set EXTI4_IRQHandler,Default_Handler
337
 
338
  .weak DMA1_Channel1_IRQHandler
339
  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
340
 
341
  .weak DMA1_Channel2_IRQHandler
342
  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
343
 
344
  .weak DMA1_Channel3_IRQHandler
345
  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
346
 
347
  .weak DMA1_Channel4_IRQHandler
348
  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
349
 
350
  .weak DMA1_Channel5_IRQHandler
351
  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
352
 
353
  .weak DMA1_Channel6_IRQHandler
354
  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
355
 
356
  .weak DMA1_Channel7_IRQHandler
357
  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
358
 
359
  .weak ADC1_2_IRQHandler
360
  .thumb_set ADC1_2_IRQHandler,Default_Handler
361
 
362
  .weak USB_HP_CAN1_TX_IRQHandler
363
  .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
364
 
365
  .weak USB_LP_CAN1_RX0_IRQHandler
366
  .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
367
 
368
  .weak CAN1_RX1_IRQHandler
369
  .thumb_set CAN1_RX1_IRQHandler,Default_Handler
370
 
371
  .weak CAN1_SCE_IRQHandler
372
  .thumb_set CAN1_SCE_IRQHandler,Default_Handler
373
 
374
  .weak EXTI9_5_IRQHandler
375
  .thumb_set EXTI9_5_IRQHandler,Default_Handler
376
 
377
  .weak TIM1_BRK_IRQHandler
378
  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
379
 
380
  .weak TIM1_UP_IRQHandler
381
  .thumb_set TIM1_UP_IRQHandler,Default_Handler
382
 
383
  .weak TIM1_TRG_COM_IRQHandler
384
  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
385
 
386
  .weak TIM1_CC_IRQHandler
387
  .thumb_set TIM1_CC_IRQHandler,Default_Handler
388
 
389
  .weak TIM2_IRQHandler
390
  .thumb_set TIM2_IRQHandler,Default_Handler
391
 
392
  .weak TIM3_IRQHandler
393
  .thumb_set TIM3_IRQHandler,Default_Handler
394
 
395
  .weak TIM4_IRQHandler
396
  .thumb_set TIM4_IRQHandler,Default_Handler
397
 
398
  .weak I2C1_EV_IRQHandler
399
  .thumb_set I2C1_EV_IRQHandler,Default_Handler
400
 
401
  .weak I2C1_ER_IRQHandler
402
  .thumb_set I2C1_ER_IRQHandler,Default_Handler
403
 
404
  .weak I2C2_EV_IRQHandler
405
  .thumb_set I2C2_EV_IRQHandler,Default_Handler
406
 
407
  .weak I2C2_ER_IRQHandler
408
  .thumb_set I2C2_ER_IRQHandler,Default_Handler
409
 
410
  .weak SPI1_IRQHandler
411
  .thumb_set SPI1_IRQHandler,Default_Handler
412
 
413
  .weak SPI2_IRQHandler
414
  .thumb_set SPI2_IRQHandler,Default_Handler
415
 
416
  .weak USART1_IRQHandler
417
  .thumb_set USART1_IRQHandler,Default_Handler
418
 
419
  .weak USART2_IRQHandler
420
  .thumb_set USART2_IRQHandler,Default_Handler
421
 
422
  .weak USART3_IRQHandler
423
  .thumb_set USART3_IRQHandler,Default_Handler
424
 
425
  .weak EXTI15_10_IRQHandler
426
  .thumb_set EXTI15_10_IRQHandler,Default_Handler
427
 
428
  .weak RTC_Alarm_IRQHandler
429
  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
430
 
431
  .weak USBWakeUp_IRQHandler
432
  .thumb_set USBWakeUp_IRQHandler,Default_Handler
433
 
434
  .weak TIM8_BRK_IRQHandler
435
  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
436
 
437
  .weak TIM8_UP_IRQHandler
438
  .thumb_set TIM8_UP_IRQHandler,Default_Handler
439
 
440
  .weak TIM8_TRG_COM_IRQHandler
441
  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
442
 
443
  .weak TIM8_CC_IRQHandler
444
  .thumb_set TIM8_CC_IRQHandler,Default_Handler
445
 
446
  .weak ADC3_IRQHandler
447
  .thumb_set ADC3_IRQHandler,Default_Handler
448
 
449
  .weak FSMC_IRQHandler
450
  .thumb_set FSMC_IRQHandler,Default_Handler
451
 
452
  .weak SDIO_IRQHandler
453
  .thumb_set SDIO_IRQHandler,Default_Handler
454
 
455
  .weak TIM5_IRQHandler
456
  .thumb_set TIM5_IRQHandler,Default_Handler
457
 
458
  .weak SPI3_IRQHandler
459
  .thumb_set SPI3_IRQHandler,Default_Handler
460
 
461
  .weak UART4_IRQHandler
462
  .thumb_set UART4_IRQHandler,Default_Handler
463
 
464
  .weak UART5_IRQHandler
465
  .thumb_set UART5_IRQHandler,Default_Handler
466
 
467
  .weak TIM6_IRQHandler
468
  .thumb_set TIM6_IRQHandler,Default_Handler
469
 
470
  .weak TIM7_IRQHandler
471
  .thumb_set TIM7_IRQHandler,Default_Handler
472
 
473
  .weak DMA2_Channel1_IRQHandler
474
  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
475
 
476
  .weak DMA2_Channel2_IRQHandler
477
  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
478
 
479
  .weak DMA2_Channel3_IRQHandler
480
  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
481
 
482
  .weak DMA2_Channel4_5_IRQHandler
483
  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
484
 
485
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/