WebSVN – dashGPS – Blame – /trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f100xb.s

Rev	Author	Line No.	Line
2	mjames	1	/**
		2	************* (C) COPYRIGHT 2017 STMicroelectronics **********************
		3	* @file startup_stm32f100xb.s
		4	* @author MCD Application Team
		5	* @brief STM32F100xB Devices vector table for Atollic toolchain.
		6	* This module performs:
		7	* - Set the initial SP
		8	* - Set the initial PC == Reset_Handler,
		9	* - Set the vector table entries with the exceptions ISR address
		10	* - Configure the clock system
		11	* - Branches to main in the C library (which eventually
		12	* calls main()).
		13	* After Reset the Cortex-M3 processor is in Thread mode,
		14	* priority is Privileged, and the Stack is set to Main.
		15	******************************************************************************
		16	* @attention
		17	*
		18	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
		19	* All rights reserved.</center></h2>
		20	*
		21	* This software component is licensed by ST under BSD 3-Clause license,
		22	* the "License"; You may not use this file except in compliance with the
		23	* License. You may obtain a copy of the License at:
		24	* opensource.org/licenses/BSD-3-Clause
		25	*
		26	******************************************************************************
		27	*/
		28
		29	.syntax unified
		30	.cpu cortex-m3
		31	.fpu softvfp
		32	.thumb
		33
		34	.global g_pfnVectors
		35	.global Default_Handler
		36
		37	/* start address for the initialization values of the .data section.
		38	defined in linker script */
		39	.word _sidata
		40	/* start address for the .data section. defined in linker script */
		41	.word _sdata
		42	/* end address for the .data section. defined in linker script */
		43	.word _edata
		44	/* start address for the .bss section. defined in linker script */
		45	.word _sbss
		46	/* end address for the .bss section. defined in linker script */
		47	.word _ebss
		48
		49	.equ BootRAM, 0xF108F85F
		50	/**
		51	* @brief This is the code that gets called when the processor first
		52	* starts execution following a reset event. Only the absolutely
		53	* necessary set is performed, after which the application
		54	* supplied main() routine is called.
		55	* @param None
		56	* @retval : None
		57	*/
		58
		59	.section .text.Reset_Handler
		60	.weak Reset_Handler
		61	.type Reset_Handler, %function
		62	Reset_Handler:
		63
		64	/* Copy the data segment initializers from flash to SRAM */
		65	movs r1, #0
		66	b LoopCopyDataInit
		67
		68	CopyDataInit:
		69	ldr r3, =_sidata
		70	ldr r3, [r3, r1]
		71	str r3, [r0, r1]
		72	adds r1, r1, #4
		73
		74	LoopCopyDataInit:
		75	ldr r0, =_sdata
		76	ldr r3, =_edata
		77	adds r2, r0, r1
		78	cmp r2, r3
		79	bcc CopyDataInit
		80	ldr r2, =_sbss
		81	b LoopFillZerobss
		82	/* Zero fill the bss segment. */
		83	FillZerobss:
		84	movs r3, #0
		85	str r3, [r2], #4
		86
		87	LoopFillZerobss:
		88	ldr r3, = _ebss
		89	cmp r2, r3
		90	bcc FillZerobss
		91
		92	/* Call the clock system intitialization function.*/
		93	bl SystemInit
		94	/* Call static constructors */
		95	bl __libc_init_array
		96	/* Call the application's entry point.*/
		97	bl main
		98	bx lr
		99	.size Reset_Handler, .-Reset_Handler
		100
		101	/**
		102	* @brief This is the code that gets called when the processor receives an
		103	* unexpected interrupt. This simply enters an infinite loop, preserving
		104	* the system state for examination by a debugger.
		105	*
		106	* @param None
		107	* @retval : None
		108	*/
		109	.section .text.Default_Handler,"ax",%progbits
		110	Default_Handler:
		111	Infinite_Loop:
		112	b Infinite_Loop
		113	.size Default_Handler, .-Default_Handler
		114	/******************************************************************************
		115	*
		116	* The minimal vector table for a Cortex M3. Note that the proper constructs
		117	* must be placed on this to ensure that it ends up at physical address
		118	* 0x0000.0000.
		119	*
		120	******************************************************************************/
		121	.section .isr_vector,"a",%progbits
		122	.type g_pfnVectors, %object
		123	.size g_pfnVectors, .-g_pfnVectors
		124
		125
		126	g_pfnVectors:
		127	.word _estack
		128	.word Reset_Handler
		129	.word NMI_Handler
		130	.word HardFault_Handler
		131	.word MemManage_Handler
		132	.word BusFault_Handler
		133	.word UsageFault_Handler
		134	.word 0
		135	.word 0
		136	.word 0
		137	.word 0
		138	.word SVC_Handler
		139	.word DebugMon_Handler
		140	.word 0
		141	.word PendSV_Handler
		142	.word SysTick_Handler
		143	.word WWDG_IRQHandler
		144	.word PVD_IRQHandler
		145	.word TAMPER_IRQHandler
		146	.word RTC_IRQHandler
		147	.word FLASH_IRQHandler
		148	.word RCC_IRQHandler
		149	.word EXTI0_IRQHandler
		150	.word EXTI1_IRQHandler
		151	.word EXTI2_IRQHandler
		152	.word EXTI3_IRQHandler
		153	.word EXTI4_IRQHandler
		154	.word DMA1_Channel1_IRQHandler
		155	.word DMA1_Channel2_IRQHandler
		156	.word DMA1_Channel3_IRQHandler
		157	.word DMA1_Channel4_IRQHandler
		158	.word DMA1_Channel5_IRQHandler
		159	.word DMA1_Channel6_IRQHandler
		160	.word DMA1_Channel7_IRQHandler
		161	.word ADC1_IRQHandler
		162	.word 0
		163	.word 0
		164	.word 0
		165	.word 0
		166	.word EXTI9_5_IRQHandler
		167	.word TIM1_BRK_TIM15_IRQHandler
		168	.word TIM1_UP_TIM16_IRQHandler
		169	.word TIM1_TRG_COM_TIM17_IRQHandler
		170	.word TIM1_CC_IRQHandler
		171	.word TIM2_IRQHandler
		172	.word TIM3_IRQHandler
		173	.word TIM4_IRQHandler
		174	.word I2C1_EV_IRQHandler
		175	.word I2C1_ER_IRQHandler
		176	.word I2C2_EV_IRQHandler
		177	.word I2C2_ER_IRQHandler
		178	.word SPI1_IRQHandler
		179	.word SPI2_IRQHandler
		180	.word USART1_IRQHandler
		181	.word USART2_IRQHandler
		182	.word USART3_IRQHandler
		183	.word EXTI15_10_IRQHandler
		184	.word RTC_Alarm_IRQHandler
		185	.word CEC_IRQHandler
		186	.word 0
		187	.word 0
		188	.word 0
		189	.word 0
		190	.word 0
		191	.word 0
		192	.word 0
		193	.word 0
		194	.word 0
		195	.word 0
		196	.word 0
		197	.word TIM6_DAC_IRQHandler
		198	.word TIM7_IRQHandler
		199	.word 0
		200	.word 0
		201	.word 0
		202	.word 0
		203	.word 0
		204	.word 0
		205	.word 0
		206	.word 0
		207	.word 0
		208	.word 0
		209	.word 0
		210	.word 0
		211	.word 0
		212	.word 0
		213	.word 0
		214	.word 0
		215	.word 0
		216	.word 0
		217	.word 0
		218	.word 0
		219	.word 0
		220	.word 0
		221	.word 0
		222	.word 0
		223	.word 0
		224	.word 0
		225	.word 0
		226	.word 0
		227	.word 0
		228	.word 0
		229	.word 0
		230	.word 0
		231	.word 0
		232	.word 0
		233	.word 0
		234	.word 0
		235	.word 0
		236	.word 0
		237	.word 0
		238	.word 0
		239	.word 0
		240	.word 0
		241	.word 0
		242	.word BootRAM /* @0x01CC. This is for boot in RAM mode for
		243	STM32F10xB Value Line devices. */
		244
		245	/*******************************************************************************
		246	*
		247	* Provide weak aliases for each Exception handler to the Default_Handler.
		248	* As they are weak aliases, any function with the same name will override
		249	* this definition.
		250	*
		251	*******************************************************************************/
		252
		253
		254	.weak NMI_Handler
		255	.thumb_set NMI_Handler,Default_Handler
		256
		257	.weak HardFault_Handler
		258	.thumb_set HardFault_Handler,Default_Handler
		259
		260	.weak MemManage_Handler
		261	.thumb_set MemManage_Handler,Default_Handler
		262
		263	.weak BusFault_Handler
		264	.thumb_set BusFault_Handler,Default_Handler
		265
		266	.weak UsageFault_Handler
		267	.thumb_set UsageFault_Handler,Default_Handler
		268
		269	.weak SVC_Handler
		270	.thumb_set SVC_Handler,Default_Handler
		271
		272	.weak DebugMon_Handler
		273	.thumb_set DebugMon_Handler,Default_Handler
		274
		275	.weak PendSV_Handler
		276	.thumb_set PendSV_Handler,Default_Handler
		277
		278	.weak SysTick_Handler
		279	.thumb_set SysTick_Handler,Default_Handler
		280
		281	.weak WWDG_IRQHandler
		282	.thumb_set WWDG_IRQHandler,Default_Handler
		283
		284	.weak PVD_IRQHandler
		285	.thumb_set PVD_IRQHandler,Default_Handler
		286
		287	.weak TAMPER_IRQHandler
		288	.thumb_set TAMPER_IRQHandler,Default_Handler
		289
		290	.weak RTC_IRQHandler
		291	.thumb_set RTC_IRQHandler,Default_Handler
		292
		293	.weak FLASH_IRQHandler
		294	.thumb_set FLASH_IRQHandler,Default_Handler
		295
		296	.weak RCC_IRQHandler
		297	.thumb_set RCC_IRQHandler,Default_Handler
		298
		299	.weak EXTI0_IRQHandler
		300	.thumb_set EXTI0_IRQHandler,Default_Handler
		301
		302	.weak EXTI1_IRQHandler
		303	.thumb_set EXTI1_IRQHandler,Default_Handler
		304
		305	.weak EXTI2_IRQHandler
		306	.thumb_set EXTI2_IRQHandler,Default_Handler
		307
		308	.weak EXTI3_IRQHandler
		309	.thumb_set EXTI3_IRQHandler,Default_Handler
		310
		311	.weak EXTI4_IRQHandler
		312	.thumb_set EXTI4_IRQHandler,Default_Handler
		313
		314	.weak DMA1_Channel1_IRQHandler
		315	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
		316
		317	.weak DMA1_Channel2_IRQHandler
		318	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
		319
		320	.weak DMA1_Channel3_IRQHandler
		321	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
		322
		323	.weak DMA1_Channel4_IRQHandler
		324	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
		325
		326	.weak DMA1_Channel5_IRQHandler
		327	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
		328
		329	.weak DMA1_Channel6_IRQHandler
		330	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
		331
		332	.weak DMA1_Channel7_IRQHandler
		333	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
		334
		335	.weak ADC1_IRQHandler
		336	.thumb_set ADC1_IRQHandler,Default_Handler
		337
		338	.weak EXTI9_5_IRQHandler
		339	.thumb_set EXTI9_5_IRQHandler,Default_Handler
		340
		341	.weak TIM1_BRK_TIM15_IRQHandler
		342	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
		343
		344	.weak TIM1_UP_TIM16_IRQHandler
		345	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
		346
		347	.weak TIM1_TRG_COM_TIM17_IRQHandler
		348	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
		349
		350	.weak TIM1_CC_IRQHandler
		351	.thumb_set TIM1_CC_IRQHandler,Default_Handler
		352
		353	.weak TIM2_IRQHandler
		354	.thumb_set TIM2_IRQHandler,Default_Handler
		355
		356	.weak TIM3_IRQHandler
		357	.thumb_set TIM3_IRQHandler,Default_Handler
		358
		359	.weak TIM4_IRQHandler
		360	.thumb_set TIM4_IRQHandler,Default_Handler
		361
		362	.weak I2C1_EV_IRQHandler
		363	.thumb_set I2C1_EV_IRQHandler,Default_Handler
		364
		365	.weak I2C1_ER_IRQHandler
		366	.thumb_set I2C1_ER_IRQHandler,Default_Handler
		367
		368	.weak I2C2_EV_IRQHandler
		369	.thumb_set I2C1_EV_IRQHandler,Default_Handler
		370
		371	.weak I2C2_ER_IRQHandler
		372	.thumb_set I2C1_ER_IRQHandler,Default_Handler
		373
		374	.weak SPI1_IRQHandler
		375	.thumb_set SPI1_IRQHandler,Default_Handler
		376
		377	.weak SPI1_IRQHandler
		378	.thumb_set SPI2_IRQHandler,Default_Handler
		379
		380	.weak USART1_IRQHandler
		381	.thumb_set USART1_IRQHandler,Default_Handler
		382
		383	.weak USART2_IRQHandler
		384	.thumb_set USART2_IRQHandler,Default_Handler
		385
		386	.weak USART3_IRQHandler
		387	.thumb_set USART3_IRQHandler,Default_Handler
		388
		389	.weak EXTI15_10_IRQHandler
		390	.thumb_set EXTI15_10_IRQHandler,Default_Handler
		391
		392	.weak RTC_Alarm_IRQHandler
		393	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
		394
		395	.weak CEC_IRQHandler
		396	.thumb_set CEC_IRQHandler,Default_Handler
		397
		398	.weak TIM6_DAC_IRQHandler
		399	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
		400
		401	.weak TIM7_IRQHandler
		402	.thumb_set TIM7_IRQHandler,Default_Handler
		403
		404	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
		405

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