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Rev	Author	Line No.	Line
2	mjames	1	;****************** (C) COPYRIGHT 2015 STMicroelectronics ******************
		2	; File Name : startup_stm32f105xc.s*
		3	; Author : MCD Application Team*
		4	; Version : V4.0.1*
		5	; Date : 31-July-2015*
		6	; Description : STM32F105xC Devices vector table for MDK-ARM toolchain.*
		7	; This module performs:*
		8	; - Set the initial SP*
		9	; - Set the initial PC == Reset_Handler*
		10	; - Set the vector table entries with the exceptions ISR address*
		11	; - Configure the clock system*
		12	; - Branches to __main in the C library (which eventually*
		13	; calls main()).*
		14	; After Reset the Cortex-M3 processor is in Thread mode,*
		15	; priority is Privileged, and the Stack is set to Main.*
		16	;********************************************************************************
		17	;*
		18	; COPYRIGHT(c) 2015 STMicroelectronics*
		19	;*
		20	; Redistribution and use in source and binary forms, with or without modification,*
		21	; are permitted provided that the following conditions are met:*
		22	; 1. Redistributions of source code must retain the above copyright notice,*
		23	; this list of conditions and the following disclaimer.*
		24	; 2. Redistributions in binary form must reproduce the above copyright notice,*
		25	; this list of conditions and the following disclaimer in the documentation*
		26	; and/or other materials provided with the distribution.*
		27	; 3. Neither the name of STMicroelectronics nor the names of its contributors*
		28	; may be used to endorse or promote products derived from this software*
		29	; without specific prior written permission.*
		30	;*
		31	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"*
		32	; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE*
		33	; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE*
		34	; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE*
		35	; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL*
		36	; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR*
		37	; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER*
		38	; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,*
		39	; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE*
		40	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
		41	;
		42	;*******************************************************************************
		43
		44	; Amount of memory (in bytes) allocated for Stack
		45	; Tailor this value to your application needs
		46	; <h> Stack Configuration
		47	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		48	; </h>
		49
		50	Stack_Size EQU 0x00000400
		51
		52	AREA STACK, NOINIT, READWRITE, ALIGN=3
		53	Stack_Mem SPACE Stack_Size
		54	__initial_sp
		55
		56
		57	; <h> Heap Configuration
		58	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		59	; </h>
		60
		61	Heap_Size EQU 0x00000200
		62
		63	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		64	__heap_base
		65	Heap_Mem SPACE Heap_Size
		66	__heap_limit
		67
		68	PRESERVE8
		69	THUMB
		70
		71
		72	; Vector Table Mapped to Address 0 at Reset
		73	AREA RESET, DATA, READONLY
		74	EXPORT __Vectors
		75	EXPORT __Vectors_End
		76	EXPORT __Vectors_Size
		77
		78	__Vectors DCD __initial_sp ; Top of Stack
		79	DCD Reset_Handler ; Reset Handler
		80	DCD NMI_Handler ; NMI Handler
		81	DCD HardFault_Handler ; Hard Fault Handler
		82	DCD MemManage_Handler ; MPU Fault Handler
		83	DCD BusFault_Handler ; Bus Fault Handler
		84	DCD UsageFault_Handler ; Usage Fault Handler
		85	DCD 0 ; Reserved
		86	DCD 0 ; Reserved
		87	DCD 0 ; Reserved
		88	DCD 0 ; Reserved
		89	DCD SVC_Handler ; SVCall Handler
		90	DCD DebugMon_Handler ; Debug Monitor Handler
		91	DCD 0 ; Reserved
		92	DCD PendSV_Handler ; PendSV Handler
		93	DCD SysTick_Handler ; SysTick Handler
		94
		95	; External Interrupts
		96	DCD WWDG_IRQHandler ; Window Watchdog
		97	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		98	DCD TAMPER_IRQHandler ; Tamper
		99	DCD RTC_IRQHandler ; RTC
		100	DCD FLASH_IRQHandler ; Flash
		101	DCD RCC_IRQHandler ; RCC
		102	DCD EXTI0_IRQHandler ; EXTI Line 0
		103	DCD EXTI1_IRQHandler ; EXTI Line 1
		104	DCD EXTI2_IRQHandler ; EXTI Line 2
		105	DCD EXTI3_IRQHandler ; EXTI Line 3
		106	DCD EXTI4_IRQHandler ; EXTI Line 4
		107	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		108	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		109	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		110	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		111	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		112	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		113	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		114	DCD ADC1_2_IRQHandler ; ADC1 and ADC2
		115	DCD CAN1_TX_IRQHandler ; CAN1 TX
		116	DCD CAN1_RX0_IRQHandler ; CAN1 RX0
		117	DCD CAN1_RX1_IRQHandler ; CAN1 RX1
		118	DCD CAN1_SCE_IRQHandler ; CAN1 SCE
		119	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		120	DCD TIM1_BRK_IRQHandler ; TIM1 Break
		121	DCD TIM1_UP_IRQHandler ; TIM1 Update
		122	DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
		123	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		124	DCD TIM2_IRQHandler ; TIM2
		125	DCD TIM3_IRQHandler ; TIM3
		126	DCD TIM4_IRQHandler ; TIM4
		127	DCD I2C1_EV_IRQHandler ; I2C1 Event
		128	DCD I2C1_ER_IRQHandler ; I2C1 Error
		129	DCD I2C2_EV_IRQHandler ; I2C2 Event
		130	DCD I2C2_ER_IRQHandler ; I2C1 Error
		131	DCD SPI1_IRQHandler ; SPI1
		132	DCD SPI2_IRQHandler ; SPI2
		133	DCD USART1_IRQHandler ; USART1
		134	DCD USART2_IRQHandler ; USART2
		135	DCD USART3_IRQHandler ; USART3
		136	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		137	DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
		138	DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
		139	DCD 0 ; Reserved
		140	DCD 0 ; Reserved
		141	DCD 0 ; Reserved
		142	DCD 0 ; Reserved
		143	DCD 0 ; Reserved
		144	DCD 0 ; Reserved
		145	DCD 0 ; Reserved
		146	DCD TIM5_IRQHandler ; TIM5
		147	DCD SPI3_IRQHandler ; SPI3
		148	DCD UART4_IRQHandler ; UART4
		149	DCD UART5_IRQHandler ; UART5
		150	DCD TIM6_IRQHandler ; TIM6
		151	DCD TIM7_IRQHandler ; TIM7
		152	DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
		153	DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
		154	DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
		155	DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
		156	DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
		157	DCD 0 ; Reserved
		158	DCD 0 ; Reserved
		159	DCD CAN2_TX_IRQHandler ; CAN2 TX
		160	DCD CAN2_RX0_IRQHandler ; CAN2 RX0
		161	DCD CAN2_RX1_IRQHandler ; CAN2 RX1
		162	DCD CAN2_SCE_IRQHandler ; CAN2 SCE
		163	DCD OTG_FS_IRQHandler ; USB OTG FS
		164	__Vectors_End
		165
		166	__Vectors_Size EQU __Vectors_End - __Vectors
		167
		168	AREA \|.text\|, CODE, READONLY
		169
		170	; Reset handler
		171	Reset_Handler PROC
		172	EXPORT Reset_Handler [WEAK]
		173	IMPORT SystemInit
		174	IMPORT __main
		175	LDR R0, =SystemInit
		176	BLX R0
		177	LDR R0, =__main
		178	BX R0
		179	ENDP
		180
		181	; Dummy Exception Handlers (infinite loops which can be modified)
		182
		183	NMI_Handler PROC
		184	EXPORT NMI_Handler [WEAK]
		185	B .
		186	ENDP
		187	HardFault_Handler\
		188	PROC
		189	EXPORT HardFault_Handler [WEAK]
		190	B .
		191	ENDP
		192	MemManage_Handler\
		193	PROC
		194	EXPORT MemManage_Handler [WEAK]
		195	B .
		196	ENDP
		197	BusFault_Handler\
		198	PROC
		199	EXPORT BusFault_Handler [WEAK]
		200	B .
		201	ENDP
		202	UsageFault_Handler\
		203	PROC
		204	EXPORT UsageFault_Handler [WEAK]
		205	B .
		206	ENDP
		207	SVC_Handler PROC
		208	EXPORT SVC_Handler [WEAK]
		209	B .
		210	ENDP
		211	DebugMon_Handler\
		212	PROC
		213	EXPORT DebugMon_Handler [WEAK]
		214	B .
		215	ENDP
		216	PendSV_Handler PROC
		217	EXPORT PendSV_Handler [WEAK]
		218	B .
		219	ENDP
		220	SysTick_Handler PROC
		221	EXPORT SysTick_Handler [WEAK]
		222	B .
		223	ENDP
		224
		225	Default_Handler PROC
		226
		227	EXPORT WWDG_IRQHandler [WEAK]
		228	EXPORT PVD_IRQHandler [WEAK]
		229	EXPORT TAMPER_IRQHandler [WEAK]
		230	EXPORT RTC_IRQHandler [WEAK]
		231	EXPORT FLASH_IRQHandler [WEAK]
		232	EXPORT RCC_IRQHandler [WEAK]
		233	EXPORT EXTI0_IRQHandler [WEAK]
		234	EXPORT EXTI1_IRQHandler [WEAK]
		235	EXPORT EXTI2_IRQHandler [WEAK]
		236	EXPORT EXTI3_IRQHandler [WEAK]
		237	EXPORT EXTI4_IRQHandler [WEAK]
		238	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		239	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		240	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		241	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		242	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		243	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		244	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		245	EXPORT ADC1_2_IRQHandler [WEAK]
		246	EXPORT CAN1_TX_IRQHandler [WEAK]
		247	EXPORT CAN1_RX0_IRQHandler [WEAK]
		248	EXPORT CAN1_RX1_IRQHandler [WEAK]
		249	EXPORT CAN1_SCE_IRQHandler [WEAK]
		250	EXPORT EXTI9_5_IRQHandler [WEAK]
		251	EXPORT TIM1_BRK_IRQHandler [WEAK]
		252	EXPORT TIM1_UP_IRQHandler [WEAK]
		253	EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
		254	EXPORT TIM1_CC_IRQHandler [WEAK]
		255	EXPORT TIM2_IRQHandler [WEAK]
		256	EXPORT TIM3_IRQHandler [WEAK]
		257	EXPORT TIM4_IRQHandler [WEAK]
		258	EXPORT I2C1_EV_IRQHandler [WEAK]
		259	EXPORT I2C1_ER_IRQHandler [WEAK]
		260	EXPORT I2C2_EV_IRQHandler [WEAK]
		261	EXPORT I2C2_ER_IRQHandler [WEAK]
		262	EXPORT SPI1_IRQHandler [WEAK]
		263	EXPORT SPI2_IRQHandler [WEAK]
		264	EXPORT USART1_IRQHandler [WEAK]
		265	EXPORT USART2_IRQHandler [WEAK]
		266	EXPORT USART3_IRQHandler [WEAK]
		267	EXPORT EXTI15_10_IRQHandler [WEAK]
		268	EXPORT RTC_Alarm_IRQHandler [WEAK]
		269	EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
		270	EXPORT TIM5_IRQHandler [WEAK]
		271	EXPORT SPI3_IRQHandler [WEAK]
		272	EXPORT UART4_IRQHandler [WEAK]
		273	EXPORT UART5_IRQHandler [WEAK]
		274	EXPORT TIM6_IRQHandler [WEAK]
		275	EXPORT TIM7_IRQHandler [WEAK]
		276	EXPORT DMA2_Channel1_IRQHandler [WEAK]
		277	EXPORT DMA2_Channel2_IRQHandler [WEAK]
		278	EXPORT DMA2_Channel3_IRQHandler [WEAK]
		279	EXPORT DMA2_Channel4_IRQHandler [WEAK]
		280	EXPORT DMA2_Channel5_IRQHandler [WEAK]
		281	EXPORT CAN2_TX_IRQHandler [WEAK]
		282	EXPORT CAN2_RX0_IRQHandler [WEAK]
		283	EXPORT CAN2_RX1_IRQHandler [WEAK]
		284	EXPORT CAN2_SCE_IRQHandler [WEAK]
		285	EXPORT OTG_FS_IRQHandler [WEAK]
		286
		287	WWDG_IRQHandler
		288	PVD_IRQHandler
		289	TAMPER_IRQHandler
		290	RTC_IRQHandler
		291	FLASH_IRQHandler
		292	RCC_IRQHandler
		293	EXTI0_IRQHandler
		294	EXTI1_IRQHandler
		295	EXTI2_IRQHandler
		296	EXTI3_IRQHandler
		297	EXTI4_IRQHandler
		298	DMA1_Channel1_IRQHandler
		299	DMA1_Channel2_IRQHandler
		300	DMA1_Channel3_IRQHandler
		301	DMA1_Channel4_IRQHandler
		302	DMA1_Channel5_IRQHandler
		303	DMA1_Channel6_IRQHandler
		304	DMA1_Channel7_IRQHandler
		305	ADC1_2_IRQHandler
		306	CAN1_TX_IRQHandler
		307	CAN1_RX0_IRQHandler
		308	CAN1_RX1_IRQHandler
		309	CAN1_SCE_IRQHandler
		310	EXTI9_5_IRQHandler
		311	TIM1_BRK_IRQHandler
		312	TIM1_UP_IRQHandler
		313	TIM1_TRG_COM_IRQHandler
		314	TIM1_CC_IRQHandler
		315	TIM2_IRQHandler
		316	TIM3_IRQHandler
		317	TIM4_IRQHandler
		318	I2C1_EV_IRQHandler
		319	I2C1_ER_IRQHandler
		320	I2C2_EV_IRQHandler
		321	I2C2_ER_IRQHandler
		322	SPI1_IRQHandler
		323	SPI2_IRQHandler
		324	USART1_IRQHandler
		325	USART2_IRQHandler
		326	USART3_IRQHandler
		327	EXTI15_10_IRQHandler
		328	RTC_Alarm_IRQHandler
		329	OTG_FS_WKUP_IRQHandler
		330	TIM5_IRQHandler
		331	SPI3_IRQHandler
		332	UART4_IRQHandler
		333	UART5_IRQHandler
		334	TIM6_IRQHandler
		335	TIM7_IRQHandler
		336	DMA2_Channel1_IRQHandler
		337	DMA2_Channel2_IRQHandler
		338	DMA2_Channel3_IRQHandler
		339	DMA2_Channel4_IRQHandler
		340	DMA2_Channel5_IRQHandler
		341	CAN2_TX_IRQHandler
		342	CAN2_RX0_IRQHandler
		343	CAN2_RX1_IRQHandler
		344	CAN2_SCE_IRQHandler
		345	OTG_FS_IRQHandler
		346
		347	B .
		348
		349	ENDP
		350
		351	ALIGN
		352
		353	;*******************************************************************************
		354	; User Stack and Heap initialization
		355	;*******************************************************************************
		356	IF :DEF:__MICROLIB
		357
		358	EXPORT __initial_sp
		359	EXPORT __heap_base
		360	EXPORT __heap_limit
		361
		362	ELSE
		363
		364	IMPORT __use_two_region_memory
		365	EXPORT __user_initial_stackheap
		366
		367	__user_initial_stackheap
		368
		369	LDR R0, = Heap_Mem
		370	LDR R1, =(Stack_Mem + Stack_Size)
		371	LDR R2, = (Heap_Mem + Heap_Size)
		372	LDR R3, = Stack_Mem
		373	BX LR
		374
		375	ALIGN
		376
		377	ENDIF
		378
		379	END
		380
		381	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***

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