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Rev	Author	Line No.	Line
2	mjames	1	;****************** (C) COPYRIGHT 2017 STMicroelectronics ******************
		2	; File Name : startup_stm32f105xc.s*
		3	; Author : MCD Application Team*
		4	; Description : STM32F105xC Devices vector table for MDK-ARM toolchain.*
		5	; This module performs:*
		6	; - Set the initial SP*
		7	; - Set the initial PC == Reset_Handler*
		8	; - Set the vector table entries with the exceptions ISR address*
		9	; - Configure the clock system*
		10	; - Branches to __main in the C library (which eventually*
		11	; calls main()).*
		12	; After Reset the Cortex-M3 processor is in Thread mode,*
		13	; priority is Privileged, and the Stack is set to Main.*
		14	;******************************************************************************
		15	; @attention*
		16	;*
		17	; Copyright (c) 2017-2021 STMicroelectronics.*
		18	; All rights reserved.*
		19	;*
		20	; This software is licensed under terms that can be found in the LICENSE file*
		21	; in the root directory of this software component.*
		22	; If no LICENSE file comes with this software, it is provided AS-IS.*
		23	;*
		24	;******************************************************************************
		25
		26	; Amount of memory (in bytes) allocated for Stack
		27	; Tailor this value to your application needs
		28	; <h> Stack Configuration
		29	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		30	; </h>
		31
		32	Stack_Size EQU 0x00000400
		33
		34	AREA STACK, NOINIT, READWRITE, ALIGN=3
		35	Stack_Mem SPACE Stack_Size
		36	__initial_sp
		37
		38
		39	; <h> Heap Configuration
		40	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		41	; </h>
		42
		43	Heap_Size EQU 0x00000200
		44
		45	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		46	__heap_base
		47	Heap_Mem SPACE Heap_Size
		48	__heap_limit
		49
		50	PRESERVE8
		51	THUMB
		52
		53
		54	; Vector Table Mapped to Address 0 at Reset
		55	AREA RESET, DATA, READONLY
		56	EXPORT __Vectors
		57	EXPORT __Vectors_End
		58	EXPORT __Vectors_Size
		59
		60	__Vectors DCD __initial_sp ; Top of Stack
		61	DCD Reset_Handler ; Reset Handler
		62	DCD NMI_Handler ; NMI Handler
		63	DCD HardFault_Handler ; Hard Fault Handler
		64	DCD MemManage_Handler ; MPU Fault Handler
		65	DCD BusFault_Handler ; Bus Fault Handler
		66	DCD UsageFault_Handler ; Usage Fault Handler
		67	DCD 0 ; Reserved
		68	DCD 0 ; Reserved
		69	DCD 0 ; Reserved
		70	DCD 0 ; Reserved
		71	DCD SVC_Handler ; SVCall Handler
		72	DCD DebugMon_Handler ; Debug Monitor Handler
		73	DCD 0 ; Reserved
		74	DCD PendSV_Handler ; PendSV Handler
		75	DCD SysTick_Handler ; SysTick Handler
		76
		77	; External Interrupts
		78	DCD WWDG_IRQHandler ; Window Watchdog
		79	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		80	DCD TAMPER_IRQHandler ; Tamper
		81	DCD RTC_IRQHandler ; RTC
		82	DCD FLASH_IRQHandler ; Flash
		83	DCD RCC_IRQHandler ; RCC
		84	DCD EXTI0_IRQHandler ; EXTI Line 0
		85	DCD EXTI1_IRQHandler ; EXTI Line 1
		86	DCD EXTI2_IRQHandler ; EXTI Line 2
		87	DCD EXTI3_IRQHandler ; EXTI Line 3
		88	DCD EXTI4_IRQHandler ; EXTI Line 4
		89	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		90	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		91	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		92	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		93	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		94	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		95	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		96	DCD ADC1_2_IRQHandler ; ADC1 and ADC2
		97	DCD CAN1_TX_IRQHandler ; CAN1 TX
		98	DCD CAN1_RX0_IRQHandler ; CAN1 RX0
		99	DCD CAN1_RX1_IRQHandler ; CAN1 RX1
		100	DCD CAN1_SCE_IRQHandler ; CAN1 SCE
		101	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		102	DCD TIM1_BRK_IRQHandler ; TIM1 Break
		103	DCD TIM1_UP_IRQHandler ; TIM1 Update
		104	DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
		105	DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
		106	DCD TIM2_IRQHandler ; TIM2
		107	DCD TIM3_IRQHandler ; TIM3
		108	DCD TIM4_IRQHandler ; TIM4
		109	DCD I2C1_EV_IRQHandler ; I2C1 Event
		110	DCD I2C1_ER_IRQHandler ; I2C1 Error
		111	DCD I2C2_EV_IRQHandler ; I2C2 Event
		112	DCD I2C2_ER_IRQHandler ; I2C1 Error
		113	DCD SPI1_IRQHandler ; SPI1
		114	DCD SPI2_IRQHandler ; SPI2
		115	DCD USART1_IRQHandler ; USART1
		116	DCD USART2_IRQHandler ; USART2
		117	DCD USART3_IRQHandler ; USART3
		118	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		119	DCD RTC_Alarm_IRQHandler ; RTC alarm through EXTI line
		120	DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
		121	DCD 0 ; Reserved
		122	DCD 0 ; Reserved
		123	DCD 0 ; Reserved
		124	DCD 0 ; Reserved
		125	DCD 0 ; Reserved
		126	DCD 0 ; Reserved
		127	DCD 0 ; Reserved
		128	DCD TIM5_IRQHandler ; TIM5
		129	DCD SPI3_IRQHandler ; SPI3
		130	DCD UART4_IRQHandler ; UART4
		131	DCD UART5_IRQHandler ; UART5
		132	DCD TIM6_IRQHandler ; TIM6
		133	DCD TIM7_IRQHandler ; TIM7
		134	DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
		135	DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
		136	DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
		137	DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
		138	DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
		139	DCD 0 ; Reserved
		140	DCD 0 ; Reserved
		141	DCD CAN2_TX_IRQHandler ; CAN2 TX
		142	DCD CAN2_RX0_IRQHandler ; CAN2 RX0
		143	DCD CAN2_RX1_IRQHandler ; CAN2 RX1
		144	DCD CAN2_SCE_IRQHandler ; CAN2 SCE
		145	DCD OTG_FS_IRQHandler ; USB OTG FS
		146	__Vectors_End
		147
		148	__Vectors_Size EQU __Vectors_End - __Vectors
		149
		150	AREA \|.text\|, CODE, READONLY
		151
		152	; Reset handler
		153	Reset_Handler PROC
		154	EXPORT Reset_Handler [WEAK]
		155	IMPORT SystemInit
		156	IMPORT __main
		157	LDR R0, =SystemInit
		158	BLX R0
		159	LDR R0, =__main
		160	BX R0
		161	ENDP
		162
		163	; Dummy Exception Handlers (infinite loops which can be modified)
		164
		165	NMI_Handler PROC
		166	EXPORT NMI_Handler [WEAK]
		167	B .
		168	ENDP
		169	HardFault_Handler\
		170	PROC
		171	EXPORT HardFault_Handler [WEAK]
		172	B .
		173	ENDP
		174	MemManage_Handler\
		175	PROC
		176	EXPORT MemManage_Handler [WEAK]
		177	B .
		178	ENDP
		179	BusFault_Handler\
		180	PROC
		181	EXPORT BusFault_Handler [WEAK]
		182	B .
		183	ENDP
		184	UsageFault_Handler\
		185	PROC
		186	EXPORT UsageFault_Handler [WEAK]
		187	B .
		188	ENDP
		189	SVC_Handler PROC
		190	EXPORT SVC_Handler [WEAK]
		191	B .
		192	ENDP
		193	DebugMon_Handler\
		194	PROC
		195	EXPORT DebugMon_Handler [WEAK]
		196	B .
		197	ENDP
		198	PendSV_Handler PROC
		199	EXPORT PendSV_Handler [WEAK]
		200	B .
		201	ENDP
		202	SysTick_Handler PROC
		203	EXPORT SysTick_Handler [WEAK]
		204	B .
		205	ENDP
		206
		207	Default_Handler PROC
		208
		209	EXPORT WWDG_IRQHandler [WEAK]
		210	EXPORT PVD_IRQHandler [WEAK]
		211	EXPORT TAMPER_IRQHandler [WEAK]
		212	EXPORT RTC_IRQHandler [WEAK]
		213	EXPORT FLASH_IRQHandler [WEAK]
		214	EXPORT RCC_IRQHandler [WEAK]
		215	EXPORT EXTI0_IRQHandler [WEAK]
		216	EXPORT EXTI1_IRQHandler [WEAK]
		217	EXPORT EXTI2_IRQHandler [WEAK]
		218	EXPORT EXTI3_IRQHandler [WEAK]
		219	EXPORT EXTI4_IRQHandler [WEAK]
		220	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		221	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		222	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		223	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		224	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		225	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		226	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		227	EXPORT ADC1_2_IRQHandler [WEAK]
		228	EXPORT CAN1_TX_IRQHandler [WEAK]
		229	EXPORT CAN1_RX0_IRQHandler [WEAK]
		230	EXPORT CAN1_RX1_IRQHandler [WEAK]
		231	EXPORT CAN1_SCE_IRQHandler [WEAK]
		232	EXPORT EXTI9_5_IRQHandler [WEAK]
		233	EXPORT TIM1_BRK_IRQHandler [WEAK]
		234	EXPORT TIM1_UP_IRQHandler [WEAK]
		235	EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
		236	EXPORT TIM1_CC_IRQHandler [WEAK]
		237	EXPORT TIM2_IRQHandler [WEAK]
		238	EXPORT TIM3_IRQHandler [WEAK]
		239	EXPORT TIM4_IRQHandler [WEAK]
		240	EXPORT I2C1_EV_IRQHandler [WEAK]
		241	EXPORT I2C1_ER_IRQHandler [WEAK]
		242	EXPORT I2C2_EV_IRQHandler [WEAK]
		243	EXPORT I2C2_ER_IRQHandler [WEAK]
		244	EXPORT SPI1_IRQHandler [WEAK]
		245	EXPORT SPI2_IRQHandler [WEAK]
		246	EXPORT USART1_IRQHandler [WEAK]
		247	EXPORT USART2_IRQHandler [WEAK]
		248	EXPORT USART3_IRQHandler [WEAK]
		249	EXPORT EXTI15_10_IRQHandler [WEAK]
		250	EXPORT RTC_Alarm_IRQHandler [WEAK]
		251	EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
		252	EXPORT TIM5_IRQHandler [WEAK]
		253	EXPORT SPI3_IRQHandler [WEAK]
		254	EXPORT UART4_IRQHandler [WEAK]
		255	EXPORT UART5_IRQHandler [WEAK]
		256	EXPORT TIM6_IRQHandler [WEAK]
		257	EXPORT TIM7_IRQHandler [WEAK]
		258	EXPORT DMA2_Channel1_IRQHandler [WEAK]
		259	EXPORT DMA2_Channel2_IRQHandler [WEAK]
		260	EXPORT DMA2_Channel3_IRQHandler [WEAK]
		261	EXPORT DMA2_Channel4_IRQHandler [WEAK]
		262	EXPORT DMA2_Channel5_IRQHandler [WEAK]
		263	EXPORT CAN2_TX_IRQHandler [WEAK]
		264	EXPORT CAN2_RX0_IRQHandler [WEAK]
		265	EXPORT CAN2_RX1_IRQHandler [WEAK]
		266	EXPORT CAN2_SCE_IRQHandler [WEAK]
		267	EXPORT OTG_FS_IRQHandler [WEAK]
		268
		269	WWDG_IRQHandler
		270	PVD_IRQHandler
		271	TAMPER_IRQHandler
		272	RTC_IRQHandler
		273	FLASH_IRQHandler
		274	RCC_IRQHandler
		275	EXTI0_IRQHandler
		276	EXTI1_IRQHandler
		277	EXTI2_IRQHandler
		278	EXTI3_IRQHandler
		279	EXTI4_IRQHandler
		280	DMA1_Channel1_IRQHandler
		281	DMA1_Channel2_IRQHandler
		282	DMA1_Channel3_IRQHandler
		283	DMA1_Channel4_IRQHandler
		284	DMA1_Channel5_IRQHandler
		285	DMA1_Channel6_IRQHandler
		286	DMA1_Channel7_IRQHandler
		287	ADC1_2_IRQHandler
		288	CAN1_TX_IRQHandler
		289	CAN1_RX0_IRQHandler
		290	CAN1_RX1_IRQHandler
		291	CAN1_SCE_IRQHandler
		292	EXTI9_5_IRQHandler
		293	TIM1_BRK_IRQHandler
		294	TIM1_UP_IRQHandler
		295	TIM1_TRG_COM_IRQHandler
		296	TIM1_CC_IRQHandler
		297	TIM2_IRQHandler
		298	TIM3_IRQHandler
		299	TIM4_IRQHandler
		300	I2C1_EV_IRQHandler
		301	I2C1_ER_IRQHandler
		302	I2C2_EV_IRQHandler
		303	I2C2_ER_IRQHandler
		304	SPI1_IRQHandler
		305	SPI2_IRQHandler
		306	USART1_IRQHandler
		307	USART2_IRQHandler
		308	USART3_IRQHandler
		309	EXTI15_10_IRQHandler
		310	RTC_Alarm_IRQHandler
		311	OTG_FS_WKUP_IRQHandler
		312	TIM5_IRQHandler
		313	SPI3_IRQHandler
		314	UART4_IRQHandler
		315	UART5_IRQHandler
		316	TIM6_IRQHandler
		317	TIM7_IRQHandler
		318	DMA2_Channel1_IRQHandler
		319	DMA2_Channel2_IRQHandler
		320	DMA2_Channel3_IRQHandler
		321	DMA2_Channel4_IRQHandler
		322	DMA2_Channel5_IRQHandler
		323	CAN2_TX_IRQHandler
		324	CAN2_RX0_IRQHandler
		325	CAN2_RX1_IRQHandler
		326	CAN2_SCE_IRQHandler
		327	OTG_FS_IRQHandler
		328
		329	B .
		330
		331	ENDP
		332
		333	ALIGN
		334
		335	;*******************************************************************************
		336	; User Stack and Heap initialization
		337	;*******************************************************************************
		338	IF :DEF:__MICROLIB
		339
		340	EXPORT __initial_sp
		341	EXPORT __heap_base
		342	EXPORT __heap_limit
		343
		344	ELSE
		345
		346	IMPORT __use_two_region_memory
		347	EXPORT __user_initial_stackheap
		348
		349	__user_initial_stackheap
		350
		351	LDR R0, = Heap_Mem
		352	LDR R1, =(Stack_Mem + Stack_Size)
		353	LDR R2, = (Heap_Mem + Heap_Size)
		354	LDR R3, = Stack_Mem
		355	BX LR
		356
		357	ALIGN
		358
		359	ENDIF
		360
		361	END
		362

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f105xc.s – Rev 2