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Rev	Author	Line No.	Line
2	mjames	1	;****************** (C) COPYRIGHT 2015 STMicroelectronics ******************
		2	; File Name : startup_stm32f101xg.s*
		3	; Author : MCD Application Team*
		4	; Version : V4.0.1*
		5	; Date : 31-July-2015*
		6	; Description : STM32F101xG Devices vector table for MDK-ARM toolchain.*
		7	; This module performs:*
		8	; - Set the initial SP*
		9	; - Set the initial PC == Reset_Handler*
		10	; - Set the vector table entries with the exceptions ISR address*
		11	; - Configure the clock system*
		12	; - Branches to __main in the C library (which eventually*
		13	; calls main()).*
		14	; After Reset the Cortex-M3 processor is in Thread mode,*
		15	; priority is Privileged, and the Stack is set to Main.*
		16	;********************************************************************************
		17	;*
		18	; COPYRIGHT(c) 2015 STMicroelectronics*
		19	;*
		20	; Redistribution and use in source and binary forms, with or without modification,*
		21	; are permitted provided that the following conditions are met:*
		22	; 1. Redistributions of source code must retain the above copyright notice,*
		23	; this list of conditions and the following disclaimer.*
		24	; 2. Redistributions in binary form must reproduce the above copyright notice,*
		25	; this list of conditions and the following disclaimer in the documentation*
		26	; and/or other materials provided with the distribution.*
		27	; 3. Neither the name of STMicroelectronics nor the names of its contributors*
		28	; may be used to endorse or promote products derived from this software*
		29	; without specific prior written permission.*
		30	;*
		31	; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"*
		32	; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE*
		33	; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE*
		34	; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE*
		35	; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL*
		36	; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR*
		37	; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER*
		38	; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,*
		39	; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE*
		40	; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
		41	;
		42	;*******************************************************************************
		43
		44	; Amount of memory (in bytes) allocated for Stack
		45	; Tailor this value to your application needs
		46	; <h> Stack Configuration
		47	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		48	; </h>
		49
		50	Stack_Size EQU 0x00000400
		51
		52	AREA STACK, NOINIT, READWRITE, ALIGN=3
		53	Stack_Mem SPACE Stack_Size
		54	__initial_sp
		55
		56	; <h> Heap Configuration
		57	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		58	; </h>
		59
		60	Heap_Size EQU 0x00000200
		61
		62	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		63	__heap_base
		64	Heap_Mem SPACE Heap_Size
		65	__heap_limit
		66
		67	PRESERVE8
		68	THUMB
		69
		70
		71	; Vector Table Mapped to Address 0 at Reset
		72	AREA RESET, DATA, READONLY
		73	EXPORT __Vectors
		74	EXPORT __Vectors_End
		75	EXPORT __Vectors_Size
		76
		77	__Vectors DCD __initial_sp ; Top of Stack
		78	DCD Reset_Handler ; Reset Handler
		79	DCD NMI_Handler ; NMI Handler
		80	DCD HardFault_Handler ; Hard Fault Handler
		81	DCD MemManage_Handler ; MPU Fault Handler
		82	DCD BusFault_Handler ; Bus Fault Handler
		83	DCD UsageFault_Handler ; Usage Fault Handler
		84	DCD 0 ; Reserved
		85	DCD 0 ; Reserved
		86	DCD 0 ; Reserved
		87	DCD 0 ; Reserved
		88	DCD SVC_Handler ; SVCall Handler
		89	DCD DebugMon_Handler ; Debug Monitor Handler
		90	DCD 0 ; Reserved
		91	DCD PendSV_Handler ; PendSV Handler
		92	DCD SysTick_Handler ; SysTick Handler
		93
		94	; External Interrupts
		95	DCD WWDG_IRQHandler ; Window Watchdog
		96	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		97	DCD TAMPER_IRQHandler ; Tamper
		98	DCD RTC_IRQHandler ; RTC
		99	DCD FLASH_IRQHandler ; Flash
		100	DCD RCC_IRQHandler ; RCC
		101	DCD EXTI0_IRQHandler ; EXTI Line 0
		102	DCD EXTI1_IRQHandler ; EXTI Line 1
		103	DCD EXTI2_IRQHandler ; EXTI Line 2
		104	DCD EXTI3_IRQHandler ; EXTI Line 3
		105	DCD EXTI4_IRQHandler ; EXTI Line 4
		106	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		107	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		108	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		109	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		110	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		111	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		112	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		113	DCD ADC1_2_IRQHandler ; ADC1_2
		114	DCD 0 ; Reserved
		115	DCD 0 ; Reserved
		116	DCD 0 ; Reserved
		117	DCD 0 ; Reserved
		118	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		119	DCD TIM9_IRQHandler ; TIM9
		120	DCD TIM10_IRQHandler ; TIM10
		121	DCD TIM11_IRQHandler ; TIM11
		122	DCD 0 ; Reserved
		123	DCD TIM2_IRQHandler ; TIM2
		124	DCD TIM3_IRQHandler ; TIM3
		125	DCD TIM4_IRQHandler ; TIM4
		126	DCD I2C1_EV_IRQHandler ; I2C1 Event
		127	DCD I2C1_ER_IRQHandler ; I2C1 Error
		128	DCD I2C2_EV_IRQHandler ; I2C2 Event
		129	DCD I2C2_ER_IRQHandler ; I2C2 Error
		130	DCD SPI1_IRQHandler ; SPI1
		131	DCD SPI2_IRQHandler ; SPI2
		132	DCD USART1_IRQHandler ; USART1
		133	DCD USART2_IRQHandler ; USART2
		134	DCD USART3_IRQHandler ; USART3
		135	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		136	DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
		137	DCD 0 ; Reserved
		138	DCD TIM12_IRQHandler ; TIM12
		139	DCD TIM13_IRQHandler ; TIM13
		140	DCD TIM14_IRQHandler ; TIM14
		141	DCD 0 ; Reserved
		142	DCD 0 ; Reserved
		143	DCD FSMC_IRQHandler ; FSMC
		144	DCD 0 ; Reserved
		145	DCD TIM5_IRQHandler ; TIM5
		146	DCD SPI3_IRQHandler ; SPI3
		147	DCD UART4_IRQHandler ; UART4
		148	DCD UART5_IRQHandler ; UART5
		149	DCD TIM6_IRQHandler ; TIM6
		150	DCD TIM7_IRQHandler ; TIM7
		151	DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
		152	DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
		153	DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
		154	DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
		155	__Vectors_End
		156
		157	__Vectors_Size EQU __Vectors_End - __Vectors
		158
		159	AREA \|.text\|, CODE, READONLY
		160
		161	; Reset handler
		162	Reset_Handler PROC
		163	EXPORT Reset_Handler [WEAK]
		164	IMPORT __main
		165	IMPORT SystemInit
		166	LDR R0, =SystemInit
		167	BLX R0
		168	LDR R0, =__main
		169	BX R0
		170	ENDP
		171
		172	; Dummy Exception Handlers (infinite loops which can be modified)
		173
		174	NMI_Handler PROC
		175	EXPORT NMI_Handler [WEAK]
		176	B .
		177	ENDP
		178	HardFault_Handler\
		179	PROC
		180	EXPORT HardFault_Handler [WEAK]
		181	B .
		182	ENDP
		183	MemManage_Handler\
		184	PROC
		185	EXPORT MemManage_Handler [WEAK]
		186	B .
		187	ENDP
		188	BusFault_Handler\
		189	PROC
		190	EXPORT BusFault_Handler [WEAK]
		191	B .
		192	ENDP
		193	UsageFault_Handler\
		194	PROC
		195	EXPORT UsageFault_Handler [WEAK]
		196	B .
		197	ENDP
		198	SVC_Handler PROC
		199	EXPORT SVC_Handler [WEAK]
		200	B .
		201	ENDP
		202	DebugMon_Handler\
		203	PROC
		204	EXPORT DebugMon_Handler [WEAK]
		205	B .
		206	ENDP
		207	PendSV_Handler PROC
		208	EXPORT PendSV_Handler [WEAK]
		209	B .
		210	ENDP
		211	SysTick_Handler PROC
		212	EXPORT SysTick_Handler [WEAK]
		213	B .
		214	ENDP
		215
		216	Default_Handler PROC
		217
		218	EXPORT WWDG_IRQHandler [WEAK]
		219	EXPORT PVD_IRQHandler [WEAK]
		220	EXPORT TAMPER_IRQHandler [WEAK]
		221	EXPORT RTC_IRQHandler [WEAK]
		222	EXPORT FLASH_IRQHandler [WEAK]
		223	EXPORT RCC_IRQHandler [WEAK]
		224	EXPORT EXTI0_IRQHandler [WEAK]
		225	EXPORT EXTI1_IRQHandler [WEAK]
		226	EXPORT EXTI2_IRQHandler [WEAK]
		227	EXPORT EXTI3_IRQHandler [WEAK]
		228	EXPORT EXTI4_IRQHandler [WEAK]
		229	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		230	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		231	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		232	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		233	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		234	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		235	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		236	EXPORT ADC1_2_IRQHandler [WEAK]
		237	EXPORT EXTI9_5_IRQHandler [WEAK]
		238	EXPORT TIM9_IRQHandler [WEAK]
		239	EXPORT TIM10_IRQHandler [WEAK]
		240	EXPORT TIM11_IRQHandler [WEAK]
		241	EXPORT TIM2_IRQHandler [WEAK]
		242	EXPORT TIM3_IRQHandler [WEAK]
		243	EXPORT TIM4_IRQHandler [WEAK]
		244	EXPORT I2C1_EV_IRQHandler [WEAK]
		245	EXPORT I2C1_ER_IRQHandler [WEAK]
		246	EXPORT I2C2_EV_IRQHandler [WEAK]
		247	EXPORT I2C2_ER_IRQHandler [WEAK]
		248	EXPORT SPI1_IRQHandler [WEAK]
		249	EXPORT SPI2_IRQHandler [WEAK]
		250	EXPORT USART1_IRQHandler [WEAK]
		251	EXPORT USART2_IRQHandler [WEAK]
		252	EXPORT USART3_IRQHandler [WEAK]
		253	EXPORT EXTI15_10_IRQHandler [WEAK]
		254	EXPORT RTC_Alarm_IRQHandler [WEAK]
		255	EXPORT TIM12_IRQHandler [WEAK]
		256	EXPORT TIM13_IRQHandler [WEAK]
		257	EXPORT TIM14_IRQHandler [WEAK]
		258	EXPORT FSMC_IRQHandler [WEAK]
		259	EXPORT TIM5_IRQHandler [WEAK]
		260	EXPORT SPI3_IRQHandler [WEAK]
		261	EXPORT UART4_IRQHandler [WEAK]
		262	EXPORT UART5_IRQHandler [WEAK]
		263	EXPORT TIM6_IRQHandler [WEAK]
		264	EXPORT TIM7_IRQHandler [WEAK]
		265	EXPORT DMA2_Channel1_IRQHandler [WEAK]
		266	EXPORT DMA2_Channel2_IRQHandler [WEAK]
		267	EXPORT DMA2_Channel3_IRQHandler [WEAK]
		268	EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
		269
		270	WWDG_IRQHandler
		271	PVD_IRQHandler
		272	TAMPER_IRQHandler
		273	RTC_IRQHandler
		274	FLASH_IRQHandler
		275	RCC_IRQHandler
		276	EXTI0_IRQHandler
		277	EXTI1_IRQHandler
		278	EXTI2_IRQHandler
		279	EXTI3_IRQHandler
		280	EXTI4_IRQHandler
		281	DMA1_Channel1_IRQHandler
		282	DMA1_Channel2_IRQHandler
		283	DMA1_Channel3_IRQHandler
		284	DMA1_Channel4_IRQHandler
		285	DMA1_Channel5_IRQHandler
		286	DMA1_Channel6_IRQHandler
		287	DMA1_Channel7_IRQHandler
		288	ADC1_2_IRQHandler
		289	EXTI9_5_IRQHandler
		290	TIM9_IRQHandler
		291	TIM10_IRQHandler
		292	TIM11_IRQHandler
		293	TIM2_IRQHandler
		294	TIM3_IRQHandler
		295	TIM4_IRQHandler
		296	I2C1_EV_IRQHandler
		297	I2C1_ER_IRQHandler
		298	I2C2_EV_IRQHandler
		299	I2C2_ER_IRQHandler
		300	SPI1_IRQHandler
		301	SPI2_IRQHandler
		302	USART1_IRQHandler
		303	USART2_IRQHandler
		304	USART3_IRQHandler
		305	EXTI15_10_IRQHandler
		306	RTC_Alarm_IRQHandler
		307	TIM12_IRQHandler
		308	TIM13_IRQHandler
		309	TIM14_IRQHandler
		310	FSMC_IRQHandler
		311	TIM5_IRQHandler
		312	SPI3_IRQHandler
		313	UART4_IRQHandler
		314	UART5_IRQHandler
		315	TIM6_IRQHandler
		316	TIM7_IRQHandler
		317	DMA2_Channel1_IRQHandler
		318	DMA2_Channel2_IRQHandler
		319	DMA2_Channel3_IRQHandler
		320	DMA2_Channel4_5_IRQHandler
		321	B .
		322
		323	ENDP
		324
		325	ALIGN
		326
		327	;*******************************************************************************
		328	; User Stack and Heap initialization
		329	;*******************************************************************************
		330	IF :DEF:__MICROLIB
		331
		332	EXPORT __initial_sp
		333	EXPORT __heap_base
		334	EXPORT __heap_limit
		335
		336	ELSE
		337
		338	IMPORT __use_two_region_memory
		339	EXPORT __user_initial_stackheap
		340
		341	__user_initial_stackheap
		342
		343	LDR R0, = Heap_Mem
		344	LDR R1, =(Stack_Mem + Stack_Size)
		345	LDR R2, = (Heap_Mem + Heap_Size)
		346	LDR R3, = Stack_Mem
		347	BX LR
		348
		349	ALIGN
		350
		351	ENDIF
		352
		353	END
		354
		355	;********************** (C) COPYRIGHT STMicroelectronics *END OF FILE***

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