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Rev	Author	Line No.	Line
3	mjames	1	;****************** (C) COPYRIGHT 2017 STMicroelectronics ******************
		2	; File Name : startup_stm32f101xe.s*
		3	; Author : MCD Application Team*
		4	; Description : STM32F101xE Devices vector table for MDK-ARM toolchain.*
		5	; This module performs:*
		6	; - Set the initial SP*
		7	; - Set the initial PC == Reset_Handler*
		8	; - Set the vector table entries with the exceptions ISR address*
		9	; - Configure the clock system*
		10	; - Branches to __main in the C library (which eventually*
		11	; calls main()).*
		12	; After Reset the Cortex-M3 processor is in Thread mode,*
		13	; priority is Privileged, and the Stack is set to Main.*
		14	;******************************************************************************
		15	; @attention*
		16	;*
		17	; Copyright (c) 2017-2021 STMicroelectronics.*
		18	; All rights reserved.*
		19	;*
		20	; This software is licensed under terms that can be found in the LICENSE file*
		21	; in the root directory of this software component.*
		22	; If no LICENSE file comes with this software, it is provided AS-IS.*
		23	;*
		24	;******************************************************************************
		25
		26	; Amount of memory (in bytes) allocated for Stack
		27	; Tailor this value to your application needs
		28	; <h> Stack Configuration
		29	; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
		30	; </h>
		31
		32	Stack_Size EQU 0x00000400
		33
		34	AREA STACK, NOINIT, READWRITE, ALIGN=3
		35	Stack_Mem SPACE Stack_Size
		36	__initial_sp
		37
		38	; <h> Heap Configuration
		39	; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
		40	; </h>
		41
		42	Heap_Size EQU 0x00000200
		43
		44	AREA HEAP, NOINIT, READWRITE, ALIGN=3
		45	__heap_base
		46	Heap_Mem SPACE Heap_Size
		47	__heap_limit
		48
		49	PRESERVE8
		50	THUMB
		51
		52
		53	; Vector Table Mapped to Address 0 at Reset
		54	AREA RESET, DATA, READONLY
		55	EXPORT __Vectors
		56	EXPORT __Vectors_End
		57	EXPORT __Vectors_Size
		58
		59	__Vectors DCD __initial_sp ; Top of Stack
		60	DCD Reset_Handler ; Reset Handler
		61	DCD NMI_Handler ; NMI Handler
		62	DCD HardFault_Handler ; Hard Fault Handler
		63	DCD MemManage_Handler ; MPU Fault Handler
		64	DCD BusFault_Handler ; Bus Fault Handler
		65	DCD UsageFault_Handler ; Usage Fault Handler
		66	DCD 0 ; Reserved
		67	DCD 0 ; Reserved
		68	DCD 0 ; Reserved
		69	DCD 0 ; Reserved
		70	DCD SVC_Handler ; SVCall Handler
		71	DCD DebugMon_Handler ; Debug Monitor Handler
		72	DCD 0 ; Reserved
		73	DCD PendSV_Handler ; PendSV Handler
		74	DCD SysTick_Handler ; SysTick Handler
		75
		76	; External Interrupts
		77	DCD WWDG_IRQHandler ; Window Watchdog
		78	DCD PVD_IRQHandler ; PVD through EXTI Line detect
		79	DCD TAMPER_IRQHandler ; Tamper
		80	DCD RTC_IRQHandler ; RTC
		81	DCD FLASH_IRQHandler ; Flash
		82	DCD RCC_IRQHandler ; RCC
		83	DCD EXTI0_IRQHandler ; EXTI Line 0
		84	DCD EXTI1_IRQHandler ; EXTI Line 1
		85	DCD EXTI2_IRQHandler ; EXTI Line 2
		86	DCD EXTI3_IRQHandler ; EXTI Line 3
		87	DCD EXTI4_IRQHandler ; EXTI Line 4
		88	DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
		89	DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
		90	DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
		91	DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
		92	DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
		93	DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
		94	DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
		95	DCD ADC1_IRQHandler ; ADC1
		96	DCD 0 ; Reserved
		97	DCD 0 ; Reserved
		98	DCD 0 ; Reserved
		99	DCD 0 ; Reserved
		100	DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
		101	DCD 0 ; Reserved
		102	DCD 0 ; Reserved
		103	DCD 0 ; Reserved
		104	DCD 0 ; Reserved
		105	DCD TIM2_IRQHandler ; TIM2
		106	DCD TIM3_IRQHandler ; TIM3
		107	DCD TIM4_IRQHandler ; TIM4
		108	DCD I2C1_EV_IRQHandler ; I2C1 Event
		109	DCD I2C1_ER_IRQHandler ; I2C1 Error
		110	DCD I2C2_EV_IRQHandler ; I2C2 Event
		111	DCD I2C2_ER_IRQHandler ; I2C2 Error
		112	DCD SPI1_IRQHandler ; SPI1
		113	DCD SPI2_IRQHandler ; SPI2
		114	DCD USART1_IRQHandler ; USART1
		115	DCD USART2_IRQHandler ; USART2
		116	DCD USART3_IRQHandler ; USART3
		117	DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
		118	DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
		119	DCD 0 ; Reserved
		120	DCD 0 ; Reserved
		121	DCD 0 ; Reserved
		122	DCD 0 ; Reserved
		123	DCD 0 ; Reserved
		124	DCD 0 ; Reserved
		125	DCD FSMC_IRQHandler ; FSMC
		126	DCD 0 ; Reserved
		127	DCD TIM5_IRQHandler ; TIM5
		128	DCD SPI3_IRQHandler ; SPI3
		129	DCD UART4_IRQHandler ; UART4
		130	DCD UART5_IRQHandler ; UART5
		131	DCD TIM6_IRQHandler ; TIM6
		132	DCD TIM7_IRQHandler ; TIM7
		133	DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
		134	DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
		135	DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
		136	DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
		137	__Vectors_End
		138
		139	__Vectors_Size EQU __Vectors_End - __Vectors
		140
		141	AREA \|.text\|, CODE, READONLY
		142
		143	; Reset handler
		144	Reset_Handler PROC
		145	EXPORT Reset_Handler [WEAK]
		146	IMPORT __main
		147	IMPORT SystemInit
		148	LDR R0, =SystemInit
		149	BLX R0
		150	LDR R0, =__main
		151	BX R0
		152	ENDP
		153
		154	; Dummy Exception Handlers (infinite loops which can be modified)
		155
		156	NMI_Handler PROC
		157	EXPORT NMI_Handler [WEAK]
		158	B .
		159	ENDP
		160	HardFault_Handler\
		161	PROC
		162	EXPORT HardFault_Handler [WEAK]
		163	B .
		164	ENDP
		165	MemManage_Handler\
		166	PROC
		167	EXPORT MemManage_Handler [WEAK]
		168	B .
		169	ENDP
		170	BusFault_Handler\
		171	PROC
		172	EXPORT BusFault_Handler [WEAK]
		173	B .
		174	ENDP
		175	UsageFault_Handler\
		176	PROC
		177	EXPORT UsageFault_Handler [WEAK]
		178	B .
		179	ENDP
		180	SVC_Handler PROC
		181	EXPORT SVC_Handler [WEAK]
		182	B .
		183	ENDP
		184	DebugMon_Handler\
		185	PROC
		186	EXPORT DebugMon_Handler [WEAK]
		187	B .
		188	ENDP
		189	PendSV_Handler PROC
		190	EXPORT PendSV_Handler [WEAK]
		191	B .
		192	ENDP
		193	SysTick_Handler PROC
		194	EXPORT SysTick_Handler [WEAK]
		195	B .
		196	ENDP
		197
		198	Default_Handler PROC
		199
		200	EXPORT WWDG_IRQHandler [WEAK]
		201	EXPORT PVD_IRQHandler [WEAK]
		202	EXPORT TAMPER_IRQHandler [WEAK]
		203	EXPORT RTC_IRQHandler [WEAK]
		204	EXPORT FLASH_IRQHandler [WEAK]
		205	EXPORT RCC_IRQHandler [WEAK]
		206	EXPORT EXTI0_IRQHandler [WEAK]
		207	EXPORT EXTI1_IRQHandler [WEAK]
		208	EXPORT EXTI2_IRQHandler [WEAK]
		209	EXPORT EXTI3_IRQHandler [WEAK]
		210	EXPORT EXTI4_IRQHandler [WEAK]
		211	EXPORT DMA1_Channel1_IRQHandler [WEAK]
		212	EXPORT DMA1_Channel2_IRQHandler [WEAK]
		213	EXPORT DMA1_Channel3_IRQHandler [WEAK]
		214	EXPORT DMA1_Channel4_IRQHandler [WEAK]
		215	EXPORT DMA1_Channel5_IRQHandler [WEAK]
		216	EXPORT DMA1_Channel6_IRQHandler [WEAK]
		217	EXPORT DMA1_Channel7_IRQHandler [WEAK]
		218	EXPORT ADC1_IRQHandler [WEAK]
		219	EXPORT EXTI9_5_IRQHandler [WEAK]
		220	EXPORT TIM2_IRQHandler [WEAK]
		221	EXPORT TIM3_IRQHandler [WEAK]
		222	EXPORT TIM4_IRQHandler [WEAK]
		223	EXPORT I2C1_EV_IRQHandler [WEAK]
		224	EXPORT I2C1_ER_IRQHandler [WEAK]
		225	EXPORT I2C2_EV_IRQHandler [WEAK]
		226	EXPORT I2C2_ER_IRQHandler [WEAK]
		227	EXPORT SPI1_IRQHandler [WEAK]
		228	EXPORT SPI2_IRQHandler [WEAK]
		229	EXPORT USART1_IRQHandler [WEAK]
		230	EXPORT USART2_IRQHandler [WEAK]
		231	EXPORT USART3_IRQHandler [WEAK]
		232	EXPORT EXTI15_10_IRQHandler [WEAK]
		233	EXPORT RTC_Alarm_IRQHandler [WEAK]
		234	EXPORT FSMC_IRQHandler [WEAK]
		235	EXPORT TIM5_IRQHandler [WEAK]
		236	EXPORT SPI3_IRQHandler [WEAK]
		237	EXPORT UART4_IRQHandler [WEAK]
		238	EXPORT UART5_IRQHandler [WEAK]
		239	EXPORT TIM6_IRQHandler [WEAK]
		240	EXPORT TIM7_IRQHandler [WEAK]
		241	EXPORT DMA2_Channel1_IRQHandler [WEAK]
		242	EXPORT DMA2_Channel2_IRQHandler [WEAK]
		243	EXPORT DMA2_Channel3_IRQHandler [WEAK]
		244	EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
		245
		246	WWDG_IRQHandler
		247	PVD_IRQHandler
		248	TAMPER_IRQHandler
		249	RTC_IRQHandler
		250	FLASH_IRQHandler
		251	RCC_IRQHandler
		252	EXTI0_IRQHandler
		253	EXTI1_IRQHandler
		254	EXTI2_IRQHandler
		255	EXTI3_IRQHandler
		256	EXTI4_IRQHandler
		257	DMA1_Channel1_IRQHandler
		258	DMA1_Channel2_IRQHandler
		259	DMA1_Channel3_IRQHandler
		260	DMA1_Channel4_IRQHandler
		261	DMA1_Channel5_IRQHandler
		262	DMA1_Channel6_IRQHandler
		263	DMA1_Channel7_IRQHandler
		264	ADC1_IRQHandler
		265	EXTI9_5_IRQHandler
		266	TIM2_IRQHandler
		267	TIM3_IRQHandler
		268	TIM4_IRQHandler
		269	I2C1_EV_IRQHandler
		270	I2C1_ER_IRQHandler
		271	I2C2_EV_IRQHandler
		272	I2C2_ER_IRQHandler
		273	SPI1_IRQHandler
		274	SPI2_IRQHandler
		275	USART1_IRQHandler
		276	USART2_IRQHandler
		277	USART3_IRQHandler
		278	EXTI15_10_IRQHandler
		279	RTC_Alarm_IRQHandler
		280	FSMC_IRQHandler
		281	TIM5_IRQHandler
		282	SPI3_IRQHandler
		283	UART4_IRQHandler
		284	UART5_IRQHandler
		285	TIM6_IRQHandler
		286	TIM7_IRQHandler
		287	DMA2_Channel1_IRQHandler
		288	DMA2_Channel2_IRQHandler
		289	DMA2_Channel3_IRQHandler
		290	DMA2_Channel4_5_IRQHandler
		291	B .
		292
		293	ENDP
		294
		295	ALIGN
		296
		297	;*******************************************************************************
		298	; User Stack and Heap initialization
		299	;*******************************************************************************
		300	IF :DEF:__MICROLIB
		301
		302	EXPORT __initial_sp
		303	EXPORT __heap_base
		304	EXPORT __heap_limit
		305
		306	ELSE
		307
		308	IMPORT __use_two_region_memory
		309	EXPORT __user_initial_stackheap
		310
		311	__user_initial_stackheap
		312
		313	LDR R0, = Heap_Mem
		314	LDR R1, =(Stack_Mem + Stack_Size)
		315	LDR R2, = (Heap_Mem + Heap_Size)
		316	LDR R3, = Stack_Mem
		317	BX LR
		318
		319	ALIGN
		320
		321	ENDIF
		322
		323	END
		324

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(root)/trunk/Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f101xe.s – Rev 3